Substrate component and semiconductor device

Abstract

To provide a semiconductor device that enables thinning and high density of a conductive path and suppresses the influence of noise.SOLUTION: A semiconductor device A1 includes a substrate 2, a conductive portion formed on a main surface 21 of the substrate, a semiconductor chip disposed on the main surface of the substrate, a control device for controlling the semiconductor chip, a sealing resin, and a first lead 15a bonded to the conductive portion and partially exposed from the sealing resin. The conductive portion includes a first pad 32a and a second pad 32b spaced apart from each other. The first lead is bonded to the first and second pads. This allows noise input to the first pad via the connecting wiring to be released from the first lead to the outside. This prevents noise from being input to other electronic components via the second pad and the connecting wiring connected thereto. This reduces the effects of noise compared to when the first lead is bonded to a single pad.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] One of the various semiconductor devices is called an IPM (Intelligent Power Module), which includes a semiconductor chip, a control chip that controls the semiconductor chip, and a sealing resin that covers the semiconductor chip and the control chip (see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-4893 Summary of the Invention [Problem to be solved by the invention]

[0004] Multiple types of signals are input to and output from the control chip. As the number of signals increases, the number of conductive paths connecting to the control chip must also increase. However, the conventional method of configuring these conductive paths using multiple metal leads can make it difficult to further increase the integration density of semiconductor devices.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that enables higher integration than ever before. [Means for solving the problem]

[0006] A semiconductor device provided by a first aspect of the present disclosure includes a substrate having a substrate main surface and a substrate back surface facing opposite each other in a thickness direction, a conductive portion made of a conductive material formed on the substrate main surface, a semiconductor chip disposed on the substrate main surface, a control device disposed on the substrate main surface and controlling the semiconductor chip, a sealing resin covering at least a portion of the substrate, the semiconductor chip, the control device, and the conductive portion, and a first lead bonded to the conductive portion via a conductive bonding material and a portion exposed from the sealing resin. The conductive portion includes a first pad and a second pad disposed spaced apart from each other. The first lead is bonded to the first pad and the second pad. [Effects of the Invention]

[0007] According to the above configuration, a conductive portion is formed on the main surface of the substrate. Therefore, a conductive path to an electronic component arranged on the main surface of the substrate can be formed by the conductive portion. Therefore, compared to when a conductive path is formed using, for example, a metal lead, it is possible to achieve a thinner and denser conductive path. Furthermore, the first lead is joined to the first pad and the second pad via a conductive bonding material. This allows noise input to the first pad via the connection wiring to be released to the outside from the first lead. Therefore, noise input to other electronic components via the second pad and the connection wiring connected thereto is suppressed. Therefore, the effects of noise are suppressed compared to when the first lead is joined to a single pad.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view showing the semiconductor device of FIG. [Figure 3]2 is a plan view showing the semiconductor device of FIG. 1, seen through a sealing resin. FIG. [Figure 4] FIG. 2 is a bottom view showing the semiconductor device of FIG. [Figure 5] FIG. 4 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 4 is a partially enlarged view of FIG. [Figure 7] FIG. 4 is a partially enlarged view of FIG. [Figure 8] FIG. 4 is a partially enlarged view of FIG. [Figure 9] FIG. 4 is a partially enlarged view of FIG. [Figure 10] FIG. [Figure 11] 2A to 2C are diagrams illustrating an example of a method for manufacturing the semiconductor device of FIG. [Figure 12] 10A and 10B are schematic diagrams for explaining the relationship between the connection state between the pad and the lead and the noise transmission state. [Figure 13] 1. FIG. 4 is a partially enlarged plan view showing a modification of the semiconductor device of FIG. [Figure 14] 1. FIG. 4 is a partially enlarged plan view showing a modification of the semiconductor device of FIG. [Figure 15] FIG. 10 is a partially enlarged plan view showing a semiconductor device according to a second embodiment of the present disclosure. [Figure 16] FIG. 10 is a simplified plan view showing a semiconductor device according to a third embodiment of the present disclosure. [Figure 17] FIG. 10 is a simplified plan view showing a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 18] FIG. 10 is a simplified plan view showing a semiconductor device according to a fifth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0011] In this disclosure, unless otherwise specified, the terms "a certain object A is formed on an object B" and "a certain object A is formed on an object B" include "a certain object A is formed directly on an object B" and "a certain object A is formed on an object B with another object interposed between the objects A and B." Similarly, the terms "a certain object A is disposed on an object B" and "a certain object A is disposed on an object B" include "a certain object A is disposed directly on an object B" and "a certain object A is disposed on an object B with another object interposed between the objects A and B," unless otherwise specified. Similarly, the term "a certain object A is located on an object B" includes "a certain object A is located on an object B in contact with the object B" and "a certain object A is located on an object B with another object interposed between the objects A and B," unless otherwise specified. Additionally, unless otherwise specified, "something A overlaps something B when viewed from a certain direction" includes "something A overlaps the entirety of something B" and "something A overlaps part of something B."

[0012] First Embodiment 1 to 10 show an example of a semiconductor device according to the present disclosure. The semiconductor device A1 of this embodiment includes a plurality of leads 1, a substrate 2, a plurality of bonding portions 25, a conductive portion 3, four semiconductor chips 4, four control devices 5, a plurality of passive elements 6, a plurality of wires 71, a plurality of wires 72, and a sealing resin 8. In this embodiment, the semiconductor device A1 is an IPM (Intelligent Power Module). The semiconductor device A1 is used, for example, in applications such as air conditioners and motor control devices.

[0013] FIG. 1 is a perspective view showing the semiconductor device A1. FIG. 2 is a plan view showing the semiconductor device A1. FIG. 3 is a plan view showing the semiconductor device A1, seen through the sealing resin 8. In FIG. 3, the outline of the sealing resin 8 is shown by an imaginary line (two-dot chain line). FIG. 4 is a bottom view showing the semiconductor device A1. FIG. 5 is a cross-sectional view taken along line VV in FIG. 3. FIGS. 6 to 9 are enlarged views of a portion of FIG. 3. FIG. 10 is a plan view showing the substrate 2.

[0014] For ease of explanation, the thickness direction (direction in plan view) of substrate 2 is defined as the z direction, and the direction along one side of substrate 2 perpendicular to the z direction (the left-right direction in FIGS. 2 to 4) is defined as the x direction. The direction perpendicular to the z direction and the x direction (the up-down direction in FIGS. 2 to 4) is defined as the y direction. The z direction is an example of the "thickness direction."

[0015] The substrate 2 is plate-shaped and has a rectangular shape when viewed in the z direction that is long in the x direction. The thickness (dimension in the z direction) of the substrate 2 is, for example, approximately 0.1 mm to 1.0 mm. The dimensions of the substrate 2 are not limited. The substrate 2 is made of an insulating material. The material of the substrate 2 is not particularly limited. For example, a material with a higher thermal conductivity than the material of the sealing resin 8 is preferable. Examples of the material of the substrate 2 include ceramics such as alumina (Al2O3), silicon nitride (SiN), aluminum nitride (AlN), and alumina containing zirconia.

[0016] The substrate 2 has a substrate main surface 21 and a substrate back surface 22. The substrate main surface 21 and the substrate back surface 22 are surfaces facing opposite each other in the z direction and are both flat surfaces perpendicular to the z direction. The substrate main surface 21 faces upward in FIG. 5. The substrate main surface 21 has conductive portions 3 and multiple joints 25 formed thereon, and is mounted with multiple leads 1 and multiple electronic components. The multiple electronic components include four semiconductor chips 4, four control devices 5, and multiple passive elements 6. The substrate back surface 22 faces downward in FIG. 5. As shown in FIG. 4, the substrate back surface 22 is exposed from the sealing resin 8. The substrate main surface 21 and the substrate back surface 22 are both rectangular in shape. The shape of the substrate 2 is not limited.

[0017] The conductive portion 3 is formed on the substrate 2. In this embodiment, the conductive portion 3 is formed on the substrate main surface 21 of the substrate 2. The conductive portion 3 is made of a conductive material. There is no particular limitation on the conductive material that constitutes the conductive portion 3. Examples of conductive materials for the conductive portion 3 include those containing silver (Ag), copper (Cu), gold (Au), etc. In the following explanation, an example will be described in which the conductive portion 3 contains silver. Note that the conductive portion 3 may contain copper instead of silver, or may contain gold instead of silver or copper. Alternatively, the conductive portion 3 may contain Ag—Pt or Ag—Pd. There is no particular limitation on the method for forming the conductive portion 3, and it may be formed, for example, by firing a paste containing these metals. There is no particular limitation on the thickness of the conductive portion 3, and it is, for example, about 5 μm to 30 μm.

[0018] The shape of the conductive portion 3 is not particularly limited. In this embodiment, the conductive portion 3 includes a plurality of pads 31, a plurality of pads 32, and a plurality of connection wires 33, as shown in FIG. 10 . Each pad 31 is, for example, rectangular, and is conductively connected to one of the control device 5, the passive element 6, and the wire 72. The shape of the pad 31 is not particularly limited. The pads 31 are arranged spaced apart from one another.

[0019] Each pad 32 is, for example, rectangular, and is electrically connected to a lead 15 (described later). The shape of the pads 32 is not limited. The pads 32 are spaced apart from one another. In this embodiment, the pads 32 are formed on one end of the main surface 21 of the substrate 2 in the y direction (the upper side in FIG. 10) or on both ends in the x direction. As shown in FIGS. 6 to 9, the pads 32 include pads 32a, 32b, 32c, 32d, 32e, 32f, 32g, and 32h. The pads 32a and 32b are connected to the same lead 1 (lead 15a, described later). The pads 32c and 32d are connected to the same lead 1 (lead 15b, described later). The pads 32e and 32f are connected to the same lead 1 (lead 15c, described later). The pads 32g and 32h are connected to the same lead 1 (lead 15d, described later).

[0020] Each connection wiring 33 connects a pad 31 to another pad 31, or connects a pad 31 to a pad 32. In this embodiment, as shown in FIGS. 6 to 9, some of the connection wirings 33 overlap the control device 5 when viewed in the z direction. That is, the connection wirings 33 are arranged between the substrate main surface 21 of the substrate 2 and the control device 5. Furthermore, some of the connection wirings 33 overlap the passive elements 6 when viewed in the z direction. That is, the connection wirings 33 are arranged between the substrate main surface 21 of the substrate 2 and the passive elements 6.

[0021] As shown in FIG. 10 , a plurality of bonding portions 25 are formed on the substrate 2. In this embodiment, the plurality of bonding portions 25 are formed on the substrate main surface 21 of the substrate 2 toward the other side in the y direction (the lower side in FIG. 10 ). The material of the bonding portions 25 is not particularly limited, and for example, the bonding portions 25 are made of a material capable of bonding the substrate 2 and the lead 1. The bonding portions 25 are made of, for example, a conductive material. The conductive material constituting the bonding portions 25 is not particularly limited. Examples of conductive materials for the bonding portions 25 include those containing silver (Ag), copper (Cu), gold (Au), etc. In the following description, an example will be given in which the bonding portions 25 contain silver. The bonding portions 25 in this example contain the same conductive material as the conductive portion 3. The bonding portions 25 may contain copper instead of silver, or may contain gold instead of silver or copper. Alternatively, the bonding portions 25 may contain Ag—Pt or Ag—Pd. The method for forming the joints 25 is not limited, and for example, they are formed by firing a paste containing these metals, similar to the conductive portion 3. The thickness of the joints 25 is not particularly limited, and is, for example, about 5 μm to 30 μm.

[0022] In this embodiment, as shown in FIG. 10 , the multiple bonding portions 25 include two bonding portions 251, two bonding portions 252, two bonding portions 253, and one bonding portion 254. The bonding portions 251, 252, 253, and 254 are spaced apart from one another. The two bonding portions 251 are formed near both ends in the x-direction on the substrate main surface 21. A lead 11 (described later) is bonded to each bonding portion 251. The bonding portion 254 is formed in the center in the x-direction on the substrate main surface 21. A lead 14 (described later) is bonded to the bonding portion 254. One bonding portion 253 is formed between one bonding portion 251 and one bonding portion 254 (on the right side in FIG. 10 ) in the x-direction on the substrate main surface 21. The other bonding portion 253 is formed between the other bonding portion 251 and one bonding portion 254 (on the left side in FIG. 10 ) in the x-direction on the substrate main surface 21. A lead 13 (described later) is bonded to each of the bonding portions 253. One bonding portion 252 is formed between one bonding portion 251 and bonding portion 254 so as to surround one bonding portion 253. The other bonding portion 252 is formed between the other bonding portion 251 and bonding portion 254 so as to surround the other bonding portion 253. A lead 12 (described later) is bonded to each of the bonding portions 252. The shapes and arrangements of the bonding portions 251, 252, 253, and 254 are not limited.

[0023] The leads 1 are made of a material containing metal and have a higher thermal conductivity than the substrate 2, for example. The metal constituting the leads 1 is not particularly limited, and may be, for example, copper (Cu), aluminum, iron (Fe), oxygen-free copper, or an alloy thereof (for example, a Cu-Sn alloy, a Cu-Zr alloy, a Cu-Fe alloy, etc.). The leads 1 may also be plated with nickel (Ni). The leads 1 may be formed, for example, by pressing a mold against a metal plate, or by patterning a metal plate by etching. The method for forming the leads 1 is not particularly limited. The thickness of each lead 1 is not particularly limited, and is, for example, about 0.4 mm to 0.8 mm. The leads 1 are spaced apart from each other.

[0024] In this embodiment, the multiple leads 1 include two leads 11, two leads 12, two leads 13, one lead 14, and multiple leads 15. The leads 11, 12, 13, and 14 form a conductive path to the semiconductor chip 4. The multiple leads 15 form a conductive path to the control device 5 or the passive element 6.

[0025] Two leads 11 are arranged on the substrate 2, and in this embodiment, are arranged on the substrate main surface 21. The leads 11 are an example of a "third lead." Each lead 11 is joined to a respective joint 25 via a joint material 75. The joint material 75 may be any material that can join the leads 11 to the joint 25. From the viewpoint of efficiently transferring heat from the leads 11 to the substrate 2, the joint material 75 is preferably one with higher thermal conductivity, and examples of such materials include silver paste, copper paste, and solder. However, the joint material 75 may also be an insulating material such as an epoxy resin or a silicone resin. Furthermore, if the joint 25 is not formed on the substrate 2, the leads 11 may be directly joined to the substrate 2. Each lead 11 is joined to a respective joint 251. When distinguishing between the two leads 11, the one joined to one joint 251 (the right joint 251 in FIG. 10) is referred to as lead 11a, and the one joined to the other joint 251 (the left joint 251 in FIG. 10) is referred to as lead 11b. A semiconductor chip 4a is joined to lead 11a, and a semiconductor chip 4c is joined to lead 11b.

[0026] There is no particular limitation on the configuration of the lead 11. In this embodiment, the lead 11 will be described by dividing it into a joint portion 111, a protruding portion 112, an inclined connection portion 113, and a parallel connection portion 114, as shown in FIG.

[0027] The bonding portion 111 has a main surface 111a and a back surface 111b. The main surface 111a and the back surface 111b are surfaces facing opposite each other in the z direction and are both flat surfaces perpendicular to the z direction. The main surface 111a faces upward in FIG. 5. The semiconductor chip 4 is bonded to the main surface 111a. The back surface 111b faces downward in FIG. 5. The back surface 111b is bonded to the bonding portion 25 by a bonding material 75. The inclined connection portion 113 and the parallel connection portion 114 are covered with a sealing resin 8. The inclined connection portion 113 is connected to the bonding portion 111 and the parallel connection portion 114 and is inclined with respect to the bonding portion 111 and the parallel connection portion 114. The parallel connection portion 114 is connected to the inclined connection portion 113 and the protruding portion 112 and is parallel to the bonding portion 111. The protruding portion 112 is connected to an end of the parallel connection portion 114 and is a portion of the lead 11 that protrudes from the sealing resin 8. The protruding portion 112 protrudes in the y direction opposite the bonding portion 111. The protruding portion 112 is used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protruding portion 112 is bent in the z direction toward the side toward which the main surface 111a of the bonding portion 111 faces.

[0028] Two leads 12 are arranged on the substrate 2, and in this embodiment, are arranged on the substrate main surface 21. The leads 12 are an example of a "third lead." Each lead 12 is joined to a respective joint 252 via a joint material 75. When distinguishing between the two leads 12, the one joined to one joint 252 (the right joint 252 in FIG. 10) is referred to as lead 12a, and the one joined to the other joint 252 (the left joint 252 in FIG. 10) is referred to as lead 12b. The configuration of the leads 12 is not particularly limited. In this embodiment, the configuration of the lead 12 is the same as the configuration of the lead 11. A semiconductor chip 4b is joined to the lead 12a, and a semiconductor chip 4d is joined to the lead 12b.

[0029] Two leads 13 are arranged on the substrate 2, and in this embodiment, are arranged on the substrate main surface 21. Each lead 13 is joined to a respective joint 253 via a joint material 75. When distinguishing between the two leads 13, the one joined to one joint 253 (the right joint 253 in FIG. 10) is referred to as lead 13a, and the one joined to the other joint 253 (the left joint 253 in FIG. 10) is referred to as lead 13b. The configuration of the lead 13 is not particularly limited. In this embodiment, the configuration of the lead 13 is the same as the configuration of the lead 11. The semiconductor chip 4 is not joined to the lead 13.

[0030] The leads 14 are arranged on the substrate 2, and in this embodiment, are arranged on the substrate main surface 21. The leads 14 are bonded to the bonding portions 254 via bonding materials 75. The configuration of the leads 14 is not particularly limited. In this embodiment, the configuration of the leads 14 is the same as the configuration of the leads 11. The semiconductor chip 4 is not bonded to the leads 14.

[0031] The multiple leads 15 are arranged on the substrate 2, and in this embodiment, are arranged on the substrate main surface 21. Each lead 15 is bonded to a pad 32 of the conductive portion 3 via a conductive bonding material 76. The conductive bonding material 76 may be any material that can bond the lead 15 to the pad 32 and electrically connect the lead 15 to the pad 32. The conductive bonding material 76 may be, for example, silver paste, copper paste, solder, or the like. Each lead 15 has an overall strip-like shape.

[0032] There is no particular limitation on the configuration of the lead 15. In this embodiment, the lead 15 will be described by dividing it into a joint portion 151, a protruding portion 152, an inclined connection portion 153, and a parallel connection portion 154, as shown in FIG.

[0033] The bonding portion 151 has a principal surface 151a and a rear surface 151b. The principal surface 151a and the rear surface 151b are surfaces facing opposite each other in the z direction and are both flat surfaces perpendicular to the z direction. The principal surface 151a faces upward in FIG. 5. The rear surface 151b faces downward in FIG. 5. The rear surface 151b is bonded to the pad 32 by a conductive bonding material 76. The inclined connection portion 153 and the parallel connection portion 154 are covered with the sealing resin 8. The inclined connection portion 153 is connected to the bonding portion 151 and the parallel connection portion 154 and is inclined relative to the bonding portion 151 and the parallel connection portion 154. The parallel connection portion 154 is connected to the inclined connection portion 153 and the protruding portion 152 and is parallel to the bonding portion 151. The protruding portion 152 is connected to an end of the parallel connection portion 154 and is the portion of the lead 15 that protrudes from the sealing resin 8. The protruding portion 152 protrudes in the y direction opposite to the joining portion 151. The protruding portion 152 is used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protruding portion 152 is bent in the z direction toward the side toward which the main surface 151 a of the joining portion 151 faces.

[0034] 3 and 6 to 9, the multiple leads 15 include leads 15a, 15b, 15c, and 15d. The leads 15a, 15b, 15c, and 15d are each bonded to two pads 32 that are spaced apart from each other. The leads 15a, 15b, 15c, and 15d are an example of a "first lead."

[0035] As shown in FIG. 6, lead 15a is bonded to both pad 32a and pad 32b. Pad 32a and pad 32b are examples of a "first pad" and a "second pad." Bonding portion 151 of lead 15a has a wide portion 151c located at the end opposite to protruding portion 152. The wide portion 151c is more than twice as wide as the other portions. Pads 32a and 32b are arranged side by side in the x direction at the end on one side in the y direction (the upper side in FIG. 6) of substrate main surface 21, and are bonded to wide portion 151c of lead 15a. Pad 32a is electrically connected to lead 53 (described below), which is an analog power supply terminal of control device 5d (described below), via connection wiring 33 and pad 31. Pad 32b is electrically connected to lead 53, which is an analog power supply terminal of control device 5c (described below), via connection wiring 33 and pad 31. That is, the lead 15a is electrically connected to the analog power supply terminals of the control device 5c and the control device 5d.

[0036] As shown in FIG. 8, lead 15c is bonded to both pad 32e and pad 32f. Pads 32e and 32f are examples of a "first pad" and a "second pad." As shown in FIG. 5, bonding portion 151 of lead 15c has a first end 151d on the protruding portion 152 side and a second end 151e on the opposite side of protruding portion 152. Pads 32e and 32f are aligned at an end on one side in the y direction (the upper side in FIG. 8) on substrate main surface 21, in a direction slightly inclined with respect to the y direction, and lead 15c's first end 151d and second end 151e are aligned in directions spaced apart from each other. Pad 32e is bonded to second end 151e, and pad 32f is bonded between first end 151d and second end 151e. Pad 32e is electrically connected to lead 53, which is an analog power supply terminal of control device 5a (described later), via connection wiring 33 and pad 31. Pad 32f is electrically connected to lead 53, which is an analog power supply terminal of control device 5b (described later), via connection wiring 33 and pad 31. In other words, lead 15c is electrically connected to the analog power supply terminals of control device 5a and control device 5b.

[0037] As shown in FIG. 7, lead 15b is bonded to both pad 32c and pad 32d. Pads 32c and 32d are examples of a "first pad" and a "second pad." Similar to bonded portion 151 of lead 15c, bonded portion 151 of lead 15b has a first end 151d on the protruding portion 152 side and a second end 151e on the opposite side from protruding portion 152. Pads 32c and 32d are aligned at an end on one side in the y direction (the upper side in FIG. 7) on substrate main surface 21, in a direction slightly inclined with respect to the x direction, and lead 15b's first end 151d and second end 151e are aligned in directions away from each other. Pad 32c is bonded to second end 151e, and pad 32d is bonded between first end 151d and second end 151e. Pad 32c is electrically connected to lead 53, which is the ground terminal of control device 5c, via connection wiring 33 and pad 31. Pad 32d is electrically connected to lead 53, which is the ground terminal of control device 5d, via connection wiring 33 and pad 31. In other words, lead 15b is electrically connected to the ground terminals of control device 5c and control device 5d.

[0038] As shown in FIG. 9, lead 15d is bonded to both pad 32g and pad 32h. Pads 32g and 32h are examples of a "first pad" and a "second pad." Similar to bonded portion 151 of lead 15c, bonded portion 151 of lead 15d has a first end 151d on the protruding portion 152 side and a second end 151e on the opposite side from protruding portion 152. Pads 32g and 32h are aligned in the y direction at an end on one side in the x direction (the right side in FIG. 9) on substrate main surface 21, and the first end 151d and the second end 151e of lead 15d are aligned in a direction away from each other. Pad 32g is bonded to second end 151e, and pad 32h is bonded between first end 151d and second end 151e. Pad 32g is electrically connected to lead 53, which is a ground terminal of control device 5b, via connection wiring 33 and pad 31. Pad 32h is electrically connected to lead 53, which is the ground terminal of control device 5a, via connection wiring 33 and pad 31. In other words, lead 15d is electrically connected to the ground terminals of control device 5a and control device 5b.

[0039] The shape of the bonding portion 151 of each lead 15 is designed appropriately depending on the arrangement of the pad 32 to be bonded. The shape of the bonding portion 151 of the leads 15a, 15b, 15c, and 15d is designed appropriately depending on the arrangement of each of the two pads 32 to be bonded.

[0040] Each of the four semiconductor chips 4 is disposed on one of the leads 1. When the four semiconductor chips 4 are to be distinguished, they are referred to as semiconductor chip 4a, semiconductor chip 4b, semiconductor chip 4c, and semiconductor chip 4d, respectively. When they are not to be distinguished, they are simply referred to as semiconductor chip 4. The type and function of the semiconductor chip 4 are not particularly limited, and in this embodiment, the semiconductor chip 4 is described as a power transistor that controls power. The semiconductor chip 4 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET) made of a silicon carbide (SiC) substrate. The semiconductor chip 4 may be a MOSFET made of a silicon (Si) substrate instead of a SiC substrate, and may include, for example, an IGBT element. The semiconductor chip 4 may also be a MOSFET containing gallium nitride (GaN). While this embodiment illustrates a case in which the semiconductor device A1 includes four semiconductor chips 4, this is merely an example, and the number of semiconductor chips 4 is not limited.

[0041] The semiconductor chip 4 has a rectangular plate shape when viewed in the z direction, and includes a main surface 41, a back surface 42, a source electrode 43, a gate electrode 44, and a drain electrode 45. The main surface 41 and the back surface 42 face opposite each other in the z direction. The main surface 41 faces upward in FIG. 5. The back surface 42 faces downward in FIG. 5. As shown in FIG. 3, the source electrode 43 and the gate electrode 44 are arranged on the main surface 41. Furthermore, the drain electrode 45 is arranged on the back surface 42. The shapes and arrangements of the source electrode 43, the gate electrode 44, and the drain electrode 45 are not limited.

[0042] As shown in FIGS. 3 and 5, the semiconductor chip 4a is disposed on the lead 11a. As shown in FIG. 5, the semiconductor chip 4a is bonded to the lead 11a with a conductive adhesive (not shown) with the back surface 42 of the element facing the lead 11a. As a result, the drain electrode 45 of the semiconductor chip 4a is electrically connected to the lead 11a with the conductive adhesive. Examples of the conductive adhesive include silver paste, copper paste, and solder. As shown in FIG. 3, the source electrode 43 of the semiconductor chip 4a is electrically connected to the lead 12a with a wire 71. The wire 71 is made of, for example, aluminum (Al) or copper (Cu). Note that the material, diameter, and number of the wire 71 are not limited. As shown in FIG. 3, the semiconductor chip 4b is disposed on the lead 12a. The semiconductor chip 4b is bonded to the lead 12a with a conductive adhesive (not shown) with the back surface 42 of the element facing the lead 12a. As a result, the drain electrode 45 of the semiconductor chip 4b is electrically connected to the lead 12a by the conductive bonding material. Also, the source electrode 43 of the semiconductor chip 4b is electrically connected to the lead 14 by the wire 71. As a result, a bridge circuit is formed in which the source electrode 43 of the semiconductor chip 4a and the drain electrode 45 of the semiconductor chip 4b are connected.

[0043] As shown in FIG. 3, the source electrode 43 and gate electrode 44 of the semiconductor chip 4a are electrically connected to the control device 5a via wires 72 and conductive portions 3, respectively. The wires 72 are made of, for example, gold (Au), silver (Ag), copper (Cu), aluminum (Al), or the like. The material, diameter, and number of the wires 72 are not limited. The control device 5a inputs a drive signal to the gate electrode 44 of the semiconductor chip 4a. The source electrode 43 and gate electrode 44 of the semiconductor chip 4b are electrically connected to the control device 5b via the wires 72 and conductive portions 3, respectively. The control device 5b inputs a drive signal to the gate electrode 44 of the semiconductor chip 4b. A DC voltage is applied between the leads 11a and 14, and a drive signal is input to the gate electrodes 44 of the semiconductor chips 4a and 4b. A switching signal, whose voltage changes in response to the drive signal, is output from the lead 12a.

[0044] As shown in FIG. 3, the semiconductor chip 4c is disposed on the lead 11b. The semiconductor chip 4c is bonded to the lead 11b with a conductive bonding material (not shown) with the back surface 42 of the semiconductor chip 4c facing the lead 11b. As a result, the drain electrode 45 of the semiconductor chip 4c is electrically connected to the lead 11b with the conductive bonding material. The source electrode 43 of the semiconductor chip 4c is electrically connected to the lead 12b with a wire 71. The semiconductor chip 4d is disposed on the lead 12b with the back surface 42 of the semiconductor chip 4d facing the lead 12b with a conductive bonding material (not shown). As a result, the drain electrode 45 of the semiconductor chip 4d is electrically connected to the lead 12b with the conductive bonding material. The source electrode 43 of the semiconductor chip 4d is electrically connected to the lead 14 with the wire 71. As a result, a bridge circuit is formed in which the source electrode 43 of the semiconductor chip 4c and the drain electrode 45 of the semiconductor chip 4d are connected.

[0045] The source electrode 43 and the gate electrode 44 of the semiconductor chip 4c are each electrically connected to the control device 5c via the wire 72 and the conductive portion 3. The control device 5c inputs a drive signal to the gate electrode 44 of the semiconductor chip 4c. The source electrode 43 and the gate electrode 44 of the semiconductor chip 4d are each electrically connected to the control device 5d via the wire 72 and the conductive portion 3. The control device 5d inputs a drive signal to the gate electrode 44 of the semiconductor chip 4d. A DC voltage is applied between the lead 11b and the lead 14, and a drive signal is input to the gate electrodes 44 of the semiconductor chips 4c and 4d, whereby a switching signal whose voltage changes in response to the drive signal is output from the lead 12b.

[0046] The four control devices 5 each control the operation of a semiconductor chip 4 and are arranged on the main surface 21 of the substrate 2. When the four control devices 5 are to be distinguished from one another, they are referred to as control device 5a, control device 5b, control device 5c, and control device 5d, respectively. When they are not to be distinguished from one another, they are simply referred to as control devices 5. Control device 5a controls the operation of semiconductor chip 4a. Control device 5b controls the operation of semiconductor chip 4b. Control device 5c controls the operation of semiconductor chip 4c. Control device 5d controls the operation of semiconductor chip 4d. As shown in FIG. 5, the control devices 5 are located between the semiconductor chip 4 and the leads 15 when viewed in the x direction. Also, as shown in FIG. 3, when viewed in the y direction, control device 5a overlaps with semiconductor chip 4a, control device 5b overlaps with semiconductor chip 4b, control device 5c overlaps with semiconductor chip 4c, and control device 5d overlaps with semiconductor chip 4d. The arrangement of the control devices 5a to 5d is not limited.

[0047] The control device 5 includes a control chip (not shown), a die pad, and multiple wires, as well as multiple leads 53 and resin 54. The control chip is an integrated circuit that controls the operation of the semiconductor chip 4 and outputs a drive signal to drive the semiconductor chip 4. The die pad and multiple leads 53 are plate-shaped members made of, for example, copper (Cu). The control chip is mounted on the die pad. Each lead 53 is electrically connected to the control chip by a wire. Resin 54 covers the entire control chip and wires and parts of each lead 53, and is made of an insulating material such as epoxy resin or silicone gel.

[0048] As shown in FIGS. 6 to 9 , the leads 53 are arranged at intervals in the x direction on both ends of the resin 54 in the y direction. Each lead 53 extends along the y direction, with a portion of each lead protruding from both side surfaces of the resin 54 in the y direction. The portion of each lead 53 protruding from the resin 54 is conductively joined to a pad 31 of the conductive portion 3. In this embodiment, the control device 5 is a small outline package (SOP) type package. Note that the package type of the control device 5 is not limited to the SOP type and may be other types of packages such as a quad flat package (QFP) type or a small outline J-lead package (SOJ) type. Each lead 53 is joined to the pad 31 of the conductive portion 3 via a conductive bonding material 76.

[0049] There are no limitations on the size, shape, number of leads, etc. of the control device 5. The control device 5 may also include multiple control chips, or may include a circuit chip other than the control chip.

[0050] In this embodiment, some of the connection wiring 33 overlaps the control device 5 when viewed in the z direction, and is disposed between the substrate main surface 21 of the substrate 2 and the opposing surface of the control device 5. The control chip of the control device 5 is covered with resin 54, which prevents the control chip from coming into contact with the connection wiring 33. If the control chip is disposed directly on the substrate 2 instead of the control device 5, arranging the connection wiring 33 so as to overlap the control device 5 will cause the control chip to come into contact with the connection wiring 33, and therefore the connection wiring 33 must be arranged in a detour.

[0051] A plurality of passive elements 6 are arranged on the main surface 21 of the substrate 2 and are conductively connected to the conductive portions 3 or the leads 1. The passive elements 6 are, for example, resistors, capacitors, coils, diodes, etc. The passive elements 6 include a shunt resistor 6a.

[0052] The shunt resistor 6a is disposed across the lead 12 and the lead 13, and is conductively joined to the lead 12 and the lead 13. The shunt resistor 6a outputs from the lead 13 a current diverted from the current flowing through the lead 12.

[0053] The other passive elements 6 are conductively joined to pads 31 of the conductive portion 3, and are electrically connected to the control device 5 via the connection wiring 33 and pads 31, or to the leads 15 via the connection wiring 33 and pads 32. The type, arrangement position, and number of each passive element 6 are not limited.

[0054] The sealing resin 8 covers at least the four semiconductor chips 4, the four control devices 5, the plurality of passive elements 6, and the entire wires 71 and 72, as well as a portion of each of the plurality of leads 1 and a portion of the substrate 2. The material of the sealing resin 8 is not particularly limited, and an insulating material such as epoxy resin or silicone gel can be used as appropriate.

[0055] The sealing resin 8 has a resin main surface 81, a resin back surface 82, and four resin side surfaces 83. The resin main surface 81 and the resin back surface 82 are surfaces facing opposite each other in the z direction and are both flat surfaces perpendicular to the z direction. The resin main surface 81 is a surface facing upward in FIG. 5. The resin back surface 82 is a surface facing downward in FIG. 5. Each resin side surface 83 is connected to the resin main surface 81 and the resin back surface 82, respectively, and faces in the x direction or y direction. As shown in FIG. 4, the substrate back surface 22 of the substrate 2 is exposed from the resin back surface 82 of the sealing resin 8. In this embodiment, as shown in FIG. 5, the substrate back surface 22 and the resin back surface 82 are flush with each other.

[0056] Next, an example of a method for manufacturing the semiconductor device A1 will be described below with reference to Fig. 11. Note that the manufacturing method described below is one means for realizing the semiconductor device A1, and is not limited to this.

[0057] As shown in FIG. 11, the manufacturing method of this example includes a conductive portion forming process (step S1), a lead frame bonding process (step S2), a semiconductor chip mounting process (step S3), a control device mounting process (step S4), a wire connecting process (step S5), a resin forming process (step S6), and a frame cutting process (step S7).

[0058] In the conductive portion forming step (step S1), first, a substrate 2 is prepared. The substrate 2 is made of, for example, ceramic. Next, a conductive portion 3 and a plurality of joints 25 are formed on a substrate main surface 21 of the substrate 2. In this example, the conductive portion 3 and the plurality of joints 25 are formed all at once. For example, a metal paste is printed and then fired to obtain the conductive portion 3 and the plurality of joints 25 containing a metal such as silver (Ag) as a conductive material.

[0059] In the lead frame bonding process (step S2), first, a bonding paste is printed on the multiple bonding portions 25, and a conductive bonding paste is printed on the multiple pads 32 of the conductive portion 3. The bonding paste and the conductive bonding paste are, for example, Ag paste or solder paste. Next, a lead frame is prepared. The lead frame includes multiple leads 1 and further has a frame to which the multiple leads 1 are connected. Note that the shape of the lead frame is not limited in any way. Next, leads 11, 12, 13, and 14 of the multiple leads 1 are made to face the multiple bonding portions 25 via the bonding paste. Furthermore, multiple leads 15 of the multiple leads 1 are made to face the conductive portion 3 (multiple pads 32) via the conductive bonding paste. For example, by heating and then cooling the bonding paste and the conductive bonding paste, a bonding material 75 is formed from the bonding paste, and a conductive bonding material 76 is formed from the conductive bonding paste. As a result, the leads 11, 12, 13, and 14 are bonded to the multiple bonding portions 25 via the bonding material 75, and the multiple leads 15 are bonded to the conductive portion 3 via the conductive bonding material 76.

[0060] In the semiconductor chip mounting process (step S3), first, a conductive adhesive paste is printed on predetermined positions of the leads 11a and 11b and the leads 12a and 12b. The conductive adhesive paste is, for example, an Ag paste or a solder paste. Next, the semiconductor chip 4a is attached to the conductive adhesive paste printed on the lead 11a, the semiconductor chip 4b is attached to the conductive adhesive paste printed on the lead 12a, the semiconductor chip 4c is attached to the conductive adhesive paste printed on the lead 11b, and the semiconductor chip 4d is attached to the conductive adhesive paste printed on the lead 12b. Then, for example, the conductive adhesive paste is heated and then cooled, thereby forming a conductive adhesive material from the conductive adhesive paste. As a result, the semiconductor chip 4a is bonded to the lead 11a via the conductive adhesive material, the semiconductor chip 4b is bonded to the lead 12a via the conductive adhesive material, the semiconductor chip 4c is bonded to the lead 11b via the conductive adhesive material, and the semiconductor chip 4d is bonded to the lead 12b via the conductive adhesive material. Furthermore, by a similar process, the shunt resistor 6a is bonded to the leads 12a and 13a, and to the leads 12b and 13b via a conductive bonding material.

[0061] In the control device mounting process (step S4), a conductive bonding paste is printed on the pads 31 of the conductive section 3. The conductive bonding paste is, for example, Ag paste or solder paste. Next, each lead 53 of the control devices 5a to 5d is attached to the conductive bonding paste. Next, for example, the conductive bonding paste is heated and then cooled, thereby bonding each lead 53 of the control devices 5a to 5d to the pads 31 via a conductive bonding material. Furthermore, by a similar process, other passive elements 6 are bonded to the pads 31 of the conductive section 3 via a conductive bonding material.

[0062] In the wire connection step (step S5), first, a plurality of wires 71 are connected. In this example, wire materials made of aluminum (Al) are connected in sequence, for example, by wedge bonding. This results in a plurality of wires 71. Next, a plurality of wires 72 are connected. In this example, wire materials made of gold (Au) are connected in sequence, for example, by capillary bonding. This results in a plurality of wires 72.

[0063] In the resin forming step (step S6), for example, a part of the lead frame, a part of the substrate 2, the semiconductor chips 4a-4d, the control devices 5a-5d, the passive elements 6, and the wires 71 and 72 are enclosed in a mold. Next, a liquid resin material is poured into the space defined by the mold. Next, the resin material is cured to obtain the sealing resin 8.

[0064] In the frame cutting process (step S7), the lead frame is cut at appropriate locations of the portions exposed from the sealing resin 8. This separates the leads 1 from one another. Thereafter, the leads 1 are subjected to processes such as bending as necessary to obtain the semiconductor device A1 described above.

[0065] Next, the effects of the semiconductor device A1 will be described.

[0066] According to this embodiment, a conductive portion 3 is formed on the substrate main surface 21 of the substrate 2. The control device 5 is conductively connected to the pad 31 of the conductive portion 3. This allows the conductive path to be formed by the conductive portion 3 formed on the substrate main surface 21. Therefore, compared to when the conductive path is formed using, for example, a metal lead, the conductive path can be made thinner and denser. Furthermore, the lead 15a is connected to both the pad 32a and the pad 32b via the conductive bonding material 76. This allows noise input to the pad 32a, for example, from the control device 5d via the connection wiring 33, to be emitted to the outside from the lead 15a. This prevents the noise from being input to the control device 5c via the pad 32b and the connection wiring 33 connected thereto. This reduces the effects of noise compared to when the lead 15 is connected to a single pad 32 that serves as both the pad 32a and the pad 32b. The same applies to pads 32c and 32d bonded to lead 15b, pads 32e and 32f bonded to lead 15c, and pads 32g and 32h bonded to lead 15d.

[0067] 12 is a schematic diagram illustrating the relationship between the connection state between pad 32 and lead 15 and the state of noise transmission. The direction of the arrow in the figure indicates the direction of noise transmission, and the thickness of the arrow indicates the magnitude of the transmitted noise.

[0068] 1A shows a state in which two connection wires 33 are connected to one pad 32, and the pad 32 is connected to a lead 15 via a conductive bonding material 76. As shown in the figure, noise input to the pad 32 via one of the connection wires 33 is released to the outside via the conductive bonding material 76 and the lead 15. However, since the noise is blocked by the resistance component of the conductive bonding material 76, it also flows to the other connection wire 33 and is input to the electronic component to which the connection wire 33 is connected.

[0069] 1(b) shows a state in which pads 32a and 32b, each connected to a connection wire 33, are each connected to lead 15a via conductive bonding material 76. As shown in the figure, noise input to pad 32a via one connection wire 33 is released to the outside via conductive bonding material 76 and lead 15a. Some of the noise also flows to pad 32b via conductive bonding material 76, but this is blocked by the resistance component of conductive bonding material 76, so that the noise is prevented from being transmitted via pad 32b and the connection wire 33 connected thereto.

[0070] As described above, the connection state shown in FIG. 1(b) can suppress the noise generated by an electronic component from flowing to other electronic components that are connected to the same lead 15 as the electronic component, compared to the connection state shown in FIG. 1(a), thereby suppressing the effects of noise.

[0071] Furthermore, according to this embodiment, the bonding portion 151 of the lead 15a includes a wide portion 151c located at the end opposite to the protruding portion 152. The wide portion 151c is suitable for bonding to the pads 32a and 32b arranged side by side in the x direction perpendicular to the direction in which the lead 15a extends (the y direction) at the end of the y direction of the substrate main surface 21. The bonding portion 151 of the lead 15b extends in a strip shape. This bonding portion 151 is suitable for bonding to the pads 32c and 32d arranged surrounded by other pads 32, 31, and connection wiring 33. The same applies to the lead 15c. The bonding portion 151 of the lead 15d also extends in a strip shape. This bonding portion 151 is suitable for bonding to the pads 32g and 32h arranged side by side in the y direction at the end of the x direction of the substrate main surface 21.

[0072] Furthermore, in this embodiment, some of the connection wiring 33 of the conductive portion 3 is arranged to overlap the control device 5 when viewed in the z direction. Therefore, compared to when the conductive path is arranged to detour so as not to overlap the control device 5, the conductive path can be shortened and the degree of freedom in designing the conductive path is increased. This can promote high integration of the semiconductor device A1.

[0073] Furthermore, according to this embodiment, the leads 1 have a higher thermal conductivity than the substrate 2, thereby suppressing the reduction in heat dissipation from the semiconductor chip 4, which may be caused by the use of the substrate 2. Each semiconductor chip 4 is directly bonded to the lead 11 or 12 with a conductive adhesive. This allows electrical continuity between the semiconductor chip 4 and the lead 11 (12), and allows heat from the semiconductor chip 4 to be more efficiently transferred to the lead 11 (12). Furthermore, the leads 1 are exposed from the encapsulation resin 8, providing a conductive path from the outside to the semiconductor chip 4 and further enhancing the heat dissipation characteristics of the semiconductor chip 4. Furthermore, a bonding portion 25 is formed on the substrate 2, and the leads 11 to 14 are bonded to the substrate 2 via the bonding portion 25. For example, the surface of the bonding portion 25 can be made smoother than the surface roughness of the main surface 21 of the substrate 2, which is made of ceramic. This prevents unintended microvoids from forming in the heat transfer path from the leads 11 to 14 to the substrate 2, thereby further promoting heat dissipation from the semiconductor chip 4. Furthermore, the rear surface 22 of the substrate 2 is exposed from the sealing resin 8. This allows the heat transferred from the semiconductor chip 4 and the like to the substrate 2 to be more efficiently dissipated to the outside.

[0074] Furthermore, in this embodiment, the conductive portion 3 and the bonding portion 25 contain the same conductive material, which allows the conductive portion 3 and the bonding portion 25 to be formed collectively on the substrate 2. This is preferable for improving the manufacturing efficiency of the semiconductor device A1. Furthermore, the multiple leads 15 are bonded to the pads 32 of the conductive portion 3 via the conductive bonding material 76. This allows the multiple leads 15 to be more firmly fixed to the substrate 2.

[0075] Although the present embodiment has been described with reference to a case where the substrate 2 is not a laminated substrate, the substrate 2 may be a multi-layer substrate such as a PCB. In this case, the conductive portion 3 can be arranged in multiple layers, allowing for more complex wiring and increasing the degree of freedom in wiring design.

[0076] Furthermore, in this embodiment, a case has been described in which multiple pads 32 electrically connected to the analog power supply terminal or the ground terminal of the control device 5 are joined to the same lead 15, but this is not limiting. For example, multiple pads 32 electrically connected to the digital power supply terminal of the control device 5 may be joined to the same lead 15, or multiple pads 32 electrically connected to the signal terminal of the control device 5 may be joined to the same lead 15.

[0077] Although the present embodiment has been described with reference to a case where the pads 32a and 32b are not connected within the conductive portion 3, this is not limiting. As shown in FIG. 13 , the pads 32a and 32b may be connected by a connection portion 34. The connection portion 34 is included in the conductive portion 3 and is made of a conductive material. The connection portion 34 is disposed between the pads 32a and 32b, with one end in the x direction connected to the pad 32a and the other end connected to the pad 32b. The dimension of the connection portion 34 in the y direction is sufficiently smaller than the dimensions of the pads 32a and 32b in the y direction. Therefore, the impedance of the connection portion 34 for high-frequency components is sufficiently higher than that of the conduction path between the pads 32a and 32b via the conductive bonding material 76 and the lead 15a. This suppresses noise transmission between the pads 32a and 32b via the connection portion 34. According to this modified example, even if either pad 32a or pad 32b cannot be joined to lead 15a, pad 32a and pad 32b are connected by connection portion 34, and electrical continuity is ensured, thereby preventing open defects.

[0078] The shape of the connection portion 34 is not limited to that shown in FIG. 13 . The connection portion 34 may be shaped to provide a circuitous path, as shown in FIG. 14 , rather than connecting the pads 32a and 32b via the shortest distance. The connection portion 34 according to this modification is U-shaped, with one side open in the y direction (the upper side in FIG. 14 ), and is disposed on the other side in the y direction (the lower side in FIG. 14 ) of the pads 32a and 32b. One end of the connection portion 34 is connected to the pad 32a, and the other end is connected to the pad 32b. The connection portion 34 includes a portion that does not overlap the lead 15a when viewed in the z direction. This modification can further increase the impedance of the connection portion 34 with respect to high-frequency components. Furthermore, when the lead 15a is bonded, the liquefied conductive bonding material 76 is prevented from flowing down the connection portion 34 and connecting the pads 32a and 32b. The shape of the connection portion 34 may be more complex (e.g., zigzag). In addition, when two pads 32 are sufficiently far apart, such as between pads 32c and 32d (see Figure 7), between pads 32e and 32f (see Figure 8), and between pads 32g and 32h (see Figure 9), there is no need to detour the path of the connection portion 34 or make it have a complex shape, as in this modified example.

[0079] 15 to 18 show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals as those in the above embodiment.

[0080] Second Embodiment Fig. 15 is a diagram illustrating a semiconductor device A2 according to a second embodiment of the present disclosure. Fig. 15 is a partially enlarged plan view showing the semiconductor device A2, and corresponds to Figs. 6 to 9. Note that the sealing resin 8 is omitted in Fig. 15. The semiconductor device A2 of this embodiment differs from the first embodiment in the arrangement positions of the pads 32b and the shape of the leads 15a.

[0081] In the semiconductor device A2 according to this embodiment, pad 32b is positioned away from pad 32a in the x direction and is on the opposite side of pad 32a in the x direction with respect to control device 5d. Furthermore, instead of wide portion 151c, bonding portion 151 of lead 15a includes first branched end 151f and second branched end 151g that branch off on the side opposite protruding portion 152. Pad 32a is bonded to first branched end 151f, and pad 32b is bonded to second branched end 151g.

[0082] In this embodiment, too, conductive portion 3 is formed on substrate main surface 21 of substrate 2, and control device 5 is conductively joined to pad 31 of conductive portion 3. This allows the conductive path to control device 5 to be formed by conductive portion 3 formed on substrate main surface 21, making it possible to achieve a thinner and denser conductive path. Furthermore, lead 15a is joined to both pad 32a and pad 32b via conductive bonding material 76, respectively. This suppresses noise transmission between pad 32a and pad 32b via conductive bonding material 76 and lead 15a.

[0083] Furthermore, in this embodiment, the bonding portion 151 of the lead 15a has a first branched end 151f and a second branched end 151g branched on the side opposite to the protruding portion 152, and the pad 32a is bonded to the first branched end 151f, and the pad 32b is bonded to the second branched end 151g. The bonding portion 151 is suitable for bonding to the pads 32a and 32b that are arranged apart from each other.

[0084] <Third embodiment> FIG. 16 is a diagram illustrating a semiconductor device A3 according to a third embodiment of the present disclosure. FIG. 16 is a simplified plan view showing the semiconductor device A3. In FIG. 16, only components necessary for explaining the semiconductor device A3 are shown, and other components are omitted. The shape and arrangement of each of the components shown are also simplified. The semiconductor device A3 of this embodiment differs from the first embodiment in that the leads 15 are bonded to four pads 32.

[0085] In the semiconductor device A1 according to the first embodiment, the lead 15a is bonded to the pad 32a electrically connected to the control device 5d and the pad 32b electrically connected to the control device 5c, and the lead 15c is bonded to the pad 32e electrically connected to the control device 5a and the pad 32f electrically connected to the control device 5b. In other words, two of the four control devices 5 are connected to the leads 15. In contrast, in the semiconductor device A3 according to the third embodiment, the lead 15a is bonded to four pads 32, namely, the pads 32a, 32b, 32e, and 32f. In other words, the four control devices 5 are connected to one lead 15a. In this embodiment, the pad 32c or the pad 32d is an example of a "third pad." The positions of the pads 32a, 32b, 32e, and 32f and the shapes of the connection wiring 33 connected to the pads 32a, 32b, 32e, and 32f are not limited and may be appropriately designed in accordance with the positions and shapes of the other pads 32, pads 31, and connection wiring 33. Furthermore, the shape of the leads 15a is not limited, and is designed to correspond to the arrangement of the pads 32a, 32b, 32e, and 32f. The substrate 2 may be a multilayer substrate, and some of the connection wiring 33 may be arranged on a layer other than the main surface 21 of the substrate.

[0086] In this embodiment, too, a conductive portion 3 is formed on the substrate main surface 21 of the substrate 2, and the control device 5 is conductively joined to the pad 31 of the conductive portion 3. This allows the conductive path to the control device 5 to be formed by the conductive portion 3 formed on the substrate main surface 21, making it possible to thin and densely arrange the conductive path. Furthermore, the lead 15a is joined to four pads 32, namely, pads 32a, 32b, 32e, and 32f, via conductive bonding materials 76, respectively. This suppresses noise transmission between the pads 32a, 32b, 32c, and 32d via the conductive bonding materials 76 and the lead 15a.

[0087] Although the first embodiment describes a case where one lead 15 is bonded to two pads 32, and the third embodiment describes a case where one lead 15 is bonded to four pads 32, the present invention is not limited to this. Each lead 15 may be bonded to three pads 32, or may be bonded to five or more pads 32.

[0088] <Fourth embodiment> FIG. 17 is a diagram illustrating a semiconductor device A4 according to a fourth embodiment of the present disclosure. FIG. 17 is a simplified plan view showing the semiconductor device A4. In FIG. 17, only components necessary for explaining the semiconductor device A4 are shown, and other components are omitted. The shape and arrangement of each of the components shown are also simplified. The semiconductor device A4 of this embodiment differs from the first embodiment in that the lead 15 is bonded to two pads 32 that are each electrically connected to different leads 53 of the same control device 5.

[0089] In the semiconductor device A1 according to the first embodiment, the lead 15a is bonded to the pad 32a electrically connected to the control device 5d and the pad 32b electrically connected to the control device 5c. That is, the lead 15a is connected to two control devices 5. On the other hand, in the semiconductor device A4 according to the fourth embodiment, the lead 15a is bonded to the pads 32a and 32b, which are electrically connected to different leads 53 of the control device 5d. That is, the lead 15a is connected to different leads 53 of the same control device 5. The pad 32a is electrically connected to the lead 53a, which is the analog power supply terminal of the control device 5d, via the connection wiring 33 and the pad 31. The pad 32b is electrically connected to the lead 53b, which is the digital power supply terminal of the control device 5d, via the connection wiring 33 and the pad 31. That is, the lead 15a is electrically connected to the analog power supply terminal and the digital power supply terminal of the control device 5d. The positions of the pads 32a and 32b and the shape of the connection wiring 33 connected to the pads 32a and 32b are not limited, and are designed appropriately in accordance with the positions and shapes of the other pads 32, pads 31, and connection wiring 33. The shape of the lead 15a is also not limited, and is designed in accordance with the positions of the pads 32a and 32b. The substrate 2 may be a multilayer substrate, and some of the connection wiring 33 may be arranged on a layer other than the main surface 21 of the substrate.

[0090] In this embodiment, too, conductive portion 3 is formed on substrate main surface 21 of substrate 2, and control device 5 is conductively joined to pad 31 of conductive portion 3. This allows the conductive path to control device 5 to be formed by conductive portion 3 formed on substrate main surface 21, making it possible to achieve a thinner and denser conductive path. Furthermore, lead 15a is joined to both pad 32a and pad 32b via conductive bonding material 76, respectively. This suppresses noise transmission between pad 32a and pad 32b via conductive bonding material 76 and lead 15a.

[0091] In the present embodiment, the case has been described in which the pad 32a is electrically connected to the lead 53a, which is an analog power supply terminal, and the pad 32b is electrically connected to the lead 53b, which is a digital power supply terminal, but this is not limiting. The pads 32a and 32b may also be electrically connected to the lead 53, which is another terminal. For example, the pad 32a may be electrically connected to the lead 53, which is an analog ground terminal, and the pad 32b may be electrically connected to the lead 53, which is a digital ground terminal.

[0092] Fifth Embodiment FIG. 18 is a diagram illustrating a semiconductor device A5 according to a fifth embodiment of the present disclosure. FIG. 18 is a simplified plan view showing the semiconductor device A5. In FIG. 18, only components necessary for explaining the semiconductor device A5 are shown, and other components are omitted. The shape and arrangement of each of the components shown are also simplified. The semiconductor device A5 of this embodiment differs from the first embodiment in that one of two pads 32 to which leads 15 are bonded is electrically connected to the other lead 15.

[0093] In the semiconductor device A1 according to the first embodiment, the lead 15a is bonded to the pad 32a electrically connected to the control device 5d and the pad 32b electrically connected to the control device 5c. That is, the lead 15a is connected to two control devices 5. On the other hand, in the semiconductor device A5 according to the fifth embodiment, the pad 32b is electrically connected to the lead 15e, not to the control device 5. That is, the lead 15a is connected to the control device 5d and the lead 15e. The pad 32a is electrically connected to the lead 53a, which is an analog power supply terminal of the control device 5d, via the connection wiring 33 and the pad 31. The pad 32b is electrically connected to the lead 15e via the connection wiring 33 and the pad 32i. The pad 32i is one of the multiple pads 32 and is arranged adjacent to the pad 32b. The lead 15e is one of the multiple leads 15 and is bonded to the pad 32i via the conductive bonding material 76. That is, the lead 15a is electrically connected to the control device 5d and the lead 15e. In this embodiment, lead 15e is an example of a "second lead," and pad 32b is an example of a "first pad." Lead 15e is connected to, for example, a capacitor outside of semiconductor device A5. Control device 5d of semiconductor device A5 does not have a function for detecting the voltage of the analog power supply, and therefore cannot detect the voltage of the analog power supply input from lead 15a inside semiconductor device A5. However, by detecting the voltage between the terminals of a capacitor connected to lead 15e, which is conductive to lead 15a, the voltage of the analog power supply can be detected outside of semiconductor device A5.

[0094] In this embodiment, too, conductive portion 3 is formed on substrate main surface 21 of substrate 2, and control device 5 is conductively joined to pad 31 of conductive portion 3. This allows the conductive path to control device 5 to be formed by conductive portion 3 formed on substrate main surface 21, making it possible to achieve a thinner and denser conductive path. Furthermore, lead 15a is joined to both pad 32a and pad 32b via conductive bonding material 76, respectively. This suppresses noise transmission between pad 32a and pad 32b via conductive bonding material 76 and lead 15a.

[0095] In the present embodiment, the case where pad 32a is electrically connected to control device 5d and pad 32b is electrically connected to pad 32i joined to lead 15e has been described, but this is not limiting. Any of the pads 32 joined to lead 15 may be electrically connected only to passive element 6 via connection wiring 33 and pad 31, or may be electrically connected via connection wiring 33 to pad 31 to which one end of a wire is joined.

[0096] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways.

[0097] Appendix 1. a substrate having a substrate main surface and a substrate back surface facing opposite directions in a thickness direction; a conductive portion formed on the main surface of the substrate; a semiconductor chip disposed on the main surface of the substrate; a control device disposed on the main surface of the substrate and controlling the semiconductor chip; a sealing resin that covers at least a portion of the substrate, the semiconductor chip, the control device, and the conductive portion; A conductive bonding material; a first lead joined to the conductive portion via the conductive bonding material and having a portion exposed from the sealing resin; Equipped with the conductive portion includes a first pad and a second pad spaced apart from each other; The first lead is bonded to the first pad and the second pad. Appendix 2. the conductive portion further includes a connection portion connected to the first pad and the second pad; 2. The semiconductor device according to claim 1, wherein the connection portion includes a portion having a smaller dimension in a direction perpendicular to the thickness direction than the first pad and the second pad. Appendix 3. 3. The semiconductor device according to claim 2, wherein the connection portion has a higher impedance than a conductive path between the first pad and the second pad via the conductive bonding material and the first lead. Appendix 4. 4. The semiconductor device according to claim 2, wherein the connection portion includes a portion that does not overlap the first lead when viewed in the thickness direction. Appendix 5. the first lead is strip-shaped and includes a protruding portion that protrudes from the sealing resin and an interconnection portion that is interconnected to the conductive portion; the joint portion has a wide portion located at an end opposite to the protruding portion, 5. The semiconductor device according to claim 1, wherein the first pad and the second pad are joined to the wide portion. Appendix 6. the first lead is strip-shaped and includes a protruding portion that protrudes from the sealing resin and an interconnection portion that is interconnected to the conductive portion; the joint portion has a first end portion on the protruding portion side and a second end portion on the opposite side to the protruding portion, 5. The semiconductor device according to any one of claims 1 to 4, wherein the first pad and the second pad are arranged side by side in a direction in which the first end and the second end are spaced apart from each other. Appendix 7. the first lead is strip-shaped and includes a protruding portion that protrudes from the sealing resin and an interconnection portion that is interconnected to the conductive portion; the joint portion has a first branched end portion and a second branched end portion branched on the opposite side to the protruding portion, the first pad is joined to the first branch end, 5. The semiconductor device according to claim 1, wherein the second pad is joined to the second branch end portion. Appendix 8. 8. The semiconductor device according to claim 1, wherein the first pad and the second pad are electrically connected to the control device. Appendix 9. the first pad is electrically connected to an analog power supply terminal of the control device; 9. The semiconductor device according to claim 8, wherein the second pad is electrically connected to a digital power terminal of the control device. Appendix 10. a second lead joined to the conductive portion and partly exposed from the sealing resin; 8. The semiconductor device according to claim 1, wherein the first pad is electrically connected to the second lead. Appendix 11. a second semiconductor chip disposed on the substrate main surface; a second control device disposed on the main surface of the substrate and controlling the second semiconductor chip; Furthermore, the first pad is electrically connected to the control device; 8. The semiconductor device according to claim 1, wherein the second pad is electrically connected to the second control device. Appendix 12. the conductive portion further includes a third pad; 12. The semiconductor device according to claim 1, wherein the first lead is joined to the third pad. Appendix 13. a third lead disposed on the main surface of the substrate, the third lead having a higher thermal conductivity than the substrate, and a part of the third lead exposed from the sealing resin; 13. The semiconductor device according to any one of claims 1 to 12, wherein the semiconductor chip is disposed on the third lead. Appendix 14. a bonding portion formed on the main surface of the substrate and including a conductive material that constitutes the conductive portion; 14. The semiconductor device according to claim 13, wherein the third lead is joined to the joint portion. Appendix 15. 15. The semiconductor device according to any one of claims 1 to 14, wherein the semiconductor chip is a power transistor that controls power. Appendix 16. 16. The semiconductor device according to any one of claims 1 to 15, wherein the semiconductor chip has a back surface electrode joined to the first lead. Appendix 17. 17. The semiconductor device according to any one of claims 1 to 16, wherein the rear surface of the substrate is exposed from the sealing resin. Appendix 18. 18. The semiconductor device according to any one of claims 1 to 17, wherein the substrate is made of ceramic. [Explanation of symbols]

[0098] A1,A2,A3,A4,A5: Semiconductor device 1, 11, 11a, 11b, 12, 12a, 12b: Lead 13, 13a, 13b, 14, 15, 15a-15e: Lead 111: Joint part 111a: Main surface 111b: Back side 112: Projecting part 113: Inclined connection part 114: Parallel connection part 151: Joint part 151a: Main surface 151b: Back side 151c: Wide part 151d: First end 151e: Second end 151f: First branch end 151g: Second branch end 152: Protruding portion 153: Inclined connecting portion 154: Parallel connection part 2: Board 21: Main surface of substrate 22: Back surface of substrate 25, 251-254: Joint 3: Conductive part 31: Pad 32, 32a to 32i: Pad 33: Connection wiring 34: Connection part 4, 4a, 4b, 4c, 4d: Semiconductor chips 41: Element main surface 42: Element back surface 43: Source electrode 44: Gate electrode 45: Drain electrode 5, 5a, 5b, 5c, 5d: Control device 53, 53a, 53b: Lead 6: Passive element 6a: Shunt resistor 71, 72: Wire 75: Bonding material 76: Conductive bonding material 8: Sealing resin 81: Main surface of resin 82: Back surface of resin 83: Side surface of resin

Claims

1. a substrate having a substrate main surface and a substrate back surface facing opposite directions in a thickness direction; a conductive portion made of a conductive material formed on the main surface of the substrate; a semiconductor chip and a second semiconductor chip disposed on the main surface of the substrate; a control device disposed on the main surface of the substrate and controlling the semiconductor chip; a second control device disposed on the main surface of the substrate and controlling the second semiconductor chip; a sealing resin that covers at least a portion of the substrate, the semiconductor chip, the control device, and the conductive portion; A conductive bonding material; a first lead joined to the conductive portion via the conductive bonding material and having a portion exposed from the sealing resin; Equipped with the conductive portion includes a first pad and a second pad spaced apart from each other; the first lead is bonded to the first pad and the second pad; the first pad is electrically connected to the control device; the second pad is electrically connected to the second control device; Semiconductor device.

2. a substrate having a substrate main surface and a substrate back surface facing opposite directions in a thickness direction; a conductive portion made of a conductive material formed on the main surface of the substrate; a semiconductor chip disposed on the main surface of the substrate; a control device disposed on the main surface of the substrate and controlling the semiconductor chip; a sealing resin that covers at least a portion of the substrate, the semiconductor chip, the control device, and the conductive portion; A conductive bonding material; a first lead joined to the conductive portion via the conductive bonding material and having a portion exposed from the sealing resin; Equipped with the conductive portion includes a first pad and a second pad spaced apart from each other; the control device includes a first terminal and a second terminal; the first lead is bonded to the first pad and the second pad; the first pad and the second pad are electrically connected to the control device; the first pad is electrically connected to the first terminal; The second pad is electrically connected to the second terminal. Semiconductor device.

3. the first terminal is an analog power supply terminal, The semiconductor device according to claim 2 , wherein the second terminal is a digital power supply terminal.

4. a substrate having a substrate main surface and a substrate back surface facing opposite directions in a thickness direction; a conductive portion made of a conductive material formed on the main surface of the substrate; a semiconductor chip disposed on the main surface of the substrate; a control device disposed on the main surface of the substrate and controlling the semiconductor chip; a sealing resin that covers at least a portion of the substrate, the semiconductor chip, the control device, and the conductive portion; A conductive bonding material; a first lead joined to the conductive portion via the conductive bonding material and having a portion exposed from the sealing resin; a second lead joined to the conductive portion and partly exposed from the sealing resin; Equipped with the conductive portion includes a first pad and a second pad spaced apart from each other; the first lead is bonded to the first pad and the second pad; the first pad is electrically connected to the second lead; Semiconductor device.

5. the conductive portion further includes a connection portion connected to the first pad and the second pad; 5. The semiconductor device according to claim 1, wherein said connection portion includes a portion whose dimension in a direction perpendicular to said thickness direction is smaller than those of said first pad and said second pad.

6. 6. The semiconductor device according to claim 5, wherein the connection portion has a higher impedance than a conduction path between the first pad and the second pad via the conductive bonding material and the first lead.

7. The semiconductor device according to claim 5 , wherein the connection portion includes a portion that does not overlap the first lead when viewed in the thickness direction.

8. the first lead is strip-shaped and includes a protruding portion that protrudes from the sealing resin and an interconnection portion that is interconnected to the conductive portion; the joint portion has a wide portion located at an end opposite to the protruding portion, 8. The semiconductor device according to claim 1, wherein said first pad and said second pad are joined to said wide portion.

9. the first lead is strip-shaped and includes a protruding portion that protrudes from the sealing resin and an interconnection portion that is interconnected to the conductive portion; the joint portion has a first end portion on the protruding portion side and a second end portion on the opposite side to the protruding portion, 8. The semiconductor device according to claim 1, wherein the first pad and the second pad are arranged side by side in a direction in which the first end and the second end are spaced apart from each other.

10. the first lead is strip-shaped and includes a protruding portion that protrudes from the sealing resin and an interconnection portion that is interconnected to the conductive portion; the joint portion includes a first branched end portion and a second branched end portion that branch off from the protruding portion, the first pad is joined to the first branch end, 8. The semiconductor device according to claim 1, wherein said second pad is bonded to said second branch end portion.

11. the conductive portion further includes a third pad; 11. The semiconductor device according to claim 1, wherein said first lead is joined to said third pad.

12. a third lead disposed on the main surface of the substrate, the third lead having a higher thermal conductivity than the substrate, and a portion of the third lead exposed from the sealing resin; 12. The semiconductor device according to claim 1, wherein the semiconductor chip is disposed on the third lead.

13. a bonding portion formed on the main surface of the substrate and including a conductive material that constitutes the conductive portion; The semiconductor device according to claim 12 , wherein the third lead is joined to the joint portion.

14. 14. The semiconductor device according to claim 1, wherein the semiconductor chip is a power transistor for controlling power.

15. 15. The semiconductor device according to claim 1, wherein the semiconductor chip includes a back electrode joined to the first lead.

16. 16. The semiconductor device according to claim 1, wherein the rear surface of the substrate is exposed from the sealing resin.

17. 17. The semiconductor device according to claim 1, wherein said substrate is made of ceramic.

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