Data transfer technique for multiple devices on shared bus

Abstract

To improve memory controller efficiency and data transfer efficiency between different memories.SOLUTION: A method includes: receiving a first chip select signal that enables a first memory device connected to an SPI bus; actuating, in a first period, the first memory device according to a clock signal for the first memory device, based on the first chip select signal, and receiving a second chip select signal to enable a second memory device; actuating, in a second period after the first period, the first and second memory devices according to clock signals for the first and second memory devices, based on the first and second chip select signals; and receiving one or more commands, via the SPI bus, on the first and second memory devices, the commands including at least one address associated with read / write operation for data transfer via the SPI bus, according to the first and second chip select signals and the clock signals.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] [Cross Reference] This patent application claims priority to U.S. patent application Ser. No. 14 / 928,988, entitled "Data Transfer Technique for Multiple Devices on a Shared Bus," to Zhang et al., filed October 30, 2015, which is assigned to the assignee of the present application and is expressly incorporated herein by reference.

[0002] [Technical field] The following relates generally to data transfer between devices, and more particularly to data transfer techniques for multiple devices on a shared bus. [Background technology]

[0003] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states into the memory device. For example, a binary device has two states that represent a logic "1" or a logic "0". Other systems In some systems, more than two states may be stored. To access the stored information, the electronic device may read or detect the stored state of the memory device. To store information, the electronic device may write or program a state into the memory device.

[0004] There are many types of memory devices, including random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and others. Memory devices can be volatile or non-volatile. Non-volatile memory, such as flash memory, can store data for long periods of time without an external power source. Volatile memory devices, such as DRAM, can lose their stored state over time if not periodically refreshed by an external power source. Certain aspects of volatile memory may offer performance advantages, such as faster read or write speeds, while certain aspects of non-volatile memory may have advantages, such as the ability to store data without periodic refreshing. Summary of the Invention [Problem to be solved by the invention]

[0005] When transferring data between devices, a memory controller may read data from a source device to a data store within the memory controller, and then write the data from the data store within the memory controller to a target device. Furthermore, memory controllers often have different types of interfaces for different storage devices, such as volatile memory and non-volatile memory. Such designs may involve the memory controller in all of them to facilitate the transfer of data. Therefore, it would be beneficial to provide techniques that enable increased efficiency of memory controllers and increased efficiency of data transfer between different electronic devices. [Means for solving the problem]

[0006] A method according to one aspect of the present invention includes setting an address in a target memory for storing data received in the target memory, and sending a single command sequence to both a source memory and the target memory for storing the data from the source memory in the target memory based at least in part on setting the address in the target memory, the single command sequence directing a first operation in the source memory and a second operation in the target memory.

[0007] An apparatus according to one embodiment of the present invention comprises a target address register, a memory array, and an operation instruction decoder that decodes a received instruction as a command to store data available on a bus in the memory array, the data being stored in the memory array from an address indicated by the target address register, the received instruction including a read instruction for a second device and a source address in the second device for a read operation associated with the read instruction, and the received instruction instructs a write operation to be performed in the apparatus according to the address in the target address register simultaneously with the read operation in the second device. [Brief explanation of the drawings]

[0008] Embodiments of the present disclosure will be described with reference to the following figures. [Figure 1] FIG. 1 illustrates a block diagram of a device including a memory system that supports direct data transfer between data storage elements using a shared bus, according to various embodiments of the present disclosure. [Figure 2] FIG. 2 illustrates a block diagram of a memory system that supports direct data transfer between data storage elements using a shared bus, according to various embodiments of the present disclosure. [Figure 3]FIG. 3 illustrates a timing diagram for multiple data storage devices providing direct data transfer between devices using a shared bus, according to various embodiments of the present disclosure. [Figure 4] FIG. 4 illustrates a block diagram of an electronic system supporting direct data transfer between data storage elements using a shared bus, according to various embodiments of the present disclosure. [Figure 5] FIG. 5 is a flowchart illustrating a method for direct data transfer between data storage elements using a shared bus, according to various embodiments of the present disclosure. [Figure 6] FIG. 6 is a flow chart illustrating a second method for direct data transfer between data storage elements using a shared bus, according to various embodiments of the present disclosure. [Figure 7] FIG. 7 is a flowchart illustrating a third method for direct data transfer between data storage elements using a shared bus, according to various embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Detailed explanation] Various embodiments of the present disclosure provide direct data transfer between devices sharing a bus with reduced involvement from a controller. In some embodiments, a controller, such as a memory controller, a source memory device, and a target memory device may be coupled to the shared bus. In some embodiments, the shared bus may be a serial peripheral interface (SPI) bus, although other types of buses may be used as well. In some examples, the controller may include a processor (e.g., a microprocessor) or operate under the control of a processor. The controller may identify a source address in the source memory device for data to be transferred to the target memory device. The controller may identify a target address in the target memory device and initiate a direct data transfer from the source memory device to the target memory device via the bus. The controller may send a command to read data to a first memory device, which may be received by a second memory device. In response to the command, the source memory device may read the data onto the bus, and the target memory device may read the data from the bus and store the data starting at the target address without further commands from the controller. In some embodiments, the command to read data from a first memory device may be a read command to the first memory device according to a set of protocols or commands, and may also be a special program command to the second memory device to store the data provided by the first memory device in the second memory device.

[0010] In some embodiments, the controller may provide an enable signal to the target memory device and write the target address to a target address register in the target memory device. The controller may then provide an enable signal to both the source and target memory devices along with a read command. The controller may also provide a clock to the source and target memory devices, and as long as the clock is provided, the source memory device may read data onto the bus and the target memory device may read data from the bus. In this manner, the controller and / or the processor managing the controller can reduce its involvement in the data transfer by simply providing the source and target addresses, read command, enable, and clock signals. This can improve system operation by freeing resources for other processing tasks, and can reduce the amount of internal memory, such as cache memory or buffer memory, required by the controller, depending on the technique by which the controller actually receives the data being transferred between memory devices. Furthermore, this technique can reduce system power and processing time compared to other techniques for data transfer.

[0011] The above-described embodiments of the present disclosure are further described below with respect to electronic systems with different devices that may have data transferred between them. Specific examples are described for memory systems that employ direct data transfer with reduced memory controller involvement. These and other embodiments of the present disclosure are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flowcharts relating to direct data transfer between devices using a shared bus.

[0012] FIG. 1 illustrates a diagram of a system 100 supporting direct data transfer between devices using a shared bus, according to various embodiments of the present disclosure. System 100 includes device 105, which may be or include a printed circuit board for connecting or physically supporting various components. Device 105 may include processor 110, BIOS component 115, peripheral components 120, input / output control components 125, and memory system 150. The above components of device 105 may be in electronic communication with each other via device bus 130. In the exemplary system 100 of FIG. 1, memory system 150 includes memory controller 155, volatile memory 160, and non-volatile memory 165, and memories 160 and 165 may be coupled to memory controller 155 by shared bus 170.

[0013] Processor 110 can be configured to interface with memory system 150 via memory controller 155. In some cases, processor 110 may perform the functions of memory controller 155, while in other cases, memory controller 155 may be integrated into processor 110. Processor 110 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these types of components, and may perform various functions described herein, including direct data transfer between devices using a shared bus. Processor 110 may be configured to execute computer-readable instructions stored in memory system 150, for example, to cause device 105 to perform various functions or tasks.

[0014] BIOS component 115 is a software component that includes a basic input / output system (BIOS) operated as firmware and may boot and operate various hardware components of system 100. BIOS component 115 may also manage data flow between processor 110 and various components (e.g., peripheral components 120, input / output controller 125, etc.). BIOS component 115 may include programs or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0015] Peripheral component 120 may be any input or output device, or interface for such a device, integrated into device 105. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a USB controller, a serial or parallel port, or a peripheral card slot, such as a Peripheral Component Interconnect (PCI) slot or an Accelerated Graphics Port (AGP) slot.

[0016] Input / output controller 125 may manage data communication between processor 110 and peripheral components 120, input devices 135, or output devices 140. Input / output controller 125 may also manage peripheral devices that are not integrated into device 105. In some cases, input / output controller 125 may be a physical connection or port to an external peripheral device.

[0017] Input 135 can be a device or signal external to device 105 that provides input to device 105 or its components. This may include a user interface or an interface with or between other devices. In some cases, input 135 may be a peripheral device that interfaces with device 105 through peripheral component 120 or may be managed by input / output controller 125.

[0018] Output device 140 may be a device or signal external to device 105 configured to receive output from device 105 or any of its components. Examples of output device 140 may include a display, audio speaker, printing device, another processor or printed circuit board, etc. In some cases, output 140 may be a peripheral device that interfaces with device 105 via peripheral component 120 or may be managed by input / output controller 125.

[0019] As described above, memory system 150 may include memory controller 155, volatile memory 160, and non-volatile memory 165, which may be coupled to memory controller 155 by shared bus 170. In one example, shared bus 170 may be an SPI bus, and memory controller 155 may use a single SPI interface to access both volatile memory 160 and non-volatile memory 165. Various existing designs for memory controllers may use separate interfaces for volatile and non-volatile memory, and using shared bus 170 with a single interface may provide a more efficient and less complex design.

[0020] Various examples of the SPI bus may use a protocol that includes instructions, addresses, and data, all in a single command sequence. Such a command sequence may be initiated by providing a chip enable or chip select signal to a particular component (e.g., volatile memory 160 and / or nonvolatile memory 165) and may be terminated by deselecting the chip enable or chip select signal. The SPI protocol instruction may define an operation to be performed (e.g., a memory read), and the address may identify where the data associated with the instruction is to be located or written. For example, the instruction may be a read instruction, and the address may be a source address indicating the initial memory location of data to be read from volatile memory 160 or nonvolatile memory 165. In various examples, a dummy cycle may be provided following the SPI protocol instruction between providing the address and outputting the data to allow a memory or other device to detect the data (e.g., detect data stored in a particular location within a memory array) before outputting the data. The techniques provided herein are described in some examples with respect to a system using an SPI shared bus. However, the technique may also be used in systems using other types of shared buses with similar command sequences that may include command, address, and data all in one and the same chip select event.

[0021] 2, a more specific example of a system 200 supporting direct data transfer between devices using a shared bus will be described, in accordance with various embodiments of the present disclosure. System 200 may include memory system 150-a, which is an example of memory system 150 of FIG. 1. Memory system 150-a may include memory controller 155-a, which is an example of memory controller 155 of FIG. 1, coupled to shared bus 170-a, which is an example of shared bus 170 of FIG. 1. Also coupled to shared bus 170-a are volatile memory 160-a and non-volatile memory 165-a, which are examples of volatile memory 160 and non-volatile memory 165 of FIG. 1, respectively.

[0022] Volatile memory 160-a may include first operation instruction decoder 205, first target address register 210, volatile memory array 215, and first chip enable 220. Volatile memory 160-a may be, for example, a single integrated circuit or chip included in memory system 150-a. In some examples, volatile memory 160-a may be a memory module consisting of a larger integrated circuit including the components described above. In other examples, first operation instruction decoder 205, first target address register 210, and volatile memory array 215 may be discrete components included in a single memory module (e.g., components mounted on a printed circuit board), and first chip enable 220 may be used to enable these (and other) components of the memory module.

[0023] The first operational instruction decoder 205 may decode instructions received via the shared bus 170-a and operate according to the decoded instructions. The first target address register 210 may be a register through which the memory controller 155-a provides a target address for data to be transferred to the volatile memory 160-a. The volatile memory array 215 may include an array of memory cells (e.g., a DRAM array or an SRAM array). Although the first target address register 210 is shown separate from the volatile memory array 215, in some examples, the first target address register 210 may be part of the volatile memory array 215. The first chip enable 220 may be an enable line that causes the volatile memory 160-a to execute instructions and communicate with other components via the shared bus 170-a.

[0024] Similarly, non-volatile memory 165-a may include second operation instruction decoder 225, second target address register 230, non-volatile memory array 235, and second chip enable 240. Non-volatile memory 165-a may be, for example, a single integrated circuit or chip included in memory system 150-a. In some examples, non-volatile memory 165-a may be a memory module consisting of a larger integrated circuit including the components described above. In other examples, second operation instruction decoder 225, second target address register 230, and non-volatile memory array 235 may be discrete components (e.g., components mounted on a printed circuit board) included in a single memory module, and second chip enable 240 may be used to enable these (and other) components of the memory module.

[0025] The second operation instruction decoder 225 may decode instructions received via the shared bus 170-a and operate according to the decoded instructions. The second target address register 230 may be a register through which the memory controller 155-a provides a target address for data to be transferred to the non-volatile memory 165-a. The non-volatile memory array 235 may include an array of non-volatile memory cells (e.g., an EEPROM array or a flash memory array). Although the second target address register 230 is shown separate from the non-volatile memory array 235, in some examples, the second target address register 230 may be part of the non-volatile memory array 235. The second chip enable 240 may be an enable line that causes the non-volatile memory 165-a to execute instructions and communicate with other components via the shared bus 170-a. Note that the example of FIG. 2 is for illustrative and descriptive purposes, and other examples may include other or additional components. For example, in this example, volatile memory 160-a and non-volatile memory 165 could be interchangeable, or additional memory or interfaces could be coupled to shared bus 170-a to enable further communication between different devices on shared bus 170-a.

[0026] The memory controller 155-a in this example may include a memory manager 245 and a chip enable (CE) manager 255. The memory manager 245 may provide instructions, such as command sequences according to the SPI protocol, to the volatile memory 160-a and the non-volatile memory 165-a. The memory controller 155-a may be coupled to other external components to provide data from the memory system 150-a to the other components or to receive data stored in the memory system 150-a from the other components. The CE manager 255 may be coupled to a first chip enable 220 of the volatile memory 160-a via a first chip enable line 246 and to a second chip enable 240 of the non-volatile memory 165-a via a second chip enable line 250. The memory controller 155-a may provide a clock 260 to the volatile memory 160-a and the non-volatile memory 165-a.

[0027] As described above, various examples of the shared bus 170-a may be an SPI bus. Various embodiments of the present disclosure use the serial protocol of the SPI bus to provide improved techniques for transferring data between the memory controller 155-a, the volatile memory 160-a, and the non-volatile memory 165-a. Both the volatile memory 160-a and the non-volatile memory 165-a are servants of the memory controller 155-a, and they have individual chip enables 220 and 240 that can be separately accessed by the memory controller 155-a. In some examples, data, such as program instructions executed by a processor external to the memory system, may be loaded from the non-volatile memory 165-a to the volatile memory 160-a. The load data process for such transfers may move data directly from the non-volatile memory 165-a to the volatile memory 160-a with limited involvement from the memory controller 155-a. Similarly, some data from volatile memory 160-a may need to be written to non-volatile memory 165-a by a write-back data process that may move data directly from volatile memory 160-a to non-volatile memory 165-a with limited involvement from memory controller 155-a. Although such load data and write-back data processes are described separately for clarity of explanation, in some examples these operations may be combined.

[0028] For the data load process, the memory controller 155-a, in one example, may determine a source address in the non-volatile memory 165-a for data to be loaded into the volatile memory 160-a. The memory controller may also determine a target address for storing the data in the volatile memory 160-a. The memory controller 155-a may initiate the data load process by setting the target address in the first target address register 210 (e.g., by enabling the first chip enable 220, writing the target address to the first target address register 210, and disabling the first chip enable 220). The memory controller 155-a may then send a command sequence over the shared bus 170-a that is received by both the volatile memory 160-a and the non-volatile memory 165-a. Such a command may, in one example, be a read command established according to the SPI protocol and may include the read command and a source address. As mentioned above, existing techniques for moving data from non-volatile memory 165-a to volatile memory 160-a may involve a read command that moves the data beginning at a source address to a data cache within memory controller 155-a. However, with the techniques described herein, both non-volatile memory 165-a and volatile memory 160-a may receive the read command, verify the command sequence, and transfer the data directly without storing the data in memory controller 155-a, i.e., without involving memory controller 155-a in the actual data movement.

[0029] In one example, memory manager 245, via CE manager 255, may provide chip enable signals to both first chip enable 220 and second chip enable 240, allowing both non-volatile memory 165-a and volatile memory 160-a to acknowledge the read command. As described above, the read command is followed by a source address that may be ignored by the volatile memory, and memory controller 155-a may provide a clock to each of non-volatile memory 165-a and volatile memory 160-a. Non-volatile memory 165-a may output data from non-volatile memory array 235 starting at the source address in accordance with the read command decoded by second operation instruction decoder 225, and may continue to output data in consecutive memory locations from the source address as long as clock 260 continues to be provided by memory controller 155-a. The first operation instruction decoder 205 of the volatile memory 160-a may receive and decode the read command, ignore the source address, and store the data provided by the non-volatile memory 165-a on the shared bus 170-a in the volatile memory array 215 from the target address location. The reading of the data and the corresponding storage of the data continue for the time duration that the clock 260 is provided to the volatile memory 160-a and the non-volatile memory 165-a. In such a manner, the memory controller 155-a may move data directly from the non-volatile memory 165-a to the volatile memory 160-a, with limited involvement of the memory controller 155-a and without storing the data in a cache or buffer of the memory controller 155-a. A similar operation may be used for a write-back operation from non-volatile memory 165-a to volatile memory 160-a, where a target address for the write-back data is stored in second target address register 230 and a read command is issued to read the data from volatile memory 160-a to shared bus 170-a.

[0030] As described above, the techniques described in various embodiments of the present disclosure include both the first operation instruction decoder 205 and the second operation instruction decoder 225 receiving commands from the memory controller 155-a. During a data load process, the nonvolatile memory 165-a may treat the instruction as a read operation, while the volatile memory 160-a may treat the instruction as a write operation. Similarly, during a write-back process, the volatile memory 160-a may treat the instruction as a read operation, while the nonvolatile memory 165-a may treat the instruction as a write operation. These instructions may be defined to match the timing requirements for both the volatile memory 160-a and the nonvolatile memory 165-a. These instructions may also utilize existing nonvolatile and volatile memory read commands defined in the SPI protocol, as long as such instructions are unique to each portion. For example, if the “0Bh” command (the existing FAST read command in SPI flash nonvolatile memory) is not used for any SPI operations on the volatile memory side, this command may be defined as a write command on the volatile memory side. The first instruction decoder 205 can then understand the FAST read command, convert that command sequence into a write sequence using its knowledge of the expected data output from the non-volatile memory 165-a, and latch the data provided to the shared bus 170-a with the correct clock and timing.

[0031] Furthermore, as described above, each of the volatile memory 160-a and the non-volatile memory 165-a may have a target address register. Such an address register may be used because a source address is provided in a command sequence but a target address is not. For example, in a load data process, the command sequence includes the address that the non-volatile memory 165-a needs to send, but it may not be the target address that the memory controller 155-a needs for the volatile memory 160-a. Therefore, before an automatic operation, the memory controller 155-a provides the volatile memory 160-a with the target address where the data from the non-volatile memory 165-a is to be loaded. Similarly, in a write-back process, the memory controller 155-a sets the second target address register 230 in the non-volatile memory 165-a so that the data from the volatile memory 160-a can be written back to the correct location. In some examples, a new command sequence may be defined that includes both a source address and a target address. However, using a target address register may reduce modifications to existing protocols and provide increased flexibility. The operations for data shadowing operations from non-volatile memory 165-a to volatile memory 160-a may be similarly described.

[0032] FIG. 3 illustrates a timing diagram 300 of signals provided from a memory controller to a memory device to support direct data transfer using a shared bus, according to various embodiments of the present disclosure. The signals of timing diagram 300 may be provided, for example, by memory controller 155, as described above with respect to FIGS. 1 and 2. In the example of FIG. 3, a non-volatile memory chip enable signal 305 (CE#_NVM) may be provided to a non-volatile memory, such as non-volatile memory 165-a of FIG. 1 or 2. A volatile memory chip enable signal 310 (CE#_RAM) may be provided to a volatile memory, such as volatile memory 160-a of FIG. 1 or 2. A data signal 315 (DQ[x:0]) may be provided to a shared bus, such as shared bus 170 of FIG. 1 or 2. A clock 320 may also be provided. The example of FIG. 3 illustrates operations for a write-back operation from volatile memory to non-volatile memory.

[0033] First, at time 325, the controller provides a low level chip enable signal 305 to the nonvolatile memory, causing data from data signal 315 to be latched into the nonvolatile memory. In this example, data signal 315 may provide an instruction to set a target address along with the target address during a first period 335. Additionally, during this first period 335, chip enable 310 is high, causing the volatile memory to remain disabled and therefore not receive the instruction. Following the instruction, chip enable signal 305 is deasserted high, and then both chip enable signals 305 and 310 are set low at time 330, enabling both the nonvolatile and volatile memories. A clock 320 is similarly provided to both memories for a duration 345, during which the controller provides a read instruction on the shared bus, data signal 315, which is received by both the nonvolatile and volatile memories. The nonvolatile memory decodes the command, recognizes it as a write-back command, ignores the source address provided in the command, and then detects the data output from the volatile memory on the shared bus. The nonvolatile memory stores the detected data from the location specified by the target address. The volatile memory also decodes the read command on the data signal 315 on the shared bus, decodes the source address from the command, begins detecting the stored data from the source address location, and outputs the data to the shared bus. As mentioned above, the command sequence from the memory controller may include several dummy cycles to allow the volatile memory to detect its stored data, so that both the volatile and nonvolatile memories know the number of dummy cycles to provide the correct timing for data transfer. These operations continue for the duration 345. When the duration 345 ends at time 340, the memory controller may deselect both chip enable signals 305 and 310 and cease providing clock 320.

[0034] While the above examples describe different memory components that may be coupled to a shared bus, the techniques described herein may also be used by other devices in addition to memory devices for direct data transfer between such devices. For example, such techniques may be used in embedded systems that may include sensors, secure digital cards, and liquid crystal displays, to name a few. Such electronic devices may use techniques for data transfer as described herein with limited involvement from a controller.

[0035] FIG. 4 illustrates a system 400 supporting direct data transfer between different types of devices using a shared bus, according to various embodiments of the present disclosure. System 400 may include a device 405, which may be or include a printed circuit board for connecting or physically supporting various components. Device 405 may include a controller 420, a first electronic device 425, a second electronic device 430, an input / output control component 435, and, optionally, one or more other components 440. These components of device 405 may electronically communicate with each other via a shared bus 445, which may be an example of shared bus 170 of FIG. 1 or 2. In the example system 400 of FIG. 4, first electronic device 425 may include a first data storage area 450 and a chip enable / clock input 455. Similarly, second electronic device 430 may include a second data storage area 460 and an associated chip enable / clock input 465.

[0036] The controller 420 may be configured to interface with the first electronic device 425, the second electronic device 430, the input / output control component 435, and / or other components 440 via the shared bus 445. The controller may, in some examples, initiate direct data transfer between the devices in a manner as described above. In some cases, the controller 420 may perform the functions of the memory controller 155 described above with respect to FIGS. 1-3. The controller 420 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these types of components. The controller 420 may perform various functions described herein, including direct data transfer between the devices using the shared bus 445. The controller 420 may, for example, be configured to execute computer-readable instructions to cause the device 405 to perform various functions or tasks.

[0037] The input / output control component 435 manages data communication between the controller 420 and external components and may be a physical connection or port to an external component. The input 410 may be a device or signal external to the device 405 that provides input to the device 405 or its components. This may include a user interface or an interface with or between other devices. In some cases, the input 410 may be a peripheral device interfacing with the device 405 or may be managed by the input / output control component 435. The output device 415 may be a device or signal external to the device 405 that is configured to receive output from the device 405 or any of its components. Examples of output devices 415 may include a display, audio speakers, a printing device, another processor or printed circuit board, etc. In some cases, the output 415 may be a peripheral device interfacing with the device 405.

[0038] As described above, the controller 420 may cause one or more components of the device 405 to transfer data directly to one or more other components of the device 405. In some examples, the controller 420 may provide chip enable and clock signals to devices transferring data via the CE / clock component 460. In the example of FIG. 4, the first electronic device 425 may be the source device and the second electronic device 430 may be the target device. Thus, data stored in the first data storage area 450 may be transferred to the second data storage area 460 of the second electronic device via the shared bus 445. In this example, the first electronic device 425 may include a chip enable / clock input 455, and the second electronic device 430 may also include a chip enable / clock input 465. The controller may use a CE / Clock component 460 to select and transmit a clock to the first electronic device 425 and the second electronic device 430, and may also provide commands and addresses to the shared bus 445 to initiate and terminate direct data transfers between the first electronic device 425 and the second electronic device 430 in a manner similar to that discussed above with respect to Figures 1-3.

[0039] 5 illustrates an example flowchart 500 for direct data transfer between devices using a shared bus, according to various embodiments of the present disclosure. Flowchart 500 may illustrate an embodiment of direct data transfer between devices using a shared bus and may be implemented in device 105, memory system 150, or device 405, as described above with respect to FIGS. 1-4.

[0040] In some examples, a device such as memory controller 155 or controller 420 may identify a source address in a source memory for data to be transferred to a target memory, as shown in block 505. Such identification may be performed by a memory manager, such as memory manager 245, which may identify a starting address for data stored in the source device, as described above with respect to FIGS. 1-4. For example, the source memory device may include program code stored in non-volatile memory of the source device for execution by a processor. The processor may identify the program code to be executed by the processor and provide this information to the memory manager. The memory manager may then identify a source address for moving the identified data from non-volatile memory to volatile memory, i.e., the target memory, so that the processor can more easily access the source address for execution of the program code. In some examples, the controller, source memory, and target memory may be coupled to a shared bus that may be used to transfer commands and data between devices on the shared bus.

[0041] At block 510, the device may send a target address to the target memory to initiate a direct data transfer from the source memory to the target memory, as described above with respect to FIGS. 1-4. The device may, for example, specify the target address as the address of where data from the source memory is to be stored in the target memory. For example, a memory controller may designate an area of ​​volatile memory for storing program code to be executed by a processor and use the starting address of this designated area as the target address. In one example, the controller may send the target address to the target memory by selecting a chip enable in the target memory, providing a clock to the target memory, outputting a command to the shared bus to set the target address in the target address register of the target memory, and outputting the target address. The target memory may decode the command, latch the data from the shared bus, and store this data in the target address register of the target memory. While in some examples, the source memory is non-volatile memory and the target memory is volatile memory, many other examples may provide source and target memories that are other types of memory or data storage components of other types of devices (e.g., displays, sensors, cards, etc.).

[0042] At block 515, the device may send a read command to the source memory to read data from the source memory, as described above with respect to FIGS. 1-4. The read command may include an indication that data is to be read from the source memory and may also include a starting address for the data to be read. In one example, the controller may send the read command by selecting chip enables in the source and target memories, providing clocks to the source and target memories, outputting a data output command to the shared bus, and outputting the source address. The source memory may decode the command (e.g., with an operation command decoder), latch the data from the shared bus, and begin transferring data starting at the source address to the shared bus. Furthermore, if the chip enable and clock are provided to the target memory at the same time that the chip enable and clock are provided to the source memory, the target memory may decode the read command, recognize the read command as the start of a data transfer, ignore the source address in the read command, and begin storing the data provided by the source memory to the shared bus.

[0043] At block 520, the source memory may transfer data directly from the source memory to the target memory, as described above with respect to FIGS. 1-4. The source memory performs the transfer by providing data to the shared bus, which may be read from the shared bus by the target memory. The data may be stored in the target memory from (starting at) a target address previously provided to the target memory. Such a transfer may continue, according to certain examples, as long as a clock is subsequently provided to the source memory and the target memory. Thus, a device such as a memory controller may determine the duration for which to provide the clock based on the amount of data to be read from the source memory and the rate at which data can be read from the source memory or written to the target memory.

[0044] 6 illustrates an example flowchart for direct data transfer between devices using a shared bus, according to various embodiments of the present disclosure. Flowchart 600 illustrates an embodiment of direct data transfer between devices using a shared bus, and may be implemented in device 105, memory system 150, or device 405, as described above with reference to FIGS. 1-4.

[0045] In some examples, a device such as memory controller 155 or controller 420 may provide a chip enable and a clock to the target device, as shown in block 605. The chip enable, or chip select, and the clock may prompt the target device to begin reading one or more commands and / or data from the shared bus, similar to that described above with respect to Figures 1-4. In some examples, the shared bus may be an SPI bus, as previously described, or another type of bus with an associated protocol that provides commands and subsequent data in a command sequence.

[0046] At block 610, the device may set an address register in the target device, similar to that described above with respect to Figures 1-4. The device may, for example, specify a target address as the address at which data from the memory of the source device (e.g., the source memory device) will be stored in the target device (e.g., the target memory device) and set this target address in the address register. For example, a memory controller may specify an area of ​​volatile memory for storing program code to be executed by a processor and use the starting address of the specified area as the target address.

[0047] At block 615, the device may disable chip enables and clocks to the target device, similar to that described above with respect to Figures 1-4. The device may terminate the command sequence being provided to the target device to set the address register, for example, by deselecting the target device (e.g., a target memory device) after providing the target address for storage in the target address register.

[0048] At block 620, the device may provide chip enables and clocks to the source and target devices in a manner similar to that described above with respect to Figures 1-4. As described above, providing chip enables and clocks to each of the source and target devices will cause both the source and target devices to attempt to decode the command provided on the shared bus and any data following the command, initiating a new command sequence for each of these devices.

[0049] At block 625, the device sends a read command to the source device, similar to that described above with respect to Figures 1-4, which may also be received by the target device. Because both the source and target devices are enabled and clocks are sent to both, the read command may be received by each device. In some examples, an operational instruction decoder in each device may decode the read command, which may indicate to the device that data is to be transferred between the source and target devices.

[0050] At block 630, the device may provide chip enables and clocks to the source device and the target device for a duration corresponding to the amount of data to be transferred, similar to that described above with respect to Figures 1-4. The source device and target device thus perform a direct transfer of data, where the source device provides data to the shared bus, and this data may be read from the shared bus by the target device. The data may be stored in the target device from the address provided in the address register at block 610. The duration for providing clocks and chip enables by a device (e.g., memory controller 155 or controller 420) may be based on the amount of data to be read from the source device and the rate at which data is read from the source device or written to the target device.

[0051] At block 635, the device may disable chip enables and clocks to the source and target devices after the duration expires, similar to that described above with respect to Figures 1-4. After the duration expires, the device (memory controller 155 or controller 420) may determine that all data has been transferred and deselect the first memory device and the second memory device.

[0052] 7 illustrates an example flowchart 700 for direct data transfer between devices using a shared bus, according to various embodiments of the present disclosure. Flowchart 700 illustrates an embodiment of direct data transfer between devices using a shared bus, and may be implemented in device 105, memory system 150, or device 405, as described above with reference to FIGS. 1-4.

[0053] In one example, as shown in block 705, and similar to that described above with respect to FIGS. 1-4, a target device (e.g., non-volatile memory 165, volatile memory 160, or second electronic device 430) may receive a target address from a controller (e.g., memory controller 155 or controller 420). The controller may transmit the target address by, in one example, selecting a chip enable associated with the device, providing a clock to the device, outputting a command to the shared bus to set the target address in a target address register of the target device, and outputting the target address. According to various examples, the target device may decode the command, latch the data from the shared bus, and store the data in the target address register.

[0054] At block 710, the target device may decode the read command sent from the controller to the source device, similar to that described above with respect to Figures 1-4. The read command includes an indication that data is to be read from the source device and may also include a starting address for the data to be read. The target device may decode this command (e.g., with an operational command decoder), latch the data from the shared bus, and store the data from the target address.

[0055] At block 715, the target device may ignore the source address included in the command, similar to what was discussed above with respect to FIGS. 1-4. As discussed above, the target device may store its own target address in a target address register, which may be different from the source address where the data is stored at the source device. Thus, if the command includes a source address, the target device may simply ignore it, as this information is irrelevant to the target device. As discussed above, in other examples, the command sequence may include both a source address and a target address, in which case the operations of blocks 710 and 715 may be combined, and each of the source and target devices may ignore the address associated with the other device. For example, the command sequence may include Add1 as the source address and Add2 as the target address:<CMDcode|Add1|Add2> In such an example, the source and target devices may be enabled with chip enable, and decoding the CMDcode may specify which device is the source device and which device is the target device (or such specification may be made in advance).

[0056] At block 720, the target device may identify data available on the bus from the source device, similar to that described above with respect to Figures 1-4. The data available on the bus may be data transferred from the source device to the shared bus (by a read command sent by the controller to the source device). In one example, the target device may wait a predetermined number of clock cycles associated with providing the source address to the shared bus, plus a predetermined number of dummy cycles to allow sufficient time for the source device to detect the data stored at the source address, before identifying the information on the shared bus that follows as data transferred from the source device.

[0057] At block 725, the target device may store the data transferred from the source device to the bus, beginning with the target address, as described above with respect to Figures 1-4. According to certain examples, such transfers may then continue as long as clocks are provided to the source and target devices. Thus, a device such as a memory controller may determine the duration for which to provide such clocks based on the amount of data being read from the source device and the rate at which data is read from the source device or written to the target device.

[0058] Thus, methods 500, 600, and 700 may provide direct data transfer using a shared bus. Note that methods 500, 600, and 700 describe possible implementations, and the operations and steps described above may be rearranged or modified to enable other implementations. In some examples, aspects from two or more of methods 500, 600, and 700 may be combined.

[0059] A method is described. In one example, the method can include identifying, at a memory controller, a source address in a source memory for data to be transferred to a target memory, where the memory controller, the source memory, and the target memory are each coupled to a bus. In one example, the method can include transmitting, by the memory controller, the target address to the target memory to initiate a transfer of the data directly from the source memory to the target memory via the bus. In one example, the method can include transmitting a read command to the source memory to read data from the source memory to the bus.

[0060] In some examples, the method may include transferring data starting from the source address onto the bus by the source memory. In some examples, the read command may be sent to the source memory via the bus. In some examples, the method may include receiving the read command by the target memory via the bus. In some examples, the method may include storing subsequent data provided from the source memory onto the bus from the target address in the target memory.

[0061] In some examples, the read command may include a data output instruction and the source address. In some examples, the method may include recognizing the read command as the start of the data transfer. In some examples, the method may include ignoring the source address. In some examples, the method may include providing a chip enable signal to each of the source memory and the target memory. In some examples, the method may include providing a clock to the source memory and the target memory throughout a time duration.

[0062] In some examples, the time duration corresponds to an amount of data transferred from the source memory to the target memory. In some examples, the bus may include a serial peripheral interconnect (SPI) bus. In some examples, the source memory may include one of a non-volatile memory or a volatile memory, and the target memory may include one of a non-volatile memory or a volatile memory.

[0063] A method is described. In one example, the method may include setting a target address in the target memory for storing data received at the target memory via a bus coupled to the target memory and the source memory. In one example, the method may include sending a command to each of the source memory and the target memory to read data from the source memory to the bus and store the data from the bus in the target memory. In one example, setting the target address may include providing the target address to a target address register of the target memory. In one example, the method may include receiving the command at an operation instruction decoder of the target memory. In one example, the method may include, in the target memory, commencing storing the data from the bus from the target address following the command.

[0064] In one example, the method may include transferring, by the source memory, data beginning at a source address onto the bus. In one example, the method may include storing, by the target memory, the data from the bus. In one example, the command may include a command sequence received at each of the source memory and the target memory. In one example, the method may include providing a chip enable signal to each of the source memory and the target memory. In one example, the method may include providing a clock to the source memory and the target memory throughout a time duration.

[0065] In some examples, the time duration corresponds to an amount of data transferred from the source memory to the target memory. In some examples, the bus may include a serial peripheral interconnect (SPI) bus. In some examples, the source memory may include one of a non-volatile memory or a volatile memory, and the target memory may include one of a non-volatile memory or a volatile memory.

[0066] An apparatus is described. In one example, the apparatus may include a first electronic device coupled to a bus, the first electronic device having a first data storage area. In another example, the apparatus may include a second electronic device coupled to the bus, the second electronic device having a second data storage area. In one example, the apparatus may include a controller coupled to the bus and in electronic communication with the first electronic device and the second electronic device, the controller supporting means for identifying a source address in the first data area for data to be transferred from the first data storage area to the second data storage area. In one example, the controller supporting means for identifying a target address in the second data storage area. In one example, the controller supporting means for initiating a transfer of the data directly from the first electronic device to the second electronic device via the bus.

[0067] In one example, the second electronic device may include a target address register, and the controller may further support means for setting the target address for storage of the data to be transferred in the target address register. In one example, the second electronic device may include an operation command decoder operable to receive a read command from the controller to initiate the transfer of the data. In one example, the controller may include a single interface with the bus for accessing each of the first electronic device and the second electronic device.

[0068] In one example, the controller may support means for providing a chip enable signal to each of the first electronic device and the second electronic device. In one example, the controller may support means for providing a clock to each of the first electronic device and the second electronic device for a time duration corresponding to an amount of data transferred from the first data storage area to the second data storage area. In one example, the first electronic device may include one of non-volatile memory or volatile memory, and the second electronic device may include one of non-volatile memory or volatile memory.

[0069] An apparatus is described. In one example, the apparatus may include a source memory module coupled to a bus. In another example, the apparatus may include a target memory module coupled to the bus. In another example, the apparatus may include a controller coupled to the bus and in electronic communication with the source memory module and the target memory module, the controller supporting means for setting a target address in the target memory module for storage of data received at the target memory module via the bus. In another example, the controller supporting means for sending a read command to the source memory module to read data from the source memory module to the bus. In another example, the target memory module is operable to receive the data read from the source memory module directly via the bus.

[0070] In one example, the target memory module may include a target address register, and the controller may support means for setting the target address for storage of the data to be transferred in the target address register. In one example, the target memory module may include an operation command decoder operable to receive the read command from the controller. In one example, the controller may support means for providing a chip enable signal to each of the source memory module and the target memory module. In one example, the controller may support means for providing a clock to each of the source memory module and the target memory module for a time duration corresponding to the amount of data to be transferred from the source memory module to the target memory module. In one example, the bus may include a serial peripheral interconnect (SPI) bus.

[0071] The description herein provides examples and is not intended to limit the scope, applicability, or examples set forth in the claims. Changes may be made in the function and arrangement of the components described above without departing from the scope of the present disclosure. Various examples may omit, substitute, or add various procedures or components, as appropriate. Also, features described with respect to one example may be combined in other examples.

[0072] The description herein, in conjunction with the accompanying drawings, depicts exemplary configurations, but does not depict every possible implementation or every example within the scope of the claims. As used herein, the terms "exemplary" and "exemplary" mean "serving as an example or embodiment," and do not mean "preferred" or "advantageous over other examples." The detailed description includes specific details to provide an understanding of the technology described herein. However, the technology of the present disclosure may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0073] In the accompanying drawings, similar components or features may have the same reference number. Furthermore, various components of the same type may be distinguished by following the reference number with a dash and a second number that distinguishes between the similar components. When a first reference number is used herein, this description may apply to any similar component having the same first reference number, regardless of the second reference number.

[0074] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the preceding description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. While a diagram may show a signal as a single signal, one skilled in the art will understand that the signal may represent a bus of signals (where the bus has various bit widths).

[0075] The term "electronic communication" describes a relationship between components that supports the flow of electrons between them. This may include a direct connection between the components or may include intermediate components. Components in electronic communication may actively exchange electrons or signals (e.g., in an energized circuit) or may not actively exchange electrons or signals (e.g., in an unenergized circuit), but may be configured or operable to exchange electrons or signals in response to being energized in the circuit. As an example, two components physically connected through a switch (e.g., a transistor) are in electronic communication regardless of the state (i.e., open or closed) of the switch.

[0076] The devices discussed herein may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions thereof may be controlled by doping with various species, including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed by ion implantation or any other doping means during the initial formation or growth of the substrate.

[0077] The various exemplary blocks, components, and modules described in connection with this disclosure may be implemented using general-purpose processors, DS processors, or other processors designed to perform the functions described herein. A processor may be implemented or performed using a DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other similar configuration).

[0078] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of this disclosure and claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features that implement the functions may also be physically located in various locations, including distribution such that portions of the functions are implemented in different physical locations. Also, as used in this specification, including the claims, "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list; for example, a list of at least one of A, B, or C means A, or B, or C, or A and B, or A and C, or B and C, or A and B and C (i.e., A and B and C).

[0079] Computer-readable media includes both non-transitory computer storage media and communication media, including any medium that enables a computer program to be transferred from one place to another. Non-transitory storage media may be any available medium that can be accessed by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, Electrically Erasable Programmable Read-Only Memory (EEPROM), Compact Disc (CD) ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or other non-transitory media that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor.

[0080] Also, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio frequency, or microwave, the coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio frequency, or microwave are included within the definition of media. As used herein, disk and disc include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, which typically reproduce data magnetically or optically with a laser. Combinations of these may also be included within the scope of computer-readable media.

[0081] The present disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the examples and designs set forth herein, but is to be accorded the widest scope consistent with the principles and novel features described herein. [Explanation of symbols]

[0082] 100 systems 105 devices 110 processors 115 BIOS Components 120 Peripheral Components 125 Input / Output Control Components 135 inputs 140 output 150, 150-a memory system 155, 155-a memory controller 160, 160-a Volatile memory 165, 165-a Nonvolatile memory 170, 170-a shared bus 200 systems 205 First operation command decoder 210 First Target Address Register 215 Volatile Memory Array 220 First Chip Enable 225 second operation command decoder 230 Second Target Address Register 235 Non-Volatile Memory Array 240 Second Chip Enable 245 Memory Manager 246 First Chip Enable Line 250 Second Chip Enable Line 255 CE Manager 260 clock 400 System 405 Devices 410 Input 415 Output 420 Controller 425 First Electronic Device 430 Second Electronic Device 435 Input / Output Control Components 440 Other Components 450 first data storage area 455 Chip Enable / Clock Input 460 Second Data Storage Area 465 Chip Enable / Clock Input

Claims

1. receiving, at a first memory device, a first chip select signal enabling the first memory device, the first memory device being one of a plurality of memory devices coupled to a serial peripheral interface (SPI) bus; operating the first memory device according to a clock signal provided to the first memory device based at least in part on the first chip select signal for a first duration; receiving, during the first duration, a second chip select signal at a second memory device of the plurality of memory devices coupled to the SPI bus, the second chip select signal enabling the second memory device; During a second duration after the first duration, operating the first memory device and the second memory device according to the clock signal provided to the first memory device and the second memory device based at least in part on the first chip select signal and the second chip select signal; receiving, at the first memory device and the second memory device via the SPI bus, one or more commands including one or more addresses associated with read operations, write operations, or both, for transferring data over the SPI bus in accordance with the first chip select signal, the second chip select signal, and the clock signal; A method comprising:

2. 2. The method of claim 1, further comprising: writing data from a first address in the first memory device to the SPI bus, wherein writing the data from the first address to the SPI bus is based at least in part on the first address being an address of the one or more addresses associated with the read operation directed by the one or more commands.

3. 3. The method of claim 2, further comprising writing the data from the SPI bus to a second address of the second memory device, the second address being an address of the one or more addresses associated with the write operation directed by the one or more commands.

4. receiving an indication of a change in the first chip select signal at the first memory device; ceasing to operate the first memory device according to the clock signal based at least in part on the change in the first chip select signal; The method of claim 1 further comprising:

5. receiving an indication of a change in the second chip select signal at the second memory device; ceasing to operate the second memory device according to the clock signal based at least in part on the change in the second chip select signal; The method of claim 1 further comprising:

6. 2. The method of claim 1, wherein receiving the first chip select signal comprises receiving a switch from a high chip select signal to a low chip select signal at the first memory device, the low chip select signal enabling the first memory device.

7. 2. The method of claim 1, wherein receiving the second chip select signal comprises receiving a switch from a high chip select signal to a low chip select signal at the second memory device, the low chip select signal enabling the second memory device.

8. 2. The method of claim 1, wherein each command of the one or more commands includes a respective instruction according to an SPI protocol of the SPI bus and a respective address associated with the respective instruction.

9. 1. A non-transitory computer-readable medium storing code, the code being configured by one or more processors to: receiving, at a first memory device, a first chip select signal enabling the first memory device, the first memory device being one of a plurality of memory devices coupled to a serial peripheral interface (SPI) bus; operating the first memory device according to a clock signal provided to the first memory device based at least in part on the first chip select signal for a first duration; receiving, during the first duration, a second chip select signal at a second memory device of the plurality of memory devices coupled to the SPI bus, the second chip select signal enabling the second memory device; During a second duration after the first duration, operating the first memory device and the second memory device according to the clock signal provided to the first memory device and the second memory device based at least in part on the first chip select signal and the second chip select signal; receiving, at the first memory device and the second memory device via the SPI bus, one or more commands including one or more addresses associated with read operations, write operations, or both, for transferring data over the SPI bus in accordance with the first chip select signal, the second chip select signal, and the clock signal; A non-transitory computer-readable medium containing executable instructions.

10. 10. The non-transitory computer-readable medium of claim 9, wherein the instructions are further executable by the one or more processors to write data from a first address in the first memory device to the SPI bus, wherein writing the data from the first address to the SPI bus is based at least in part on the first address being an address of the one or more addresses associated with the read operation directed by the one or more commands.

11. 11. The non-transitory computer-readable medium of claim 10, wherein the instructions are further executable by the one or more processors to write the data from the SPI bus to a second address in the second memory device, the second address being an address of the one or more addresses associated with the write operation directed by the one or more commands.

12. The instructions are then transmitted to the one or more processors: receiving an indication of a change in the first chip select signal at the first memory device; ceasing to operate the first memory device according to the clock signal based at least in part on the change in the first chip select signal; The non-transitory computer-readable medium of claim 10 further operable to:

13. The instructions are then transmitted to the one or more processors: receiving an indication of a change in the second chip select signal at the second memory device; ceasing to operate the second memory device according to the clock signal based at least in part on the change in the second chip select signal; 10. The non-transitory computer-readable medium of claim 9, further operable to:

14. 10. The non-transitory computer-readable medium of claim 9, wherein the instructions are executable by the one or more processors to receive, at the first memory device, a switch from a high chip select signal to a low chip select signal to receive the second chip select signal, the low chip select signal enabling the first memory device.

15. 10. The non-transitory computer-readable medium of claim 9, wherein the instructions are executable by the one or more processors to receive the second chip select signal, receiving at the second memory device a switch from a high chip select signal to a low chip select signal, the low chip select signal enabling the second memory device.

16. 10. The non-transitory computer-readable medium of claim 9, wherein each command of the one or more commands includes a respective instruction according to an SPI protocol of the SPI bus and a respective address associated with the respective instruction.

17. a serial peripheral interface (SPI) bus; a plurality of memory devices coupled to the SPI bus; one or more controllers coupled to the SPI bus and the plurality of memory devices; A memory system comprising: The one or more controllers: transmitting a first chip select signal to a first memory device of the plurality of memory devices, the first chip select signal enabling the first memory device; providing a clock signal to the first memory device based at least in part on the first chip select signal for a first duration; transmitting a second chip select signal to a second memory device of the plurality of memory devices coupled to the SPI bus during the first duration, the second chip select signal enabling the second memory device; providing the clock signal to the first memory device and the second memory device based at least in part on the first chip select signal and the second chip select signal during a second duration after the first duration; sending one or more commands to the first memory device and the second memory device via the SPI bus in accordance with the first chip select signal, the second chip select signal, and the clock signal, the commands including one or more addresses associated with read operations, write operations, or both, for transferring data via the SPI bus; a memory system operable to:

18. The one or more controllers: sending an indication of a change in the first chip select signal to the first memory device; ceasing to provide the clock signal to the first memory device based at least in part on the change in the first chip select signal; 20. The memory system of claim 17 further operable to:

19. The one or more controllers: sending an indication of the change in the second chip select signal to the second memory device; ceasing to provide the clock signal to the second memory device based at least in part on the change in the second chip select signal; 20. The memory system of claim 17 further operable to:

20. 20. The memory system of claim 17, wherein transmitting the first chip select signal includes switching the first chip select signal from a high chip select signal to a low chip select signal, the low chip select signal enabling the first memory device.

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