Semiconductor device and manufacturing method for the same

Abstract

To solve a problem of the conventional semiconductor device in which, at the etching of a concave part, the concave part cannot be formed as designed.SOLUTION: A semiconductor device 1 includes a semiconductor substrate SUB having a first surface where a source terminal and a gate electrode of a vertical transistor are formed and a second surface where a drain terminal of the vertical transistor is formed, a bonding region BR formed on an upper surface of a region where the source terminal is formed on the first surface side and connected to a bonding wire that supplies current to the source terminal, and a plurality of concave parts RP formed in a region including at least a region of the second surface that faces the first surface where the bonding region BR is formed. An extending direction of an outer periphery of an opening part of the concave parts RP is set displaced from an extending direction of a side of an element pattern formed on the first surface.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, for example, a semiconductor device including a power transistor. [Background technology]

[0002] In a power transistor configured with a vertical transistor in which current flows in the thickness direction of a semiconductor substrate, one possible measure to reduce the on-resistance is to thin the drain region by polishing the semiconductor substrate from the second surface side, which becomes the drain terminal. Therefore, Patent Document 1 discloses a technique for thinning the semiconductor substrate.

[0003] The semiconductor device described in Patent Document 1 includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a gate insulating film formed on the first surface, a gate formed on the first surface via the gate insulating film, a source region formed on the first surface side of the semiconductor substrate, a body region formed in contact with the source region and including a channel region, a drain region formed on the second surface side of the semiconductor substrate, and a drift region formed in contact with the second surface side of the body region and the first surface side of the drain region. The gate faces the channel region with the gate insulating film interposed therebetween. The semiconductor substrate has at least one recess formed in the second surface that is recessed toward the first surface. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-112707 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in Patent Document 1, if the extension direction of the sides of the element pattern formed on the first surface coincides with the extension direction of the sides of the recess formed on the second surface, there is a problem in that the recess cannot be formed as designed when etching the recess.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment includes a semiconductor substrate having a first surface on which a source terminal and a gate electrode of a vertical transistor are formed, and a second surface on which a drain terminal of the vertical transistor is formed, a bonding region formed on the first surface above an area where the source terminal is formed, and to which a bonding wire that supplies current to the source terminal is connected, and a plurality of recesses formed in an area of ​​the second surface that includes at least an area facing the first surface where the bonding region is formed, and the extending direction of the outer peripheries of the openings of the plurality of recesses is set in a direction that is shifted from the extending direction of the sides of an element pattern formed on the first surface.

[0008] A method for manufacturing a semiconductor device according to one embodiment includes an element formation step of forming transistors on a first surface of a semiconductor substrate, a wiring formation step of forming wiring and bonding regions associated with the transistors on the first surface, a protective layer formation step of forming a protective layer on surfaces of the wiring and the bonding regions, a mask pattern formation step of forming a mask pattern corresponding to openings of a plurality of recesses on a second surface of the semiconductor substrate opposite the first surface, an etching step of etching the semiconductor substrate exposed in the openings by wet etching with TMAH, and a mask pattern removal step of removing the mask pattern, wherein the extension direction of the sides of the openings of the mask pattern is set to a direction shifted from the extension direction of the sides of the element pattern formed on the first surface. [Effects of the Invention]

[0009] In the semiconductor device and the method for manufacturing the semiconductor device according to an embodiment, it is possible to improve the accuracy of forming the recess pattern formed on the second surface on which the drain terminal of the vertical transistor is formed. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic diagram of a semiconductor device according to a first embodiment. [Figure 2] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 3] 3A and 3B are diagrams illustrating the relationship between an element pattern and a recess pattern formed in the semiconductor device according to the first embodiment. [Figure 4] 3A to 3C are diagrams illustrating an anisotropic etching process used in the semiconductor device according to the first embodiment. [Figure 5] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to a first embodiment. [Figure 6] 3A and 3B are diagrams illustrating a first example of a recess pattern of the semiconductor device according to the first embodiment. [Figure 7] 10A and 10B are diagrams illustrating a second example of a recess pattern of the semiconductor device according to the first embodiment. [Figure 8] 10A and 10B are diagrams illustrating a third example of a recess pattern of the semiconductor device according to the first embodiment. [Figure 9] 10A and 10B are diagrams illustrating a fourth example of a recess pattern of the semiconductor device according to the first embodiment. [Figure 10] 5 is a diagram illustrating another example of a region where a recess pattern is formed in the semiconductor device according to the first embodiment. FIG. [Figure 11] 5 is a diagram illustrating another example of a region where a recess pattern is formed in the semiconductor device according to the first embodiment. FIG. [Figure 12] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. Furthermore, in each drawing, the same elements are given the same reference numerals, and repeated explanations are omitted as necessary. Specifically, the shapes and the like shown in the drawings in the following description are simplified for the purpose of explanation. It should be noted that the number, size, and density of the recesses RP in particular are determined by the product specifications of the semiconductor device and may differ from the number, size, and density shown in the drawings.

[0012] Embodiment 1 Fig. 1 shows a schematic diagram of a semiconductor device 1 according to the first embodiment. The schematic diagram shown in Fig. 1 shows a semiconductor chip 10 viewed from above from a first surface side on which circuit elements are formed on a semiconductor substrate, and also shows the positions of recesses RP formed on a second surface side opposite to the first surface.

[0013] As shown in FIG. 1, a semiconductor chip 10 has a power transistor formation region 11 and a control logic formation region 12 on a first surface, and a backside recess pattern formation region 13 on a second surface. In the power transistor formation region 11, a vertical transistor that passes a current in the thickness direction of the semiconductor substrate (the Z direction in FIG. 1) is formed. Note that a vertical transistor is a power transistor that can pass a larger current than a horizontal transistor, and in the following description, a vertical transistor will be referred to as a power transistor. In addition, a bonding region BR that serves as an edge region that supplies current to the source terminal of the power transistor is formed in the power transistor formation region 11.

[0014] A horizontal transistor that passes a current in the lateral direction of the semiconductor substrate (the X direction or the Y direction in FIG. 1) is formed in the control logic formation region 12. In the semiconductor device 1 according to the first embodiment, a power transistor formed in the power transistor formation region 11 is controlled by a circuit formed in the control logic formation region 12.

[0015] The back surface recess pattern formation region 13 is set to an area narrower than the power transistor formation region 11, and a plurality of recesses RP are formed therein. The periphery defining the power transistor formation region 11 is set at a position spaced a predetermined distance (for example, 100 μm (micrometers) or more) from the periphery of the semiconductor chip 10.

[0016] Here, the single crystal silicon constituting the semiconductor substrate has the characteristic that the mobility of electric charges varies depending on the crystal lattice of silicon. Specifically, Miller indices that represent the planes and orientations of the crystal lattice are known. <100> Therefore, in the semiconductor device 1 having a power transistor, the direction along the surface of the single crystal silicon constituting the semiconductor substrate is the direction in which the charge mobility is highest. <100> The vertical channel direction of the power transistor is aligned with this surface. It is also known that the etching rate in the etching process during the manufacturing process varies significantly depending on the Miller indices (crystal orientation) of single-crystal silicon. When focusing on this difference in etching rate, the bottom surface of the recess RP is <100> The side walls of the recess RP are set on a plane perpendicular to the surface. <111> However, if the extending direction of the etching pattern on the second surface or the shape pattern of the recesses RP is made the same as that on the first surface, which prioritizes the transistor performance of the semiconductor substrate, the direction of etching progresses. <111> It was found that it was difficult to set the direction of the surface, resulting in uneven etching.

[0017] Therefore, in the semiconductor device 1 according to the first embodiment, the extending direction of the sides of the recessed portion RP pattern formed on the second surface side is shifted from the extending direction of the sides of the element pattern or wiring pattern formed on the first surface side. In FIG. 1, the pattern of the bonding region BR formed on the first surface side is square, while the recessed portion RP formed on the second surface side is a rhombus formed by rotating a square. In this way, in the semiconductor device 1 according to the first embodiment, the extending direction of the sides of the recessed portion RP pattern formed on the second surface side is rotated from the extending direction of the sides of the element pattern or wiring pattern formed on the first surface side. Furthermore, the recessed portion RP is a pattern independent of the element pattern, wiring pattern, and bonding region BR on the first surface side, and is patterned independently of the pattern on the first surface. The configuration of the recessed portion RP will be described in detail below.

[0018] Fig. 2 shows a cross-sectional view of the semiconductor device 1 according to the first embodiment. The cross-sectional view shown in Fig. 2 shows an outline of the cross-sectional structure of the semiconductor chip 10 taken along line II-II in Fig. 1. As shown in Fig. 2, the semiconductor chip 10 is provided with a power transistor forming region 11, a control logic forming region 12, and a rear surface recess pattern forming region 13.

[0019] In the semiconductor chip 10, an element formation layer DEV is formed on the surface on the first side of the semiconductor substrate SUB. A power transistor is formed in a portion of the element formation layer DEV corresponding to a power transistor formation region 11. In the example shown in Fig. 2, a trench-type power transistor in which a gate electrode is buried in a trench is formed. A lateral transistor is formed in a portion of the element formation layer DEV corresponding to a control logic formation region 12.

[0020] An interconnect formation layer MW is formed in an upper layer on the first surface side of the semiconductor substrate SUB. In the example shown in Figure 2, a first-layer interconnect ML1, a second-layer interconnect ML2, a third-layer interconnect ML3, and a bonding region BR are formed in the interconnect formation layer MW. The transistors, first-layer interconnect ML1, second-layer interconnect ML2, and third-layer interconnect ML3 formed in the semiconductor substrate SUB are insulated from one another by an interlayer insulating film IL, and are connected to one another by vias VC that are provided to penetrate the interlayer insulating film IL.

[0021] 2, a bonding region BR, which is an end region for supplying current to the source terminal of the power transistor, is formed in the uppermost layer of the wiring formation layer MW in the power transistor formation region 11. In FIG. 2, a bonding wire BW connecting the bonding region BR to the lead frame is shown bonded to the bonding region BR.

[0022] As shown in FIG. 2, a plurality of recesses RP are formed in a backside recess pattern formation region 13 on the second surface side of the semiconductor substrate SUB. The recesses RP have a shape that is recessed from the second surface toward the first surface of the semiconductor substrate SUB. The thickness of the semiconductor substrate SUB is thinner in the portion where the recesses RP are formed, thereby reducing the resistance caused by the semiconductor substrate SUB. The thickness D1 from the bottom of the recess RP to the surface of the first surface of the semiconductor substrate SUB is preferably ¼ or less, and more preferably about ⅕, of the thickness D2 from the flat surface of the second surface in the peripheral portion of the recess RP to the surface of the first surface of the semiconductor substrate SUB (for example, when the thickness D2 is 150 μm, the thickness D1 is about 30 μm).

[0023] Next, the relationship between the element pattern formed on the first surface and the pattern of recesses RP formed on the second surface will be described in detail. Fig. 3 shows a diagram for explaining the relationship between the element pattern and recesses pattern formed in the semiconductor device according to the first embodiment. Fig. 3 shows the element pattern on the first surface of the power transistor and the pattern of recesses RP as the element pattern formed on the first surface.

[0024] 3 shows the gate electrode G, source contact SC, and column CLM of the power transistor. These element patterns are formed on the surface of the first surface. The extension directions Xa and Ya of the sides of these element patterns are set parallel to the X and Y directions parallel to the outer periphery of the semiconductor chip 10.

[0025] On the other hand, the extending direction RPa of the pattern of the recess RP is set to be shifted by a rotation angle θ with respect to the extending directions Xa, Ya of the sides of the element pattern. This rotation angle θ is an angle determined by the plane orientation of the single crystal silicon, and in the semiconductor device 1 according to the first embodiment, it is preferably 45 degrees (45°).

[0026] Next, the plane orientation and anisotropic etching of single crystal silicon will be described. FIG. 4 shows a diagram for explaining the anisotropic etching process used in the semiconductor device 1 according to the first embodiment. First, when forming the recess RP in the semiconductor device 1 according to the first embodiment, anisotropic etching by wet etching is performed. In this anisotropic etching, tetramethylammonium hydroxide (TMAH) is used as an etching solution. When etching is performed using this TMAH, the surface orientation of the single crystal silicon is <100> The etching rate for the plane perpendicular to the plane is <111> The etching rate for the plane perpendicular to the surface is significantly slower than that for the plane perpendicular to the surface. <100> The plane perpendicular to the surface is the flat surface of the second surface, <111> When etching is performed on a surface perpendicular to the first surface, the angle between the wall surface of the recess and the flat surface of the second surface is equal to or greater than 50 degrees and less than 60 degrees, and is approximately 55 degrees, more precisely 54.7 degrees.

[0027] In addition, when etching is performed using TMAH, the <111> The etching rate for the plane perpendicular to the plane is <110> The etching rate is significantly slower than that for the plane perpendicular to the plane.

[0028] Due to this difference in etching rate, etching using TMAH <100> When etching is performed on a semiconductor substrate SUB with a surface perpendicular to the first surface as the second surface, a trapezoidal or triangular groove is formed with the opening of the mask MSK as the base. <110> When this is performed on a semiconductor substrate SUB with a surface perpendicular to the first surface as the second surface, a rectangular groove is formed as if the shape of the opening of the mask MSK has been dug out directly.

[0029] In the semiconductor device 1 according to the first embodiment, the charge transfer path of the power transistor is <100> To use the second face, <100> That is, in the semiconductor device 1 according to the first embodiment, the recess RP has a wall surface shown in the upper diagram of FIG. <111> If the opening of the mask MSK is square, the shape of the recess RP will be a truncated quadrangular pyramid, with the length of each side of the opening being the width OW, the depth being H, and the length of each side of the bottom being the width LW.

[0030] Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described. Fig. 5 shows a diagram for explaining the manufacturing process of the semiconductor device according to the first embodiment. Although Fig. 5 illustrates four steps S1 to S4, one step may include multiple steps.

[0031] Specifically, step S1 includes an element formation process and a wiring formation process. In the element formation process, transistors are formed on the first surface of the semiconductor substrate. In this element formation process, not only vertical transistors but also horizontal transistors may be formed. In this element formation process, circuit elements such as transistors are formed in the element formation layer DEV. In the wiring formation process, wiring and bonding regions related to the transistors are formed on the first surface. This forms the wiring formation layer MW.

[0032] Next, step S2 includes a surface protection layer formation step. In the surface protection layer formation step, a surface protection layer PL is formed on the surfaces of the wiring and bonding regions. Step S2 shown in FIG. 5 also illustrates a step of forming a CVD (Chemical Vapor Deposition) film CV, which serves as a mask MSK, on ​​the second surface of the semiconductor substrate SUB after the surface protection layer formation step. This CVD film CV is formed on the second surface of the semiconductor substrate SUB with the surface protection layer PL facing down.

[0033] Next, step S3 includes a mask pattern forming process and an etching process. In the mask pattern forming process, a mask pattern corresponding to the openings of the plurality of recesses is formed on a second surface of the semiconductor substrate SUB opposite to the first surface. In the etching process, the semiconductor substrate SUB exposed at the openings of the mask MSK is etched by wet etching using TMAH (Tetramethylammonium hydroxide). This etching process forms the recesses RP of the semiconductor device 1 according to the first embodiment.

[0034] The subsequent step S4 includes a mask pattern removal process and a back surface plating process. In the mask pattern removal process, the CVD film remaining as the mask MSK is removed. In the back surface plating process, a metal layer (e.g., back surface metal plating RM) is formed on the second surface. This back surface metal plating RM serves as a back surface electrode and also improves the adhesiveness of the paste material applied when mounting the semiconductor chip 10 on a lead frame.

[0035] As explained above, in the semiconductor device 1 according to the first embodiment, uneven etching is suppressed in the etching process used to form the recesses RP by shifting the extending direction of the sides of the pattern that forms the recesses RP on the second surface of the semiconductor substrate SUB from the extending direction of the sides of the pattern that is formed on the first surface. This makes it possible for the semiconductor device 1 according to the first embodiment to form the shape of the recesses RP as designed.

[0036] Furthermore, the semiconductor device 1 having the recessed portions RP can ensure excellent performance with low resistance by reducing the thickness of the semiconductor substrate SUB, which becomes the drain region of the power transistor. In the example shown in Fig. 1, a plurality of recessed portions RP are formed in a lattice pattern. By forming the recessed portions RP in such a lattice pattern, the semiconductor substrate SUB in the lattice portion acts as a frame, making it possible to prevent damage to the semiconductor chip 10.

[0037] Here, various shapes are conceivable for the formation pattern of the recesses RP, and modified examples of the formation pattern of the recesses RP are shown in FIGS. 6 to 9. FIG. 6 is a diagram illustrating a first example of a recess pattern of the semiconductor device according to the first embodiment. In the first example shown in FIG. 6, the recesses RP are formed so as to be surrounded by a lattice-shaped mask MSK, as in FIG. 1. FIG. 7 is a diagram illustrating a first example of a recess pattern of the semiconductor device according to the first embodiment. In a second example shown in FIG. 6, the recesses RP are formed so as to be surrounded by a staggered mask MSK. FIG. 8 is a diagram illustrating a third example of a recess pattern of the semiconductor device according to the first embodiment. In the third example shown in FIG. 8, each recess RP has a rectangular shape, and the recesses RP are formed so as to be surrounded by a staggered mask MSK. FIG. 9 is a diagram illustrating a fourth example of a recess pattern of the semiconductor device according to the first embodiment. In the third example shown in FIG. 9, grooves extending in one direction have a shape that is continuous in a direction perpendicular to the groove extension direction, and the mask MSK is formed to separate these grooves. In any of the examples shown in Figures 6 to 9, the extension direction RPa of the side of the mask pattern is set to have a rotation angle θ (for example, 45 degrees) with respect to the X direction or Y direction, which is the extension direction of the side of the element or wiring pattern on the first surface.

[0038] As described above, various shapes and arrangement methods of the recesses RP are possible, but the thickness of the semiconductor substrate SUB at the portion that becomes the drain terminal of the power transistor can be reduced in any case, and therefore, it is possible to obtain the effects of improving the low resistance of the power transistor and ensuring the strength of the substrate, similar to the semiconductor device 1 described in Figures 1 to 5.

[0039] Also, various configurations are possible for setting the rear surface recess pattern formation region 13 where the recesses RP are formed. Modified examples of the rear surface recess pattern formation region 13 are shown in FIGS.

[0040] Fig. 10 is a diagram illustrating another example of the recess pattern formation region in the semiconductor device according to embodiment 1. In the first example shown in Fig. 10, the back surface recess pattern formation region 13a is set so that the recesses RP are mainly arranged on the second surface opposite to the region where the bonding region BR, where the current density is particularly high, is arranged.

[0041] 11 is a diagram illustrating another example of a recess pattern formation region in the semiconductor device according to the first embodiment. In the second example shown in Fig. 11, a back surface recess pattern formation region 13b is also set in a region of the second surface of the semiconductor substrate SUB that includes a region facing the control logic formation region 12. In this second example, a recess RP is also formed in the second surface facing the control logic formation region 12.

[0042] In this way, the extent to which the recess RP is formed is adjusted based on the balance between the low resistance performance required of the power transistor and the heat dissipation performance of the semiconductor device 1, and there is no difference in the basic effect of forming the recess RP.

[0043] Embodiment 2 In the second embodiment, a semiconductor device 2 will be described in which the semiconductor device 1 according to the first embodiment is mounted on a lead frame. In the description of the second embodiment, the components described in the first embodiment will be assigned the same reference numerals as in the first embodiment, and the description thereof will be omitted.

[0044] Fig. 12 shows a cross-sectional view of a semiconductor device according to the second embodiment. The semiconductor chip 10 shown in Fig. 12 is the semiconductor chip 10 described in Fig. 2 with a backside metal plating RM formed thereon. In the semiconductor device 2 according to the second embodiment, a thermally conductive paste material HP is interposed between the backside metal plating RM and the lead frame LF. This thermally conductive paste material is a paste material having a lower thermal conductivity and a lower electrical resistance than the semiconductor substrate SUB, and is, for example, a paste material whose main component is silver.

[0045] In this way, by interposing the heat-conductive paste material HP between the rear surface metal plating RM and the lead frame LF, the heat-conductive paste material HP enters the recessed portion RP and is transferred through the paste material, allowing electricity and heat to flow to the lead frame LF. Furthermore, by using the heat-conductive paste material HP, which has a lower thermal conductivity and a lower electrical resistance than the semiconductor substrate SUB, it is possible to improve the low-resistance performance of the power transistor and to improve heat dissipation performance of the entire semiconductor device 2.

[0046] When forming the semiconductor device 2, a paste application process and a chip mounting process are added to the manufacturing process described with reference to Fig. 5. In the paste application process, a paste material (thermally conductive paste material HP) having a lower thermal conductivity than the semiconductor substrate SUB is applied to the surface of a metal layer (for example, backside metal plating RM). In the chip mounting process, the semiconductor substrate SUB is mounted on a lead frame LF via the thermally conductive paste material HP.

[0047] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible within the scope of the gist of the invention. [Explanation of symbols]

[0048] 1. Semiconductor device 2. Semiconductor Devices 10 Semiconductor chips 11 Power transistor formation area 12 Control Logic Formation Area 13 Back surface recess pattern forming area RP recess BR Bonding Area MW wiring formation layer DEV device formation layer SUB Semiconductor substrate ML1 1st layer wiring ML2 2nd layer wiring ML3 3rd layer wiring IL Interlayer insulating film VC via BW Bonding Wire G gate electrode SC Source Contact CLM Column RPa Side extension direction of concave pattern MSK Mask PL surface protection layer CV CVD membrane RM backside metal plating

Claims

1. a semiconductor substrate having a first surface on which a source terminal and a gate electrode of a vertical transistor are formed, and a second surface on which a drain terminal of the vertical transistor is formed; a bonding region formed on the first surface side above a region where the source terminal is formed, the bonding region being connected to a bonding wire that supplies a current to the source terminal; a plurality of recesses formed in a region of the second surface including at least a region facing the first surface on which the bonding region is formed; The semiconductor device is configured such that the direction of extension of the outer peripheries of the openings of the plurality of recesses is set to be offset from the direction of extension of the sides of the element pattern formed on the first surface.

2. 2. The semiconductor device according to claim 1, wherein the extending direction of the outer peripheries of the openings of the plurality of recesses is set to a direction rotated by 45 degrees with respect to the extending direction of the sides of the element pattern formed on the first surface.

3. wall surfaces of the plurality of recesses are surfaces perpendicular to the <111> plane of the single crystal silicon; The flat surface of the second surface is a surface perpendicular to the <100> plane of the single crystal silicon. The semiconductor device according to claim 1 .

4. The semiconductor device according to claim 1 , wherein the plurality of recesses have a lattice pattern, a staggered pattern, or a pattern in which a plurality of grooves are continuous in a direction perpendicular to the extending direction.

5. The semiconductor device according to claim 1 , wherein the plurality of recesses have a shape of a truncated quadrangular pyramid with a flat bottom surface.

6. The semiconductor device according to claim 1 , wherein the wall surfaces of the plurality of recesses are inclined at an angle of 50 degrees to 60 degrees with respect to the flat surface of the second surface.

7. The semiconductor device according to claim 1 , wherein the plurality of recesses are formed in a region of the second surface facing a region in which the vertical transistor is formed.

8. a control logic forming region in which a horizontal transistor constituting a control unit that is a control circuit for the vertical transistor is formed on the first surface; The semiconductor device according to claim 1 , wherein the plurality of recesses are also formed in a region of the second surface that includes a region facing the control logic formation region.

9. The semiconductor device according to claim 1 , wherein the second surface is bonded to a lead frame via a paste material having a lower thermal conductivity than the semiconductor substrate.

10. 2. The semiconductor device according to claim 1, wherein the region where the plurality of recesses are formed is set at a position 100 [mu]m or more away from the end face of the semiconductor substrate.

11. 2. The semiconductor device according to claim 1, wherein the thickness from the bottom surface of the plurality of recesses to the surface of the first side of the semiconductor substrate is less than 1 / 4 of the thickness from the flat surface of the second side in the peripheral portion of the plurality of recesses to the surface of the first side of the semiconductor substrate.

12. an element forming step of forming a transistor on a first surface of a semiconductor substrate; a wiring forming step of forming wiring and bonding regions related to the transistor on the first surface; a surface protection layer forming step of forming a surface protection layer on the surfaces of the wiring and the bonding region; a mask pattern forming step of forming a mask pattern corresponding to openings of a plurality of recesses on a second surface of the semiconductor substrate opposite to the first surface; an etching step of etching the semiconductor substrate exposed in the opening by wet etching using TMAH (Tetramethylammonium hydroxide); a mask pattern removing step of removing the mask pattern, A method of manufacturing a semiconductor device, wherein the extending direction of the sides of the opening of the mask pattern is set to a direction shifted from the extending direction of the sides of the element pattern formed on the first surface.

13. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the extending direction of the sides of the opening of the mask pattern is set to a direction rotated by 45 degrees with respect to the extending direction of the sides of the element pattern formed on the first surface.

14. wall surfaces of the plurality of recesses are surfaces perpendicular to the <111> plane of the single crystal silicon; The flat surface of the second surface is a surface perpendicular to the <100> plane of the single crystal silicon. The method for manufacturing a semiconductor device according to claim 12.

15. After the mask pattern removing step, a backside plating step of forming a metal layer on the second surface; a paste application step of applying a paste material having a thermal conductivity lower than that of the semiconductor substrate to a surface of the metal layer; a chip mounting step of mounting the semiconductor substrate on a lead frame via the paste material; The method for manufacturing a semiconductor device according to claim 12, further comprising:

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