Current generating circuit, semiconductor device, electronic device and vehicle

Abstract

To generate low noise minute currents with high precision.SOLUTION: A current generating circuit 100 includes: a plurality of capacitive ladder circuits 110 and 120 that generate shunt currents I12 and I22 from reference currents I10 and I20, respectively; and a controller 130 that drives the plurality of capacitive ladder circuits 110 and 120 in a time-division manner. The current generating circuit 100 generates an output current Iout by adding together the plurality of shunt currents I12 and I22 output from the plurality of capacitive ladder circuits 110 and 120, respectively.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a current generating circuit, a semiconductor device, an electronic device, and a vehicle. [Background technology]

[0002] Current generating circuits are used in a variety of applications.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-097476

[0005] [overview] Conventional current generating circuits have had difficulty generating low-noise, minute currents with high precision.

[0006] For example, a current generating circuit according to the present disclosure includes a plurality of capacitive ladder circuits each configured to generate a diversion current from a reference current, and a controller configured to drive the plurality of capacitive ladder circuits in a time-division manner, and generates an output current by adding together a plurality of diversion currents output from the plurality of capacitive ladder circuits. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of an electronic device. [Figure 2] FIG. 2 is a diagram illustrating a first embodiment of a current generating circuit. [Figure 3] FIG. 3 is a diagram showing a current output operation of the first embodiment. [Figure 4] FIG. 4 is a diagram showing a second embodiment of the current generating circuit. [Figure 5]FIG. 5 is a diagram showing a current output operation of the second embodiment. [Figure 6] FIG. 6 is a diagram showing a third embodiment of the current generating circuit. [Figure 7] FIG. 7 is a diagram showing a current output operation of the third embodiment. [Figure 8] FIG. 8 is a diagram showing the exterior of the vehicle.

[0008] [Detailed explanation] <Electronic equipment> 1 is a diagram showing an example of the configuration of an electronic device. Electronic device A of this example configuration includes a semiconductor device 1 as means for detecting the ambient illuminance.

[0009] The semiconductor device 1 is an illuminance sensor integrated circuit (IC) that converts incident light into an electrical signal. Referring to the figure, the semiconductor device 1 includes a light receiving circuit 10, a detection circuit 20, an A / D (analog / digital) converter 30, and control logic 40.

[0010] The light receiving circuit 10 generates a current signal S1 according to the incident light. The stronger the incident light, the larger the current signal S1 becomes, and the weaker the incident light, the smaller the current signal S1 becomes. Referring to this diagram, the light receiving circuit 10 may include a photodiode 11 as a photoelectric conversion element. In this case, the cathode of the photodiode 11 is connected to the application terminal of the current signal S1. The anode of the photodiode 11 is connected to the ground terminal.

[0011] The detection circuit 20 generates the analog detection signal S2 by integrating the current signal S1 over a predetermined integration period (e.g., about 100 ms). From another perspective, the detection circuit 20 can be understood as a circuit that detects, amplifies, and filters the current signal S1.

[0012] Referring to the figure, the detection circuit 20 includes an amplifier 21 and a capacitor 22. The inverting input terminal (-) of the amplifier 21 is connected to an application terminal of the current signal S1. The capacitor 22 is connected between the inverting input terminal (-) of the amplifier 21 and an output terminal of the amplifier 21. The output terminal of the amplifier 21 is connected to an application terminal of the analog detection signal S2.

[0013] The A / D converter 30 converts the analog detection signal S2 into a digital detection signal S3.

[0014] The control logic 40 performs digital signal processing on the digital detection signal S3 to generate a digital output signal S4. The digital output signal S4 may have a digital value (for example, 16 bits) corresponding to the illuminance (brightness) of the incident light. The digital output signal S4 may be, for example, I 2 The digital output signal S4 may be output to the outside via a serial communication interface conforming to the C (inter-integrated circuit) communication protocol. In this case, the digital output signal S4 may be output to the outside as a data signal SDA synchronized with the clock signal SCL.

[0015] However, the semiconductor device 1 is not necessarily limited to a digital output type, but may be an analog output type (for example, configured to output an analog detection signal S2 to the outside).

[0016] <Self-diagnosis function> In recent years, many vehicles are equipped with electronic devices that are controlled according to the ambient brightness (such as anti-glare mirrors, automatic lights, and cluster panels with brightness adjustment functions). As a result, the number of vehicles equipped with illuminance sensor ICs is increasing. To ensure the safety of vehicle operation, illuminance sensor ICs for automotive use are required to comply with functional safety standards such as ISO [International Organization for Standardization] 26262.

[0017] For example, the semiconductor device 1 described above may be equipped with a self-diagnosis mode for diagnosing whether the detection circuit 20 is operating correctly, in addition to a normal mode for detecting incident light. Here, in order to perform the self-diagnosis of the detection circuit 20, it is necessary to generate a current that simulates the current signal S1 generated by the photodiode 11.

[0018] When the photodiode 11 is built into the semiconductor device 1, the element area of ​​the photodiode 11 may be much smaller than the element area of ​​a discrete product. Furthermore, the built-in photodiode 11 may have a simple structure such as a Si type, rather than a highly sensitive structure such as a PIN type. Therefore, the current signal S1 generated by the photodiode 11 may have an extremely small current value.

[0019] In particular, when the semiconductor device 1 has high sensitivity specifications, the detection circuit 20 has an extremely high resolution and can handle a current signal S1 on the order of pA (1 pA or more and less than 1000 pA). Therefore, in order to perform self-diagnosis of the detection circuit 20, it is necessary to generate a low-noise minute current (for example, on the order of pA) with high accuracy.

[0020] <Considerations on methods for generating minute currents> Next, methods for generating minute currents are considered. The simplest method is to generate a current by applying a voltage across a resistor. However, to generate minute currents on the order of pA (e.g., 100 pA) from a voltage (e.g., 1 V) that is easy for a semiconductor device to handle, a very high resistance (e.g., 10 GΩ) is required. It is not realistic to integrate such high resistances into a semiconductor device. Furthermore, even if it were possible to integrate high resistances into a semiconductor device, the thermal noise generated by the high resistance would be large. Therefore, the minute currents generated by high resistances contain a lot of noise, making them unsuitable for self-diagnosis applications.

[0021] Another method is to repeat the current mirror process multiple times to reduce the current. It is generally relatively easy to generate a current of 1 μA inside a semiconductor device. Therefore, if four current mirrors, each with a 10:1 mirror ratio, are connected in tandem, and a current of 1 μA is input to the first current mirror, a minute current of 100 pA can be output from the last current mirror.

[0022] However, a typical current mirror formed by a pair of MOS (metal oxide semiconductor) transistors tends to have a poor mirror ratio in the small current range (e.g., nA order), making it difficult to generate minute currents with high accuracy.

[0023] If the current mirror is formed using a pair of bipolar transistors, the precision of generating a minute current can be improved. However, this requires the selection of a manufacturing process that can use bipolar elements, which increases the cost of the semiconductor device.

[0024] In the following, in view of the above considerations, a first embodiment capable of generating a low-noise minute current with high precision will be proposed.

[0025] <Current Generating Circuit (First Embodiment)> FIG. 2 is a diagram showing a first embodiment of the current generating circuit 100 (corresponding to a comparative example to be compared with the second embodiment described later).

[0026] The current generating circuit 100 of this embodiment is mounted on the aforementioned semiconductor device 1. When the semiconductor device 1 is in self-diagnosis mode, the current generating circuit 100 outputs an output current Iout to the detection circuit 20 instead of the current signal S1. The current generating circuit 100 can be understood as a capacitive ladder circuit that shunts a reference current I0 to output the output current Iout. Referring to this diagram, the current generating circuit 100 includes capacitors 101 to 104, a current source 105, and switches 106 to 108.

[0027] A first terminal of each of the capacitors 101 and 102 is connected to an application terminal of the voltage V1. A second terminal of the capacitor 101 is connected to an application terminal of a stable DC voltage, for example, a ground terminal (=an application terminal of the ground voltage GND). A second terminal of the capacitor 102 is connected to an application terminal of the voltage V2. In this way, the capacitors 101 and 102 connected in parallel to the application terminal of the voltage V1 function as a parallel capacitance circuit PC1 that divides the reference current I0 input from the current source 105 in the previous stage in accordance with the capacitance ratio of the capacitors 101 and 102 and outputs the divided current to the subsequent stage.

[0028] The capacitance ratio of the capacitors 101 and 102 may be, for example, 100:1 (=10 pF:0.1 pF). In this case, the shunt current I1 output to the subsequent stage of the parallel capacitance circuit PC1 is approximately 1 / 100 of the reference current I0 input from the previous stage of the parallel capacitance circuit PC1. For example, if the reference current I0 is 1 μA, the shunt current I1 is approximately 10 nA.

[0029] A first terminal of each of the capacitors 103 and 104 is connected to an application terminal of the voltage V2. A second terminal of the capacitor 103 is connected to an application terminal of a stable DC voltage, for example, a ground terminal (=an application terminal of the ground voltage GND). A second terminal of the capacitor 104 is connected to an application terminal of the voltage V3. In this way, the capacitors 103 and 104 connected in parallel to the application terminal of the voltage V2 function as a parallel capacitance circuit PC2 that divides the shunt current I1 input from the parallel capacitance circuit PC1 of the preceding stage in accordance with the capacitance ratio of the capacitors 103 and 104 and outputs the divided current I1 to the subsequent stage.

[0030] The capacitance ratio of capacitors 103 and 104 may be, for example, 100:1 (=10 pF:0.1 pF). In this case, the shunt current I2 output to the subsequent stage of parallel capacitance circuit PC2 is approximately 1 / 100 of the shunt current I1 input from the previous stage of parallel capacitance circuit PC2. For example, if the reference current I0 is 1 μA, the shunt current I2 is approximately 100 pA.

[0031] The current source 105 is connected between an application terminal for a stable DC voltage, for example, a power supply terminal (= an application terminal for the power supply voltage VCC) and an application terminal for the voltage V1. The current source 105 outputs a reference current I0 to the parallel capacitance circuit PC1. The reference current I0 may be, for example, 1 μA. The DC voltage applied to one terminal of the current source 105 only needs to be higher than the DC voltages applied to the second terminals of the capacitors 101 and 103 and the DC voltage applied to one terminal of the switch 106 (both of which are ground voltage GND in this figure).

[0032] The switch 106 is connected between an application terminal of the voltage V1 and an application terminal of a stable DC voltage, for example, a ground terminal (=an application terminal of the ground voltage GND). For example, the switch 106 is turned on when the switching signal SWA is at a high level, and turned off when the switching signal SWA is at a low level.

[0033] The DC voltage applied to the second terminal of capacitor 101, the DC voltage applied to the second terminal of capacitor 103, and the DC voltage applied to one terminal of switch 106 do not necessarily have to be the same voltage.

[0034] The switch 107 is connected between the application terminal of the voltage V3 and the input terminal of the detection circuit 20 (= the inverting input terminal (-) of the amplifier 21). For example, the switch 107 is turned on when the switching signal SWB is at a high level, and turned off when the switching signal SWB is at a low level. The switching signals SWA and SWB may be driven complementarily.

[0035] However, the term "complementary" in this specification should be understood in a broad sense to include not only the case where the on / off states of the switches 106 and 107 are completely reversed, but also the case where a period during which the switches 106 and 107 are simultaneously off (so-called dead time) is provided.

[0036] The switch 108 is connected between the application terminal of the voltage V3 and the application terminal of the bias voltage Vref. For example, the switch 108 is turned on when the inverted switching signal XSWB is at a high level, and turned off when the inverted switching signal XSWB is at a low level. The inverted switching signal XSWB may be a logically inverted signal of the switching signal SWB. That is, the inverted switching signal XSWB is at a low level when the switching signal SWB is at a high level, and is at a high level when the switching signal SWB is at a low level. Therefore, the switch 108 is turned off when the switch 107 is turned on, and turned on when the switch 107 is turned off.

[0037] When the switching signal SWA is set to a low level and the switching signal SWB is set to a high level, the switches 106 and 108 are turned off and the switch 107 is turned on. At this time, the current generating circuit 100 outputs the shunt current I2 as the output current Iout. The output current Iout is output to the inverting input terminal (-) of the amplifier 21, which corresponds to the constant voltage node X.

[0038] The amplifier 21 generates an analog output signal AOUT such that its inverting input terminal (-) and non-inverting input terminal (+) are imaginarily shorted. The analog output signal AOUT corresponds to the analog detection signal S2 mentioned above. The non-inverting input terminal (+) of the amplifier 21 is connected to, for example, a terminal to which a bias voltage Vref is applied. The bias voltage Vref has a constant voltage value. Therefore, the inverting input terminal (-) of the amplifier 21 can be understood as a constant voltage node X.

[0039] 3 is a diagram showing the current output operation of the current generating circuit 100 in the first embodiment. In this diagram, from the top, the switching signals SWA and SWB, the voltages V1 to V3, and the analog output signal AOUT are depicted.

[0040] Before time t1, the switching signal SWA is set to a high level and the switching signal SWB is set to a low level. Therefore, the switches 106 and 108 are turned on, and the switch 107 is turned off. That is, the application terminal of the voltage V1 is connected to the application terminal of the ground voltage GND via the switch 106 until the integration operation begins. As a result, the capacitors 101 to 104 are discharged, and the voltages V1 to V3 all become the ground voltage GND. Furthermore, since the output current Iout is not output from the current generating circuit 100 to the detection circuit 20, the detection circuit 20 does not perform the integration operation of the output current Iout. Therefore, the analog output signal AOUT is matched with the bias voltage Vref. For example, if the bias voltage Vref, rather than the ground voltage GND, is applied to one end of the switch 106, the voltages V1 to V3 all become the bias voltage Vref before time t1.

[0041] At time t1, the switching signal SWA is set to low level and the switching signal SWB is set to high level. Therefore, the switches 106 and 108 are turned off, and the switch 107 is turned on. As a result, the capacitors 101 to 104 start to charge, and the voltages V1 to V3 each start to rise. The slope of the voltage V1 is approximately 0.1 V / μs.

[0042] Furthermore, for example, if the reference current I0 is 1 μA, the capacitance ratio of capacitors 101 and 102 is 100:1 (=10 pF:0.1 pF), and the capacitance ratio of capacitors 103 and 104 is 100:1 (=10 pF:0.1 pF), the slope of voltage V2 is 1 / 100 of the slope of voltage V1.

[0043] On the other hand, the application terminal of voltage V3 is connected to constant voltage node X via switch 107. The constant voltage node X is virtually shorted to the application terminal of bias voltage Vref by the action of amplifier 21. Therefore, the application terminal of voltage V3 is also virtually shorted to the application terminal of bias voltage Vref. As a result, voltage V3 becomes almost completely flat.

[0044] At this time, a minute output current Iout is output from the current generating circuit 100 in the direction toward the detection circuit 20. Therefore, the analog output signal AOUT decreases from the bias voltage Vref as the output current Iout is integrated. The output current Iout may be on the order of pA (1 pA or more and less than 1000 pA).

[0045] In this way, by using a capacitance ladder circuit to shunt the reference current I0, it is possible to generate an arbitrary output current Iout by attenuating the reference current I0 according to the capacitance ratio of the parallel capacitance circuits PC1 and PC2.

[0046] It is easier to ensure accuracy in the capacitance ratio of each of the parallel capacitance circuits PC1 and PC2 than in the mirror ratio of a current mirror formed by MOS transistors. Also, by increasing the number of stages of the parallel capacitance circuits, it is possible to generate an output current Iout smaller than 100 pA. Furthermore, essentially no noise occurs when each of the capacitors 101 to 104 is charged. Therefore, if the S / N (signal / noise) of the original reference current I0 is small, a low-noise output current Iout can be obtained.

[0047] However, in the current generating circuit 100 of the first embodiment, when the voltage V1 rises to a value VCC-Vx (e.g., VCC-0.1 V) close to the power supply voltage VCC at time t2 and saturates, the output current Iout stops flowing. That is, there is a limit to the time during which the output current Iout can be generated. Therefore, it is difficult to generate a minute output current Iout in a DC manner for a certain long period of time.

[0048] For example, it is necessary to continuously generate the output current Iout for a period of about 100 ms in order to perform self-diagnosis of the detection circuit 20. Therefore, a second embodiment will be proposed below, which is capable of generating a minute output current Iout in a DC manner.

[0049] <Current Generating Circuit (Second Embodiment)> 4 is a diagram showing a second embodiment of the current generating circuit 100. The current generating circuit 100 of this embodiment includes capacitive ladder circuits 110 and 120 and a controller 130. Note that the same reference numerals as in FIG. 2 are used for the components and signals already described, and redundant explanations may be omitted.

[0050] The capacitance ladder circuit 110 divides the reference current I10 to generate a divided current I12. Referring to the figure, the capacitance ladder circuit 110 includes capacitors 111-114, a current source 115, and switches 116-118.

[0051] A first terminal of each of the capacitors 111 and 112 is connected to an application terminal of the voltage V11. A second terminal of the capacitor 111 is connected to an application terminal of a stable DC voltage, for example, a ground terminal (=an application terminal of the ground voltage GND). A second terminal of the capacitor 112 is connected to an application terminal of the voltage V12. In this way, the capacitors 111 and 112 connected in parallel to the application terminal of the voltage V11 function as a parallel capacitance circuit PC11 that divides the reference current I10 input from the current source 115 of the previous stage in accordance with the capacitance ratio of the capacitors 111 and 112 and outputs the divided current to the subsequent stage.

[0052] The capacitance ratio of the capacitors 111 and 112 may be, for example, 100:1 (=10 pF:0.1 pF). In this case, the shunt current I11 output to the subsequent stage of the parallel capacitance circuit PC11 is approximately 1 / 100 of the reference current I10 input from the previous stage of the parallel capacitance circuit PC11. For example, if the reference current I10 is 1 μA, the shunt current I11 is approximately 10 nA.

[0053] A first terminal of each of the capacitors 113 and 114 is connected to an application terminal of the voltage V12. A second terminal of the capacitor 113 is connected to an application terminal of a stable DC voltage, for example, a ground terminal (=application terminal of the ground voltage GND). A second terminal of the capacitor 114 is connected to the application terminal of the voltage V13. In this way, the capacitors 113 and 114 connected in parallel to the application terminal of the voltage V12 function as a parallel capacitance circuit PC12 that divides the shunt current I11 input from the parallel capacitance circuit PC11 of the previous stage in accordance with the capacitance ratio of the capacitors 113 and 114 and outputs the divided current I11 to the subsequent stage.

[0054] The capacitance ratio of the capacitors 113 and 114 may be, for example, 100:1 (=10 pF:0.1 pF). In this case, the shunt current I12 output to the subsequent stage of the parallel capacitance circuit PC12 is approximately 1 / 100 of the shunt current I11 input from the previous stage of the parallel capacitance circuit PC12. For example, if the reference current I10 is 1 μA, the shunt current I12 is approximately 100 pA.

[0055] The current source 115 is connected between an application terminal for a stable DC voltage, for example, a power supply terminal (= an application terminal for the power supply voltage VCC) and an application terminal for the voltage V11. The current source 115 outputs a reference current I10 to the parallel capacitance circuit PC11. The reference current I10 may be, for example, 1 μA. The DC voltage applied to one terminal of the current source 115 only needs to be higher than the DC voltages applied to the second terminals of the capacitors 111 and 113 and the DC voltage applied to one terminal of the switch 116 (both of which are ground voltage GND in this figure).

[0056] The switch 116 is connected between an application terminal of the voltage V11 and an application terminal of a stable DC voltage, for example, a ground terminal (=an application terminal of the ground voltage GND). For example, the switch 116 is turned on when the switching signal SWA is at a high level, and turned off when the switching signal SWA is at a low level.

[0057] The DC voltage applied to the second terminal of capacitor 111, the DC voltage applied to the second terminal of capacitor 113, and the DC voltage applied to one terminal of switch 116 do not necessarily have to be the same voltage.

[0058] The switch 117 is connected between the application terminal of the voltage V13 and the input terminal (= the inverting input terminal (-) of the amplifier 21) of the detection circuit 20. For example, the switch 117 is turned on when the switching signal SWB is at a high level, and turned off when the switching signal SWB is at a low level.

[0059] The switch 118 is connected between the application terminal of the voltage V13 and the application terminal of the bias voltage Vref. For example, the switch 118 is turned on when the inverted switching signal XSWB is at a high level, and turned off when the inverted switching signal XSWB is at a low level.

[0060] The capacitance ladder circuit 120 divides the reference current I20 to generate a divided current I22. Referring to the figure, the capacitance ladder circuit 120 includes capacitors 121-124, a current source 125, and switches 126-128.

[0061] A first terminal of each of the capacitors 121 and 122 is connected to an application terminal of the voltage V21. A second terminal of the capacitor 121 is connected to an application terminal of a stable DC voltage, for example, a ground terminal (=an application terminal of the ground voltage GND). A second terminal of the capacitor 122 is connected to an application terminal of the voltage V22. In this way, the capacitors 121 and 122 connected in parallel to the application terminal of the voltage V21 function as a parallel capacitance circuit PC21 that divides the reference current I20 input from the current source 125 of the previous stage in accordance with the capacitance ratio of the capacitors 121 and 122 and outputs the divided current to the subsequent stage.

[0062] The capacitance ratio of the capacitors 121 and 122 may be, for example, 100:1 (=10 pF:0.1 pF). In this case, the shunt current I21 output to the subsequent stage of the parallel capacitance circuit PC21 is approximately 1 / 100 of the reference current I20 input from the previous stage of the parallel capacitance circuit PC21. For example, if the reference current I20 is 1 μA, the shunt current I21 is approximately 10 nA.

[0063] A first terminal of each of the capacitors 123 and 124 is connected to an application terminal of the voltage V22. A second terminal of the capacitor 123 is connected to an application terminal of a stable DC voltage, for example, a ground terminal (=an application terminal of the ground voltage GND). A second terminal of the capacitor 124 is connected to the application terminal of the voltage V23. In this way, the capacitors 123 and 124 connected in parallel to the application terminal of the voltage V22 function as a parallel capacitance circuit PC22 that divides the shunt current I21 input from the parallel capacitance circuit PC21 of the preceding stage in accordance with the capacitance ratio of the capacitors 123 and 124 and outputs the divided current I21 to the subsequent stage.

[0064] The capacitance ratio of the capacitors 123 and 124 may be, for example, 100:1 (=10 pF:0.1 pF). In this case, the shunt current I22 output to the subsequent stage of the parallel capacitance circuit PC22 is approximately 1 / 100 of the shunt current I21 input from the previous stage of the parallel capacitance circuit PC22. For example, if the reference current I20 is 1 μA, the shunt current I22 is approximately 100 pA.

[0065] The current source 125 is connected between an application terminal for a stable DC voltage, for example, a power supply terminal (= an application terminal for the power supply voltage VCC) and an application terminal for the voltage V21. The current source 125 outputs a reference current I20 to the parallel capacitance circuit PC21. The reference current I20 may be, for example, 1 μA. The DC voltage applied to one terminal of the current source 125 only needs to be higher than the DC voltages applied to the second terminals of the capacitors 121 and 123 and the DC voltage applied to one terminal of the switch 126 (both of which are ground voltage GND in this figure).

[0066] The switch 126 is connected between an application terminal of the voltage V21 and an application terminal of a stable DC voltage, for example, a ground terminal (=an application terminal of the ground voltage GND). For example, the switch 126 is turned on when the switching signal SWB is at a high level, and turned off when the switching signal SWB is at a low level.

[0067] The DC voltage applied to the second terminal of capacitor 121, the DC voltage applied to the second terminal of capacitor 123, and the DC voltage applied to one terminal of switch 126 do not necessarily have to be the same voltage.

[0068] The switch 127 is connected between the application terminal of the voltage V23 and the input terminal (= the inverting input terminal (-) of the amplifier 21) of the detection circuit 20. For example, the switch 127 is turned on when the switching signal SWA is at a high level, and turned off when the switching signal SWA is at a low level.

[0069] The switch 128 is connected between the application terminal of the voltage V23 and the application terminal of the bias voltage Vref. For example, the switch 128 is turned on when the inverted switching signal XSWA is at a high level and turned off when the inverted switching signal XSWA is at a low level. The inverted switching signal XSWA may be a logically inverted signal of the switching signal SWA. That is, the inverted switching signal XSWA is at a low level when the switching signal SWA is at a high level and is at a high level when the switching signal SWA is at a low level. Therefore, the switch 128 is turned off when the switch 127 is turned on and turned on when the switch 127 is turned off.

[0070] The controller 130 generates the switching signals SWA and SWB and the inverted switching signals XSWA and XSWB so as to drive the capacitive ladder circuits 110 and 120 in a time-division manner.

[0071] The switches 116 to 118 function as a first switch circuit that switches between outputting the current output from the final-stage parallel capacitance circuit PC12 as the shunt current I12 or discharging the capacitors 111 to 114, depending on the switching signal SWA and the inverted switching signal XSWA instructed by the controller 130.

[0072] In addition, the switches 126 to 128 function as a second switch circuit that switches between outputting the current output from the final-stage parallel capacitance circuit PC12 as the shunt current I22 or discharging the capacitors 121 to 124, depending on the switching signal SWA and the inverted switching signal XSWA instructed by the controller 130.

[0073] The current generating circuit 100 generates the output current Iout by adding together multiple shunt currents I12 and I22 output from the capacitive ladder circuits 110 and 120, respectively. However, as described above, the capacitive ladder circuits 110 and 120 are driven in a time-division manner by the controller 130. Therefore, the output current Iout can be understood as a result of one of the shunt currents I12 and I22 being selectively output in a time-division manner.

[0074] For example, when the switching signal SWA is set to a low level and the switching signal SWB is set to a high level, the switches 116, 118, and 127 are turned off, and the switches 117, 126, and 128 are turned on. That is, the capacitive ladder circuit 110 is in a driving state (= a state in which the shunt current I12 is output), and the capacitive ladder 120 is in a non-driving state (= a state in which the shunt current I22 is not output). At this time, the current generating circuit 100 outputs the shunt current I12 of the capacitive ladder circuit 110 as the output current Iout.

[0075] On the other hand, when the switching signal SWA is set to a high level and the switching signal SWB is set to a low level, the switches 116, 118, and 127 are turned on, and the switches 117, 126, and 128 are turned off. That is, the capacitive ladder circuit 120 is in a driving state (= a state in which the shunt current I22 is output), and the capacitive ladder circuit 110 is in a non-driving state (= a state in which the shunt current I12 is not output). At this time, the current generating circuit 100 outputs the shunt current I22 of the capacitive ladder circuit 120 as the output current Iout.

[0076] The output current Iout thus generated is output to the inverting input terminal (-) of the amplifier 21, which corresponds to the constant voltage node X, in the same manner as in the first embodiment (FIG. 2).

[0077] 5 is a diagram showing the current output operation of the current generating circuit 100 in the second embodiment. In this diagram, from the top, the switching signals SWA and SWB, the voltages V11 and V21, and the analog output signal AOUT are depicted.

[0078] Between times t11 and t12, the switching signal SWA is set to low level and the switching signal SWB is set to high level. Therefore, the capacitive ladder circuit 110 is driven. As a result, the capacitors 111 to 114 are charged, and the voltage V11 rises from an initial value (for example, the ground voltage GND) at a predetermined slope. At this time, a minute output current Iout (=I12) is output from the current generating circuit 100 toward the detection circuit 20. Therefore, the analog output signal AOUT decreases from the bias voltage Vref as the output current Iout is integrated. The output current Iout may be on the order of pA (1 pA or more and less than 1000 pA).

[0079] Furthermore, from time t11 to time t12, the capacitive ladder circuit 120 is in a non-driving state, and therefore the capacitors 121 to 124 are discharged, so that the voltage V21 is reset to an initial value (for example, the ground voltage GND).

[0080] Next, from time t12 to t13, the switching signal SWA is set to high level and the switching signal SWB is set to low level. Therefore, the capacitive ladder circuit 120 is driven. As a result, the capacitors 121 to 124 are charged, and the voltage V21 rises from its initial value at a predetermined slope. At this time, a minute output current Iout (=I22) is continuously output in the direction from the current generating circuit 100 to the detection circuit 20. Therefore, the analog output signal AOUT continues to decrease from the bias voltage Vref due to the integration operation of the output current Iout. As before, the output current Iout may be on the order of pA (1 pA or more but less than 1000 pA).

[0081] Furthermore, from time t12 to time t13, the capacitive ladder circuit 110 is in a non-driving state, and therefore the capacitors 111 to 114 are discharged, and the voltage V11 is reset to the initial value.

[0082] After time t13, the time-division driving of the capacitive ladder circuits 110 and 120 is repeated in the same manner as above.

[0083] The time-division driving period T (=times t11 to t13) described above should be set appropriately within a range in which the voltages V11 and V21 do not rise to a value VCC-Vx (for example, VCC-0.1 V) close to the power supply voltage VCC and become saturated.

[0084] The switching signals SWA and SWB may be driven with their phases shifted by 180°, for example. That is, the driving period of the capacitive ladder circuit 110 (=time t11 to t12) and the driving period of the capacitive ladder circuit 120 (=time t12 to t13) may each be set to T / 2.

[0085] The current generating circuit 100 of this embodiment can continuously generate a small DC output current Iout in the direction from the current generating circuit 100 to the detection circuit 20 for a relatively long time (for example, about 100 ms). Furthermore, similar to the first embodiment (FIG. 2), high accuracy and low noise of the output current Iout can be achieved. Therefore, self-diagnosis of the detection circuit 20 using the output current Iout is also fully possible.

[0086] The current generating circuit 100 may be configured to drive three or more capacitive ladder circuits in a time-division manner. More generally, n capacitive ladder circuits (where n is an integer greater than or equal to 2) may be driven with a phase shift of 360° / n. This configuration lengthens the non-driving period of each of the multiple capacitive ladder circuits. Therefore, even if the time-division drive period T is short, the reset time (= capacitor discharge time) of each of the multiple capacitive ladder circuits can be ensured.

[0087] <Current Generating Circuit (Third Embodiment)> 6 is a diagram showing a third embodiment of the current generating circuit 100. The current generating circuit 100 of this embodiment is based on the second embodiment (FIG. 4) described above, but is configured so that the reference currents I10 and I20, the shunt currents I11 and I21, and the shunt currents I12 and I22 flow in the opposite directions to those in the second embodiment (FIG. 4). That is, comparing the second embodiment (FIG. 4) with the third embodiment (FIG. 6), the application terminals of the ground voltage GND and the power supply voltage VCC are interchanged.

[0088] 7 is a diagram showing the current output operation of the current generating circuit 100 in the third embodiment. In this diagram, as in the above-mentioned FIG. 5, from top to bottom, the switching signals SWA and SWB, the voltages V11 and V21, and the analog output signal AOUT are depicted.

[0089] Between times t21 and t22, the switching signal SWA is set to low level and the switching signal SWB is set to high level. Therefore, the capacitive ladder circuit 110 is driven. As a result, the capacitors 111 to 114 are charged, and the voltage V11 decreases from its initial value (for example, the power supply voltage VCC) at a predetermined rate. At this time, a minute output current Iout (=I12) is output from the detection circuit 20 toward the current generation circuit 100. Therefore, the analog output signal AOUT increases from the bias voltage Vref in accordance with the integration of the output current Iout. The output current Iout may be on the order of pA (1 pA or more and less than 1000 pA).

[0090] Furthermore, from time t21 to time t22, the capacitive ladder circuit 120 is in a non-driving state, and therefore the capacitors 121 to 124 are discharged, so that the voltage V21 is reset to an initial value (for example, the power supply voltage VCC).

[0091] Next, from time t22 to t23, the switching signal SWA is set to a high level and the switching signal SWB is set to a low level. Therefore, the capacitive ladder circuit 120 is driven. As a result, the capacitors 121 to 124 are charged, and the voltage V21 decreases from its initial value at a predetermined rate. At this time, a minute output current Iout (=I22) is continuously output from the detection circuit 20 toward the current generation circuit 100. Therefore, the analog output signal AOUT continues to increase from the bias voltage Vref in accordance with the integration of the output current Iout. As before, the output current Iout may be on the order of pA (1 pA or more but less than 1000 pA).

[0092] Furthermore, from time t22 to time t23, the capacitive ladder circuit 110 is in a non-driving state, and therefore the capacitors 111 to 114 are discharged, and the voltage V11 is reset to the initial value.

[0093] After time t23, the time-division driving of the capacitive ladder circuits 110 and 120 is repeated in the same manner as above.

[0094] The time-division drive period T (=times t21 to t23) is preferably set appropriately within a range in which the voltages V11 and V21 do not drop to a value Vy (for example, 0.1 V) close to the ground voltage GND and become saturated.

[0095] The switching signals SWA and SWB may be driven with their phases shifted by 180°, for example. That is, the driving period of the capacitive ladder circuit 110 (=time t21 to t22) and the driving period of the capacitive ladder circuit 120 (=time t22 to t23) may each be set to T / 2.

[0096] The current generating circuit 100 of this embodiment can continuously generate a small DC output current Iout in the direction from the detection circuit 20 toward the current generating circuit 100 for a relatively long time (for example, about 100 ms). Furthermore, similar to the first embodiment (FIG. 2) and the second embodiment (FIG. 4) described above, high accuracy and low noise of the output current Iout can also be achieved. Therefore, self-diagnosis of the detection circuit 20 using the output current Iout becomes fully possible.

[0097] The current generating circuit 100 may be configured to drive three or more capacitive ladder circuits in a time-division manner. More generally, n capacitive ladder circuits (where n is an integer greater than or equal to 2) may be driven with a phase shift of 360° / n. This configuration lengthens the non-driving period of each of the multiple capacitive ladder circuits. Therefore, even if the time-division driving period T is short, the reset time (=capacitor discharge time) of each of the multiple capacitive ladder circuits can be ensured. This is no different from the second embodiment (FIG. 4) discussed above.

[0098] <Application to vehicles> 8 is a diagram showing the exterior of a vehicle. Vehicle B of this configuration example is equipped with various electronic devices that operate by receiving power supply from a battery.

[0099] Vehicle B includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0100] The electronic device A described above can be mounted on a vehicle B as an electronic device controlled according to the ambient brightness (such as an anti-glare mirror, an automatic light, and a cluster panel with a brightness adjustment function).

[0101] <Modification> The application of the current generating circuit according to the present disclosure is not limited to illuminance sensor ICs, but can be applied to optical sensor ICs such as color sensor ICs or image sensor ICs, as well as general applications in which current signals generated by photodiodes are input and output over a relatively long period of time.

[0102] Furthermore, the current generating circuit according to the present disclosure is not limited to use in self-diagnosis, but can be applied to any application that requires the generation of a minute DC current for a relatively long period of time.

[0103] <Additional Notes> The current generating circuit according to the above disclosure can generate a low-noise, minute current with high precision.

[0104] [Appendix 1] a plurality of capacitive ladder circuits (110, 120) configured to generate shunt currents (I12, I22) from reference currents (I10, I20), respectively; a controller (130) configured to drive the plurality of capacitive ladder circuits (110, 120) in a time-division manner; Equipped with A current generating circuit (100) adds up a plurality of shunt currents (I12, I22) output from the plurality of capacitive ladder circuits (110, 120), respectively, to generate an output current (Iout).

[0105] [Appendix 2] Each of the plurality of capacitive ladder circuits (110, 120) comprises: At least one stage of parallel capacitance circuit (PC11, PC12, PC21, PC22) configured to divide a current input from a previous stage in accordance with the capacitance ratio of parallel-connected capacitors (111 and 112, 113 and 114, 121 and 122, and 123 and 124) and output the divided current to a subsequent stage; current sources (115, 125) configured to output the reference currents (I10, I20) to the parallel capacitance circuits (PC11, PC21) at the front stage; switch circuits (116-118, 126-128) configured to switch whether to output the current output from the final-stage parallel capacitance circuit (PC12, PC22) as the shunt current (I12, I22) or to discharge the capacitors (111-114, 121-124) in response to an instruction (SWA, XSWA, SWB, XSWB) from the controller (130); 2. The current generating circuit (100) of claim 1, comprising:

[0106] [Appendix 3] 3. The current generating circuit (100) according to claim 1 or 2, wherein the output current (Iout) is output to a constant voltage node (X).

[0107] [Appendix 4] 4. The current generating circuit (100) according to any one of appendices 1 to 3, wherein the output current (Iout) is equal to or greater than 1 pA and less than 1000 pA.

[0108] [Appendix 5] a light receiving circuit (10) configured to generate a current signal (S1) in response to incident light; a detection circuit (20) configured to integrate the current signal (S1) to generate an analog detection signal (S2); A current generating circuit (100) according to any one of Supplementary Notes 1 to 4; A semiconductor device (1) comprising: The semiconductor device (1), wherein the current generating circuit (100) outputs the output current (Iout) to the detection circuit (20) instead of the current signal (S1) when the semiconductor device (1) is in a specific mode different from a normal mode.

[0109] [Appendix 6] The semiconductor device (1) according to appendix 5, wherein the specific mode is a self-diagnosis mode for diagnosing whether the detection circuit (20) is operating correctly.

[0110] [Appendix 7] a converter (30) configured to convert the analog detection signal (S2) into a digital detection signal (S3); a control logic (4) configured to perform digital signal processing on the digital detection signal (S3); The semiconductor device (1) according to appendix 5 or 6, further comprising:

[0111] [Appendix 8] An electronic device (A) comprising the semiconductor device (1) according to any one of appendices 5 to 7.

[0112] [Appendix 9] A vehicle (B) equipped with an electronic device (A) according to Appendix 8.

[0113] <Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0114] 1. Semiconductor device (illuminance sensor IC) 10 Photodetector circuit 11 Photodiode 20 Detection circuit 21 Amplifier 22 Capacitor 30 A / D converter 40 Control Logic 100 Current generation circuit 101~104 Capacitors 105 Current source 106~108 Switch 110 Capacitive Ladder Circuit 111~114 Capacitor 115 Current source 116~118 Switch 120 Capacitive Ladder Circuit 121~124 Capacitor 125 Current source 126~128 Switch 130 Controller A Electronic equipment B vehicle PC1, PC2, PC11, PC12, PC21, PC22 Parallel capacitance circuit X constant voltage node

Claims

1. a plurality of capacitive ladder circuits each configured to generate a shunt current from a reference current; a controller configured to drive the plurality of capacitive ladder circuits in a time-division manner; Equipped with a current generating circuit that generates an output current by adding together a plurality of shunt currents output from the plurality of capacitive ladder circuits, respectively;

2. Each of the plurality of capacitive ladder circuits comprises: at least one stage of parallel capacitance circuit configured to divide a current input from a previous stage in accordance with a capacitance ratio of capacitors connected in parallel and output the current to a subsequent stage; a current source configured to output the reference current to the first-stage parallel capacitance circuit; a switch circuit configured to switch between outputting the current output from the parallel capacitance circuit at the final stage as the shunt current and discharging the capacitor in response to an instruction from the controller; The current generating circuit of claim 1 , comprising:

3. The current generating circuit according to claim 1 , wherein the output current is output to a constant voltage node.

4. The current generating circuit according to claim 1 , wherein the output current is equal to or greater than 1 pA and less than 1000 pA.

5. a light receiving circuit configured to generate a current signal in response to incident light; a detection circuit configured to integrate the current signal to generate an analog detection signal; a current generating circuit according to any one of claims 1 to 4; A semiconductor device comprising: The current generating circuit outputs the output current to the detection circuit instead of the current signal when the semiconductor device is in a specific mode different from a normal mode.

6. 6. The semiconductor device according to claim 5, wherein said specific mode is a self-diagnosis mode for diagnosing whether said detection circuit is operating correctly.

7. a converter configured to convert the analog detection signal into a digital detection signal; control logic configured to perform digital signal processing on the digital detection signal; The semiconductor device according to claim 5 , further comprising:

8. An electronic device comprising the semiconductor device according to claim 5 .

9. A vehicle comprising the electronic device according to claim 8.

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