Semiconductor module

Abstract

To provide a semiconductor module having no gap between a module and a cooling member, small size, high cooling efficiency, high reliability, and small parasitic inductance.SOLUTION: In a double-sided cooling type semiconductor module 10 including a lower heat dissipation circuit board 11 and an upper heat dissipation circuit board 12 facing each other, the lower heat dissipation circuit board is formed by laminating an anode metal wiring layer 105, a cathode metal wiring layer 106, and a wiring layer of a control electrode on a heat dissipation plate via an insulating layer, and the upper heat dissipation circuit board is formed by laminating an output electrode metal wiring layer 107 and a wiring layer of a control electrode on the heat dissipation plate via the insulating layer. An anode-side semiconductor element is bonded to the anode metal wiring layer, a cathode-side semiconductor element is bonded to the output electrode metal wiring layer. A main electrode and a control electrode on the surfaces of the anode-side semiconductor element and the cathode-side semiconductor element are connected to opposing metal wiring layers via a conductor plate, respectively, and the wiring layer of the control electrode is formed separately from the opposing metal wiring layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module used in a power conversion device. [Background technology]

[0002] For example, the following patents have been published regarding double-sided cooled semiconductor modules used in power conversion devices. The semiconductor module shown in Patent Document 1 (JP 2001-308263 A) is composed of three metal plates: a high-side plate, a middle-side plate, and a low-side plate. The high-side plate and the low-side plate are spaced apart and positioned facing the middle-side plate. A high-side semiconductor is sandwiched between the high-side plate and the middle-side plate, and a low-side semiconductor is sandwiched between the low-side plate and the middle-side plate, joined together, and fixed with sealing resin. The outside of these three metal plates is attached to a cooling device via an insulating material and a layer of silicone grease. Wire bonds are used to connect the control electrode pads on the semiconductor surface to the external control terminal leads.

[0003] Furthermore, the power semiconductor module described in Patent Document 2 (JP 2013-009501 A) consists of four conductor plates. The first and second conductor plates sandwich the upper arm semiconductor of the inverter between them to form a first package, and the third and fourth conductor plates sandwich the lower arm semiconductor of the inverter between them to form a second package. These are housed in a metal case that houses the first and second packages, and the first and second packages are connected inside the case by an intermediate connector. The four heat dissipation surfaces of the first and second packages are in contact with the inner surface of the metal case via an insulating material, allowing them to be cooled from the outside of the case. The four conductor plates are connected to main electrode terminals, and although the document does not describe the connection between the control electrode pads on the semiconductor surface and the external control terminal leads, it can be inferred that they are connected by wire bonds based on the arrangement of the electrode pads on the chip surface and the external terminal leads in Figure 4 of this document. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-308263 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-009501 Summary of the Invention [Problem to be solved by the invention]

[0005] As various systems in society become increasingly powerful, power conversion devices are also becoming higher in voltage and current. In particular, there is growing pressure to minimize power loss in power conversion devices that consume large amounts of energy, especially power semiconductor modules, as a measure to combat global warming.

[0006] In power semiconductor modules for power conversion equipment, both continuous driving loss and switching loss increase as the temperature of the semiconductor rises, so a package with a high cooling effect is required to lower the temperature of the semiconductor. In the future, SiC devices and other devices will operate continuously at higher temperatures than at present, so a module structure that is reliable even at high temperatures will be required. Furthermore, the parasitic inductance of the package increases switching loss and can sometimes cause surge voltage breakdown, so there is a demand for packages with low parasitic inductance. Furthermore, in order to increase the degree of freedom in system design, there is a need for modules that can accommodate various cooling methods, such as natural air cooling, forced air cooling, and water cooling, in line with the miniaturization of power semiconductor modules and the diversification of cooling devices.

[0007] In the semiconductor module described in Patent Document 1, the cooling capacity is improved by double-sided cooling, but there are the following problems. First, a high voltage is applied to the outer main surface of the semiconductor module (the outer surface of the metal plate), and a process of inserting and adhering an insulating layer between the semiconductor module and the cooling member is essential. Next, when assembling a semiconductor module, two of the three metal plates are bonded to another metal plate, but slight differences in the inclination between the two metal plates when they are bonded together can cause gaps to form between them and the cooling device. Adjusting the parallelism is time-consuming. In reality, in addition to the insulating layer, silicone grease is sandwiched between the semiconductor module and the cooling member. Any gaps that occur are filled with grease. Therefore, the thickness of the grease is not uniform, which causes variations in thermal resistance values. In addition, wire bonds are used to connect to the control terminals of the built-in semiconductor elements, but wire bond connections place stresses on the bonding wires on the semiconductor chip due to differences in thermal expansion coefficients during power cycles at even higher temperatures, which can lead to a deterioration in reliability. Furthermore, wire bonds impose limitations on the distance between the control electrode pads on the semiconductor chip and the terminal leads, which limits the placement of bonding pads during chip design and increases the inductance of the wiring to the control terminals due to the parasitic inductance of the wires.

[0008] The power semiconductor module structure described in Patent Document 2 appears to provide cooling from both sides. However, in this case, the package is created in two separate pieces and inserted into a metal case, resulting in wasted space and a larger power semiconductor module. Furthermore, evenly attaching the heat dissipation surfaces of the four conductor plates to the inner surface of the case via an insulating layer would likely require considerable effort to ensure the parallelism of the four plates. In practice, the inner surface of the metal case is thinned, and pressure is applied to this thinned portion at high temperatures to deform it, thereby ensuring contact with the insulating layer. Even with this, there are concerns about variations in thermal resistance. Furthermore, while there is no specific mention of wiring to the control terminals, it appears that wire bonds are used. As with Patent Document 1, there are concerns about the reliability of the wire bond bond strength due to differences in thermal expansion coefficients at even higher temperatures in the future, and it is necessary to address increased instability, such as ringing due to parasitic inductance.

[0009] Although both Patent Documents 1 and 2 have gone to great lengths to create small modules, they are unable to form uniform bonds with cooling members such as cooling fins, and this leaves a problem. Furthermore, both Patent Documents 1 and 2 use wire bonds for wiring to the control terminals, and if high-temperature and high-speed operation of semiconductor modules is realized in the future through the adoption of semiconductor elements such as SiC, issues regarding reliability and parasitic inductance due to the use of wire bonds may become apparent.

[0010] A main object of the present invention is to provide a semiconductor module that can solve the problem of joining a semiconductor module and a cooling member, and can also realize improved reliability and reduced parasitic inductance. [Means for solving the problem]

[0011] (1) According to one aspect, a semiconductor module sandwiches semiconductor elements between metal plates and cools them from both sides, the semiconductor module comprising two substrates, a lower heat dissipation circuit board and an upper heat dissipation circuit board, facing each other; the lower heat dissipation circuit board is formed by laminating at least an anode metal wiring layer, a cathode metal wiring layer, and a cathode-side control electrode metal wiring layer on a heat dissipation plate with an insulating layer interposed between them; the upper heat dissipation circuit board is formed by laminating at least an output electrode metal wiring layer and an anode-side control electrode metal wiring layer on a heat dissipation plate with an insulating layer interposed between them; anode-side semiconductor elements are bonded to the anode metal wiring layer, and cathode-side semiconductor elements are bonded to the output electrode metal wiring layer; main electrodes and control electrodes on the surfaces of the anode-side semiconductor elements and cathode-side semiconductor elements are connected to the opposing metal wiring layers via conductor plates, respectively; and the anode-side control electrode metal wiring layer and the cathode-side control electrode metal wiring layer are formed separately from the main electrode metal wiring layers facing the respective semiconductor elements. In the above description, the anode metal wiring layer is on the lower side and the output electrode metal wiring layer is on the upper side, but they may be reversed so that the anode metal wiring layer is on the upper side and the output electrode metal wiring layer is on the lower side.Furthermore, the semiconductor module may be arranged so that its plane is vertical rather than horizontal. The control electrode is, for example, the gate electrode of an IGBT.

[0012] In a power converter for converting DC power to AC power, a circuit configuration is used in which anode-side semiconductor elements and cathode-side semiconductor elements are connected in series and alternately turned on and off. In such a circuit configuration, in order to realize a semiconductor module that is small and has high cooling efficiency, it is desirable to sandwich the anode-side semiconductor elements and the cathode-side semiconductor elements between metal plates and cool them from both sides. In fact, such a structure is adopted in the semiconductor module illustrated in Patent Document 1. In Patent Document 1, three metal plates form the main electrodes of the inverter, two of the metal plates sandwich a semiconductor chip between each other, the outer surface of each metal plate is exposed from the resin seal, and this protruding portion is in contact with the metal case via an electrical insulating layer.

[0013] However, the semiconductor module of the prior art has the following problems. First, a high voltage is applied to the outer main surfaces of the semiconductor module (the outer surfaces of the metal plates), and the semiconductor module can only be used by being in close contact with a cooling member via an electrical insulating layer. In contrast, a semiconductor module according to one aspect has insulating layers inserted between the anode metal wiring layer, the cathode metal wiring layer, and the output electrode metal wiring layer and the heat sink, and can be used not only when the semiconductor module is cooled using a cooling device, but also when the heat sink is exposed and air is cooled. Next, in the semiconductor module of Patent Document 1, two of the three metal plates are bonded to another metal plate during assembly. However, slight differences in the inclination between the two metal plates during bonding can result in gaps between the cooling device and the module. The formation of gaps leads to a loss of in-plane uniformity in the cooling effect, reducing cooling efficiency. Furthermore, if the resulting gaps are filled with grease, the grease thickness will not be consistent, resulting in variations in thermal resistance. In contrast, in a semiconductor module according to one aspect, two substrates—a lower heat dissipation circuit board with anode and cathode metal wiring layers stacked on one another, and an upper heat dissipation circuit board with an output electrode metal wiring layer stacked on another—are bonded together only once, making adjustments easy. Furthermore, because the heat dissipation surface and circuit surface are integrated into the heat dissipation circuit board, no gaps form between the module and the cooling device.

[0014] Furthermore, in conventional semiconductor modules, wire bonds are used to connect the control terminals of the built-in semiconductor elements. However, with wire bond connections, the bonding wires are directly bonded to the bonding pads on the semiconductor chip, and stress is applied between the bonding pads and the bonding wires due to thermal expansion and other factors, which can degrade reliability during power cycles. In particular, in semiconductor modules using SiC semiconductors with a wide operating temperature range, which are expected to be installed in vehicles in the future, wiring to the control terminals using wire bonds increases the risk of reliability degradation during power cycles. In contrast, in a semiconductor module according to one aspect, a conductor plate is bonded to the bonding pads on the semiconductor chip, and this conductor plate is bonded to the opposing metal wiring layer. The connection with the external terminal is part of a thick control electrode metal wiring layer provided on a heat sink via an insulating layer. This allows for a high-strength lead connection, similar to the connection with the external terminal of the main electrode, and is free from stress due to thermal expansion and other factors, preventing reliability degradation even during power cycles at high temperatures.

[0015] Another issue with wire bonding is that it limits the distance between the external control terminals to which the wires are connected and the pads on the surface of the semiconductor chip. In particular, in configurations where a high-side or low-side plate faces a middle-side plate, the distance between the high-side or low-side plate and the middle-side plate is limited, thereby limiting the loop height and length of the wire bond. While this can be addressed by removing a portion of the metal plate for wire bonding, it is difficult to position the semiconductor chip far from the external control terminals. Placing multiple chips side by side may require redesign and redevelopment of the semiconductor chip. In contrast, in a semiconductor module according to one aspect, the wiring layer for the control electrodes can be formed by patterning a metal wiring layer facing the semiconductor control electrodes, thereby increasing the flexibility in the placement of the control terminals of the semiconductor chip. This allows multiple semiconductor chips to be placed side by side without redesigning the semiconductor chip. Another issue is that wire bonds have large parasitic inductance. In contrast, a semiconductor module according to one aspect does not use wire bonds, and therefore the parasitic inductance of the control wiring can be reduced. In semiconductor modules capable of high-speed operation using SiC or the like, which are expected to be developed in the future, the parasitic inductance of the wire bonds may become an issue. In such cases, a semiconductor module according to one aspect that does not use wire bonds is expected to solve the issue. As described above, in the present invention, a module is formed starting from a heat dissipation circuit board having both a heat dissipation surface and a circuit surface, so the completed module does not require a step of bonding to a heat dissipation member. Furthermore, the semiconductor module of the present invention has insulating layers inserted between the anode metal wiring layer, cathode metal wiring layer, and output electrode metal wiring layer and the heat sink, and since high voltage is not applied to the heat sink, if heat sink fins are machined on this heat sink surface, it becomes a module with heat sink fins. If a channel for passing a coolant is made on the heat sink surface, pipe cooling is also possible. Therefore, the present invention is also effective in diversifying cooling methods.

[0016] (2) In a semiconductor module according to another aspect, in the semiconductor module according to the one aspect, the anode metal wiring layer, the cathode metal wiring layer, and the cathode-side control electrode metal wiring layer may be arranged spaced apart from each other on the same plane.

[0017] In the semiconductor module according to the second aspect of the present invention, the anode metal wiring layer, the cathode metal wiring layer, and the cathode-side control electrode metal wiring layer of the lower heat dissipation circuit board are each stacked on a heat sink with an insulating layer interposed between them, so that the thermal resistance between the anode metal wiring layer and the heat sink and the cathode metal wiring layer is small and substantially the same, and the distance between the anode metal wiring layer and the cathode metal wiring layer and the opposing output electrode metal wiring layer is also the same. Therefore, a thinner semiconductor module with a higher heat dissipation effect can be realized. Furthermore, in semiconductor modules, when the output is switched, the current flowing through the anode metal wiring layer and the cathode metal wiring layer changes significantly, resulting in a large induced voltage due to parasitic inductance. This induced voltage poses a risk of dielectric breakdown and / or increased switching loss in the semiconductor elements. In the semiconductor module according to the second invention, the anode metal wiring layer and the cathode metal wiring layer are stacked on a lower metal heat sink via an insulating layer, and eddy currents are generated in the heat sink, thereby reducing the effective parasitic inductance of the anode metal wiring layer and the cathode metal wiring layer. A similar reduction in parasitic inductance is also achieved between the anode metal wiring layer and the cathode metal wiring layer and the output electrode metal wiring layer (see "Difference in effective inductance due to the relative positions of the two electrode wiring layers" in the second embodiment). This reduction in inductance is more effective the narrower the spacing between the anode metal wiring layer and the negative electrode metal wiring layer. Since the minimum spacing between the metal wiring layers in this invention can be narrowed to the limit of the spacing that can be processed by photoetching, a reduction in inductance can be expected.

[0018] (3) In a semiconductor module according to a third aspect of the present invention, the cathode metal wiring layer and the cathode-side control electrode metal wiring layer may be stacked on the anode metal wiring layer via an insulating layer.

[0019] In the semiconductor module according to the third invention, when the output is switched, currents of approximately the same magnitude flow in opposite directions through the anode metal wiring layer and the cathode metal wiring layer, which are stacked via an insulating layer. The interaction of the generated magnetic fields reduces the effective parasitic inductance, significantly reducing the risk of dielectric breakdown of the semiconductor element and / or increased switching loss due to this induced voltage (see "Difference in effective inductance due to the relative positions of two electrode wirings" in the second embodiment). The thinner the insulating layer between the anode metal wiring layer and the cathode metal wiring layer, the greater the effect of this reduction in inductance. In this invention, a thin, high-thermal-conductivity insulating resin sheet is used as the insulating layer, achieving an extremely thin thickness.

[0020] (4) A semiconductor module according to a fourth aspect of the present invention is the semiconductor module according to the second or third aspect of the present invention, wherein the anode metal wiring layer, the cathode metal wiring layer, the output electrode metal wiring layer, the anode-side control electrode metal wiring layer, and the cathode-side control electrode metal wiring layer may each protrude in a planar direction and have a joint with an external terminal.

[0021] In this case, since no wire bonding process is used, it is possible to realize low-resistance and low-inductance wiring from each chip surface electrode to the external terminal, and highly reliable bonding to the external terminal.

[0022] (5) A semiconductor module according to a fifth aspect of the present invention is a semiconductor module according to the second or third aspect of the present invention, wherein the lower heat dissipation circuit board and the upper heat dissipation circuit board face each other with the heat dissipation surfaces of the heat dissipation plates facing outward, the space between the lower heat dissipation circuit board and the upper heat dissipation circuit board is filled with insulating resin, and the lower heat dissipation circuit board and the upper heat dissipation circuit board are fixed and held by the insulating resin with their respective heat dissipation surfaces protruding.

[0023] If there is a gap between the lower heat dissipation circuit board and the upper heat dissipation circuit board, the dielectric strength decreases and the thermal resistance increases. In the semiconductor module according to the fifth invention, the space between the two heat dissipation circuit boards is filled with insulating resin, thereby preventing a decrease in dielectric strength and an increase in thermal resistance. In addition, in the semiconductor module according to the fifth invention, the two heat dissipation circuit boards are fixed and held with insulating resin, thereby improving the physical strength of the semiconductor module, and the heat dissipation effect is enhanced by having the heat dissipation surface of the heat sink protrude from the insulating resin. [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 is a schematic diagram showing a circuit configuration of a semiconductor module according to a first embodiment. [Figure 2] FIG. 2 is a top view of the semiconductor module. [Figure 3] 3A, 3B, and 3C are cross-sectional views taken along lines AA', BB', and CC' in FIG. 2, respectively. [Figure 4] FIG. 2 is a schematic explanatory diagram of a main body portion of the semiconductor module as viewed from above. [Figure 5] Figure 5(A) is a schematic diagram of the state in which an anode-side semiconductor element is bonded to a lower heat dissipation circuit board of a semiconductor module, and Figure 5(B) is a schematic diagram of the state in which a cathode-side semiconductor element is bonded to an upper heat dissipation circuit board of a semiconductor module. [Figure 6] 1 is a schematic side view of a semiconductor module in which heat dissipation fins are formed on the heat dissipation surface of a heat sink; [Figure 7] Figure 7(A) is a schematic diagram of the state in which an anode-side semiconductor element is bonded to a lower heat dissipation circuit board of a semiconductor module of the second embodiment, and Figure 7(B) is a schematic diagram of the state in which a cathode-side semiconductor element is bonded to an upper heat dissipation circuit board of a semiconductor module of the second embodiment. [Figure 8] FIG. 8 is a cross-sectional view taken along the line DD′ of FIG. 7. [Figure 9] FIG. 10 is a schematic perspective view of the shape of a wiring layer used in calculating inductance. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same components are denoted by the same reference numerals. The names and functions of the components are also the same. Therefore, detailed description thereof will not be repeated.

[0026] [First embodiment] FIG. 1 is a schematic diagram showing the circuit configuration of semiconductor modules 10, 10a of the present invention, FIG. 2 is a top view of the semiconductor module 10 of the first embodiment, and FIGS. 3(A), (B), and (C) are cross-sectional views taken along lines A-A', B-B', and C-C' of FIG. 2, respectively. 4 is a schematic explanatory diagram of the main body portion 15 of the semiconductor module 10 (excluding the heat sinks 101 and 102) as viewed from above, FIG. 5(A) is a schematic drawing of the state in which an anode-side semiconductor element is bonded to the lower heat sink circuit board 11 of the semiconductor module 10, and FIG. 5(B) is a schematic drawing of the state in which a cathode-side semiconductor element is bonded to the upper heat sink circuit board 12 of the semiconductor module 10 (excluding the heat sinks 101 and 102).

[0027] The semiconductor module 10 is used in power conversion devices for converting DC power to AC power in systems such as solar power generation, wind power generation, and electric vehicles. In FIG. 1, DC power is applied between the anode external terminal 108 and the cathode external terminal 109, and AC power is output from the output electrode external terminal 110 by alternately turning on and off the anode-side semiconductor elements (IGBT chip 201 and diode chip 203) and the cathode-side semiconductor elements (IGBT chip 202 and diode chip 204) using drive circuits A1 (207) and A2 (208), respectively. Parasitic inductance exists in the wiring between the semiconductor elements and the external terminals. The circuit diagram in FIG. 1 is also common to the semiconductor module 10a of the second embodiment. Of these parasitic inductances, it is particularly important to reduce the parasitic inductance between the anode external terminal 108 and the anode-side semiconductor element, and between the cathode external terminal 109 and the cathode-side semiconductor element. This is because, if an inductive load is connected to the output electrode external terminal 110, a large transient current flows through the path from the anode external terminal 108 to the cathode external terminal 109 when the anode-side semiconductor element and the cathode-side semiconductor element are turned on / off, and if these parasitic inductances are large, excessive voltage due to ringing will be generated on the anode external terminal 108 side of the anode-side semiconductor element and on the cathode external terminal 109 of the cathode-side semiconductor element, which may lead to insulation breakdown of the semiconductor elements and / or increased switching loss. As for the parasitic inductance on the drive circuit side, no issues have surfaced so far, but if SiC is used in semiconductor elements in the future and the drive circuits become faster, ringing may occur in the control signal, which could lead to insulation breakdown in the semiconductor elements and / or increased switching losses. Although the present embodiment uses an IGBT and a diode as the semiconductor element, a SiC MOS transistor and a diode may also be used. Alternatively, if a diode built into an IGBT or SiC MOS transistor is used as the diode, an independent diode may not be necessary. 1 shows only the gate terminal and emitter terminal of the IGBT as the control terminals, but in some cases a thermistor for measuring temperature may also be mounted on the semiconductor module 10. In that case, the terminal of the thermistor is also added to the control terminals.

[0028] Fig. 2 is a top view of the semiconductor module 10, and Figs. 3(A), (B), and (C) are, respectively, the A-A' cross-sectional view, the B-B' cross-sectional view, and the C-C' cross-sectional view of Fig. 2. The semiconductor module 10 is a double-sided cooling type, with a lower heat sink 101 and an upper heat sink 102 exposed on the bottom and top surfaces, and an anode external terminal 108, a cathode external terminal 109, an output electrode external terminal 110, and a control external terminal 111 protruding from both side surfaces and fixed and held in place by transfer molding insulating resin 114. Bonded onto the lower heat sink 101 are a lower insulating layer 103, an anode metal wiring layer 105, a cathode metal wiring layer 106, a cathode-side IGBT gate wiring layer 1061, and a cathode-side IGBT emitter wiring layer 1062. Bonded below the upper heat sink 102 are an upper insulating layer 104, an output electrode metal wiring layer 107, an anode-side IGBT gate wiring layer 1071, and an anode-side IGBT emitter wiring layer 1072. In this embodiment, a structure in which a lower insulating layer 103, an anode metal wiring layer 105, a cathode metal wiring layer 106, a cathode-side IGBT gate wiring layer 1061, and a cathode-side IGBT emitter wiring layer 1062 are laminated on a lower heat sink 101 is referred to as a lower heat dissipation circuit board 11, and a structure in which an upper insulating layer 104, an output electrode metal wiring layer 107, an anode-side IGBT gate wiring layer 1071, and an anode-side IGBT emitter wiring layer 1072 are laminated on an upper heat sink 102 is referred to as an upper heat dissipation circuit board 12. In this embodiment, the main electrode metal wiring layers correspond to the anode metal wiring layer 105 and the cathode metal wiring layer 106. Similarly, the cathode side control electrode metal wiring layer corresponds to the cathode side IGBT gate wiring layer 1061 and the cathode side IGBT emitter wiring layer 1062, and the anode side control electrode metal wiring layer corresponds to the anode side IGBT gate wiring layer 1071 and the anode side IGBT emitter wiring layer 1072. The anode metal wiring layer 105, the cathode metal wiring layer 106, the output electrode metal wiring layer 107, and the control wiring layers (the cathode side IGBT gate wiring layer 1061, the cathode side IGBT emitter wiring layer 1062, the anode side IGBT gate wiring layer 1071, and the anode side IGBT emitter wiring layer 1072) protrude in the horizontal direction (the left-right direction in FIG. 3), and are joined to the anode external terminal 108, the cathode external terminal 109, the output electrode external terminal 110, and the control external terminal 111, respectively. In the cross-sectional view of FIG. 3, the vertical scale and the horizontal scale are not 1:1, and the vertical scale is enlarged.

[0029] Figure 4 is a schematic explanatory diagram of the main body portion 15 of the semiconductor module 10 (excluding the heat sink) as viewed from above, Figure 5(A) is a schematic drawing of the state in which an anode-side semiconductor element is bonded to the lower heat dissipation circuit board 11 of the semiconductor module 10, and Figure 5(B) is a schematic drawing of the state in which a cathode-side semiconductor element is bonded to the upper heat dissipation circuit board 12 of the semiconductor module 10 (excluding the heat sink). In Fig. 4, lower heat dissipation circuit board 11 and anode-side semiconductor elements are indicated by solid lines, and upper heat dissipation circuit board 12 and cathode-side semiconductor elements are indicated by dotted lines. In Fig. 4 and Fig. 5, conductor plate 113 bonded onto the electrode portions on the front surface of each semiconductor element is hatched. Furthermore, upper heat dissipation circuit board 12 and semiconductor elements in Fig. 5 have a shape that is the left-right inversion of the upper heat dissipation circuit board 12 and semiconductor elements in Fig. 4.

[0030] 5(A), an anode-side IGBT chip 201 and an anode-side diode chip 203 are bonded to the anode metal wiring layer 105, and a conductor plate 113 is bonded to the electrode portion of each semiconductor chip. Also, in FIG. 5(B), a cathode-side IGBT chip 202 and a cathode-side diode chip 204 are bonded to the output electrode metal wiring layer 107, and a conductor plate 113 is bonded to the electrode portion of each semiconductor chip. In FIG. 4, the upper heat dissipation circuit board 12 of FIG. 5(B) is flipped left and right and joined to FIG. 5(A), and the conductor plates 113 joined to the surfaces of the emitter electrodes of the anode side IGBT chips 201 and the anode side diode chips 203 are joined to the output electrode metal wiring layer 107, and the conductor plate 113 joined to the gate electrode surface of the anode side IGBT chips 201 is joined to the anode side IGBT gate wiring layer 1071. In addition, the conductor plate 113 bonded to the surface of the emitter electrode of the cathode side IGBT chip 202 and the surface of the cathode side diode chip 204 is bonded to the cathode metal wiring layer 106, and the conductor plate 113 bonded to the surface of the gate electrode of the cathode side IGBT chip 202 is bonded to the cathode side IGBT gate wiring layer 1061. The cathode IGBT emitter wiring layer 1062 is short-circuited to the cathode metal wiring layer 106 near the cathode IGBT chip 202 , and the anode IGBT emitter wiring layer 1072 is short-circuited to the output electrode metal wiring layer 107 near the anode IGBT chip 201 .

[0031] In Figures 4 and 5, the anode-side semiconductor chip is bonded to the anode metal wiring layer 105, and the cathode-side semiconductor chip is bonded to the output electrode metal wiring layer 107. Mounting both the anode-side and cathode-side semiconductor chips on a single metal wiring layer reduces the cooling effect because one of them is always on. Therefore, by bonding the anode-side and cathode-side semiconductor chips to separate metal wiring layers and bonding these metal wiring layers together, cooling from both sides is possible. Furthermore, by connecting the electrodes on the surface of the semiconductor element to the opposing metal wiring layer with a conductor plate 113, heat is dissipated not only from the back side of the semiconductor chip but also from the surface electrode side through the opposing metal wiring layer. Heat transferred from the semiconductor element to the metal wiring layers on both sides is transferred via the lower insulating layer 103 and upper insulating layer 104 to the lower heat sink 101 and upper heat sink 102, where it is dissipated to a cooling medium outside the semiconductor module 10. This allows efficient cooling of both the anode-side and cathode-side semiconductor chips.

[0032] Furthermore, when a semiconductor chip is sandwiched between metal plates and soldered together, the surface of the semiconductor chip contains electrodes with different functions, such as the emitter and gate of an IGBT, which must be connected separately. In this embodiment, the gate electrode of the IGBT is connected via a conductor plate 113 to a cathode-side IGBT gate wiring layer 1061 and an anode-side IGBT gate wiring layer 1071, which are formed by patterning opposing metal wiring layers. The cathode-side IGBT emitter wiring layer 1062 and the anode-side IGBT emitter wiring layer 1072 are also separately wired up to the vicinity of the emitter electrodes of the IGBT chip, thereby reducing the effects of voltage fluctuations in the metal wiring layers due to transient currents. The control terminal wiring layer protrudes horizontally and forms a junction with the control external terminal 111. Therefore, even if the control electrode of the semiconductor chip is located away from the junction with the control external terminal 111, the wiring can be extended to the required location by patterning the opposing metal wiring layer, and even when multiple semiconductor chips are arranged side by side, wiring can be provided to the control electrode of each semiconductor chip. Furthermore, wiring formed by patterning a metal wiring layer does not form an arc shape that has a large parasitic inductance like wire bonds, and parasitic inductance can be further reduced by widening the wiring width as needed. Additionally, there are cases where a thermistor for measuring temperature is mounted on the semiconductor module 10. In that case, a wiring layer for the control terminal of the thermistor is also added to the control terminal wiring layer.

[0033] Furthermore, when the gap between the opposing metal wiring layers is approximately the thickness of the semiconductor chip, the presence of air bubbles may reduce the breakdown voltage, posing a risk of breakdown in power semiconductor inverters, which are becoming increasingly sensitive to high voltages. In this embodiment, a conductor plate 113 is inserted between the electrode of the semiconductor element and the opposing metal wiring layer to ensure a space between the two metal wiring layers, and this space is further filled with insulating resin to maintain a high breakdown voltage between the two metal wiring layers.

[0034] (Addition of heat dissipation fins 1011 and 1021) FIG. 6 is a schematic side view of the semiconductor module 10 in which heat dissipation fins 1011 and 1021 are formed on the heat dissipation surfaces of the heat dissipation plates 101 and 102. In FIG. The semiconductor module 10 can be used in a wide range of systems, from large systems such as solar power generation, wind power generation, and electric vehicles to small systems such as home inverters, and the fins are becoming more diverse, with water-cooled fins, air-cooled fins, and other types available to suit various systems. The shapes of the heat dissipating fins 1011 and 1021 are diverse, including plate-like, polygonal, elliptical, and cylindrical protrusion shapes and arrangements.

[0035] (Manufacturing process of semiconductor module 10) The manufacturing process of the semiconductor module 10 is as follows. (1-1) Formation of the lower heat dissipation circuit board 11: A lower insulating layer 103 is formed on the circuit side of the lower heat sink 101, opposite the heat dissipation side having the protrusions. An anode metal wiring layer 105, a cathode metal wiring layer 106, a cathode-side IGBT gate wiring layer 1061, and a cathode-side IGBT emitter wiring layer 1062 are then laminated on top of this. The lamination method may involve laminating one wiring layer and then patterning each wiring layer by etching or the like, or it may involve providing tie bars outside the lower insulating layer 103 to connect the wiring layers, and then cutting the tie bars after filling with resin as in (1-5) (see FIG. 5(A)). The circuit side of the lower heat sink 101, the lower insulating layer 103, and the metal wiring layer may be laminated separately, or all three layers may be laminated at once. In this embodiment, a high thermal conductivity insulating resin sheet is used as the lower insulating layer 103 on the lower heat sink 101. An insulating resin sheet with high thermal conductivity is laminated on the copper-based lower heat sink 101, and a copper plate is laminated on top of this and bonded together, after which an anode metal wiring layer 105, a cathode metal wiring layer 106, a cathode-side IGBT gate wiring layer 1061, and a cathode-side IGBT emitter wiring layer 1062 are formed by photoetching. (1-2) Formation of the upper heat dissipation circuit board 12: An upper insulating layer 104 is formed on the circuit side opposite to the heat dissipation side having the protruding portion of the upper heat sink 102, and an output electrode metal wiring layer 107, an anode side IGBT gate wiring layer 1071, and an anode side IGBT emitter wiring layer 1072 are stacked on top of this (see Figure 5(B)). (1-3) Bonding of anode-side semiconductor element: An anode side IGBT chip 201 and an anode side diode chip 203 are bonded to the anode metal wiring layer 105, and a conductor plate 113 is bonded to the main electrode and control electrode on the surface of each chip (see FIG. 5(A)). (1-4) Bonding of the cathode-side semiconductor element: The cathode side IGBT chip 202 and the cathode side diode chip 204 are bonded to the output electrode metal wiring layer 107, and the conductor plate 113 is bonded to the main electrode and control electrode on the surface of each chip (see FIG. 5(B)).

[0036] (1-5) Bonding the lower heat dissipation circuit board 11 and the upper heat dissipation circuit board 12: A high thermal conductivity insulating resin sheet 112, with the portions of the conductor plate 113 bonded onto the electrodes of the semiconductor chips hollowed out, is laminated on the lower heat dissipation circuit board 11. Thereafter, the lower heat dissipation circuit board 11 and the upper heat dissipation circuit board 12 are arranged facing each other with their heat dissipation surfaces facing outward and are brought into close contact with each other, so that the conductor plate 113 bonded to the anode side IGBT chip 201 and the anode side diode chip 203 is bonded to the output electrode metal wiring layer 107 and the anode side IGBT gate wiring layer 1071, and at the same time, the conductor plate 113 bonded to the cathode side IGBT chip 202 and the cathode side diode chip 204 is bonded to the cathode metal wiring layer 106 and the cathode side IGBT gate wiring layer 1061 (see FIGS. 4 and 5). In this embodiment, for the lower heat dissipation circuit board 11 and the upper heat dissipation circuit board 12, a highly thermally conductive insulating resin sheet 112 with holes drilled to match the shape of the conductor plate 113 to be installed is laid, solder is placed on the conductor plate 113, preheating is performed, and then the lower heat dissipation circuit board 11 and the upper heat dissipation circuit board 12 are overlapped and main heating is performed to bond the lower heat dissipation circuit board 11 and the upper heat dissipation circuit board 12. Note that instead of laying the insulating resin sheet 112, insulating resin may be potted. (1-6) Connection with external terminals: The anode metal wiring layer 105, the cathode metal wiring layer 106, and the output electrode metal wiring layer 107 have portions protruding in the surface direction (horizontal direction) that are connected to an anode external terminal 108, a cathode external terminal 109, and an output electrode external terminal 110, respectively. The cathode side IGBT gate wiring layer 1061, the cathode side IGBT emitter wiring layer 1062, the anode side IGBT gate wiring layer 1071, and the anode side IGBT emitter wiring layer 1072 have portions protruding in the horizontal direction that are connected to a control external terminal 111, and these joints are joined to external terminals by soldering, resistance welding, ultrasonic bonding, laser bonding, or the like (see FIG. 1). (1-7) Completion of semiconductor module 10: The lower heat sink 101, the upper heat sink 102, the anode external terminal 108, the cathode external terminal 109, and the output electrode external terminal 110 are filled with transfer molding insulating resin 114 to fix and hold them (see FIG. 1). The anode metal wiring layer 105, the cathode metal wiring layer 106, the output electrode metal wiring layer 107, and the conductor plate 113 may be formed of copper, tungsten, molybdenum, or an aluminum alloy. Soldering can be used to join the metal wiring layer to the back surface of the semiconductor chip, to join the electrode portion on the front surface of the semiconductor chip to the conductor plate 113, and to join the conductor plate 113 to the metal wiring layer.

[0037] [Second embodiment] The semiconductor module 10a of the second embodiment is different from the semiconductor module 10 of the first embodiment in that the cathode metal wiring layer 106 is joined onto the anode metal wiring layer 105 via an intermediate insulating layer 103a, thereby reducing the effective inductance of the anode metal wiring layer 105 and the cathode metal wiring layer 106. FIG. 7(A) is a schematic diagram of the state in which an anode-side semiconductor element is joined to the lower heat dissipation circuit board 11a of the semiconductor module 10a of the second embodiment, and FIG. 7(B) is a schematic diagram of the state in which a cathode-side semiconductor element is joined to the upper heat dissipation circuit board 12a of the semiconductor module 10a of the second embodiment. The structure of semiconductor module 10a in Fig. 7 will be described below, focusing on the differences from Fig. 5. In Fig. 5(A), anode metal wiring layer 105 and cathode metal wiring layer 106 are arranged spaced apart on the same plane on lower insulating layer 103, but in Fig. 7(A), anode metal wiring layer 105 is arranged on lower insulating layer 103, and cathode metal wiring layer 106 is arranged on anode metal wiring layer 105 via intermediate insulating layer 103a. 7B, the cathode-side IGBT (T2) 202 and the cathode-side diode (D2) 204 are arranged on the upper side, so that when the output is switched, a cathode-side power supply current flows from these chips to the cathode external terminal 109 through the cathode metal wiring layer 106, and an anode-side power supply current flows to the anode external terminal 108 through the anode metal wiring layer 105 below these chips. With this structure, when the output is switched, currents flow in opposite directions in the upper conductor (cathode metal wiring layer 106) and the lower conductor (anode metal wiring layer 105) in at least a portion of the anode metal wiring layer 105 and the cathode metal wiring layer 106, thereby reducing the effective inductance of the anode metal wiring layer 105 and the cathode metal wiring layer 106. The effect of this effective inductance reduction will be described later. The other components, such as the anode metal wiring layer 105, cathode metal wiring layer 106, output electrode metal wiring layer 107, cathode side IGBT gate wiring layer 1061, cathode side IGBT emitter wiring layer 1062, anode side IGBT gate wiring layer 1071, and anode side IGBT emitter wiring layer 1072, are arranged in the same manner as in FIG. 5. In FIG. 7, the protruding portion (denoted by P) of the anode metal wiring layer 105 and the protruding portion (denoted by N) of the cathode metal wiring layer 106 are spaced apart in the horizontal direction, but they may be arranged in the same position with the intermediate insulating layer 103a interposed therebetween.

[0038] FIG. 8 is a cross-sectional view taken along the line DD' in FIG. 8 with Figures 3(A) and (C), the difference is that the cathode metal wiring layer 106 is disposed on the intermediate insulating layer 103a, not on the lower insulating layer 103, but the cross section near the cathode side diode chip 204 and the anode side IGBT chip 201 is the same as in Figure 3. However, since the distance between the anode metal wiring layer 105 and the output electrode metal wiring layer 107 is larger than in Figure 3, the thickness of the conductor plate 113a above the anode side IGBT (T1) in Figure 8 is thicker than the conductor plate 113 above the anode side IGBT chip 201 in Figure 3(A) and the conductor plate 113 below the cathode side diode chip 204 in Figure 3(C).

[0039] (Difference in effective inductance due to the relative positions of the two electrode wiring) In the first embodiment, the anode metal wiring layer 105 and the cathode metal wiring layer 106 are arranged in parallel in the horizontal direction, whereas in the second embodiment, they are arranged so that they overlap at least partially. Furthermore, in the semiconductor modules 10 and 10a, when the output is switched, currents of approximately the same magnitude flow in opposite directions through the anode metal wiring layer 105 and the cathode metal wiring layer 106. In this case, a magnetic field is generated by the current flowing through the opposing metal wiring layers, and the effect of this magnetic field can reduce the effective wiring inductance. To verify this effect, the inductance of the metal wiring layer was calculated using the FDTD (Finite Difference Time Domain) method. The shapes of the wiring layers for which the inductance was calculated are shown in Figure 9. Note that in Figures 9(A) to 9(D) below, the dimensions of each wiring layer and the distance between each wiring layer differ from the actual wiring layers. 9(A) shows two wiring layers arranged side by side on the same plane, with power supplied from the bottom and short-circuited at the top. These two wiring layers correspond to the anode metal wiring layer 105 and cathode metal wiring layer 106 of the first embodiment. The two wiring layers are 15 mm wide, 20 mm long, and 1 mm thick, with a distance of 2 mm between them. Figure 9(B) shows a floating wiring layer superimposed on the two wiring layers of Figure 9(A). This floating wiring layer corresponds to the heat sink 101 or output electrode metal wiring layer 107 of the first embodiment. The floating layer is 32 mm wide, 20 mm long, and 1 mm thick, with a 1 mm gap between the two wiring layers. 9(C) shows two overlapping wiring layers, with power supplied from the bottom and short-circuited at the top. These two wiring layers correspond to the anode metal wiring layer 105 and cathode metal wiring layer 106 of the second embodiment. The two wiring layers are 15 mm wide, 20 mm long, and 1 mm thick, with a 1 mm gap between them. Figure 9(D) shows a floating wiring layer superimposed on the two wiring layers of Figure 9(C). This floating wiring layer corresponds to the heat sink 101 or output electrode metal wiring layer 107 of the second embodiment. The floating layer is 15 mm wide, 20 mm long, and 1 mm thick, and is spaced 1 mm apart from the upper wiring layer. Therefore, the shape of the metal wiring layer in the first embodiment corresponds to (B) of FIG. 9, and the shape of the metal wiring layer in the second embodiment corresponds to (D) of FIG.

[0040] The impedance of these shapes was calculated using the FDTD method, and the reactance X (the imaginary part of the impedance) was found at f = 500 MHz and 1.5 GHz. Reactance X is expressed in the following equation 1 using angular frequency w, inductance L, and capacitance C. Therefore, when X calculated at angular frequencies w1 and w2 is X1 and X2, respectively, inductance L can be calculated using the following equation 2. The values ​​of inductance L calculated using this method for the shapes (A), (B), (C), and (D) above are shown in Table 1.

[0041]

number

[0042]

number

[0043] [Table 1]

[0044] Comparing (B) in Table 1, which corresponds to the metal wiring layer of the first embodiment, with (D) in Table 1, which corresponds to the metal wiring layer of the second embodiment, the inductance of (D) is about 1 / 3 of that of (B). The second embodiment is slightly different from (D), in that there are some portions where the cathode metal wiring layer 106 is not stacked on the anode metal wiring layer 105, but in the portion where the cathode metal wiring layer 106 is stacked on the anode metal wiring layer 105, the inductance can be reduced to about 1 / 3. In addition, even in (B) which corresponds to the metal wiring layer of the first embodiment, the inductance can be reduced to about 3 / 4 by adding a floating layer which corresponds to the heat sink 101 or the output electrode metal wiring layer 107.

[0045] (Manufacturing process of semiconductor module 10a) The manufacturing process of the semiconductor module 10a of the second embodiment is the same as the manufacturing process of the semiconductor module 10 of the first embodiment, except for the following points. First, in the manufacturing process (1-1) of the semiconductor module 10 of the first embodiment, a lower insulating layer 103 is laminated on a lower heat sink 101, and an anode metal wiring layer 105, a cathode metal wiring layer 106, a cathode-side IGBT gate wiring layer 1061, and a cathode-side IGBT emitter wiring layer 1062 are laminated on the lower insulating layer 103. Meanwhile, in the manufacturing process (2-1) of the semiconductor module 10a of the second embodiment, the anode metal wiring layer 105 is laminated on the lower insulating layer 103, and then an intermediate insulating layer 103a is laminated thereon, and then the cathode metal wiring layer 106, the cathode-side IGBT gate wiring layer 1061, and the cathode-side IGBT emitter wiring layer 1062 are laminated on the intermediate insulating layer 103a (see FIG. 7). Furthermore, in the manufacturing process (1-3) of the semiconductor module 10 of the first embodiment, the conductor plate 113 is bonded to the surfaces of the anode-side IGBT chip 201 and the anode-side diode chip 203, whereas in the manufacturing process of the semiconductor module 10a of the second embodiment, the conductor plate 113a is bonded to the surfaces of the anode-side IGBT chip 201 and the anode-side diode chip 203. Both the conductor plate 113 and the conductor plate 113a connect the electrodes on the surfaces of the semiconductor chips to the opposing metal wiring layers. However, in the semiconductor module 10a of the second embodiment, the distance between the semiconductor chips and the opposing metal wiring layers is thicker than in the first embodiment by the thickness of the intermediate insulating layer 103a and the cathode metal wiring layer 106, and therefore the thickness of the conductor plate 113a is thicker by that amount (see FIG. 10 ). Furthermore, in the manufacturing process (1-5) of the semiconductor module 10 of the first embodiment, the distance between the anode metal wiring layer 105 and the output electrode metal wiring layer 107 and the distance between the cathode metal wiring layer 106 and the output electrode metal wiring layer 107 are the same, and the thickness of the insulating resin sheet 112 is also uniform, but in the second embodiment, the distance between the anode metal wiring layer 105 and the output electrode metal wiring layer 107 and the distance between the cathode metal wiring layer 106 and the output electrode metal wiring layer 107 are different, and therefore the thickness of the insulating resin sheet 112 differs between the portion laminated on the anode metal wiring layer 105 and the portion laminated on the cathode metal wiring layer 106.

[0046] In this embodiment, the lower heat dissipation circuit boards 11 and 11a correspond to the "lower heat dissipation circuit board", the upper heat dissipation circuit boards 12 and 12a correspond to the "upper heat dissipation circuit board", the lower heat dissipation plate 101 corresponds to the "lower heat dissipation plate", the upper heat dissipation plate 102 corresponds to the "upper heat dissipation plate", the anode metal wiring layer 105 corresponds to the "anode metal wiring layer", the cathode metal wiring layer 106 corresponds to the "cathode metal wiring layer", the output electrode metal wiring layer 107 corresponds to the "output electrode metal wiring layer", the anode side IGBT chip 201 and the anode side diode chip 203 correspond to the "anode side semiconductor element", the cathode side IGBT chip 202 and the cathode side diode chip 204 correspond to the "cathode side semiconductor element", and the conductor plates 113 and 113a correspond to the "anode side semiconductor element". the anode external terminal 108, the cathode external terminal 109, the output electrode external terminal 110, and the control external terminal 111 correspond to the "external terminals", the cathode-side IGBT gate wiring layer 1061 and the cathode-side IGBT emitter wiring layer 1062 correspond to the "cathode-side control electrode metal wiring layer", the anode-side IGBT gate wiring layer 1071 and the anode-side IGBT emitter wiring layer 1072 correspond to the "anode-side control electrode metal wiring layer", and the insulating resin sheet 112 and transfer molded insulating resin 114 correspond to the "insulating resin".

[0047] Although a preferred embodiment of the present invention has been described above, the present invention is not limited thereto. It will be understood that various other embodiments can be made without departing from the spirit and scope of the present invention. Furthermore, although the actions and effects of the configuration of the present invention are described in this embodiment, these actions and effects are merely examples and do not limit the present invention. [Explanation of symbols]

[0048] 10, 10a Semiconductor module 11, 11a Lower heat dissipation circuit board 12, 12a Upper heat dissipation circuit board 101 Lower heat sink 102 Upper heat sink 103 Lower insulating layer 103a Intermediate insulating layer 104 Upper insulating layer 105 Anode metal wiring layer 106 Cathode metal wiring layer 1061 Cathode side IGBT gate wiring layer 1062 Cathode side IGBT emitter wiring layer 107 Output metal wiring layer 1071 Anode side IGBT gate wiring layer 1072 Anode side IGBT emitter wiring layer 108 Anode external terminal 109 Cathode external terminal 110 Output pole external terminal 111 External control terminal 112 Insulating resin sheet 113, 113a Conductor plate 114 Transfer molding insulating resin 201 Anode side IGBT chip 202 Cathode side IGBT chip 203 Anode side diode chip 204 Cathode side diode chip

Claims

1. In a semiconductor module in which a semiconductor element is sandwiched between metal plates and cooled from both sides, The device comprises two substrates, a lower heat dissipation circuit substrate and an upper heat dissipation circuit substrate, which are opposed to each other; the lower heat dissipation circuit board is formed by laminating at least an anode metal wiring layer, a cathode metal wiring layer, and a cathode-side control electrode metal wiring layer on a heat dissipation plate with an insulating layer interposed therebetween, and the upper heat dissipation circuit board is formed by laminating at least an output electrode metal wiring layer and an anode-side control electrode metal wiring layer on a heat dissipation plate with an insulating layer interposed therebetween, an anode-side semiconductor element is bonded to the anode metal wiring layer, and a cathode-side semiconductor element is bonded to the output electrode metal wiring layer; the main electrodes and control electrodes on the surfaces of the anode-side semiconductor element and the cathode-side semiconductor element are connected to opposing metal wiring layers via conductor plates, 10. A semiconductor module, wherein the anode side control electrode metal wiring layer and the cathode side control electrode metal wiring layer are formed separately from main electrode metal wiring layers opposite to the respective semiconductor elements.

2. 2. The semiconductor module according to claim 1, wherein said anode metal wiring layer, said cathode metal wiring layer, and said cathode-side control electrode metal wiring layer are arranged on the same plane and spaced apart from one another.

3. 2. The semiconductor module according to claim 1, wherein said cathode metal wiring layer and said cathode-side control electrode metal wiring layer are stacked on said anode metal wiring layer via an insulating layer.

4. 4. The semiconductor module according to claim 2, wherein the anode metal wiring layer, the cathode metal wiring layer, the output electrode metal wiring layer, the anode-side control electrode metal wiring layer, and the cathode-side control electrode metal wiring layer each have a joint portion protruding in a planar direction and connected to an external terminal.

5. 4. The semiconductor module according to claim 2, wherein the lower heat dissipation circuit board and the upper heat dissipation circuit board face each other with the heat dissipation surfaces of the heat dissipation plates facing outward, the space between the lower heat dissipation circuit board and the upper heat dissipation circuit board is filled with insulating resin, and the lower heat dissipation circuit board and the upper heat dissipation circuit board are fixed and held by the insulating resin with their respective heat dissipation surfaces protruding.

Images