Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device in which a crystal defect region is locally formed, and a manufacturing method thereof.SOLUTION: A semiconductor device includes a first electrode, a semiconductor layer provided on the first electrode, and a second electrode provided on the semiconductor layer. The semiconductor layer includes a first semiconductor layer of a first conductivity type containing a rare earth element, and a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, in contact with the first semiconductor layer, and electrically connected to the second electrode. The first semiconductor layer has an impurity region located between the second semiconductor layer and the first electrode, and a crystal defect region located between the impurity region and the first electrode and containing crystal defects. The concentration peak of the rare earth element is in the impurity region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Power loss in power semiconductor devices can be divided into conduction loss and switching loss from a functional perspective. These losses are generally in a trade-off relationship. Reducing switching loss is particularly important in diodes, and for this reason, the lifetime of the drift layer is often controlled. However, this also increases the forward voltage drop, which causes the problem of worsening conduction loss. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5036569 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a semiconductor device in which a crystal defect region is locally formed, and a method for manufacturing the same. [Means for solving the problem]

[0005] According to an embodiment, a semiconductor device includes a first electrode, a semiconductor layer provided on the first electrode, and a second electrode provided on the semiconductor layer. The semiconductor layer includes a first semiconductor layer of a first conductivity type containing a rare earth element, and a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, in contact with the first semiconductor layer, and electrically connected to the second electrode. The first semiconductor layer includes an impurity region located between the second semiconductor layer and the first electrode, and a crystal defect region located between the impurity region and the first electrode and containing crystal defects. A concentration peak of the rare earth element is located in the impurity region. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] 2A to 2C are schematic cross-sectional views showing a method for manufacturing the semiconductor device of the first embodiment. [Figure 3] 2A to 2C are schematic cross-sectional views showing a method for manufacturing the semiconductor device of the first embodiment. [Figure 4] 2A to 2C are schematic cross-sectional views showing a method for manufacturing the semiconductor device of the first embodiment. [Figure 5] FIG. 10 is a circuit diagram showing a configuration of a semiconductor device according to a second embodiment. [Figure 6] FIG. 10 is a schematic cross-sectional view of a diode portion in a semiconductor device according to a second embodiment. [Figure 7] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 8] 5A to 5C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] In diodes, switching loss, i.e., loss during reverse recovery, is a major problem, even more so than conduction loss. Forming a low-lifetime layer in the semiconductor layer (drift layer) is an effective way to reduce switching loss in diodes. The low-lifetime layer can reduce switching loss by promoting the recombination of carriers remaining in the drift layer during reverse recovery. However, the introduction of a low-lifetime layer increases the forward voltage drop of the diode, which is a factor in increasing conduction loss. For this reason, efforts are ongoing to find conditions that reduce the impact on conduction loss.

[0008] The main methods for forming low-lifetime layers are electron beam, H, He, etc. irradiation (Method 1) and doping with precious metals such as Au and Pt that create deep levels (Method 2). However, the lifetime layers formed by these methods are widely distributed in the depth direction, reducing the lifetime across almost the entire drift layer and inevitably affecting conduction loss. In addition, Method 1 has low thermal and process stability, requiring thinning the wafer and irradiating it from both the front and back sides with high acceleration voltages in the final device fabrication process. This requires a difficult and expensive backside process. Furthermore, it is unstable due to the light element impurity density in the wafer. Method 2 uses elements with high diffusion rates in silicon, making it impossible to form a low-lifetime layer locally not only in the depth direction but also in the planar direction. Therefore, in an insulated gate bipolar transistor (IGBT) (RC-IGBT), which integrates an IGBT and a diode into a single device, this method may impair the IGBT's performance.

[0009] As explained above, lifetime control technology, which promotes carrier recombination by forming a low-lifetime layer in the drift layer, is effective in reducing switching loss, but in reality, it achieves this reduction while allowing for increased conduction loss. Furthermore, the many process constraints hinder cost reduction.

[0010] Hereinafter, embodiments will be described with reference to the drawings. Note that the same components in each drawing are assigned the same reference numerals. In the drawings shown below, directions are indicated by the X-axis, Y-axis, and Z-axis. The direction along the X-axis is the first direction X. The direction along the Z-axis is the second direction Z, which is perpendicular to the first direction X. The direction along the Y-axis is the third direction Y, which is perpendicular to the first direction X and the second direction Z.

[0011] [First embodiment] FIG. 1 shows a diode as a semiconductor device 1 of the first embodiment.

[0012] The semiconductor device 1 includes a first electrode 31, a second electrode 32, and a semiconductor layer 10 provided between the first electrode 31 and the second electrode 32 in the second direction Z. The first electrode 31 is a cathode electrode of the diode, and the second electrode 32 is an anode electrode of the diode. A current flows vertically (in the second direction Z) between the first electrode 31 and the second electrode 32 through the semiconductor layer 10. In the second direction Z, the direction from the first electrode 31 to the second electrode 32 is defined as up or upward, and the direction from the second electrode 32 to the first electrode 31 is defined as down or downward.

[0013] The semiconductor layer 10 is, for example, a silicon layer. In this specification, the first conductivity type of the semiconductor layer 10 is defined as n-type, and the second conductivity type is defined as p-type. Note that the first conductivity type may be p-type, and the second conductivity type may be n-type.

[0014] The semiconductor layer 10 has an n-type first semiconductor layer 11 provided on a first electrode 31, and a p-type second semiconductor layer 12 provided on the first semiconductor layer 11. The second semiconductor layer 12 is in contact with the first semiconductor layer 11, and the second semiconductor layer 12 and the first semiconductor layer 11 form a p-n junction 41. A second electrode 32 is provided on the second semiconductor layer 12. The second semiconductor layer 12 is in contact with the second electrode 32 and is electrically connected to the second electrode 32.

[0015] The semiconductor layer 10 further includes an n-type third semiconductor layer 13 provided between the first electrode 31 and the first semiconductor layer 11 in the second direction Z. The n-type impurity concentration of the third semiconductor layer 13 is higher than the n-type impurity concentration of the first semiconductor layer 11. The third semiconductor layer 13 is in contact with the first electrode 31 and is electrically connected to the first electrode 31.

[0016] The first semiconductor layer 11 serves as a drift layer in the diode, the second semiconductor layer 12 serves as an anode layer in the diode, and the third semiconductor layer 13 serves as a cathode layer in the diode.

[0017] The first semiconductor layer 11 contains a rare earth element. The first semiconductor layer 11 contains, for example, a lanthanoid element as the rare earth element. Examples of the lanthanoid element contained in the first semiconductor layer 11 include erbium (Er) and thulium (Tm).

[0018] The first semiconductor layer 11 has an impurity region 21 and a crystal defect region 22 containing crystal defects. In the first semiconductor layer 11, a concentration peak of the rare earth element is in the impurity region 21. In the first semiconductor layer 11, a density peak of the crystal defects is in the crystal defect region 22.

[0019] The impurity region 21 is located between the second semiconductor layer 12 and the crystal defect region 22 in the second direction Z. The impurity region 21 is located below the second semiconductor layer 12. That is, the concentration peak of the rare earth element is located below the pn junction 41 between the second semiconductor layer 12 and the first semiconductor layer 11. The crystal defect region 22, which has a density peak of crystal defects, is located between the impurity region 21 and the first electrode 31 in the second direction Z.

[0020] Crystal defect region 22 has a high density of crystal defects (stacking faults, dislocation defects, etc.). Because crystal defects act as carrier recombination centers, crystal defect region 22 functions as a lifetime control region. Crystal defect region 22 promotes the recombination of carriers injected from the anode and remaining in first semiconductor layer 11 (drift layer) when semiconductor device 1 is turned off. This suppresses and quickly reduces reverse recovery current, thereby reducing switching loss.

[0021] Furthermore, according to this embodiment, as will be described later, the crystal defect region 22 can be formed locally at a necessary position in the first semiconductor layer 11. This makes it possible to reduce switching loss while suppressing conduction loss of the diode.

[0022] Next, a method for manufacturing the semiconductor device 1 of the first embodiment will be described with reference to FIGS.

[0023] The manufacturing method of the semiconductor device 1 of the first embodiment includes a step of implanting a rare earth element into a first semiconductor layer 11 (silicon substrate) to form an amorphous region 20A in the first semiconductor layer 11, as shown in Fig. 2. In Fig. 2, the amorphous region 20A is shown as a shaded region. An impurity region 21 having a concentration peak of the rare earth element is located near the average stop depth Rp of the rare earth element.

[0024] A region is limited from the surface of the first semiconductor layer 11, and the first semiconductor layer 11 is irradiated with 1×10 14 cm -2 Er ions are implanted at a dose of 1000 .mu.m / s. In the first semiconductor layer 11, the silicon crystal in the region where Er is implanted becomes amorphous.

[0025] Rare earth elements are located at lattice points in silicon crystals and exhibit a stable four-coordination. Rare earth elements are not as heavy as noble metals, but are heavier than the elements used to control the conductivity type of silicon. Crystal damage caused by ion implantation occurs when the implanted ions displace silicon atoms at lattice points. When many silicon atoms are displaced from their lattice positions, the silicon crystal becomes amorphous. The number of silicon atoms displaced is greatly affected by the ion implantation conditions, such as the implantation dose and acceleration voltage, as well as the weight of the implanted element. Elements such as B and P are light, so the silicon crystal in the implanted area almost never becomes amorphous, but ion implantation of rare earth elements easily causes amorphous formation.

[0026] The method for manufacturing the semiconductor device 1 of the first embodiment includes a first heat treatment step after forming the amorphous region 20A by ion implantation of a rare earth element. The first heat treatment step crystallizes the amorphous region 20A, and also forms a crystal defect region 22 below the region 20C crystallized from the amorphous region 20A, as shown in FIG.

[0027] In the first heat treatment step, for example, heat treatment is performed at 950°C for 30 minutes in a nitrogen (N2) atmosphere. As a result, amorphous region 20A is recrystallized to become region 20C without crystal defects. At the same time, crystal defect region 22, where crystal defects exist at a high density, is formed below the boundary between amorphous region 20A and the underlying crystalline region 20B that was not amorphized.

[0028] The interstitial silicon displaced by ion implantation diffuses within the semiconductor layer during subsequent heat treatment at around 1000°C, generating and stabilizing crystal defects such as stacking faults. The region of crystal defects formed after heat treatment varies depending on whether the ion-implanted region has been amorphized. If amorphization does not occur, crystal defects remain over a wide range in the depth direction (thickness direction of the semiconductor layer), centered on the average stopping depth Rp of the implanted ions. The amount of remaining crystal defects is significantly affected by the heat treatment temperature, with the amount of remaining crystal defects being small at temperatures above 1000°C.

[0029] On the other hand, when the amorphous structure is formed by ion implantation, the boundary between amorphous region 20A and the underlying crystalline region 20B separates amorphous region 20A into region 20C recrystallized by the first heat treatment and crystal defect region 22. In region 20B that remains crystalline, excess silicon atoms diffuse into a relatively narrow region deeper than the amorphous / crystalline boundary, causing crystal defects to aggregate. The amount of crystal defects in crystal defect region 22 is affected by the heat treatment temperature, but the crystal defects once generated in crystal defect region 22 are stable and do not change much.

[0030] As described above, according to this embodiment, the amorphous region 20A can be easily formed by ion implantation of a heavy rare-earth element. As a result, the crystal defect region 22 can be locally formed in a region deeper than the average stop depth Rp of the implanted ions. This makes it possible to reduce switching loss while suppressing conduction loss of the diode.

[0031] The manufacturing method of the semiconductor device 1 of the first embodiment further includes a step of injecting p-type impurities into the first semiconductor layer 11 after forming the crystal defect region 22, and a step of forming a p-type second semiconductor layer 12 located above the crystal defect region 22 by a second heat treatment, as shown in FIG.

[0032] In the step of implanting p-type impurities into the first semiconductor layer 11, for example, a region is limited from the surface of the first semiconductor layer 11, and the first semiconductor layer 11 is implanted at an acceleration voltage of 70 keV and a fluence of 1×10 14 cm -2 In the second heat treatment step, for example, heat treatment is performed in a nitrogen (N2) atmosphere at 950° C. for 30 minutes.

[0033] The method for manufacturing the semiconductor device 1 of the first embodiment includes the step of forming the second electrode 32 on the second semiconductor layer 12 after forming the second semiconductor layer 12.

[0034] The manufacturing method of the semiconductor device 1 of the first embodiment includes the steps of forming the second electrode 32, then, if necessary, grinding the back surface of the first semiconductor layer 11 (silicon substrate) to thin the first semiconductor layer 11 (silicon substrate), and then forming the third semiconductor layer 13 and the first electrode 31.

[0035] In the above embodiment, the first heat treatment after the ion implantation of the rare earth element and the second heat treatment after the ion implantation of the p-type impurity are performed separately, but the first heat treatment and the second heat treatment can also be performed simultaneously as the same heat treatment. Furthermore, the ion implantation of the p-type impurity may be performed after the ion implantation of the rare earth element, or the ion implantation of the p-type impurity may be performed after the ion implantation of the rare earth element. The second semiconductor layer 12 can also be formed before the ion implantation of the rare earth element.

[0036] [Second embodiment] 5, the semiconductor device 2 of the second embodiment includes a transistor section 50 and a diode section 60. The semiconductor device 2 is, for example, an RC-IGBT in which the transistor section 50 and the diode section 60 are fabricated in the same semiconductor layer and integrated into a single chip.

[0037] The transistor section 50 has a collector electrode 51, an emitter electrode 52, and a gate electrode 53. The diode section 60 is connected in parallel to the transistor section 50. The anode of the diode section 60 is connected to the emitter electrode 52, and the cathode of the diode section 60 is connected to the collector electrode 51.

[0038] FIG. 6 is a schematic cross-sectional view of the diode section 60. As shown in FIG.

[0039] The diode section 60 includes a first electrode 91, a second electrode 92, and a semiconductor layer 70 provided between the first electrode 91 and the second electrode 92 in the second direction Z. The first electrode 91 is a cathode electrode in the diode section 60 and also serves as a collector electrode 51 in the transistor section 50. The second electrode 92 is an anode electrode in the diode section 60 and also serves as an emitter electrode 52 in the transistor section 50. A current flows between the first electrode 91 and the second electrode 92 in the vertical direction (second direction Z) through the semiconductor layer 70.

[0040] The semiconductor layer 70 is, for example, a silicon layer. The semiconductor layer 70 has an n-type first semiconductor layer 71 provided on a first electrode 91, and a p-type second semiconductor layer 72 provided on the first semiconductor layer 71. The second semiconductor layer 72 is in contact with the first semiconductor layer 71, and the second semiconductor layer 72 and the first semiconductor layer 71 form a p-n junction. A second electrode 92 is provided on the second semiconductor layer 72. The second semiconductor layer 72 is in contact with the second electrode 92 and is electrically connected to the second electrode 92.

[0041] The semiconductor layer 70 further includes an n-type third semiconductor layer 73 provided between the first electrode 91 and the first semiconductor layer 71 in the second direction Z. The n-type impurity concentration of the third semiconductor layer 73 is higher than the n-type impurity concentration of the first semiconductor layer 71. The third semiconductor layer 73 is in contact with the first electrode 91 and is electrically connected to the first electrode 91.

[0042] In the transistor section 50, a p-type collector layer is provided between the first electrode 91 and the first semiconductor layer 71.

[0043] The diode section 60 further has a plurality of trench structures 100 extending in the second direction Z from the surface of the semiconductor layer 70 and reaching the first semiconductor layer 71. The plurality of trench structures 100 are aligned in the first direction X and extend in the third direction Y. The second semiconductor layer 72 is located between the trench structures 100 adjacent to each other in the first direction X.

[0044] The trench structure 100 has a conductive member 111 and an insulating film 112 provided between the conductive member 111 and the semiconductor layer 70. The upper end of the conductive member 111 is connected to the second electrode 92, and the conductive member 111 is electrically connected to the second electrode 92. The lower end of the trench structure 100 and the lower end of the conductive member 111 are located below the pn junction between the second semiconductor layer 72 and the first semiconductor layer 71. The conductive member 111 can be made of, for example, polycrystalline silicon or a metal. The insulating film 112 is, for example, a silicon oxide film.

[0045] The transistor section 50 also has a plurality of trench structure sections 100 arranged therein, similar to the diode section 60. However, the conductive member 111 of the transistor section 50 is not connected to the second electrode 92 and functions as a gate electrode in the IGBT.

[0046] The first semiconductor layer 71 includes a rare earth element. The first semiconductor layer 71 includes, as the rare earth element, a lanthanoid element, for example. Examples of the lanthanoid element included in the first semiconductor layer 71 include erbium (Er) and thulium (Tm).

[0047] The first semiconductor layer 71 has an impurity region 81 and a crystal defect region 82 containing crystal defects. In the first semiconductor layer 71, a concentration peak of the rare earth element is in the impurity region 81. In the first semiconductor layer 71, a density peak of the crystal defects is in the crystal defect region 82.

[0048] The impurity region 81 is located between the trench structure 100 and the crystal defect region 82, and between the second semiconductor layer 72 and the crystal defect region 82, in the second direction Z. The impurity region 81 is located below the second semiconductor layer 72. That is, the concentration peak of the rare earth element is located below the pn junction between the second semiconductor layer 72 and the first semiconductor layer 71. The crystal defect region 82, which has a density peak of crystal defects, is located between the impurity region 81 and the first electrode 91 in the second direction Z. In the drawing, the impurity region 81 and the crystal defect region 82 are not connected to each other in the first direction X, but they may be connected, and a concentration distribution may exist in the first direction X.

[0049] The crystal defect region 82 promotes recombination of carriers injected from the anode and remaining in the first semiconductor layer 71 (drift layer) when the semiconductor device 2 is turned off. This suppresses and quickly reduces the reverse recovery current, thereby reducing switching loss.

[0050] Also in this embodiment, the crystal defect regions 82 can be formed locally at necessary positions in the first semiconductor layer 71. This makes it possible to reduce switching loss while suppressing conduction loss of the diode.

[0051] 6, the crystal defect region 82 is located in the first semiconductor layer 71 below the second semiconductor layer 72 in a region below the trench structure 100 (including not only the region directly below the trench structure 100 but also the region below the second semiconductor layer 72). The crystal defect region 82 may be continuous in the first direction X in the region below the trench structure 100. Alternatively, the crystal defect region 82 may not be located directly below the trench structure 100 in the region below the trench structure 100, but may be located only below the second semiconductor layer 72. Alternatively, the crystal defect region 82 may be located between adjacent trench structures 100 in the first direction X.

[0052] When the crystal defect region 82 is located in a region below the trench structure 100 , carriers tend to recombine more efficiently than when it is located between the trench structures 100 .

[0053] Next, a method for manufacturing the semiconductor device 2 of the second embodiment will be described with reference to FIGS.

[0054] 7, a plurality of trenches T are formed in a first semiconductor layer 71 (silicon substrate). The plurality of trenches T are aligned in a first direction X and extend in a third direction Y. For example, the plurality of trenches T can be formed by a reactive ion etching (RIE) method using a mask of an interlayer film covering the first semiconductor layer 71.

[0055] After forming the trench T while leaving the interlayer film mask covering the first semiconductor layer 71, a rare earth element is implanted into the first semiconductor layer 71 in the same manner as in the first embodiment to form an amorphous region directly below the trench T in the first semiconductor layer 71. A region is limited from the surface of the first semiconductor layer 71, and an accelerating voltage of, for example, 70 keV and 1×10 15 cm -2 Er ions are implanted at a dose of 1000 .mu.m / s. In the first semiconductor layer 71, the silicon crystal in the region where Er is implanted becomes amorphous.

[0056] After the amorphous region is formed, a first heat treatment is performed in the same manner as in the first embodiment. The first heat treatment crystallizes the amorphous region, and a crystal defect region 82 is formed below the region that has been crystallized from the amorphous region, as shown in Fig. 8. An impurity region 81 having a concentration peak of the rare earth element is located near the average stop depth Rp of the rare earth element.

[0057] In the second embodiment, too, an amorphous region can be easily formed by ion implantation of a heavy rare-earth element. As a result, it is possible to locally form the crystal defect region 82 in a region deeper than the average stop depth Rp of the implanted ions. This makes it possible to reduce switching loss while suppressing conduction loss in the diode.

[0058] After the crystal defect region 82 is formed, an insulating film 112 is formed on the inner wall of the trench T by, for example, thermal oxidation. After the insulating film 112 is formed, a conductive member 111 is embedded in the trench T by, for example, CVD (Chemical Vapor Deposition).

[0059] Alternatively, after forming the insulating film 112 and the conductive member 111 in the trench T, the amorphous region may be formed by ion implantation of a rare earth element, and the crystal defect region 82 may be formed by the first heat treatment.

[0060] After forming the trench structure including the insulating film 112 and the conductive member 111, similar to the first embodiment, the following steps are performed: forming a second semiconductor layer 72 by ion implantation of p-type impurities and a second heat treatment; forming a second electrode 92; forming a third semiconductor layer 73; and forming a first electrode 91.

[0061] In the above-described embodiments, Er is used as the rare earth element, but similar effects can be obtained by using other rare earth elements such as Tm. The ion implantation conditions and heat treatment conditions are given as examples and can be optimized accordingly. The crystal defect regions 22 and 82 are formed below the average stopping depth Rp of the implanted rare earth element. The distance between Rp and the crystal defect regions 22 and 82 can be adjusted by the heat treatment conditions, etc., and it is possible to change the distance between Rp and the crystal defect regions 22 and 82 from a state in which they are almost in contact to a state in which they are separated by about 1 μm.

[0062] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0063] REFERENCE SIGNS LIST 1, 2... semiconductor device, 10... semiconductor layer, 11... first semiconductor layer, 12... second semiconductor layer, 13... third semiconductor layer, 21... impurity region, 22... crystal defect region, 31... first electrode, 32... second electrode, 20A... amorphous region, 50... transistor portion, 51... collector electrode, 52... emitter electrode, 60... diode portion, 70... semiconductor layer, 71... first semiconductor layer, 72... second semiconductor layer, 73... third semiconductor layer, 81... impurity region, 82... crystal defect region, 91... first electrode, 92... second electrode, 111... conductive member, 112... insulating film, 100... trench structure portion

Claims

1. A first electrode; a semiconductor layer provided on the first electrode; a second electrode provided on the semiconductor layer; Equipped with The semiconductor layer is a first semiconductor layer of a first conductivity type containing a rare earth element; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, in contact with the first semiconductor layer, and electrically connected to the second electrode; and the first semiconductor layer has an impurity region located between the second semiconductor layer and the first electrode, and a crystal defect region located between the impurity region and the first electrode and including crystal defects; The semiconductor device has a concentration peak of the rare earth element in the impurity region.

2. 2. The semiconductor device according to claim 1, wherein the density peak of the crystal defects is in the crystal defect region.

3. a plurality of trench structures extending from a surface of the semiconductor layer to the first semiconductor layer and aligned in a first direction; The semiconductor device according to claim 1 , wherein the second semiconductor layer is located between the trench structures adjacent to each other in the first direction.

4. 4. The semiconductor device according to claim 3, wherein the crystal defect region is located below the second semiconductor layer in a region below the trench structure.

5. The semiconductor device according to claim 3 , wherein said trench structure portion has a conductive member electrically connected to said second electrode.

6. 6. The semiconductor device according to claim 1, wherein the rare earth element is a lanthanoid element.

7. implanting a rare earth element into a first semiconductor layer of a first conductivity type to form an amorphous region in the first semiconductor layer; a step of crystallizing the amorphous region and forming a crystal defect region below the crystallized region by a first heat treatment; A method for manufacturing a semiconductor device, comprising:

8. implanting a second conductivity type impurity into the first semiconductor layer before or after implanting the rare earth element into the first semiconductor layer; forming a second semiconductor layer of a second conductivity type located above the crystal defect region by a second heat treatment; The method for manufacturing a semiconductor device according to claim 7 , further comprising:

Images