Semiconductor device and power conversion apparatus

Abstract

To provide a semiconductor device having improved reliability in insulation performance and reduced inductance of a current path.SOLUTION: A semiconductor device includes a semiconductor element 4, a first electrode 7, a second electrode 8, and an insulating material 9. The first electrode 7 includes a first contact surface 7A that extends. The second electrode 8 includes a second contact surface 8A that is disposed so as to face the first contact surface 7A and extend in parallel with the first contact surface 7A. The insulating material 9 is disposed between the first electrode 7 and the second electrode 8. The insulating material 9 extends between the first contact surface 7A and the second contact surface 8A, and is in contact with both of them. The first electrode 7 includes a first corner portion 7B located at an end of the first contact surface 7A in a width direction. The second electrode 8 includes a second corner portion 8B located at an end of the second contact surface 8A in the width direction. Each of the first corner portion 7B and the second corner portion 8B includes either a chamfered section 12 or a sag section 14.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a power conversion device. [Background technology]

[0002] In a semiconductor device in which a positive terminal and a negative terminal are arranged parallel to each other and the same current flows through the positive terminal and the negative terminal in opposite directions, the inductance of the current path is reduced (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-213408 Summary of the Invention [Problem to be solved by the invention]

[0004] In semiconductor devices with an insulating material between two electrodes, the inductance of the current path can be reduced while the distance between the electrodes is reduced. However, depending on the shape of the electrodes, the insulating material may be damaged by the electrodes, resulting in a deterioration of the insulating properties.

[0005] In order to solve the above-mentioned problems, an object of the present disclosure is to provide a semiconductor device in which the reliability of insulation performance is improved and the inductance of the current path is reduced. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure includes a semiconductor element, a first electrode, a second electrode, and an insulating material. The first electrode includes an extending first contact surface and is electrically connected to the semiconductor element. The second electrode includes a second contact surface facing the first contact surface and extending parallel to the first contact surface. The second electrode is electrically connected to the semiconductor element. The insulating material is provided between the first electrode and the second electrode. The insulating material extends between and contacts the first contact surface and the second contact surface. The first electrode includes a first corner located at an end of the first contact surface in the width direction. The second electrode includes a second corner located at an end of the second contact surface in the width direction. Each of the first corner and the second corner includes either a chamfered portion or a sagging portion. [Effects of the Invention]

[0007] According to the present disclosure, a semiconductor device is provided in which the reliability of insulation performance is improved and the inductance of the current path is reduced.

[0008] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a perspective view showing the configuration of a first electrode, a second electrode, and an insulating material. [Figure 3] FIG. 2 is a cross-sectional view showing the configuration of a first electrode, a second electrode, and an insulating material. [Figure 4] 10 is a cross-sectional view showing the configuration of an insulating material disposed between a first electrode and a second electrode on which a burr portion is formed. FIG. [Figure 5] 10 is a cross-sectional view showing the configuration of a first electrode, a second electrode, and an insulating material in the second embodiment. FIG. [Figure 6] 10 is a cross-sectional view showing the configuration of a first electrode, a second electrode, and an insulating material in the third embodiment. FIG. [Figure 7]10 is a cross-sectional view showing the configuration of a first electrode, a second electrode, and an insulating material in accordance with a fourth embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] <First Embodiment> FIG. 1 is a diagram showing the configuration of a semiconductor device in embodiment 1. The semiconductor device includes a base plate 1, an insulating substrate 2, a metal pattern 3, a semiconductor element 4, a case 5, a metal wire 6, a first electrode 7 and a second electrode 8 which are main electrodes, an electrode 15 which is another main electrode, an insulating material 9, and a sealing material 10. FIG. 2 is a perspective view showing the configuration of the first electrode 7, the second electrode 8, and the insulating material 9. FIG. 3 is a cross-sectional view showing the configuration of the first electrode 7, the second electrode 8, and the insulating material 9. FIG. 3 shows a cross section taken along plane A shown in FIG. 2.

[0011] The base plate 1 is a plate made of a metal such as copper or aluminum, or a plate made of an AlSiC composite material.

[0012] The insulating substrate 2 is provided on the base plate 1. The insulating substrate 2 may be an insulating film formed on the base plate 1. The insulating substrate 2 is made of, for example, resin, ceramic, or the like.

[0013] The metal pattern 3 is provided on the upper surface of the insulating substrate 2. The metal pattern 3 is made of, for example, copper.

[0014] The semiconductor element 4 is mounted on the metal pattern 3 via a bonding material 11. The bonding material 11 is a conductive material such as solder. The semiconductor element 4 is formed of a semiconductor such as Si. The semiconductor element 4 is preferably formed of a wide bandgap semiconductor such as SiC or GaN. The semiconductor element 4 is a power semiconductor element, a control IC (Integrated Circuit) for controlling the power semiconductor element, or the like. The semiconductor element 4 includes, for example, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a Schottky barrier diode, or the like. Alternatively, the semiconductor element 4 may include an RC-IGBT (Reverse-Conducting IGBT) in which an IGBT and a freewheeling diode are formed within a single semiconductor chip.

[0015] The case 5 has a rectangular frame body in a plan view. The case 5 accommodates the semiconductor element 4 and the like inside the frame body. The case 5 is made of, for example, resin.

[0016] The metal wire 6 connects any two of the semiconductor element 4, the terminal, and the metal pattern 3. The terminal includes the first electrode 7 and the second electrode 8.

[0017] The first electrode 7 and the second electrode 8 are electrically connected to the semiconductor element 4. In the first embodiment, the first electrode 7 and the second electrode 8 are electrically connected to the semiconductor element 4 via the metal pattern 3 or the metal wire 6. The first electrode 7 and the second electrode 8 are main electrodes of the semiconductor device. If the semiconductor element 4 is an IGBT, the first electrode 7 and the second electrode 8 are electrically connected to the emitter and the collector, respectively. The first electrode 7 and the second electrode 8 are metal plates formed by processing a flat plate made of metal such as copper into a predetermined shape. A portion of the first electrode 7 and the second electrode 8 may be embedded and fixed in the case 5.

[0018] As shown in FIG. 3 , the first electrode 7 includes a first contact surface 7A and a first corner 7B. The first corner 7B is located at the end of the first contact surface 7A in the width direction. The width direction is a direction intersecting the extension direction of the first electrode 7, and in the first embodiment, the width direction is a direction perpendicular to the extension direction. The second electrode 8 includes a second contact surface 8A and a second corner 8B. The second contact surface 8A faces the first contact surface 7A and extends parallel to the first contact surface 7A. The second corner 8B is located at the end of the second contact surface 8A in the width direction. Each of the first corner 7B and the second corner 8B includes a chamfered portion 12. The chamfered portion 12 is formed by chamfering. In the first embodiment, each of the first corner 7B and the second corner 8B includes a chamfered portion 12. The chamfered portion 12 may be a C-chamfer or an R-chamfer.

[0019] The insulating material 9 is provided between the first electrode 7 and the second electrode 8. In the first embodiment, the insulating material 9 is an insulating sheet 9A. The insulating sheet 9A extends between and contacts the first contact surface 7A and the second contact surface 8A. However, the insulating sheet 9A does not contact the chamfered portion 12 of the first corner 7B or the chamfered portion 12 of the second corner 8B. The thickness of the insulating sheet 9A is, for example, 0.05 mm or less. In this way, the first contact surface 7A of the first electrode 7 and the second contact surface 8A of the second electrode 8 are arranged parallel to and close to each other with the insulating material 9 interposed therebetween.

[0020] 1, the sealing material 10 fills the space inside the frame of the case 5. The sealing material 10 seals the semiconductor element 4, a portion of the first electrode 7, a portion of the second electrode 8, a portion of the electrode 15, etc. The sealing material 10 is, for example, a silicone resin, an epoxy resin, or the like.

[0021] The first electrode 7 and the second electrode 8 in the first embodiment are formed by press working. As a result of the press working, burrs are formed at the first corner 7B of the first electrode 7 and the second corner 8B of the second electrode 8. FIG. 4 is a cross-sectional view showing the configuration of the insulating material 9 disposed between the first electrode 7 and the second electrode 8, on which burrs 13 are formed. If burrs 13 are formed, the insulating material 9 is likely to be damaged by the burrs 13. In the semiconductor device of the first embodiment, the burrs 13 are removed by chamfering. As shown in FIG. 3, chamfered portions 12 are formed at the first corner 7B and the second corner 8B. As a result, deterioration of the insulating performance is reduced, and the reliability and performance of the semiconductor device are improved.

[0022] In summary, the semiconductor device according to the first embodiment includes a semiconductor element 4, a first electrode 7, a second electrode 8, and an insulating material 9. The first electrode 7 includes an extending first contact surface 7A and is electrically connected to the semiconductor element 4. The second electrode 8 includes a second contact surface 8A that faces the first contact surface 7A and extends parallel to the first contact surface 7A. The second electrode 8 is electrically connected to the semiconductor element 4. The insulating material 9 is provided between the first electrode 7 and the second electrode 8. The insulating material 9 extends between and is in contact with the first contact surface 7A and the second contact surface 8A. The first electrode 7 includes a first corner 7B located at an end in the width direction of the first contact surface 7A. The second electrode 8 includes a second corner 8B located at an end in the width direction of the second contact surface 8A. Each of the first corner 7B and the second corner 8B includes a chamfered portion 12.

[0023] This configuration prevents the insulating sheet 9A from being damaged by burrs 13 that are generated during the press working of the first electrode 7 and the second electrode 8. This reduces insulation defects and improves the reliability and performance of the insulating performance of the semiconductor device.

[0024] Furthermore, the distance between the first electrode 7 and the second electrode 8 is reduced, which reduces the internal inductance and improves the performance of the semiconductor device. If the thickness of the insulating sheet 9A is 0.05 mm or less, the inductance is further reduced.

[0025] Since the semiconductor element 4 is made of a wide bandgap semiconductor, the accuracy of overcurrent protection is improved and the semiconductor device can be made smaller.

[0026] The semiconductor device of the first embodiment can be applied to a power converter. For example, the power converter includes at least one of the semiconductor devices described above. This allows the power converter to be miniaturized. Examples of the power converter include an inverter, a converter, a servo amplifier, and a power supply unit.

[0027] <Embodiment 2> 5 is a cross-sectional view showing the configuration of the first electrode 7, the second electrode 8, and the insulating material 9 in the second embodiment. Each of the first corner portion 7B and the second corner portion 8B includes a sagging portion 14. In other words, the first contact surface 7A and the second contact surface 8A are formed as sagging surfaces including the sagging portion 14. The sagging portion 14 is formed by press working.

[0028] The insulating material 9 in the second embodiment is an insulating sheet 9A. The insulating sheet 9A is in contact with the first contact surface 7A and the second contact surface 8A. On the other hand, the insulating sheet 9A is not in contact with the sagging portion 14 of the first corner 7B or the sagging portion 14 of the second corner 8B.

[0029] According to this configuration, there is no need for processing to remove burrs 13 generated by press processing. In addition to the effects of the first embodiment, the number of steps in the manufacturing process of the semiconductor device is reduced, improving productivity.

[0030] To summarize embodiments 1 and 2, by each of the first corner portion 7B and the second corner portion 8B including either the chamfered portion 12 or the sagging portion 14, the reliability of the insulation performance is improved and the inductance of the current path is reduced.

[0031] <Third Embodiment> 6 is a cross-sectional view showing the configuration of the first electrode 7, the second electrode 8, and the insulating material 9 in the third embodiment. The insulating material 9 is an insulating coating layer 9B that covers the second contact surface 8A. The width of the second contact surface 8A is greater than the width of the first contact surface 7A. The insulating coating layer 9B is in contact with the first contact surface 7A, the second contact surface 8A, and the sagging portion 14 of the second corner 8B. On the other hand, the insulating coating layer 9B is not in contact with the sagging portion 14 of the first corner 7B.

[0032] According to this configuration, the step of inserting insulating sheet 9A is not required in the manufacturing process of the semiconductor device, and work efficiency is improved. In addition to the effects of the first embodiment, productivity in the manufacturing process of the semiconductor device is improved.

[0033] Although not shown, a chamfered portion 12 may be formed at the second corner 8B of the second electrode 8, similar to the first corner 7B of the first electrode 7 (see FIG. 3). An insulating coating layer 9B may be provided so as to be in contact with the chamfered portion 12 at the second corner 8B. Even with such a configuration, the same effects as those of the third embodiment can be obtained.

[0034] <Fourth Embodiment> 7 is a cross-sectional view showing the configuration of the first electrode 7, the second electrode 8, and the insulating material 9 in the fourth embodiment. The insulating material 9 is an insulating coating layer 9B that covers the second contact surface 8A. The insulating coating layer 9B in the fourth embodiment is formed on the entire outer periphery of the second electrode 8.

[0035] According to this configuration, the creepage distance of the second electrode 8 is ensured, thereby improving the reliability of the semiconductor device.

[0036] In the present disclosure, the embodiments can be freely combined, and the embodiments can be modified or omitted as appropriate.

[0037] Various aspects of the present disclosure are summarized below as appendices.

[0038] (Appendix 1) A semiconductor element; a first electrode including an extending first contact surface electrically connected to the semiconductor element; a second electrode including a second contact surface facing the first contact surface and extending parallel to the first contact surface, the second electrode being electrically connected to the semiconductor element; an insulating material provided between the first electrode and the second electrode, extending between and in contact with the first contact surface and the second contact surface; the first electrode includes a first corner portion located at an end of the first contact surface in a width direction, the second electrode includes a second corner portion located at an end of the second contact surface in a width direction, The semiconductor device, wherein each of the first corner portion and the second corner portion includes either a chamfered portion or a sagging portion.

[0039] (Appendix 2) A base plate and an insulating substrate including a metal pattern and provided on the base plate; 2. The semiconductor device according to claim 1, wherein the semiconductor element is mounted on the metal pattern of the insulating substrate.

[0040] (Appendix 3) the insulating material is an insulating sheet, 3. The semiconductor device according to claim 1, wherein the insulating sheet has a thickness of 0.05 mm or less.

[0041] (Appendix 4) the insulating material is an insulating sheet, 4. The semiconductor device according to claim 1, wherein the insulating sheet is not in contact with the first corner portion and the second corner portion.

[0042] (Appendix 5) the insulating material is an insulating coating layer covering the second contact surface; 4. The semiconductor device according to claim 1, wherein the width of the second contact surface is greater than the width of the first contact surface.

[0043] (Appendix 6) 6. The semiconductor device according to claim 5, wherein the insulating coating layer is formed on the entire outer periphery of the second electrode.

[0044] (Appendix 7) the insulating material is an insulating coating layer covering the second contact surface; 4. The semiconductor device according to claim 1, wherein the insulating coating layer is not in contact with the first corner portion and is in contact with the second corner portion.

[0045] (Appendix 8) 8. The semiconductor device according to claim 1, wherein the semiconductor element is formed of a wide bandgap semiconductor.

[0046] (Appendix 9) A power conversion device including the semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 8. [Explanation of symbols]

[0047] 1 base plate, 2 insulating substrate, 3 metal pattern, 4 semiconductor element, 5 case, 6 metal wire, 7 first electrode, 7A first contact surface, 7B first corner portion, 8 second electrode, 8A second contact surface, 8B second corner portion, 9 insulating material, 9A insulating sheet, 9B insulating coating layer, 10 sealing material, 11 bonding material, 12 chamfered portion, 13 burr portion, 14 sagging portion, 15 electrode.

Claims

1. A semiconductor element; a first electrode including an extending first contact surface electrically connected to the semiconductor element; a second electrode including a second contact surface facing the first contact surface and extending parallel to the first contact surface, the second electrode being electrically connected to the semiconductor element; an insulating material provided between the first electrode and the second electrode, extending between and in contact with the first contact surface and the second contact surface; the first electrode includes a first corner portion located at an end of the first contact surface in a width direction, the second electrode includes a second corner portion located at an end of the second contact surface in a width direction, The semiconductor device, wherein each of the first corner portion and the second corner portion includes either a chamfered portion or a sagging portion.

2. A base plate and an insulating substrate including a metal pattern and provided on the base plate; 2. The semiconductor device according to claim 1, wherein the semiconductor element is mounted on the metal pattern of the insulating substrate.

3. the insulating material is an insulating sheet, 2. The semiconductor device according to claim 1, wherein the insulating sheet has a thickness of 0.05 mm or less.

4. the insulating material is an insulating sheet, The semiconductor device according to claim 1 , wherein the insulating sheet is not in contact with the first corner portion and the second corner portion.

5. the insulating material is an insulating coating layer covering the second contact surface; The semiconductor device according to claim 1 , wherein the width of said second contact surface is greater than the width of said first contact surface.

6. 6. The semiconductor device according to claim 5, wherein said insulating coating layer is formed on the entire outer periphery of said second electrode.

7. the insulating material is an insulating coating layer covering the second contact surface; 2. The semiconductor device according to claim 1, wherein said insulating coating layer is not in contact with said first corner portion and is in contact with said second corner portion.

8. 2. The semiconductor device according to claim 1, wherein said semiconductor element is formed of a wide bandgap semiconductor.

9. A power conversion device comprising the semiconductor device according to claim 1.

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