Method of manufacturing fan-out packaging device and fan-out packaging device manufactured thereby

Abstract

To attain improvement in quality of a dielectric layer and a redistribution layer in a subsequent step by forming a base metal layer on a partial area of a fan-out packaging substrate, to improve a surface topology of the dielectric layer formed in an upper layer by the base metal layer, and to improve the quality of the redistribution layer formed in an upper layer.SOLUTION: There is provided a method of manufacturing a fan-out packaging device using a wafer level packaging process or a panel level packaging process. The method includes the steps of: forming a base metal layer 100 on a partial area of a fan-out packaging substrate 10; forming a first dielectric layer 200 on the base metal layer; patterning the first dielectric layer to form a via hole 220; forming a redistribution layer 300 on the first dielectric layer and the via hole; forming a second dielectric layer 400 on the redistribution layer; and patterning the second dielectric layer to form a bump structure 500 connected to the redistribution layer.SELECTED DRAWING: Figure 1D

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a fan-out packaging device using a wafer level packaging process or a panel level packaging process, in which a base metal layer is formed on a fan-out packaging substrate to improve characteristics, and a fan-out packaging device manufactured thereby. [Background technology]

[0002] The eight major semiconductor processes are the wafer process, oxidation process, photo process, etching process, thin film process, wiring process, test process and packaging process, which are carried out in this order.

[0003] The present invention relates to a packaging process in a semiconductor manufacturing process. Generally, the semiconductor packaging process includes the steps of wafer dicing, die attach, die interconnection, molding, and packaging test.

[0004] While the traditional semiconductor packaging process involves cutting wafers and then carrying out the packaging process, the recent trend is to carry out the "Wafer Level Packaging (WLP)" process while maintaining the die in wafer form. This process involves carrying out the packaging process and testing at once in wafer form, and then cutting the die (chips), which has the advantage of reducing package production costs compared to conventional methods.

[0005] In addition, research into the Panel Level Packaging (PLP) process, which goes beyond wafer level packaging, is also active. This has the advantage of being able to package a larger number of dies than the WLP process, further reducing production costs.

[0006] Meanwhile, as semiconductor devices become more highly integrated, perform better, and smaller, various packaging technologies have evolved based on the wafer level packaging or panel level packaging method, and fan-in (wafer or panel level packaging) and fan-out (wafer or panel level packaging) technologies are being actively researched.

[0007] In particular, Fan-Out Wafer or Panel Level Packaging (hereinafter referred to as Fan-Out Wafer Level Packaging for convenience, and also referred to as "Fan Out WLP" or "FO-WLP" as needed) technology is a fan-out technology that increases the number of I / O pins. It uses a Re-Distribution Layer (RDL) process to expand the wiring formation area outside the die area, thereby securing a wiring formation surface that is larger than the die size.

[0008] In such fan-out wafer level packaging, the RDL process forms a dielectric layer on the surface of the die, then forms a wiring layer using copper plating, and if necessary, repeats these processes to extend the wiring formation area outside the die.

[0009] Here, in order to improve the yield and contact resistance of the wiring layer in the RDL process, it is very important to improve the quality of the plating layer in the copper plating process.

[0010] In order to improve the quality of such plating layers, attempts have been made to slow down the plating speed or improve the plating process conditions, but this slows down the process speed and does not ensure process reproducibility.

[0011] Furthermore, when forming such RDL wiring layers in multiple layers, a dielectric layer is formed during the plating process, which can lead to problems such as unevenness of the dielectric layer and deterioration of surface topology due to deterioration of the quality of the plating layer, ultimately resulting in defects in the wiring layer during the subsequent RDL process, which in turn leads to increased contact resistance and impedance and a low operating frequency. Summary of the Invention [Problem to be solved by the invention]

[0012] The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing a fan-out packaging device having improved characteristics by forming a base metal layer on a fan-out packaging substrate, and a fan-out packaging device manufactured thereby. [Means for solving the problem]

[0013] To achieve the above object, the present invention provides a method for manufacturing a packaging device using a wafer level packaging process or a panel level packaging process, comprising the steps of: forming a base metal layer on a portion of a fan-out packaging substrate; forming a first dielectric layer on the base metal layer; patterning the first dielectric layer to form via holes; forming a redistribution layer (RDL) on the first dielectric layer and the via holes; forming a second dielectric layer on the redistribution layer; and patterning the second dielectric layer to form bump structures connected to the redistribution layer.

[0014] Another technical aspect of the present invention is a packaging device manufactured using a wafer level packaging process or a panel level packaging process, comprising: a fan-out packaging substrate; a base metal layer formed on a portion of the fan-out packaging substrate; a first dielectric layer formed on the base metal layer and including a via hole exposing a portion of the base metal layer; a redistribution layer (RDL) formed on the first dielectric layer and the via hole; a second dielectric layer formed on the redistribution layer and patterned to expose a portion of the redistribution layer; and a bump structure formed on the second dielectric and connected to the redistribution layer.

[0015] Furthermore, it is preferable that the base metal layer is realized by a signal portion formed on the signal pad area of ​​the die and a base portion separated from the signal portion and formed on all or part of the remaining area of ​​the fan-out packaging substrate.

[0016] In addition, it is preferable that the base metal layer is realized by a signal portion formed on a signal pad area of ​​the die, a first base portion separated from the signal portion and formed on the fan-out packaging element, and a second base portion formed along an edge of the fan-out packaging element or an edge of the fan-out packaging substrate.

[0017] It is also preferable that a bridge portion be formed between the first base portion and the second base portion.

[0018] The signal portion is preferably formed in an area larger than the signal pad of the die, and is preferably aligned with and in contact with the redistribution layer.

[0019] Preferably, the redistribution layer and the ground plane of the bump structure are connected to the base portion through via holes in the first dielectric.

[0020] It is also preferable that holes or uneven patterns are formed in one region or the entire region of the base metal layer, and the diameter of the holes and uneven patterns is preferably formed to be less than twice the thickness of the base metal layer.

[0021] Preferably, the base metal layer includes a copper (Cu) material, and may be implemented as a copper layer on a titanium (Ti) or titanium tungsten (TiW) layer. Preferably, the base metal layer is formed to have a thickness of 1 to 2.2 μm.

[0022] Preferably, the base metal layer is formed by forming a metal layer on the fan-out substrate, forming a photoresist pattern on the metal layer by a photolithography process, etching the metal layer using the photoresist pattern as an etching mask, and then removing the photoresist pattern.

[0023] Preferably, the base metal layer is formed by forming a photoresist pattern on the fan-out substrate by a photolithography process, depositing a metal layer using the photoresist pattern as a deposition mask, and then removing the photoresist pattern.

[0024] In addition, it is preferable that the base metal layer is formed by a process of forming a plating layer on the fan-out substrate, forming a photoresist pattern on the plating layer by a photolithography process, depositing a metal layer using the photoresist pattern as a deposition mask, removing the photoresist pattern, and then etching the plating layer.

[0025] Also, it is preferable that the first dielectric forming process to the redistribution layer forming process are repeated to form multiple redistribution layers / dielectric layers. [Effects of the Invention]

[0026] As described above, according to an embodiment of the present invention, by forming a base metal layer in a portion of a fan-out packaging substrate, it is possible to ensure high quality of the dielectric layer and the redistribution layer in the subsequent processes. Therefore, the base metal layer improves the surface topology of the dielectric layer formed thereon, thereby improving the quality of the redistribution layer formed thereon.

[0027] In addition, the base portion is separated from the signal pad and configured to cover the entire remaining device, and is connected to the ground plane of the subsequent redistribution layer or bump structure (UBM layer) through via holes, thereby ensuring stable operation of the device.

[0028] Furthermore, in the subsequent process of electroplating for forming a redistribution layer and a bump structure, the base metal layer serves as a seed layer, thereby providing a very low impedance connection in the plating process, thereby enabling uniform plating thickness in the redistribution layer and the bump structure layer without the need to significantly reduce the plating speed, and providing a seed layer with a large area provides a maximized conductive layer, thereby improving the quality of the redistribution layer and the bump structure, which can be more effectively applied when forming multiple redistribution layers.

[0029] Furthermore, when the base metal layer according to the present invention is used as a ground plate, it provides a low impedance signal return path for the redistribution layer, enabling very high frequency operation.

[0030] Furthermore, the base metal layer according to the present invention provides an electrical shielding function between the redistribution layer and the die, thereby enabling stable electrical operation.

[0031] In addition, the base metal layer according to the present invention is formed on the edge of each unit fan-out packaging element or in the spaced area between adjacent fan-out packaging elements, which not only facilitates dicing, but also maximizes the role of a conductive layer in the plating process since the base metal layer is formed over the entire area of ​​the wafer or panel (up to the edge or edge). [Brief explanation of the drawings]

[0032] [Figure 1A] 1A to 1C are side schematic views illustrating a method for manufacturing a fan-out packaging element according to an embodiment of the present invention. [Figure 1B] 1A to 1C are side schematic views illustrating a method for manufacturing a fan-out packaging element according to an embodiment of the present invention. [Figure 1C] 1A to 1C are side schematic views illustrating a method for manufacturing a fan-out packaging element according to an embodiment of the present invention. [Figure 1D] 1A to 1C are side schematic views illustrating a method for manufacturing a fan-out packaging element according to an embodiment of the present invention. [Figure 2A] 1A to 1C are schematic diagrams illustrating various embodiments of a base metal layer formed on a fan-out packaging substrate according to the present invention. [Figure 2B] 1A to 1C are schematic diagrams illustrating various embodiments of a base metal layer formed on a fan-out packaging substrate according to the present invention. [Figure 2C] 1A to 1C are schematic diagrams illustrating various embodiments of a base metal layer formed on a fan-out packaging substrate according to the present invention. [Figure 3] 1 is a schematic plan view of a fan-out packaging substrate on which a base metal layer is formed according to various embodiments of the present invention; [Figure 4] 1 is a schematic plan view of a fan-out packaging substrate on which a base metal layer is formed according to various embodiments of the present invention; [Figure 5] 1 is a schematic plan view of a fan-out packaging substrate on which a base metal layer is formed according to various embodiments of the present invention; [Figure 6]1A to 1C are schematic diagrams illustrating a process of forming a base metal layer on a fan-out packaging substrate according to various embodiments of the present invention. [Figure 7] 1A to 1C are schematic diagrams illustrating a process of forming a base metal layer on a fan-out packaging substrate according to various embodiments of the present invention. [Figure 8] 1A to 1C are schematic diagrams illustrating a process of forming a base metal layer on a fan-out packaging substrate according to various embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0033] The present invention relates to a fan-out packaging device using a wafer level packaging process or a panel level packaging process, and provides a fan-out packaging device with improved electrical characteristics by forming a base metal layer on a fan-out packaging substrate.

[0034] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Fig. 1 is a side view showing a method for manufacturing a fan-out packaging device according to an embodiment of the present invention, Fig. 2 is a view showing various embodiments of a base metal layer formed on a fan-out packaging substrate according to the present invention, Figs. 3 to 5 are plan views of a fan-out packaging substrate on which a base metal layer is formed according to various embodiments of the present invention, and Figs. 6 to 8 are views showing processes for forming a base metal layer on a fan-out packaging substrate according to various embodiments of the present invention.

[0035] As shown in FIG. 1, a method for manufacturing a fan-out packaging device according to an embodiment of the present invention is a method for manufacturing a packaging device using a wafer-level packaging process or a panel-level packaging process, and includes the steps of forming a base metal layer 100 on a portion of a fan-out packaging substrate 10, forming a first dielectric layer 200 on the base metal layer 100, patterning the first dielectric layer 200 to form a via hole 220, forming a redistribution layer (RDL, Re-Destribution Line or Re-Destribution Layer) 300 on the first dielectric layer 200 and the via hole 220, forming a second dielectric layer 400 on the redistribution layer 300, and patterning the second dielectric layer 400 to form a bump structure 500 connected to the redistribution layer 300.

[0036] Therefore, a fan-out packaging device according to one embodiment of the present invention is manufactured using a wafer level packaging process or a panel level packaging process, and includes a fan-out packaging substrate, a base metal layer 100 formed on a portion of the fan-out packaging substrate 10, a first dielectric layer 200 formed on the base metal layer 100 and including a via hole 220 exposing a portion of the base metal layer 100, a redistribution layer (RDL) 300 formed on the first dielectric layer 200 and the via hole 220, a second dielectric layer 400 formed on the redistribution layer 300 and patterned to expose a portion of the redistribution layer 300, and a bump structure 500 formed on the second dielectric and connected to the redistribution layer 300.

[0037] The present invention manufactures a packaging device using a wafer level packaging process or a panel level packaging process, and first forms a base metal layer 100 on a partial area of ​​a fan-out packaging substrate 10 (see FIGS. 1a and 1b).

[0038] The fan-out packaging substrate 10 according to an embodiment of the present invention is a wafer or substrate on which a single chip or a plurality of chip arrays are formed, or is provided by dicing such chips, reconstituting and arranging them on a wafer or panel, and then embedding the chips using EMC (Epoxy Molding Compound), etc. In the present invention, the terms "chip" and "die" 12 are used interchangeably.

[0039] In this manner, by implementing the embedded die 12 on a wafer or panel, the input / output (I / O) signal pads 14 of the die 12 are exposed, the area other than the signal pads 14 is provided after passivation, and the area outside the die 12 is provided as a fan-out area.

[0040] In one embodiment of the present invention, a base metal layer 100 is formed on a portion of a fan-out packaging substrate 10 that is reconstructed on a wafer or panel and includes embedded dies 12 (see FIG. 1a).

[0041] The base metal layer 100 may be formed in a portion of the fan-out packaging substrate 10, for example, in the remaining region of the fan-out packaging substrate 10 excluding the die 12 (FIG. 2a), the signal pad 14 region of the die 12 and the remaining region of the fan-out packaging substrate 10 excluding the die 12 (FIG. 2b), or the signal pad 14 region of the die 12 and the remaining region separated therefrom excluding the signal pad 14 region (FIG. 2c). The region where the base metal layer 100 is formed is not limited thereto, and the base metal layer 100 may be formed in various regions on the fan-out packaging substrate 10 depending on the use and purpose of the device.

[0042] In one embodiment of the present invention, the base metal layer 100 may be realized by a signal portion 120 formed on the signal pad 14 area of ​​the die 12 and a base portion 140 separated from the signal portion 120 and formed on all or part of the remaining area of ​​the fan-out packaging substrate 10.

[0043] That is, the base metal layer 100 can be formed in various regions on the fan-out packaging substrate 10, and when it is formed on the signal pad 14 region of the die 12, it is called the signal portion 120, and when it is formed in any other region, it is called the base portion 140.

[0044] In the case of Figure 2a, the base metal layer 100 is formed from a base portion 140 formed on the remaining fan-out packaging area excluding the die 12, in the case of Figure 2b, the base metal layer 100 is formed from a signal portion 120 formed on the signal pad 14 area of ​​the die 12 and from a base portion 140 formed on the remaining fan-out packaging area excluding the die 12, and in the case of Figure 2c, the base metal layer 100 is formed from a base portion 140 formed on the signal pad 14 area of ​​the die 12 and the entire area separated therefrom.

[0045] In another embodiment of the present invention, the base metal layer 100 may be realized by a signal portion 120 formed on the signal pad 14 area of ​​the die 12, a first base portion 142 separated from the signal portion 120 and formed on the fan-out packaging element, and a second base portion 144 formed along the edge of the fan-out packaging element or the edge of the fan-out packaging substrate 10.

[0046] As described above, the base metal layer 100 formed on the signal pad 14 area of ​​the die 12 is the signal portion 120, and the base metal layer 100 formed on the other area is the base portion 140. In the above embodiment, when the die 12 is embedded on a wafer, the base metal layer 100 formed on the die 12 area other than the signal pad 14 area and the fan-out area (fan-out packaging element) is referred to as the first base portion 142, and the base metal layer 100 formed along the edge of the fan-out packaging substrate 10 (when there is only one die 12, the fan-out packaging element and the fan-out packaging substrate have the same area; see FIGS. 2 and 3) is referred to as the second base portion 144.

[0047] This can also be applied when two or more dies 12 are embedded on a wafer or panel, and the base metal layer 100 formed on the die 12 area and fan-out area other than the signal pad 14 area on the die 12, i.e., on each unit fan-out packaging element, is referred to as a first base portion 142, and the base metal layer 100 formed on other fan-out packaging elements and along the edge of the fan-out packaging substrate 10 is referred to as a second base portion 144.

[0048] This can also be applied when multiple dies 12 are packaged depending on the size of the wafer or panel, as shown in FIGS.

[0049] FIG. 4 is a schematic diagram showing a plan view of four dies 12 embedded in a wafer or panel with a base metal layer 100 formed on top of them, showing an example in which the base metal layer 100 is formed on the signal pad 14 area (signal portion 120) of the die 12 and the entire area spaced apart from it (base portion 140).

[0050] A first base portion 142 is formed on the die 12 area and fan-out area other than the signal pad 14 area of ​​the die 12, i.e., on each unit fan-out packaging element, and a second base portion 144 is formed along the edge of each unit fan-out packaging element and the edge of the fan-out packaging substrate 10.

[0051] Here, the edge of each unit fan-out packaging element refers to the edge itself or a separation region between adjacent fan-out packaging elements. This region can be the region where the dicing process is performed for each unit fan-out packaging element, providing convenience for dicing. In addition, the base metal layer 100 can be formed over the entire area of ​​the wafer or panel (up to the edge), thereby maximizing the role of a conductive layer in the plating process.

[0052] 5 shows the embodiment of FIG. 4 in which a bridge portion 146 is formed between the first base portion 142 and the second base portion 144. This is to facilitate the dicing process of the unit fan-out packaging devices. That is, the influence of the base metal layer 100 on the separation of the unit fan-out packaging devices is minimized, and the bridge portion 146 allows each unit fan-out packaging device to be easily separated. For this reason, it is preferable that the width of the bridge portion 146 be 100 μm or less.

[0053] Meanwhile, the signal part 120 according to the embodiment of the present invention is formed over a larger area than the signal pad 14 of the die 12. That is, the signal part 120, which is the base metal layer 100 formed on the signal pad 14 area of ​​the die 12, is formed over a larger area so as to completely cover the signal pad 14 of the die 12. This increases the contact area, providing a higher degree of contact freedom than the diameter of the via hole 220 (described later). This allows for greater tolerance for alignment errors in subsequent processes, improving design and process convenience. This also improves contact resistance and achieves a higher manufacturing yield.

[0054] In other words, since the signal pad 14 of the existing die 12 has a small area, alignment errors with the redistribution layer 300 can easily cause open or short circuit connections during the packaging process, ultimately resulting in low manufacturing yields. However, the present invention minimizes this alignment error problem by implementing a signal section 120 that is wider than the signal pad 14 of the die 12.

[0055] In addition, by forming a signal section 120 that is wider than the signal pad 14 area of ​​the die 12, the routing resources of the redistribution layer 300 are not used, and the open signal section 120 is used, so that the actual die 12 area can be utilized without being wasted.

[0056] Of course, when forming the base metal layer 100 on the signal pad 14 of the die 12 (forming the signal portion 120), it can be selectively applied depending on the process conditions and the use and purpose of the device.

[0057] Meanwhile, holes 160 or uneven patterns may be formed in a certain region or the entire region of the base metal layer 100. Figures 3 to 5 mainly show a fan-out region of a fan-out packaging device in which holes 160 are formed. The holes 160 are intended to distribute mechanical or thermal stress throughout the base metal layer 100 (to prevent warping of the wafer or panel).

[0058] In addition, in an embodiment of the present invention, the diameter of the hole 160 and the uneven pattern is preferably formed to be equal to or less than twice the thickness of the base metal layer 100. This is to maintain the surface topology of the dielectric layer formed thereon, in addition to the effect of dispersing the mechanical or thermal stress. If the diameter of the hole 160 and the uneven pattern is greater than twice the thickness of the base metal layer 100, the surface topology of the dielectric layer formed thereon may be degraded, resulting in an uneven dielectric layer, and further, the quality of the redistribution layer 300 may be degraded, resulting in defects in the wiring layer.

[0059] The base metal layer 100 is made of a metal having excellent electrical conductivity and thermal conductivity, and copper (Cu) is used in this embodiment of the present invention. In addition, in order to improve coating properties and adhesion to the surface of the fan-out packaging substrate 10, the base metal layer 100 may be implemented as a composite metal layer in which a titanium (Ti) or titanium tungsten (TiW) layer is first formed and a copper layer is then formed thereon.

[0060] Overall, the thickness of the base metal layer 100 may be formed to a thickness of 2.2 μm or less, preferably 1 to 2 μm, taking into consideration the thickness and function of the device, and in the case of the composite metal layer, the thickness of the titanium (Ti) or titanium tungsten (TiW) layer may be formed to a thickness of 0.05 to 0.1 μm.

[0061] As described above, the base metal layer 100 may be formed on a portion of the fan-out packaging substrate 10. Figures 6 to 8 are diagrams showing a process of forming the base metal layer 100 on the fan-out packaging substrate 10. The base metal layer 100 in Figures 6 to 8 is formed on the signal pad 14 area of ​​the die 12 and the remaining area of ​​the fan-out packaging substrate 10 excluding the die 12 (see Figure 2(b)).

[0062] 6 is a diagram showing the formation of a base metal layer 100 through a patterning process and an etching process. This is achieved by forming a metal layer (titanium (Ti) or titanium tungsten (TiW) layer having a thickness of 0.05 to 0.1 μm and a copper layer 20 having a thickness of 1 to 2 μm on the fan-out substrate, forming a photoresist pattern 30 on top of them through a photolithography process, etching the metal layer 20 using this as an etching mask, and then removing the photoresist pattern 30. Here, the metal layer 20 is formed by a known physical or chemical thin film deposition method, and in one embodiment of the present invention, it is formed by a sputtering process.

[0063] 7 is a diagram showing the formation of a base metal layer 100 through a patterning process and a deposition process. This is formed by forming a photoresist pattern 30 on the fan-out substrate through a photolithography process, depositing a metal layer 20 using this as a deposition mask, and then removing the photoresist pattern 30.

[0064] 8 shows that a base metal layer 100 is formed by first forming a plating layer 40, then performing a patterning process, a process of depositing a metal layer 20, and a process of etching the plating layer 40. This is done by forming a plating layer 40 on the fan-out substrate, forming a photoresist pattern 30 on the plating layer 40 using a photolithography process, depositing a metal layer 20 using this as a deposition mask, removing the photoresist pattern 30, and then etching the plating layer 40.

[0065] As such, the base metal layer 100 according to the present invention may be formed on a portion of the fan-out packaging substrate 10 by first forming a metal layer on the fan-out packaging substrate 10 and then patterning and etching the metal layer; by first forming a photoresist pattern 30, then forming a metal layer 20, and then removing the photoresist pattern 30; or by first forming a plating layer 40, then depositing an additional metal layer 20 through a patterning process, and then etching the plating layer 40. Alternatively, the base metal layer 100 may be formed on a portion of the fan-out packaging substrate 10 by combining various processes such as physical and chemical vapor deposition, etching, and lift-off.

[0066] As described above, according to the embodiment of the present invention, by forming the base metal layer 100 in a portion of the fan-out packaging substrate 10, it is possible to ensure high quality of the dielectric layer and the redistribution layer 300 in the subsequent processes. Therefore, the base metal layer 100 improves the surface topology of the dielectric layer formed thereon, and also improves the quality of the redistribution layer 300 formed thereon.

[0067] In addition, the base portion 140 is separated from the signal pad 14 to cover the entire remaining device, and is connected to the ground surface of the subsequent redistribution layer 300 or bump structure (solder bump and UBM layer) 500 through the via hole 220, thereby providing high freedom of device contact and connection and ensuring stable device operation.

[0068] Furthermore, the base metal layer 100 serves as a seed layer during electrolytic plating for forming the redistribution layer 300 and the bump structure 500 in the subsequent process. This provides a very low impedance connection during the plating process, thereby enabling uniformity in the plating thickness of the redistribution layer 300 and the bump structure 500 without the need to significantly reduce the plating speed. Furthermore, by providing a seed layer with a large area, a maximized conductive layer can be provided, improving the quality of the redistribution layer 300 and the bump structure 500. This can be more effectively applied when forming multiple redistribution layers 300.

[0069] Furthermore, when the base metal layer 100 according to the present invention is used as a ground plate, it provides a low impedance signal return path for the redistribution layer 300, enabling operation at very high frequencies.

[0070] Furthermore, the base metal layer 100 according to the present invention provides an electrical shielding function between the redistribution layer 300 and the die 12, thereby enabling stable electrical operation.

[0071] After the base metal layer 100 is formed on the fan-out packaging substrate 10, a process for forming a dielectric layer and a redistribution layer 300 is carried out (FIG. 1c).

[0072] First, a first dielectric layer 200 is formed on the base metal layer 100, and the first dielectric layer 200 is patterned to form a via hole 220. Then, a redistribution layer 300 is formed on the first dielectric layer 200 and the via hole 220.

[0073] The first dielectric layer 200 may be made of an organic or inorganic dielectric material, such as a polymer material such as polyimide, PBO (Polybenzoxazole), or BCB (Benzocyclobutene), or an inorganic material such as an oxide or nitride. Preferably, silicon nitride or silicon oxide may be used. In various embodiments, SiO2, SiO x , oxides such as Al2O3, ZrO2, Ta2O5, SiN x Nitrides such as SiN, ZrN, AlN, BN, TaN, and TaN can be used, and two or more materials can be mixed as needed. Also, the second dielectric layer 400 described below can be made of the same or different material.

[0074] Such a dielectric layer can be formed by a process such as spin coating, CVD (Chemical Vapor Deposition), sputtering, laminating, or a combination thereof, and can be formed by suitable physical and chemical vapor deposition processes. The first dielectric layer 200 is then patterned to form a via hole 220. The via hole 220 is formed by an etching process in a patterning process, and is filled with metal to form an electrical connection path between upper and lower components.

[0075] A plurality of via holes 220 are formed in the first dielectric layer 200, thereby exposing a portion of the base metal layer 100. The via holes 220 are also formed in the signal pad 14 region of the die 12. That is, a plurality of via holes 220 are formed at appropriate positions on the first dielectric layer 200, thereby exposing the base metal layer 100 and the signal pad 14 region, and may also be formed in other required regions.

[0076] The via hole 220 can be filled with various metal materials such as aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), etc., and can be filled by sputtering, atomic layer deposition (ALD), CVD, or electroplating processes.

[0077] According to an embodiment of the present invention, electrolytic plating is used, which has good step coverage and is excellent in cost and productivity, and copper is used as the metal material.

[0078] Then, a redistribution layer 300 is formed on the first dielectric layer 200 and the via hole 220, so that the redistribution layer 300 is electrically connected to the base metal layer 100 or the signal pad 14 of the die 12. The redistribution layer 300 is realized by forming a metal layer on the first dielectric layer 200 during or after the formation of the via hole 220, and forming a metallization pattern thereof.

[0079] That is, the redistribution layer 300 according to one embodiment of the present invention is formed by electroplating a copper layer, and then patterning and etching the copper layer to form signal lines for redistribution of electrical connection wiring of the signal pads 14 exposed from the die 12.

[0080] The redistribution layer 300 can be realized as a single, multiple, or double-sided redistribution layer 300. That is, a multiple redistribution layer / dielectric layer can be realized by repeatedly forming a dielectric layer and a metal layer (repeating the first dielectric forming process to the redistribution layer 300 forming process) to form a redistribution signal line in the fan-out region.

[0081] As described above, according to an embodiment of the present invention, forming the base metal layer 100 in a portion of the fan-out packaging substrate 10 can improve the quality of the subsequent dielectric layer and redistribution layer 300. Therefore, the base metal layer 100 improves the surface topology of the dielectric layer formed thereon, thereby improving the quality of the redistribution layer 300 formed thereon.

[0082] In addition, the base portion 140 is separated from the signal pad 14 to cover the entire remaining device, and is connected to the ground surface of the subsequent redistribution layer 300 or bump structure (solder bump and UBM layer) 500 through the via hole 220, thereby ensuring stable operation of the device.

[0083] In addition, during the subsequent electroplating process for forming the redistribution layer 300 and the bump structure 500, the base metal layer 100 acts as a seed layer, thereby providing an additional path for current to flow, thereby improving the plating speed due to the low impedance of the redistribution layer 300 and the bump structure 500, and by providing a large-area seed layer, the uniformity of the plating layer can be improved, thereby improving the quality of the redistribution layer 300 and the bump structure 500.

[0084] Furthermore, the base metal layer 100 according to the present invention provides an electrical shielding function between the redistribution layer 300 and the die 12, thereby enabling stable electrical operation.

[0085] In addition, the base metal layer 100 according to the present invention is formed on the edge of each unit fan-out packaging element or in the spaced apart area between adjacent fan-out packaging elements, thereby providing convenience for dicing. In addition, the base metal layer 100 is formed over the entire area of ​​the wafer or panel (edge ​​or edge), thereby maximizing the role of a conductive layer in the plating process.

[0086] A second dielectric layer 400 is formed on the redistribution layer 300, and the second dielectric layer 400 is patterned to form a bump structure 500 connected to the redistribution layer 300 (FIG. 1d).

[0087] The second dielectric layer 400 is formed using the same or similar material and process as the first dielectric layer 200 and is patterned to form a bump structure 500 connected to the redistribution layer 300 .

[0088] Here, when forming multiple redistribution layers 300, via holes 220 are formed by patterning the second dielectric layer 400 in the same manner as the first dielectric layer 200, and the redistribution layers 300 are formed by a plating process, and then the redistribution layers 300 are connected to each other and to the base metal layer 100.

[0089] In FIG. 1d, a base metal layer 100 is formed on a fan-out packaging substrate 10, a first dielectric layer 200 is formed, a via hole 220 is formed, a redistribution layer 300 is formed on top of it, and then a second dielectric layer 400 is formed on top of it, and a bump structure 500 is formed in a predetermined position by a patterning process.

[0090] The bump structure 500 according to the embodiment of the present invention is formed by forming an Under Bump Metallization (UBM) (depositing and patterning a Ti / Cu layer) on the pattern (or via hole) of the second dielectric layer 400, removing the solder plating and photoresist, removing unnecessary metal layers, and forming a solder bump by reflow. For the sake of convenience, such a solder bump and UBM are referred to as the bump structure 500 in the present invention.

[0091] In this way, solder bumps can be formed at the wafer level or panel level, and after performing an additional or general packaging process, the unit fan-out packaging elements can be separated by a dicing process.

[0092] According to an embodiment of the present invention, by forming a base metal layer in a portion of a fan-out packaging substrate, it is possible to improve the quality of the subsequent dielectric layer and redistribution layer. Therefore, the base metal layer improves the surface topology of the dielectric layer formed thereon, thereby improving the quality of the redistribution layer formed thereon.

[0093] In addition, the base portion is separated from the signal pad to cover the entire remaining device, and is connected to the ground plane of the subsequent redistribution layer or bump structure (solder bump and UBM layer) through the via hole, thereby ensuring stable operation of the device.

[0094] Furthermore, in the subsequent process of electroplating for forming a redistribution layer and a bump structure, the base metal layer serves as a seed layer, thereby providing a very low impedance connection in the plating process, thereby enabling uniform plating thickness of the redistribution layer and the bump structure without the need to significantly reduce the plating speed, and providing a seed layer with a large area provides a maximized conductive layer, improving the quality of the redistribution layer and the bump structure, which can be more effectively applied when forming multiple redistribution layers.

[0095] Furthermore, when the base metal layer according to the present invention is used as a ground plate, it provides a low impedance signal return path for the redistribution layer, enabling operation at very high frequencies.

[0096] Furthermore, the base metal layer according to the present invention provides an electrical shielding function between the redistribution layer and the die, thereby enabling stable electrical operation.

[0097] In addition, the base metal layer according to the present invention is formed on the edge of each unit fan-out packaging element or in the spaced area between adjacent fan-out packaging elements, thereby providing convenience for dicing. In addition, the base metal layer is formed over the entire area of ​​the wafer or panel (up to the edge), thereby maximizing the role of a conductive layer in the plating process.

Claims

1. A method for manufacturing a packaging device using a wafer level packaging process or a panel level packaging process, forming a base metal layer on a portion of the fan-out packaging substrate; forming a first dielectric layer on the base metal layer; patterning the first dielectric layer to form a via hole; forming a redistribution layer (RDL) on the first dielectric layer and the via hole; forming a second dielectric layer on the redistribution layer; patterning the second dielectric layer to form a bump structure connected to the redistribution layer; A method for manufacturing a fan-out packaging element, comprising:

2. The base metal layer comprises: a signal portion formed on a signal pad area of ​​the die; a base portion separated from the signal portion and formed on all or part of the remaining area of ​​the fan-out packaging substrate; The method for manufacturing a fan-out packaging device according to claim 1 , wherein the method is realized by:

3. The base portion is a first base portion separated from the signal portion and formed on the fan-out packaging element; a second base portion formed along an edge of the fan-out packaging element or an edge of the fan-out packaging substrate; The method for manufacturing a fan-out packaging device according to claim 2 , wherein the method is realized by:

4. The method for manufacturing a fan-out packaging element according to claim 3 , wherein a bridge portion is formed between the first base portion and the second base portion.

5. The signal section 3. The method of claim 2, wherein the signal pads are formed in an area larger than the signal pads of the die.

6. The method of claim 2 , wherein the signal part is aligned with and contacts the redistribution layer.

7. 3. The method of claim 2, wherein the redistribution layer and the ground plane of the bump structure are respectively connected to the base portion through via holes in the first dielectric.

8. The method for manufacturing a fan-out packaging element according to claim 1 , wherein holes or uneven patterns are formed in a part or the entire area of ​​the base metal layer.

9. The method of claim 8 , wherein the diameter of the holes and the uneven pattern is formed to be equal to or less than twice the thickness of the base metal layer.

10. The method for manufacturing a fan-out packaging element according to claim 1 , wherein the base metal layer comprises a copper (Cu) material.

11. 11. The method of claim 10, wherein the base metal layer is formed of a copper layer on a titanium (Ti) or titanium tungsten (TiW) layer.

12. 2. The method of claim 1, wherein the base metal layer is formed to have a thickness of 1 to 2.2 μm.

13. 2. The method of claim 1, wherein the base metal layer is formed by forming a metal layer on the fan-out substrate, forming a photoresist pattern on the metal layer by a photolithography process, etching the metal layer using the photoresist pattern as an etching mask, and then removing the photoresist pattern.

14. 2. The method of claim 1, wherein the base metal layer is formed by forming a photoresist pattern on the fan-out substrate by a photolithography process, depositing a metal layer using the photoresist pattern as a deposition mask, and then removing the photoresist pattern.

15. 2. The method of claim 1, wherein the base metal layer is formed by forming a plating layer on the fan-out substrate, forming a photoresist pattern on the plating layer by a photolithography process, depositing a metal layer using the photoresist pattern as a deposition mask, removing the photoresist pattern, and then etching the plating layer.

16. 2. The method of claim 1, wherein the first dielectric forming process to the redistribution layer forming process are repeatedly performed to implement multiple redistribution layers / dielectric layers.

17. A packaging device manufactured using a wafer level packaging process or a panel level packaging process, a fan-out packaging substrate; a base metal layer formed on a portion of the fan-out packaging substrate; a first dielectric layer formed on the base metal layer and including a via hole exposing a portion of the base metal layer; a redistribution layer (RDL) formed on the first dielectric layer and the via hole; a second dielectric layer formed on the redistribution layer and patterned to expose a portion of the redistribution layer; a bump structure formed on the second dielectric and connected to the redistribution layer; A fan-out packaging element comprising:

18. The base metal layer comprises: a signal portion formed on a signal pad area of ​​the die; a base portion separated from the signal portion and formed on all or part of the remaining area of ​​the fan-out packaging substrate; 20. The fan-out packaging element of claim 17, embodied from:

19. The base portion is a first base portion separated from the signal portion and formed on a fan-out packaging element; a second base portion formed along an edge of the fan-out packaging element or an edge of the fan-out packaging substrate; 20. The fan-out packaging element of claim 18, embodied from:

20. 20. The fan-out packaging element of claim 19, wherein a bridge portion is formed between the first base portion and the second base portion.

21. 20. The fan-out packaging element of claim 18, wherein the signal portion is formed over an area larger than a signal pad of the die.

22. The fan-out packaging device of claim 18 , wherein the signal portion is aligned with and contacts the redistribution layer.

23. The fan-out packaging device of claim 18 , wherein the redistribution layer and the ground plane of the bump structure are respectively connected to the base portion through via holes in the first dielectric.

24. The fan-out packaging device according to claim 17 , wherein the base metal layer has a hole or a concave-convex pattern formed therethrough in one or all of the areas.

25. The fan-out packaging element of claim 24 , wherein the diameter of the holes and the uneven pattern is formed to be equal to or less than twice the thickness of the base metal layer.

26. 20. The fan-out packaging element of claim 17, wherein the base metal layer comprises a copper (Cu) material.

27. 27. The fan-out packaging device of claim 26, wherein the base metal layer is realized by a copper layer formed on a titanium (Ti) or titanium tungsten (TiW) layer.

28. 18. The fan-out packaging device of claim 17, wherein the base metal layer is formed to have a thickness of 1 to 2.2 μm.

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