Display device

Abstract

To provide a display device for preventing restriction from being imposed on a usage environment condition.SOLUTION: In a display device, the drain of each of first multiple signal line inspection transistors is connected to the other end of each of multiple signal lines, a signal line IC chip applies a first voltage from one end of each of multiple signal lines during light source lighting periods of multiple light sources, the first multiple signal line inspection transistors are turned on when an inspection video control signal is inputted via an inspection video control wire during the light source lighting periods, and a second voltage different from the first voltage is applied from the source of each of the first multiple signal line inspection transistors in an on state.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] A display device in which a heater is mounted on a liquid crystal display panel has been developed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-047455 Summary of the Invention [Problem to be solved by the invention]

[0004] This embodiment provides a display device that is not restricted by the conditions of the usage environment. [Means for solving the problem]

[0005] A display device according to an embodiment includes: an array substrate; A counter substrate; a liquid crystal layer provided between the array substrate and the counter substrate; Multiple light sources; Equipped with The array substrate comprises: A plurality of scan lines; A plurality of signal lines; a plurality of pixels provided at intersections of the plurality of scanning lines and the plurality of signal lines; a signal line inspection circuit connected to the plurality of signal lines; a plurality of first signal line inspection transistors provided in the signal line inspection circuit and connected to the plurality of signal lines; an inspection video control wiring connected to gates of the plurality of first signal line inspection transistors; a first inspection video line connected to the sources of the plurality of first signal line inspection transistors; a signal line IC chip connected to one end of each of the plurality of signal lines; Equipped with a drain of each of the plurality of first signal line test transistors is connected to the other end of each of the plurality of signal lines; the signal line IC chip applies a first voltage to one end of each of the plurality of signal lines during a light source lighting period of the plurality of light sources; during the light source lighting period, an inspection video control signal is input via the inspection video control wiring, thereby turning on the plurality of first signal line inspection transistors; A second voltage different from the first voltage is applied from the source of each of the plurality of first signal line inspection transistors in the on state.

[0006] Moreover, the display device according to one embodiment includes: an array substrate; A counter substrate; a liquid crystal layer including a polymer dispersed liquid crystal, the liquid crystal layer being disposed between the array substrate and the counter substrate; Multiple light sources; Equipped with The array substrate comprises: A plurality of scan lines; A plurality of signal lines; a plurality of pixels provided at intersections of the plurality of scanning lines and the plurality of signal lines; a signal line inspection circuit connected to the plurality of signal lines; a plurality of first signal line inspection transistors provided in the signal line inspection circuit and connected to the plurality of signal lines; an inspection video control wiring connected to gates of the plurality of first signal line inspection transistors; an inspection video line connected to the sources of the plurality of first signal line inspection transistors; a signal line IC chip connected to one end of each of the plurality of signal lines; a plurality of second signal line test transistors provided between the signal line IC and the plurality of pixels; Equipped with a drain of each of the first signal line test transistors is connected to one end of each of the signal lines; the drains of the second signal line test transistors are connected to the other ends of the signal lines, respectively; an inspection video control signal is input via the inspection video control wiring during a light source lighting period of the plurality of light sources, thereby turning on the plurality of first signal line inspection transistors and the plurality of second signal line inspection transistors; During the light source lighting period, a first voltage is applied from each of the drains of the plurality of first signal line inspection transistors in the on state to one end of each of the plurality of signal lines; During the light source lighting period, a second voltage different from the first voltage is applied from each of the drains of the second signal line inspection transistors in the on state to the other end of each of the signal lines. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view showing a schematic configuration of a display device according to a first embodiment. [Figure 2] FIG. 2 is a plan view showing a schematic configuration of the display area of ​​the display device of FIG. [Figure 3] FIG. 3 is a cross-sectional view showing an example of a configuration that can be applied to the display panel shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view showing an example of a schematic configuration of a display panel. [Figure 5] FIG. 5 is a circuit diagram showing a schematic configuration of the display area and the inspection circuit of the display device. [Figure 6] FIG. 6 is a timing chart showing the driving of the display device. [Figure 7] FIG. 7 is a diagram showing the voltage applied to the signal line during the heat generation power supply period. [Figure 8] FIG. 8 is a circuit diagram showing an example of the configuration of a display device according to the second embodiment. [Figure 9] FIG. 9 is a timing chart showing the driving of the display device. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, in order to clarify the explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, elements similar to those described above with reference to the previous drawings may be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0009] The embodiments described in this specification are not general but are embodiments that describe the same or corresponding special technical features of the present invention. Hereinafter, a display device according to an embodiment will be described in detail with reference to the drawings.

[0010] In this embodiment, the first direction X, the second direction Y, and the third direction Z are perpendicular to one another, but may intersect at an angle other than 90 degrees. The direction toward the tip of the arrow of the third direction Z is defined as up or upward, and the direction opposite to the direction toward the tip of the arrow of the third direction Z is defined as down or downward. The first direction X, the second direction Y, and the third direction Z may also be referred to as the X direction, the Y direction, and the Z direction, respectively.

[0011] Furthermore, when the terms "second member above the first member" and "second member below the first member" are used, the second member may be in contact with the first member or may be located apart from the first member. In the latter case, a third member may be interposed between the first and second members. On the other hand, when the terms "second member above the first member" and "second member below the first member" are used, the second member is in contact with the first member.

[0012] Furthermore, it is assumed that an observation position for observing the display device is located at the tip of the arrow in the third direction Z, and viewing from this observation position toward the XY plane defined by the first direction X and the second direction Y is called planar view. Viewing a cross section of the display device in the XZ plane defined by the first direction X and the third direction Z, or in the YZ plane defined by the second direction Y and the third direction Z, is called cross-sectional view.

[0013] [Embodiment 1] Fig. 1 is a plan view showing a schematic configuration of a display device in embodiment 1. Fig. 2 is a plan view showing a schematic configuration of a display area of ​​the display device in Fig. 1. In embodiment 1, the first direction X and the second direction Y correspond to directions parallel to the main surfaces of the substrates constituting the display device DSP.

[0014] In the first embodiment, a liquid crystal display device employing a polymer dispersed liquid crystal (PDLC) is disclosed as a display device DSP. The display device DSP includes a display panel PNL, a wiring board FPC, an IC chip ICP (drive circuit), and a plurality of light sources LS.

[0015] The display panel PNL includes a substrate SUB1 (array substrate), a substrate SUB2 (counter substrate), a liquid crystal layer LC, and a sealing material SAL. The substrates SUB1 and SUB2 are formed in the shape of flat plates parallel to the XY plane and face each other in the third direction Z. The liquid crystal layer LC is disposed between the substrates SUB1 and SUB2.

[0016] The display panel PNL has a display area DA for displaying an image and a frame-shaped peripheral area PA surrounding the display area DA. A sealing material SAL is disposed surrounding the display area DA. The display area DA has a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y.

[0017] The sealant SAL is made of a cured mixture of a photocurable resin and a thermosetting resin. For example, an acrylic resin is used as the photocurable resin. For example, an epoxy resin is used as the thermosetting resin. The acrylic resin is cured by ultraviolet light (UV), and the epoxy resin is cured by heat.

[0018] The display area DA is provided with a plurality of scanning lines GL that extend along a first direction X and are arranged side by side along a second direction Y. A plurality of signal lines SL that are arranged side by side along the first direction X and extend along the second direction Y are also provided. Pixels PX are provided at the intersections of the plurality of scanning lines GL and the plurality of signal lines SL. One pixel PX is located in an area surrounded by two scanning lines GL and two signal lines SL.

[0019] Each of the pixels PX includes a switching element SW, a pixel electrode PE, and a common electrode CE. The switching element SW is formed of, for example, a thin film transistor (TFT) and is electrically connected to one scanning line GL and one signal line SL. The scanning line GL is electrically connected to the switching element SW in each of the pixels PX aligned in the first direction X. The signal line SL is electrically connected to the switching element SW in each of the pixels PX aligned in the second direction Y.

[0020] The pixel electrodes PE are electrically connected to the switching elements SW. A common electrode CE is provided in common to the plurality of pixel electrodes PE. The liquid crystal layer LC is driven by an electric field generated between the pixel electrodes PE and the common electrode CE. A capacitance CS is formed, for example, between an electrode having the same potential as the common electrode CE and an electrode having the same potential as the pixel electrodes PE.

[0021] The scanning lines GL, signal lines SL, switching elements SW, and pixel electrodes PE are provided on a substrate SUB1, and the common electrode CE is provided on a substrate SUB2. The scanning lines GL extend into the peripheral area PA and are electrically connected to the IC chip GIC. The signal lines SL extend into the peripheral area PA and are electrically connected to the IC chip SIC. When the IC chip GIC and the IC chip SIC are not distinguished, they are referred to as an IC chip ICP (drive circuit).

[0022] The IC chip ICP is electrically connected to the wiring board FPC. The IC chip ICP has built-in components such as a display driver that outputs signals necessary for image display. The IC chip ICP may also be mounted on the wiring board FPC.

[0023] The wiring board FPC is electrically connected to terminals arranged on the extension portion Ex of the board SUB1. The extension portion Ex corresponds to a portion of the board SUB1 that does not face the board SUB2. For example, the wiring board FPC is a flexible printed wiring board.

[0024] The plurality of light sources LS overlaps the extension portion Ex. The light sources LS are arranged at intervals along the first direction X. Each of the plurality of light sources LS includes, for example, a light-emitting element that emits red (R) light, a light-emitting element that emits green (G) light, and a light-emitting element that emits blue (B) light. These light-emitting elements may be, for example, light-emitting diodes (LEDs), but are not limited to this example.

[0025] Fig. 3 is a cross-sectional view showing an example of a configuration applicable to the display panel shown in Fig. 1. The substrate SUB1 includes a base material BA1, insulating layers INS1 and INS2, a capacitive electrode YE, an alignment film AL1, a switching element SW, and a pixel electrode PE. The base material BA1 has a surface BA1a and a surface BA1b located on the opposite side of the surface BA1a along the third direction Z. The surfaces BA1a and BA1b are also referred to as the lower surface and upper surface of the base material BA1, respectively.

[0026] The switching element SW is disposed on the surface BA1b. The insulating layer INS1 covers the switching element SW. Although the switching element SW is simplified in FIG. 3, in reality, the switching element SW includes a semiconductor layer and various electrodes. Furthermore, the scanning lines GL and signal lines SL shown in FIG. 1 are disposed between the base material BA1 and the insulating layer INS1, but are not shown in FIG. 3.

[0027] The capacitance electrode YE is disposed between the insulating layers INS1 and INS2. The pixel electrode PE is disposed for each pixel PX between the insulating layer INS2 and the alignment film AL1. The pixel electrode PE is electrically connected to the switching element SW through an opening OP in the capacitance electrode YE. The pixel electrode PE faces the capacitance electrode YE to form the above-mentioned capacitance CS. The alignment film AL1 covers the pixel electrode PE. The capacitance CS may be formed between other electrodes, rather than between the pixel electrode PE and the capacitance electrode YE.

[0028] The substrate SUB2 includes a base material BA2, a light-shielding layer LB, an overcoat layer (insulating layer) OC, an alignment film AL2, and a common electrode CE. The substrate BA2 has a surface BA2a facing the substrate SUB1 and a surface BA2b located on the opposite side of the surface BA2a along the third direction Z. The surfaces BA2a and BA2b are also referred to as the lower surface and upper surface of the substrate BA2, respectively.

[0029] In the present disclosure, the substrates BA1 and BA2 are also referred to as the first substrate and the second substrate, respectively, and the alignment films AL1 and AL2 are also referred to as the first alignment film and the second alignment film, respectively.

[0030] The light-shielding layer LB and the common electrode CE are disposed on the surface BA2a side. For example, the light-shielding layer LB faces the switching elements SW, the scanning lines GL, and the signal lines SL. The common electrode CE is disposed across the plurality of pixels PX and faces the plurality of pixel electrodes PE in the third direction Z. The common electrode CE also covers the light-shielding layer LB. The common electrode CE has the same potential as the capacitive electrode YE. An overcoat layer OC covers the common electrode CE. An alignment film AL2 covers the overcoat layer OC. The liquid crystal layer LC is disposed between the alignment films AL1 and AL2 and is in contact with these alignment films AL1 and AL2. Note that the overcoat layer OC may not be provided, and the alignment film AL2 may cover the common electrode CE.

[0031] The common electrode CE may be included in the substrate SUB1 instead of the substrate SUB2. When the common electrode CE is provided on the substrate SUB1, the common electrode CE may be disposed so that a horizontal electric field is generated between the pixel electrodes PE and the common electrode CE.

[0032] As described above, the light source LS and the wiring board FPC are provided on the extension portion Ex on the substrate SUB1 (on the base material BA1). The light source LS does not have to be provided on the extension portion Ex. The light source LS may be disposed outside the display panel PNL, on the opposite side of the extension portion Ex along the direction opposite to the second direction Y.

[0033] The substrates BA1 and BA2 are transparent insulating substrates such as glass substrates or plastic substrates. The insulating layer INS1 is formed of a transparent insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or acrylic resin. In one example, the insulating layer INS1 includes an inorganic insulating film and an organic insulating film. The insulating layer INS2 is an inorganic insulating film such as silicon nitride. The capacitive electrode YE, the pixel electrode PE, and the common electrode CE are transparent electrodes formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0034] The configuration of the display panel PNL is not limited to the examples in Figures 1 and 2. For example, the substrate SUB1 may not include the capacitive electrode YE, and the substrate SUB2 may not include the light-shielding layer LB.

[0035] The display device DSP does not include a polarizing plate. That is, no polarizing plate is provided on the surface BA1a of the substrate SUB1 of the display panel PNL, and no polarizing plate is provided on the surface BA2b of the substrate SUB2.

[0036] 4 is a cross-sectional view showing an example of a schematic configuration of a display panel. The display panel PNL has a liquid crystal layer LC between a substrate SUB1 and a substrate SUB2. In embodiment 1, the liquid crystal layer LC is a polymer dispersed liquid crystal (PDLC) and has a polymer PM containing polymer chains and liquid crystal molecules MC. The liquid crystal molecules MC are dispersed in the gaps between the polymer PM.

[0037] The substrate SUB1 includes a base material BA1, an insulating layer INS1, a signal line SL, an insulating layer INS2, a capacitive electrode YE, a pixel electrode PE, and an alignment film AL1.

[0038] The insulating layer INS1 is provided on the surface BA1b of the base material BA1. The signal line SL is provided between the base material BA1 and the insulating layer INS1 and is covered by the insulating layer INS1. The capacitive electrode YE is provided on the insulating layer INS1 and is covered by the insulating layer INS2.

[0039] The pixel electrode PE is provided on the insulating layer INS2 in the opening OP and is covered with an alignment film AL1. That is, the capacitive electrode YE is provided between the base material BA1 and the pixel electrode PE. The pixel electrode PE faces the capacitive electrode YE with an insulating layer INS2 sandwiched therebetween, forming a capacitance CS of the pixel PX. The alignment film AL1 is in contact with the liquid crystal layer LC.

[0040] The substrate SUB2 includes a base material BA2, a common electrode CE, and an alignment film AL2. As in Fig. 3, an overcoat layer may be provided between the common electrode CE and the alignment film AL2. The common electrode CE is provided in contact with a surface BA2a of the base material BA2 and is covered with the alignment film AL2.

[0041] In addition, on the substrate SUB2, a light-shielding layer may be provided directly above each of the switching elements SW, the scanning lines GL, and the signal lines SL. Also, a transparent insulating layer (overcoat layer) may be provided between the base material BA2 and the common electrode CE. The common electrode CE faces a plurality of pixel electrodes PE. Also, the common electrode CE is electrically connected to the capacitive electrode YE and has the same potential as the capacitive electrode YE. The alignment film AL2 is in contact with the liquid crystal layer LC.

[0042] The polymer PM and the liquid crystal molecules MC each have optical anisotropy or refractive index anisotropy. The response of the polymer PM to an electric field is lower than that of the liquid crystal molecules MC. For example, the alignment direction of the polymer PM hardly changes regardless of the electric field between the pixel electrode PE and the common electrode CE. On the other hand, the alignment direction of the liquid crystal molecules MC changes depending on the electric field.

[0043] When no electric field is applied to the liquid crystal layer LC or when the electric field is extremely weak, the optical axes of the polymer PM and the liquid crystal molecules MC are approximately parallel to each other. The refractive indices of the liquid crystal molecules MC and the polymer PM are substantially equal. In other words, the difference in refractive index between the liquid crystal molecules MC and the polymer PM is substantially eliminated. Therefore, light incident on the liquid crystal layer LC is transmitted through the liquid crystal layer LC with almost no scattering within the liquid crystal layer LC. Hereinafter, this state will be referred to as the transparent state. The voltage applied to the pixel electrode PE to achieve the transparent state will be referred to as the transparent voltage. The transparent voltage may be the same as the common voltage applied to the common electrode CE, or it may be a voltage slightly different from the common voltage.

[0044] On the other hand, when a sufficient electric field is applied to the liquid crystal layer LC, the optical axes of the polymer PM and the liquid crystal molecules MC intersect with each other. Therefore, light incident on the liquid crystal layer LC is scattered within the liquid crystal layer LC. This state is hereinafter referred to as the scattering state. The voltage applied to the pixel electrode PE to achieve the scattering state is called the scattering voltage. The scattering voltage is a voltage that creates a larger potential difference with the common electrode CE than the transparent voltage.

[0045] As described above, in a display device that uses a polymer dispersed liquid crystal (PDLC) as the liquid crystal layer LC, the pixels PX are driven by field sequential driving. To drive the display device at higher speed, multiple signal lines SL are provided between adjacent pixels PX. This makes it possible to simultaneously write video signals to pixels on multiple rows.

[0046] However, because the operating temperature range of polymer-dispersed liquid crystals is narrow, in display devices using polymer-dispersed liquid crystals (PDLCs) as the liquid crystal layer LC, the liquid crystal layer LC may not function at low temperatures, resulting in poor display. Therefore, such display devices may be subject to limitations on the environmental conditions under which they can be used, particularly in terms of the temperature range. Alternatively, a heater or other device may need to be added to the display device, which may increase the manufacturing process and manufacturing costs.

[0047] In the display device DSP of the first embodiment, the signal lines SL for sending video signals to the pixels PX are also equipped with the function of a heat source. This allows the liquid crystal layer LC to be placed within a temperature range in which the polymer dispersed liquid crystal can be driven. This makes it possible to obtain a display device that is not restricted by the environmental conditions under which it can be used.

[0048] The heat source in the first embodiment is provided in a test circuit, which is a test circuit for checking whether the signal lines SL, scanning lines GL, switching elements SW (thin film transistors (TFTs)), etc. function normally before mounting an IC chip ICP (drive circuit) and a wiring board FPC.

[0049] 5 is a circuit diagram showing a schematic configuration of the display area and test circuit of the display device DSP. The display device DSP shown in FIG. 5 is provided with a scanning line test circuit GTC and a signal line test circuit STC outside the display area DA.

[0050] The scanning line inspection circuit GTC is provided between the display area DA and the IC chip GIC. The scanning line inspection circuit GTC is electrically connected to a plurality of scanning lines GL. The scanning line inspection circuit GTC is provided with a plurality of transistors GTR, which are inspection switches. That is, the plurality of scanning lines GL are electrically connected to the scanning line inspection circuit GTC and the IC chip GIC, respectively.

[0051] The signal line inspection circuit STC is provided between the display area DA and the IC chip SIC. The signal line inspection circuit STC is electrically connected to a plurality of signal lines SL. The signal line inspection circuit STC is provided with a plurality of transistors STR, which serve as inspection switches. That is, the plurality of signal lines SL are electrically connected to the signal line inspection circuit STC and the IC chip SIC, respectively.

[0052] It is assumed that the plurality of scanning lines GL includes m scanning lines GL1 to GLm, the plurality of signal lines SL includes n signal lines SL1 to SLn, the plurality of transistors GTR includes m transistors GTR1 to GTRm, and the plurality of transistors STR includes n transistors STR1 to STRn.

[0053] Each of the pixels PX is provided in an area surrounded by two scanning lines GL and two signal lines SL. Each of the pixels PX has one scanning line GL, one signal line SL, one switching element SW, and one capacitance CS.

[0054] 5, the common electrode CE is connected to the wiring CEO, and one of the pair of electrodes of the capacitor CS is connected to the wiring CEA. The wiring CEO is provided on the substrate SUB2, and the wiring CEA is provided on the substrate SUB1. However, the display device DSP of the first embodiment is not limited to this. As in FIG. 2, the common electrode CE and one of the pair of electrodes of the capacitor CS may be connected to the same wiring.

[0055] FIG. 5 shows pixel PX11 having scan line GL1 and signal line SL1, pixel PX21 having scan line GL2 and signal line SL1, pixel PX12 having scan line GL1 and signal line SL2, and pixel PX22 having scan line GL2 and signal line SL2.

[0056] The m transistors GTR1 to GTRm are electrically connected to the scan lines GL1 to GLm, respectively. The n transistors STR1 to STRn are electrically connected to the signal lines SL1 to SLn, respectively. When the transistors GTR1 to GTRm are not distinguished from one another, they are referred to as transistors GTR. When the transistors STR1 to STRn are not distinguished from one another, they are referred to as transistors STR.

[0057] The gate of the transistor GTR is electrically connected to the wiring TGCL. The source of the transistor GTR is electrically connected to the wiring TGL. The drain of the transistor GTR is electrically connected to the scanning line GL. An inspection scanning control signal TGCS is input to the gate of the transistor GTR via the wiring TGCL. An inspection scanning signal TGS is input to the source of the transistor GTR via the wiring TGL.

[0058] The gate of the transistor STR is electrically connected to the wiring TVCL. The source of the transistor STR is electrically connected to the wiring TVL. The drain of the transistor STR is electrically connected to the signal line SL. A test video control signal TVCS is input to the gate of the transistor STR via the wiring TVCL. A test video signal TVS is input to the source of the transistor STR via the wiring TVL.

[0059] During inspection before mounting the IC chip ICP, a test scan signal TGS is input from the scan line inspection circuit GTC to the scan line GL. Similarly, a test video signal TVS is input from the signal line inspection circuit STC to the signal line SL. This drives the switching element SW, which writes a video signal to the pixel PX. This makes it possible to detect defects in the display panel PNL. If there are no defects in the display panel PNL, the IC chip ICP and wiring board FPC are mounted, and the display device DSP is completed.

[0060] Although not shown, in order to detect defects between adjacent signal lines SL or scanning lines GL, it is also possible to provide separate systems for odd-numbered rows and even-numbered rows or odd-numbered columns and even-numbered columns.

[0061] In reality, the scan line inspection circuit GTC and the signal line inspection circuit STC are unnecessary after the display device DSP is completed. Therefore, it is necessary to prevent the scan line inspection circuit GTC and the signal line inspection circuit STC from operating. For example, the transistor GTR is always in an off state, and similarly, the transistor STR is always in an off state. However, in the present invention, as will be described later, the scan line inspection circuit GTC and the signal line inspection circuit STC are reused as heat sources after the IC chip ICP and the wiring board FPC are mounted.

[0062] Fig. 6 is a timing chart showing the driving of the display device. One sub-frame period PSF shown in Fig. 6 includes a video signal writing period WVS, a heat generation power supply period AHT, a light source lighting period LSO, a reset period RST, and a common voltage inversion period ICM.

[0063] During the video signal writing period WVS, a sequential scanning drive signal is input to the scanning lines GL1 to GLm. As a result, the scanning lines GL1 to GLm are sequentially changed from a low potential state (also called a low state) to a high potential state (also called a high state) and from the high potential state to the low potential state.

[0064] When each of the scanning lines GL1 to GLm changes from a low potential state to a high potential state, the switching element SW of the pixel PX connected to the scanning line GL that has changed to the high potential state changes to the ON state. Next, video signals are input sequentially to the signal lines SL1 to SLn. While video signals are input to the signal lines SL1 to SLn, as described above, the scanning line inspection circuit GTC and the signal line inspection circuit STC do not operate. When video signals are input to all of the signal lines SL1 to SLn, the scanning line GL that is in the high potential state changes to the low potential state. As a result, the switching element SW that is in the ON state changes to the OFF state.

[0065] During the video signal writing period WVS, the voltage COM applied to the common electrode CE is in a low potential state. The potential of the inspection video control signal TVCS is also in a low potential state. This causes the transistor STR to be in an off state. The potential of the inspection video signal TVS is in a high impedance state (Hi-z).

[0066] During the heat generation and power supply period AHT and the light source lighting period LSO, a high voltage Vh is written to the signal line SL from the IC chip SIC. The high-voltage inspection video control signal TVCS is input to the gate of the transistor STR of the signal line inspection circuit STC. This turns on the transistor STR.

[0067] A test video signal TVS of voltage Ve is input to the source of the transistor STR via the wiring TVL. As described above, the scanning line GL is in a low potential state and the switching element SW is in an off state, so the test video signal TVS of voltage Ve is not written to the pixel PX. The voltage Ve may be any voltage lower than the voltage Vh. However, this is not limited thereto, and the voltage Ve may be a voltage higher than the voltage Vh. If the voltages Ve and Vh are different voltages, a potential difference, as described below, occurs, generating Joule heat.

[0068] During the heat generation and power supply period AHT and the light source light-on period LSO, a low potential is applied to the scanning lines GL1 to GLm, which turns off the switching element SW of the pixel PX. The voltage COM applied to the common electrode CE is in a low potential state.

[0069] During the light source lighting period LSO in which the light source LS is turned on, as described above, the switching element SW of the pixel PX is in the off state, so no signal is written to the pixel PX. By providing the heat generation and power supply period AHT simultaneously with the light source lighting period LSO, there is no need to provide a separate heat generation and power supply period AHT.

[0070] As described above, the signal line SL is supplied with a voltage Ve from the source of the transistor STR and a voltage Vh from the IC chip SIC. This generates a potential difference ΔV (=Vh-Ve) across the signal line SL. When the potential difference ΔV occurs, Joule heat is generated due to the resistance of the signal line SL. The generated Joule heat heats the liquid crystal layer LC and, in turn, the display panel PLN.

[0071] 7 is a diagram showing the voltage applied to the signal line during the heat generation and power supply period. As described above, by utilizing the generated Joule heat, it is possible to obtain a display device that is not restricted by the environmental conditions for use.

[0072] Returning to Figure 6, at the end of the heat generation power supply period AHT, the inspection video control signal TVCS is set to a low potential state, which turns off the transistor STR. This stops the application of voltage Ve to the signal line SL, and stops the generation of Joule heat.

[0073] After the end of the heat generation power supply period AHT, a reset period RST and a common voltage inversion period ICM are passed, followed by the end of one sub-frame period PSF. During the common voltage inversion period ICM, the voltage COM applied to the common electrode CE is inverted from a low potential state to a high potential state. The voltage COM is repeatedly inverted between the low potential state and the high potential state for each sub-frame period PSF.

[0074] The potential applied to the signal line SLn and the potential of the signal from the IC chip SIC are in a low potential state during the reset period RST, and are in a high impedance state (Hi-z) during the common voltage inversion period ICM.

[0075] In the reset period RST and the common voltage inversion period ICM, the potential of the inspection video control signal TVCS is in a low potential state, as in the video signal writing period WVS. In the reset period RST and the common voltage inversion period ICM, the potential of the inspection video signal TVS is in a high impedance state (Hi-z), as in the video signal writing period WVS.

[0076] 6, the heat generation power supply period AHT is provided for each sub-frame period PSF, but the first embodiment is not limited to this. The heat generation power supply period AHT may be provided once every two sub-frame periods PSF, for example. The frequency of the heat generation power supply period AHT relative to the sub-frame period PSF may be changed depending on the ambient temperature of the display device DSP.

[0077] The amount of heat generated can also be controlled by changing the voltage Vh, which is the output voltage of the IC chip SIC. For example, by increasing the voltage Vh, the potential difference ΔV can be increased. The larger the potential difference ΔV, the greater the amount of heat generated. By changing the voltage Vh according to the ambient temperature of the display device DSP, the amount of heat generated can also be changed.

[0078] In the display device DSP of embodiment 1, the signal line test circuit STC is used to heat the liquid crystal layer LC containing polymer dispersed liquid crystal. The temperature of the liquid crystal layer LC can be increased without providing an external heat source such as a heater. This prevents degradation of the display quality of the display device DSP and makes it possible to obtain a display device that is not restricted by the environmental conditions under which it is used.

[0079] [Embodiment 2] Fig. 8 is a circuit diagram showing a configuration example of a display device according to embodiment 2. The configuration example shown in Fig. 8 differs from the configuration example shown in Fig. 5 in that a transistor is also provided on the IC chip SIC side.

[0080] 8, a transistor STRB equivalent to the transistor STR, which is an inspection switch, is provided between the IC chip SIC and the signal line SL. When the signal line SL generates heat, power is supplied not from the IC chip SIC but from the wiring TVBL connected to the transistor STRB.

[0081] As described above, the transistor STRB, the wiring TVBL, and the wiring TVCL are provided between the IC chip SIC and the signal line SL. The transistor STRB includes a transistor STRB1 and a transistor STRB2.

[0082] The gate of the transistor STRB is connected to the line TVCL, the source of the transistor STRB is connected to the line TVBL, and the drain of the transistor STRB is connected to the signal line SL.

[0083] The wiring TVCL extends from the outside of the display area DA along the edge of the display area DA, reaching from the signal line test circuit STC to the gate of the transistor STRB. A test video control signal TVCS is input to the gate of the transistor STRB via the wiring TVCL. A test video signal TVBS is input to the source of the transistor STRB via the wiring TVBL.

[0084] In FIG. 8, for ease of understanding, the illustration of essential components such as the scanning line test circuit GTC is omitted.

[0085] Fig. 9 is a timing chart showing the driving of the display device. In the timing chart shown in Fig. 9, unlike the timing chart shown in Fig. 6, the IC chip SIC does not output during the heat generation power supply period AHT, and is put into a high impedance (Hi-z) state.

[0086] In FIG. 9, the driving of the signal line SLn, the scanning line GL1, the scanning line GL2, the scanning line GL3, the scanning line GLm, and the voltage COM is the same as in FIG. 6, so the description of FIG. 6 will be used and will be omitted.

[0087] During the heat generation power supply period AHT, the inspection video control signal TVCS in a high potential state is input to the gate of the transistor STR via the line TVCL, thereby turning on the transistor STR.

[0088] A test video signal TVS in a low potential state (voltage Ve) is input to the source of the transistor STR via a line TVL.

[0089] The inspection video control signal TVCS in a high potential state is input to the gate of the transistor STRB via the line TVCL, thereby turning on the transistor STRB.

[0090] A test video signal TVBS in a high potential state (voltage Vh) is input to the source of the transistor STRB via a line TVBL.

[0091] As described above, a voltage Ve is input to the signal line SL from the source of the transistor STR, and a voltage Vh is input to the source of the transistor STRB. This generates a potential difference ΔV (=Vh-Ve) on the signal line SL. When the potential difference ΔV occurs, Joule heat is generated due to the resistance of the signal line SL. The generated Joule heat heats the liquid crystal layer LC and further the display panel PLN.

[0092] As in the first embodiment, in the second embodiment, the voltage Ve may be lower than the voltage Vh. However, without being limited to this, the voltage Ve may be higher than the voltage Vh. If the voltages Ve and Vh are different voltages, a potential difference ΔV occurs, generating Joule heat.

[0093] At the end of the heat generation power supply period AHT, the inspection video control signal TVCS is set to a low potential state, which turns off the transistors STR and STRB. This stops the application of voltage to the signal line SL, and stops the generation of Joule heat.

[0094] In the second embodiment, too, it is possible to obtain a display device that is not restricted by the environmental conditions for use by utilizing the generated Joule heat.

[0095] Furthermore, by not using the IC chip SIC, it is possible to reduce the self-power consumption of the IC chip SIC. Power can be supplied directly from a power source as the test video signal TVBS without going through the IC chip SIC. This reduces power loss as a display device DSP.

[0096] In this disclosure, the transistor STR is referred to as the first signal line inspection transistor, and the transistor STRB is referred to as the second signal line inspection transistor. The transistor GTR is referred to as the scan line inspection transistor. The IC chip GIC and the IC chip SIC are referred to as the scan line IC chip and the signal line IC chip, respectively. The wiring TVL is referred to as the first inspection video wiring, the wiring TVCL is referred to as the inspection video control wiring, and the wiring TVBL is referred to as the second inspection video wiring. The voltages Vh and Ve are referred to as the first voltage and the second voltage, respectively.

[0097] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0098] AHT...heat generation power supply period, DSP...display device, GIC...IC chip, GL...scanning line, GTC...scanning line inspection circuit, GTR...transistor, LC...liquid crystal layer, LS...light source, LSO...light source lighting period, PLN...display panel, PX...pixel, SIC...IC chip, SL...signal line, STC...signal line inspection circuit, STR...transistor, STRB...transistor, TGCL...wiring, TGCS...inspection scanning control signal, TGL...wiring, TGS...inspection scanning signal, TVBL...wiring, TVBS...inspection video signal, TVCL...wiring, TVCS...inspection video control signal, TVL...wiring, TVS...inspection video signal, Ve...voltage, Vh...voltage.

Claims

1. an array substrate; A counter substrate; a liquid crystal layer provided between the array substrate and the counter substrate; Multiple light sources; Equipped with The array substrate comprises: A plurality of scan lines; A plurality of signal lines; a plurality of pixels provided at intersections of the plurality of scanning lines and the plurality of signal lines; a signal line inspection circuit connected to the plurality of signal lines; a plurality of first signal line inspection transistors provided in the signal line inspection circuit and connected to the plurality of signal lines; an inspection video control wiring connected to gates of the plurality of first signal line inspection transistors; a first inspection video line connected to the sources of the plurality of first signal line inspection transistors; a signal line IC chip connected to one end of each of the plurality of signal lines; Equipped with a drain of each of the plurality of first signal line inspection transistors is connected to the other end of each of the plurality of signal lines; the signal line IC chip applies a first voltage to one end of each of the plurality of signal lines during a light source lighting period of the plurality of light sources; during the light source lighting period, an inspection video control signal is input via the inspection video control wiring, thereby turning on the plurality of first signal line inspection transistors; A display device, wherein a second voltage different from the first voltage is applied from the source of each of the plurality of first signal line inspection transistors in the on state.

2. The display device of claim 1 , wherein the second voltage is lower than the first voltage.

3. The display device according to claim 1 , wherein the liquid crystal layer is a liquid crystal layer containing a polymer dispersed liquid crystal.

4. a scan line test circuit connected to the plurality of scan lines; a plurality of scan line inspection transistors provided in the scan line inspection circuit and connected to the plurality of scan lines; The display device of claim 1 further comprising:

5. an array substrate; A counter substrate; a liquid crystal layer including a polymer dispersed liquid crystal, the liquid crystal layer being disposed between the array substrate and the counter substrate; Multiple light sources; Equipped with The array substrate comprises: A plurality of scan lines; A plurality of signal lines; a plurality of pixels provided at intersections of the plurality of scanning lines and the plurality of signal lines; a signal line inspection circuit connected to the plurality of signal lines; a plurality of first signal line inspection transistors provided in the signal line inspection circuit and connected to the plurality of signal lines; an inspection video control wiring connected to gates of the plurality of first signal line inspection transistors; an inspection video line connected to the sources of the plurality of first signal line inspection transistors; a signal line IC chip connected to one end of each of the plurality of signal lines; a plurality of second signal line inspection transistors provided between the signal line IC and the plurality of pixels; Equipped with a drain of each of the plurality of first signal line inspection transistors is connected to one end of each of the plurality of signal lines; a drain of each of the second signal line inspection transistors is connected to the other end of each of the signal lines; during a light source lighting period of the plurality of light sources, an inspection video control signal is input via the inspection video control wiring, thereby turning on the plurality of first signal line inspection transistors and the plurality of second signal line inspection transistors; a first voltage is applied from each of the drains of the plurality of first signal line inspection transistors in the on state to one end of each of the plurality of signal lines during the light source lighting period; a second voltage different from the first voltage is applied from each of the drains of the second signal line inspection transistors in the on state to the other end of each of the signal lines during the light source lighting period.

6. The display device according to claim 5 , wherein the second voltage is higher than the first voltage.

7. The display device according to claim 5 , wherein the liquid crystal layer is a liquid crystal layer containing a polymer dispersed liquid crystal.

8. a scan line test circuit connected to the plurality of scan lines; a plurality of scan line inspection transistors provided in the scan line inspection circuit and connected to the plurality of scan lines; The display device of claim 5 further comprising:

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