Capacitor array circuit and measurement method of difference in capacity value

Abstract

To realize more precise measurement of a difference in a capacity value between capacitors.SOLUTION: A capacitor array circuit 1 comprises: at least two basic circuits 21, 22 composed of a capacity circuit composed of at least one capacitor, and a switch circuit; a first switch Q1 that is connected to one end of the basic circuits 21, 22 in a first node N1 and applies first potential VB1; a measurement terminal 3; and a second switch Q2 between the first node N1 and the measurement terminal 3. A switch circuit SW1 switches application of second potential VB2 to a first capacity circuit CC1 and application of third potential VB3 that is lower than the second potential VB2. A switch circuit SW2 switches application of the second potential VB2 to a second capacity circuit CC2 and application of the third potential VB3, and allows current (i) based on the charge of the first node N1 to flow in and out by inverting the polarity of voltage applied to a series circuit SC of the first capacity circuit CC1 and the second capacity circuit CC2 between when the first switch Q1 is closed and when it is open.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a capacitor array circuit and a method for measuring differences in capacitance values. [Background technology]

[0002] Generally, electronic circuits that require high-precision operation require high accuracy in the characteristic values ​​of the passive elements that make up the electronic circuit. For example, in a capacitive DA converter, the multiple capacitors provided corresponding to each bit of the input digital value require high accuracy because the weight of each bit of the digital value depends on its capacitance value. Furthermore, to achieve high linearity in the output analog value, the capacitance values ​​of the capacitors corresponding to each bit must have high relative accuracy. In other words, a high degree of matching may be required, such that two capacitors have extremely accurate identical capacitance values. However, if a capacitance mismatch exists, in which the required matching is not fully achieved, the characteristics desired for the electronic circuit may not be achieved.

[0003] On the other hand, various electronic circuits often contain parasitic capacitance and stray capacitance that are not intended by the circuit designer. Unintentional capacitance components such as parasitic capacitance can affect the operation of electronic circuits, degrading their characteristics or causing malfunctions. When such parasitic capacitance occurs around multiple capacitors that require high matching, the actual matching accuracy may be insufficient even if the capacitance values ​​of the target capacitors themselves are sufficiently matched. In particular, among the various types of semiconductor integrated circuit devices that require high-speed or high-precision operation, capacitance mismatches due to the influence of unintended parasitic capacitance can significantly impair the characteristics of the device.

[0004] In order to detect in advance electronic circuits that do not achieve the intended characteristics due to capacitance mismatching and take necessary measures, it is necessary to accurately measure the actual capacitance difference between the target capacitors. That is, it is required to be able to accurately measure the capacitance difference between the target capacitors in an actually realized electronic circuit, including capacitance values ​​such as parasitic capacitance. As a technology for accurately measuring minute differences in capacitance, including parasitic capacitance, between two capacitors, a known method is to measure the parasitic capacitance between metal wirings in an integrated circuit device using the so-called CBCM (Charge Based Capacitance Measurement) method (see, for example, Non-Patent Document 1).

[0005] In the method described in Non-Patent Document 1, as shown in FIG. 13, the parasitic capacitance C101 of metal wiring M101 having an intersection X102 with metal wiring M102 in an adjacent layer is charged and discharged together with the parasitic capacitance C100 of metal wiring M100 that does not have the intersection. The capacitance value of the parasitic capacitance at the intersection X102 is then measured from the difference between the currents I100 and I101 flowing through the respective charge / discharge circuits formed by transistors Q101 to Q104. That is, as shown in FIG. 14, currents I100 and I101 flow through the drive circuit in response to gate signals φ101 and φ102 of transistors Q101 to Q104 that constitute the charge / discharge circuit of FIG. 13. Specifically, during a period P100 when the gate signal φ101 of P-channel MOSFET transistors Q101 and Q102 is at VDD, the transistors Q101 and Q102 are in the off state, and therefore the currents I100 and I101 do not flow.

[0006] On the other hand, during period P101 when the level of gate signal φ101 is 0V and the level of gate signal φ102 of N-channel MOSFET transistors Q103 and Q104 is 0V, transistors Q101 and Q102 are on and transistors Q103 and Q104 are off. Therefore, current I100 flows through transistor Q101 to charge parasitic capacitance C100, and similarly, current I101 flows through transistor Q102 to charge parasitic capacitance C101. Currents I100 and I101 decrease as charging of parasitic capacitances C100 and C101 is completed. The charges stored in parasitic capacitances C100 and C101 are discharged during the next period P100. This charging and discharging is repeated at frequency f.

[0007] During such a charge / discharge cycle, the average value of current I100 and the average value of current I101 are measured by each ammeter. The average current Ia0 of current I100 and the average current Ia1 of current I101 are theoretically expressed by the following equations 101 and 102. Here, VDD is the charge voltage, f is the frequency of the charge / discharge cycle, Cv0 is the capacitance value of the parasitic capacitance of metal wiring M100 and its surrounding parts, Cv1 is the capacitance value of the parasitic capacitance of metal wiring M101 and its surrounding parts, and Cv2 is the capacitance value of the parasitic capacitance at intersection X102. Ia0=Cv0·VDD·f (Formula 101) Ia1=(Cv1+Cv2)·VDD·f···(Formula 102)

[0008] If metal wiring M100 and its periphery and metal wiring M101 and its periphery have the same structure except for the presence or absence of intersection X102, capacitance value Cv0 and capacitance value Cv1 are considered to be equal, and the following equation 103 holds: Regarding equation 103, since the charging voltage VDD and frequency f are known, capacitance value Cv2 of the parasitic capacitance due to intersection X102 can be obtained from average currents Ia0 and Ia1 obtained by measurement. Ia1-Ia0=Cv2·VDD·f (Formula 103)

[0009] Here, if the capacitance values ​​Cv0 and Cv1 are considered to be the two capacitance values ​​that require matching, and the capacitance value Cv2 is considered to be the difference between the capacitance values ​​Cv0 and Cv1, then it is believed that the above method can be used to measure even the slight difference in the capacitance values ​​of two capacitors that are expected to have approximately the same capacitance value.

[0010] On the other hand, it is known that the mismatch in capacitance values ​​of capacitors is inversely proportional to the 1 / 2 power of the electrode area of ​​the capacitors that generate each capacitance value (see, for example, Non-Patent Document 2). Therefore, from the perspective of obtaining a capacitor pair with high matching, it is considered desirable to form the target capacitors so that they have a larger area and therefore a larger capacitance value. [Prior art documents] [Non-patent literature]

[0011] [Non-Patent Document 1] James C. Chen et al., “An On-Chip, Attofarad Interconnect Charge-Based Capacitance Measurement (CBCM) Technique” 1996, IEDM [Non-patent document 2] Marcel.JMPelgrom, "Analog-to-Digital Conversion (4th Ed.)" Springer Publishing, p.299 Summary of the Invention [Problem to be solved by the invention]

[0012] When applying the CBCM method disclosed in Non-Patent Document 1 to measure the difference in capacitance between capacitors that require high matching, it is necessary to calculate the difference in the average charging currents (average currents) of two capacitors measured by an ammeter by subtraction, as shown in Equation 103 above. Here, the difference in the average currents of two capacitors designed to have the same capacitance is expected to be small. Therefore, in the subtraction to determine the difference between the two average currents, significant digits may be lost due to the accuracy of the measurement system including the ammeter, and the required accuracy for the final capacitance difference may not be obtained. In other words, if the measurement accuracy of the capacitance difference is such that the measured two average current values ​​are greater than the difference between the two currents by, for example, two or more digits, significant digits of the difference may be lost when the measurements are subtracted, resulting in the number of significant digits limiting the measurement accuracy of the capacitance difference. In particular, as described in Non-Patent Document 2, from the perspective of matching, it is desirable to form capacitors with larger capacitance values, and therefore a large charging current is expected to flow through each capacitor. Furthermore, ammeters capable of measuring large charging currents, or the measurement range capable of such measurements, are unlikely to have significant digits up to, say, a few pA, which is the number of significant digits required to detect a difference in current value corresponding to a difference in capacitance value. As a result, it may not be possible to measure the difference in capacitance value with the required accuracy.

[0013] In view of the above-mentioned problems, the present invention aims to achieve more accurate measurement of the difference in capacitance between the capacitors being measured than has been possible in the past by enabling direct measurement of the current corresponding to the difference in capacitance, rather than obtaining the difference in capacitance by subtracting measured current values. [Means for solving the problem]

[0014] A capacitor array circuit according to an embodiment of the present invention is a capacitor array circuit comprising at least two basic circuits each formed of a series circuit of a capacitance circuit formed of at least one capacitor and a switch circuit for switching a bias applied to the capacitance circuit, a first switch connected to one end of each of the at least two basic circuits at a first node and applying a first potential to the capacitance circuit when the first switch is in a closed state, a measurement terminal for causing a current based on a charge stored in the first node to flow in or out, and a second switch for connecting or disconnecting the first node and the measurement terminal, wherein the switch constituting a first basic circuit which is one of the at least two basic circuits is The switch circuit, which constitutes a second basic circuit, is one of the at least two basic circuits other than the first basic circuit, and switches between applying the second potential and applying the third potential to a second basic circuit, which is the capacitance circuit that constitutes the second basic circuit. When the first switch is in a closed state and when it is in an open state, the polarity of the voltage applied to the series circuit of the first capacitance circuit and the second capacitance circuit via the first node is reversed, thereby causing a current based on the charge stored in the first node to flow out or in from the measurement terminal.

[0015] A method for measuring a difference in capacitance values ​​according to an embodiment of the present invention is a method for measuring a difference between a capacitance value of a capacitance circuit made up of one or more first capacitors among a plurality of capacitors connected to each other at one end at a first node, and a capacitance value of a capacitance circuit made up of one or more second capacitors among the plurality of capacitors, the method including: a first step of applying a first potential to the one end of the first capacitor and the one end of the second capacitor via the first node by closing a first switch while separating the first node from an ammeter, applying a second potential to the other end of the first capacitor, and applying a third potential lower than the second potential to the other end of the second capacitor; and a second step of closing the first switch after the first step. a second step of isolating the first node from the first potential by opening the first capacitor; a third step of, after the second step, applying the third potential to the other end of the first capacitor and applying the second potential to the other end of the second capacitor, thereby reversing the polarity of the voltage applied to the series circuit of the first capacitor and the second capacitor via the first node; a fourth step of, after the third step, applying the first potential to the first node via the ammeter by connecting the first node and the ammeter with a second switch; and a fifth step of repeating the first step to the fourth step and measuring the average current flowing through the ammeter with the ammeter. [Effects of the Invention]

[0016] The capacitor array circuit and the method for measuring the difference in capacitance of the present invention enable direct measurement of the current corresponding to the difference in capacitance, and are therefore believed to enable measurement of the difference in capacitance between the capacitors being measured with higher accuracy than previously possible. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 2 is a circuit diagram showing an example of a capacitor array circuit according to the embodiment. [Figure 2]5A and 5B are timing charts showing an example of the open / closed states of each switch and the current flowing through the measurement terminals when measuring the difference in capacitance value in the capacitor array circuit according to the embodiment. [Figure 3A] FIG. 2 is a circuit diagram showing a first state of the capacitor array circuit according to the embodiment. [Figure 3B] FIG. 4 is a circuit diagram showing a second state of the capacitor array circuit according to the embodiment. [Figure 3C] FIG. 10 is a circuit diagram showing a third state of the capacitor array circuit according to the embodiment. [Figure 3D] FIG. 10 is a circuit diagram showing a fourth state of the capacitor array circuit according to the embodiment. [Figure 4A] 5A and 5B are schematic diagrams illustrating the potential of a first node and the state of charge accumulation in a first state; [Figure 4B] 5A and 5B are schematic diagrams illustrating the potential of the first-node and the charge accumulation state in a third state; [Figure 4C] 5A and 5B are schematic diagrams illustrating the potential of the first-node and the charge accumulation state in a fourth state; [Figure 5A] FIG. 10 is a circuit diagram showing a modified example of the capacitance circuit of the capacitor array circuit according to the embodiment. [Figure 5B] FIG. 10 is a circuit diagram showing a modified example of the capacitance circuit of the capacitor array circuit according to the embodiment. [Figure 6] FIG. 10 is a circuit diagram showing a modified example of the capacitor array circuit of the embodiment. [Figure 7] FIG. 10 is a diagram showing a modified example of a switch in the basic circuit of the capacitor array circuit according to the embodiment. [Figure 8] 4A and 4B are diagrams illustrating dummy switches provided in the capacitor array circuit according to the embodiment; [Figure 9] FIG. 2 is a circuit diagram showing a first application example of the capacitor array circuit according to the embodiment. [Figure 10] 10 is a timing diagram showing an example of the connection state of each switch in the capacitor array circuit of FIG. 9 and the current flowing through the measurement terminal. [Figure 11] FIG. 10 is a circuit diagram showing a second application example of the capacitor array circuit according to the embodiment. [Figure 12A] 12 is a timing chart showing an example of the connection state of each switch in the capacitor array circuit of FIG. 11 and the current flowing through the measurement terminal. [Figure 12B] 12 is a timing chart showing an example of the connection state of each switch in the capacitor array circuit of FIG. 11 and the current flowing through the measurement terminal. [Figure 13] FIG. 10 is a diagram showing a conventional method for measuring a parasitic capacitance value between metal wirings in an integrated circuit device. [Figure 14] 14 is a timing diagram illustrating switch states and currents in the method shown in FIG. 13. DETAILED DESCRIPTION OF THE INVENTION

[0018] The capacitor array circuit and the method for measuring the difference in capacitance values ​​of the present invention will be described in order with reference to the drawings. However, the capacitor array circuit and the method for measuring the difference in capacitance values ​​of the present invention are not limited to the embodiments described below. For example, the circuits shown in each drawing may include circuit elements that are not shown, or conversely, may not include all of the circuit elements that are shown. Furthermore, each element shown in each drawing may have any characteristics or constants, and it should be understood that the characteristics and constants of each element are limited only by the description of the claims.

[0019] <Basic configuration of capacitor array circuit> 1 shows a capacitor array circuit 1 of a first embodiment having a basic configuration, which is an example of a capacitor array circuit of an embodiment. The capacitor array circuit 1 includes a first switch Q1, a second switch Q2, a measurement terminal 3, a first node N1, and at least two basic circuits. The capacitor array circuit 1 of the example of FIG. 1 includes two basic circuits: a first basic circuit 21 and a second basic circuit 22. However, the capacitor array circuit of the embodiment may include any number of the basic circuits described below.

[0020] Each basic circuit is configured with a series circuit of a capacitance circuit composed of at least one capacitor and a switch circuit that switches the bias applied to this capacitance circuit. In the example capacitor array circuit 1 of FIG. 1, the first basic circuit 21 is configured with a series circuit of a first capacitance circuit CC1 and a switch circuit SW1. The second basic circuit 22 is configured with a series circuit of a second capacitance circuit CC2 and a switch circuit SW2. The switch circuit SW1 switches the bias applied to the first capacitance circuit CC1. The switch circuit SW2 switches the bias applied to the second capacitance circuit CC2.

[0021] One end of each of the first basic circuit 21 and the second basic circuit 22 is connected to the first node N1, and a second potential VB2 and a third potential VB3 are applied to the other end of each of the first basic circuit 21 and the second basic circuit 22. Here, the third potential VB3 is lower than the second potential VB2.

[0022] One end of the first switch Q1 is connected to one end of each of the first basic circuit 21 and the second basic circuit 22 at the first node N1. A first potential VB1 is applied to the other end of the first switch Q1. In the first basic circuit 21, one end of the first capacitance circuit CC1 is connected to the first node N1, and in the second basic circuit 22, one end of the second capacitance circuit CC2 is connected to the first node N1. Therefore, when the first switch Q1 is in a closed state, the first potential VB1 is applied to each capacitance circuit (each of the first capacitance circuit CC1 and the second capacitance circuit CC2).

[0023] The first potential VB1, the second potential VB2, and the third potential VB3 may be generated within the capacitor array circuit 1 by a voltage regulator or the like, or may be generated outside the capacitor array circuit 1 and supplied to the capacitor array circuit 1. As an example, the second potential VB2 may be the potential of a power supply of a device in which the capacitor array circuit 1 is used, and the third potential VB3 may be the ground potential of the device in which the capacitor array circuit 1 is used.

[0024] The first potential VB1 is a potential between the second potential VB2 and the third potential VB3. Preferably, the first potential VB1 is a midpoint potential between the second potential VB2 and the third potential VB3. If the first potential VB1 is a midpoint potential between the second potential VB2 and the third potential VB3, it may be preferable because it can reduce the influence of unintended leakage or outflow of charge from the first node N1 on the measurement. Therefore, it is preferable that VB1=(VB2+VB3) / 2. In particular, when VB3 is the ground potential (0 V), it is preferable that VB1=(VB2) / 2.

[0025] 1, the first capacitance circuit CC1 is composed of one capacitor C10 (first capacitor), and the second capacitance circuit CC2 is composed of one capacitor C20 (second capacitor). However, in the capacitor array circuit of the embodiment, the capacitance circuits constituting each basic circuit may include any number of capacitors, each having one end connected to the first node N1.

[0026] One end of the second switch Q2 is connected to the first node N1, and the other end is connected to the measurement terminal 3. The second switch Q2 connects or disconnects the first node N1 and the measurement terminal 3. The measurement terminal 3 allows a current based on the charge stored in the first node N1 to flow out of or into the capacitor array circuit 1 when the second switch Q2 is closed.

[0027] The open / closed states of the first switch Q1, the second switch Q2, the first switch circuit SW1, and the second switch circuit SW2 may be operated manually, but are preferably controlled by predetermined control signals that are generated inside the capacitor array circuit 1 or that are generated and supplied externally.

[0028] In the first basic circuit 21, the other end of the first capacitance circuit CC1 is connected to terminal T11 of the switch circuit SW1. Similarly, in the second basic circuit 22, the other end of the second capacitance circuit CC2 is connected to terminal T21 of the switch circuit SW2. In addition to terminal T11, switch circuit SW1 has terminals T12 and T13 that are connected to terminal T11 depending on the state of switch circuit SW1. Similarly, in addition to terminal T21, switch circuit SW2 has terminals T22 and T23 that are connected to terminal T21 depending on the state of switch circuit SW2.

[0029] In the example of FIG. 1, switch circuit SW1 is composed of switches Q3a and Q3b. One end of switch Q3a and one end of switch Q3b are connected to terminal T11, the other end of switch Q3a is connected to terminal T12, and the other end of switch Q3b is connected to terminal T13. Similarly, switch circuit SW2 is composed of switches Q4a and Q4b. One end of switch Q4a and one end of switch Q4b are connected to terminal T21, the other end of switch Q4a is connected to terminal T22, and the other end of switch Q4b is connected to terminal T23. A second potential VB2 is applied to terminal T12 of switch circuit SW1 and terminal T22 of switch circuit SW2, and a third potential VB3 is applied to terminal T13 of switch circuit SW1 and terminal T23 of switch circuit SW2.

[0030] In switch circuit SW1, switches Q3a and Q3b are configured to switch their open / closed states in synchronization so that when one of terminals T12 and T13 is connected to terminal T11, the other is disconnected from terminal T11. Similarly, in switch SW2, switches Q4a and Q4b are configured to switch their open / closed states in synchronization so that when one of terminals T22 and T23 is connected to terminal T21, the other is disconnected from terminal T21.

[0031] Therefore, the switch circuit SW1 constituting the first basic circuit 21 switches between application of the second potential VB2 and application of the third potential VB3 to the other end opposite to the one end connected to the first node N1 in the first capacitance circuit CC1. The switch circuit SW2 constituting the second basic circuit 22 switches between application of the second potential VB2 and application of the third potential VB3 to the other end opposite to the one end connected to the first node N1 in the second capacitance circuit CC2.

[0032] The switch circuit SW1 constituting the first basic circuit 21 preferably applies the third potential VB3 to the first capacitance circuit CC1 when the second potential VB2 is applied to the second capacitance circuit CC2 constituting the second basic circuit 22. Furthermore, the switch circuit SW1 preferably applies the second potential VB2 to the first capacitance circuit CC1 when the third potential VB3 is applied to the second capacitance circuit CC2. In other words, the switch circuit SW2 constituting the second basic circuit 22 preferably applies the third potential VB3 to the second capacitance circuit CC2 when the second potential VB2 is applied to the first capacitance circuit CC1 constituting the first basic circuit 21. Furthermore, the switch circuit SW2 preferably applies the second potential VB2 to the second capacitance circuit CC2 when the third potential VB3 is applied to the first capacitance circuit CC1. When the switch circuit SW1 and the switch circuit SW2 are switched from an open state to a closed state or from a closed state to an open state, the polarity of the voltage applied to both ends of the series circuit SC formed by the first capacitance circuit CC1 and the second capacitance circuit CC2 connected at the first node N1 is reversed.

[0033] In the capacitor array circuit 1, the polarity of the voltage applied to the series circuit SC of the first capacitance circuit CC1 and the second capacitance circuit CC2 is reversed depending on whether the first switch Q1 is in the closed state or the open state, causing a current based on the charge stored in the first node N1 to flow in or out of the measurement terminal 3. Therefore, in the capacitor array circuit 1 of this embodiment, as described below, the first switch Q1, the second switch Q2, and the switch circuits SW1 and SW2 of each basic circuit are controlled to measure the difference in capacitance value between the capacitance circuits constituting each basic circuit. Specifically, the difference in capacitance value between the capacitance circuits constituting each basic circuit can be obtained by measuring the average current (Io) of the current i flowing out of or into the measurement terminal 3 using an ammeter Im placed between the measurement terminal 3 and the first potential VB1.

[0034] <Concept of measuring difference in capacitance value in capacitor array circuit of embodiment> The basic concept of measuring the difference in capacitance values ​​in a capacitor array circuit of an embodiment (hereinafter also simply referred to as "difference measurement of an embodiment") will be described using the capacitor array circuit 1 of Fig. 1 as an example. The difference measurement of an embodiment is based on the idea of ​​storing an amount of charge corresponding to the difference in capacitance values ​​of two capacitors to be measured at the first node N1, causing a current of a magnitude based only on the stored charge to flow in or out, and obtaining the difference in capacitance values ​​of the capacitors to be measured from the average current value.

[0035] That is, first, two capacitors (first capacitance circuit CC1 and second capacitance circuit CC2 in FIG. 1) whose capacitance difference is to be measured, and a first node N1 are placed in a specific bias state, so that a charge corresponding to the difference between the two capacitance values ​​to be measured is stored in the first node N1. Specifically, a first potential VB1 is applied to the first node N1 without an ammeter Im connected. A voltage of a first polarity resulting from the potential difference between the second potential VB2 and the third potential VB3 is applied across a series circuit SC formed by the first capacitance circuit CC1 and the second capacitance circuit CC2 to be measured (hereinafter, this state will also be referred to as the "first state").

[0036] After a charge corresponding to the difference between the two capacitance values ​​to be measured is accumulated at the first node N1 and a steady state is reached, the first node N1 and the first potential VB1 are separated (hereinafter, this state is also referred to as the "second state").

[0037] Next, the polarity of the voltage applied across the series circuit SC formed by the first capacitance circuit CC1 and the second capacitance circuit CC2 is reversed. That is, a voltage resulting from the potential difference between the second potential VB2 and the third potential VB3 is applied with a second polarity opposite to the first polarity (hereinafter, this state is also referred to as the "third state"). By reversing the polarity of the voltage applied to the first capacitance circuit CC1 and the second capacitance circuit CC2 in this manner, a charge proportional to the difference in capacitance value between the capacitors C10 and C20 is stored in the first node N1, and a current having a magnitude based solely on that charge can flow between the first node N1 and the first potential VB1.

[0038] In this state, the first node N1 is connected to the measurement terminal 3 (hereinafter, this state is also referred to as the "fourth state"). One end of the ammeter Im is connected to the first potential VB1, and the other end is connected to the measurement terminal 3, so that a current based solely on the charge stored in the first node N1 and corresponding to the capacitance difference between the capacitors being measured flows through the ammeter Im. By repeating the first to fourth states and reading the average current value Io indicated by the ammeter Im, the difference ΔC in capacitance between the two capacitors being measured can be obtained based on the following equation 1. ΔC=(C2-C1)=2×Io / (f×(VB2-VB3)) (Formula 1)

[0039] In Equation 1, C1 is the capacitance value of the first capacitance circuit CC1 (the capacitance value of capacitor C10 in the example of FIG. 1), C2 is the capacitance value of the second capacitance circuit CC2 (the capacitance value of capacitor C20 in the example of FIG. 1), and f is the frequency at which the first to fourth states are repeated.

[0040] As shown in Equation 1, the difference measurement in this embodiment can obtain the capacitance difference between the devices being measured without subtracting the current measured by the ammeter. This is because a current based solely on the amount of charge stored in the first node N1 in the first state, which corresponds to the capacitance difference between the devices being measured, flows, and the current value is measured directly. Furthermore, after the amount of charge corresponding to the capacitance difference between the devices being measured is stored in the first node N1, the polarity of the voltages applied to the first capacitance circuit CC1 and the second capacitance circuit CC2 is reversed, allowing a current based solely on the amount of charge stored in the first node N1 to flow through the measurement terminal 3. Even if a capacitor other than the device being measured is connected to the first node N1, the current flowing through the measurement terminal 3 is not affected by the capacitor other than the device being measured, as long as the bias state of that capacitor is not changed.

[0041] That is, in the difference measurement of the embodiment, only the amount of charge present in the measurement circuit corresponding to the capacitance difference between the capacitors being measured can be drawn into or discharged from the capacitor array circuit through the measurement terminal 3. In the difference measurement of the embodiment, the current value actually measured is the current value corresponding to the capacitance difference between the capacitors being measured. Therefore, unlike the method described in Non-Patent Document 1, there is no possibility of a difference of several orders of magnitude between the current value to be actually measured and the current value corresponding to the capacitance difference between the capacitors being measured. Therefore, the measurement accuracy of the capacitance difference is unlikely to be limited by the number of significant digits of the measurement system for measuring a current that is, for example, several orders of magnitude larger than the current corresponding to the capacitance difference. Therefore, the capacitance difference between the capacitors being measured can be measured with higher accuracy than before.

[0042] As described above, the capacitor array circuit 1 of the embodiment includes the first switch Q1, the second switch Q2, and the switch circuits SW1 and SW2. Therefore, the first node N1, the first capacitance circuit CC1, and the second capacitance circuit CC2 can be brought into a bias state that changes from the first state to the third state. Furthermore, the fourth state can be brought into the measurement terminal 3, causing a current corresponding to the difference in capacitance between the first capacitance circuit CC1 and the second capacitance circuit CC2 to flow. Therefore, the capacitor array circuit 1 of the embodiment can measure the difference in capacitance between the first capacitance circuit CC1 and the second capacitance circuit CC2, which constitute each basic circuit, with higher accuracy than conventional methods.

[0043] <Description of the internal state of the capacitor array circuit in difference measurement of the embodiment> The difference measurement of the embodiment in the capacitor array circuit 1 of FIG. 1 will be described in more detail, including theoretical verification of the charge stored in the first node N1 and the potential of the first node N1. FIG. 2 shows a timing diagram illustrating the open / closed states of each switch in the capacitor array circuit 1 and the current i flowing through the measurement terminal 3 during the difference measurement of the embodiment. In FIG. 2, a high level shown in the chart of each switch, such as Q1, indicates that the switch is in a closed state (or on state), and a low level indicates that the switch is in an open state (or off state). FIGS. 3A to 3D show the capacitor circuit 1 in the first to fourth states brought about by control of each switch shown in FIG. 2. Furthermore, FIGS. 4A to 4C schematically show the potential of the first node N1 and the state of charge accumulation at the first node N1 in the states shown in FIGS. 3A, 3C, and 3D, respectively. Note that the reference numerals shown in FIG. 1 are omitted in FIGS. 3A to 3D as appropriate.

[0044] During period P1 in FIG. 2, the first switch Q1 is in an on state, the second switch Q2 is in an off state, and the switch Q3a of switch circuit SW1 and the switch Q4b of switch circuit SW2 are in a closed state. Therefore, the switch Q3b of switch circuit SW1 and the switch Q4a of switch circuit SW2 are controlled to be in an open state. That is, the capacitor array circuit 1 is controlled to the first state S1 shown in FIG. 3A. In the first state S1, a first potential VB1 is applied to one end of each of the first capacitance circuit CC1 and the second capacitance circuit CC2 via the first switch Q1 in a closed state. A second potential VB2 is applied to the other end of the first capacitance circuit CC1 via the switch Q3a in a closed state, and a third potential VB3 is applied to the other end of the second capacitance circuit CC2 via the switch Q4b in a closed state. Meanwhile, the measurement terminal 3 and the first node N1 are separated by the second switch Q2 in an open state.

[0045] In the first state S1, as shown in Fig. 4A, a charge q1 is stored between the electrodes of the capacitor C10, and a charge q2 is stored between the electrodes of the capacitor C20. The charges q1 and q2 are expressed as follows: q1=C1×(VB2-VB1) q2=C2×(VB1-VB3) Here, C1 and C2 are the capacitance values ​​of the capacitors C10 and C20, respectively, including errors relative to the design values ​​and parasitic capacitances.

[0046] The charge generated at the first node N1 is expressed as the sum of a charge −q1 and a charge q2, and therefore a charge Δq1 shown in the following equation 2 is stored. Δq1=q2-q1 (Formula 2) As an example, when the first potential VB1 is a midpoint potential between the second potential VB2 and the third potential VB3, Δq1=(C2-C1) / 2×(VB2-VB3) From the above equation, it can be seen that if the capacitance values ​​C1 and C2 are exactly equal, no charge is stored at the first node N1, but if there is a difference between the capacitance values ​​C1 and C2, a charge Δq1 proportional to the difference between the capacitance values ​​C1 and C2 is stored. Here, if the capacitance value C2 is greater than the capacitance value C1, a positive charge is stored at the first node N1, and conversely, if the capacitance value C1 is greater than the capacitance value C2, a negative charge is stored at the first node N1.

[0047] After the charge is stored as described above, during the period P2 shown in FIG. 2, the first switch Q1 is opened, and the capacitor array circuit 1 enters the second state S2 shown in FIG. 3B. As shown in FIG. 3B, in the second state S2, the first switch Q1 is controlled from the first state S1 to the open state, isolating the first capacitance circuit CC1 and the second capacitance circuit CC2, together with the first node N1, from the first potential VB1. That is, application of the first potential VB1 to the first capacitance circuit CC1 and the second capacitance circuit CC2 is stopped. During the next period P3, the first switch Q1 is opened before switching the bias states of the first capacitance circuit CC1 and the second capacitance circuit CC2, thereby performing so-called bottom plate sampling. The bottom plate sampling reduces the impact on measurement accuracy caused by the discharge of charge to the first node N1, which may occur when switching the states of the switches Q3a and Q4b.

[0048] 2, the switch Q3a of the switch circuit SW1 and the switch Q4b of the switch circuit SW2 are controlled to be in the open state, and therefore the switch Q3b of the switch circuit SW1 and the switch Q4a of the switch circuit SW2 are controlled to be in the closed state. That is, the capacitor array circuit 1 is controlled to the third state S3 shown in FIG. 3C. As shown in FIG. 3C, in the third state S3, the third potential VB3 is applied to the other end of the first capacitance circuit CC1 via the closed switch Q3b, and the second potential VB2 is applied to the other end of the second capacitance circuit CC2 via the closed switch Q4a.

[0049] In the third state S3, as shown in Fig. 4B, the first node N1 is in a floating state. Furthermore, a charge q3 is stored in the capacitor C20 of the second capacitance circuit CC2 to which the second potential VB2 is applied, and a charge q4 is stored in the capacitor C10 of the first capacitance circuit CC1 to which the third potential VB3 is applied. The charges q3 and q4 are calculated by using the potential Vo that the first node N1 reaches in the third state S3 as follows: q3=C2×(VB2-Vo) q4=C1×(Vo-VB3) The total amount of charge Δq1 shown in the above formula 2 for the first state S1 does not change because the first node N1 is in a floating state. Therefore, the following formula 3 holds. q4-q3=q2-q1 (Formula 3) Substituting the charges q1 to q4 into the above equation 3 and solving for the potential Vo, we get Vo=(VB2-VB3) / 2+(C2-C1) / (C1+C2)×(VB2-VB3) (Formula 4) Here, for example, when the second potential VB2 is the power supply potential VDD and the third potential VB3 is the ground potential (0V), if the difference between the second potential VB2 and the third potential VB3 is VDD, then the above formula 4 becomes: Vo=VDD / 2+(C2-C1) / (C2+C1)×VDD (Formula 5) This becomes:

[0050] Furthermore, when the difference between the second potential VB2 and the third potential VB3 is VDD and the first potential VB1 is VDD / 2, such that the above equation 5 holds, as shown in equation 5, the potential Vo of the first-node N1 will be different from the first potential VB1 unless the capacitance values ​​C1 and C2 are exactly the same. As can be seen from equation 5 above, when the capacitance value C2 is larger, the potential Vo of the first-node N1 in the third state S3 is higher than the first potential VB1 (=VDD / 2). As described above, when the capacitance value C2 is larger than the capacitance value C1, a positive charge is stored in the first-node N1. Because the potential Vo of the first-node N1 is higher than the first potential VB1, when the first potential VB1 is applied via the ammeter Im in the next fourth state, a current based on the charge stored in the first-node N1 can be caused to flow out of the measurement terminal 3.

[0051] On the other hand, when the capacitance value C1 is greater than the capacitance value C2, as can be seen from Equation 5 above, the potential Vo of the first-node N1 in the third state S3 is higher than the first potential VB1 (=VDD / 2). As described above, when the capacitance value C1 is greater than the capacitance value C2, a negative charge is stored at the first-node N1. Because the potential Vo of the first-node N1 is lower than the first potential VB1, when the first potential VB1 is applied via the ammeter Im in the next fourth state, a current based on the charge stored at the first-node N1 can be caused to flow in from the measurement terminal 3. In this way, in the third state S3, the polarity of the voltage applied to the series circuit of the first capacitance circuit CC1 and the second capacitance circuit CC2 is reversed, causing a current to flow in or out of the first-node N1 depending on the magnitude of the capacitance values ​​C1 and C2.

[0052] When the potential of the first node N1 settles in the third state S3, the second switch Q2 is closed during the period P4 shown in Fig. 2, and the capacitor array circuit 1 enters the fourth state S4 shown in Fig. 3D. As shown in Fig. 3D, in the fourth state S4, the measurement terminal 3 and the first node N1 are connected via the second switch Q2 in the closed state. As described above, a current i based on the amount of charge stored in the first node N1 flows through the measurement terminal 3.

[0053] In the fourth state, as shown in Fig. 4C, the charge accumulation state changes so that a charge q5 is accumulated in the capacitor C20 to which the second potential VB2 is applied, and a charge q6 is accumulated in the capacitor C10 to which the third potential VB3 is applied. The charges q5 and q6 are q5=C2×(VB2-VB1) q6=C1×(VB1-VB3) Therefore, a charge Δq2 shown in the following equation 6 is stored in the first node N1. Δq2=q6-q5 (Formula 6) As an example, when the first potential VB1 is a midpoint potential between the second potential VB2 and the third potential VB3, Δq2=(C1-C2) / 2×(VB2-VB3) This becomes:

[0054] In the fourth state S4, a current i based on the difference in charge between the charge stored in the first state S1 and the charge stored in the fourth state S4 flows out or in from the measurement terminal 3. The amount of change Δq0 in the charge stored in the first node N1 due to the state transition from the first state S1 to the fourth state S4 is calculated from the above equations 2 and 6 as follows: Δq0=Δq1-Δq2=(C2-C1)×(VB2-VB3) (Formula 7) In particular, when the difference between the second potential VB2 and the third potential VB3 is VDD, such as when the second potential VB2 is the power supply potential VDD and the third potential VB3 is the ground potential (0 V), Δq0 is given by Δq0=(C2-C1)×VDD This becomes:

[0055] A current i based on Δq0 shown in Equation 7 flows into the measurement terminal 3. As is clear from Equation 7, Δq0 includes only the component of the capacitance difference between the capacitors under test, in addition to the known second potential VB2 and third potential VB3. Therefore, a current i based solely on the capacitance difference between the capacitors under test flows out of or into the measurement terminal 3 of the capacitor array circuit 1. Because the average value of current i (average current Io) can be measured by the ammeter Im, the difference in capacitance between the two capacitors under test can be measured by repeatedly transitioning from the first state S1 to the fourth state S4 and measuring the average current Io with the ammeter Im. That is, using the measured average current Io, the difference in capacitance ΔC between the two capacitors under test can be obtained with high measurement accuracy using the above-mentioned Equation 1, ΔC = (C1 - C2) = 2 × Io / (f × (VB2 - VB3)).

[0056] The capacitance value for which the difference in capacitance value is measured by the difference measurement of the embodiment is, for example, 10 fF to 100 pF. It is also believed that a difference in capacitance value of about 10 aF to 100 fF can be measured with high accuracy. The voltage due to the potential difference between the second potential VB2 and the third potential VB3 used for measurement is, for example, 0.1 V to 5 V. However, the difference in capacitance value measured by the difference measurement of the embodiment and the magnitude of the voltage used for measurement are not limited to these.

[0057] <Modifications of Capacitance Circuit and Switch Circuit> In the capacitor array circuit 1 of the embodiment, each basic circuit such as the first basic circuit 21 may be configured with a capacitance circuit CC consisting of multiple capacitors C and a switch circuit SW, as in the basic circuit 2 illustrated in FIG. 5A. In the example of FIG. 5A, the capacitance circuit CC is configured with multiple capacitors C connected in parallel. For larger capacitance values, the difference from other capacitance circuits can be measured. One end of each of the multiple capacitors C is connected to each other and collectively connected to a first node N1. The other ends of the capacitors C are also connected to each other and connected to a single switch circuit SW. Using a single switch circuit SW can simplify the control circuit and wiring of the switch SW.

[0058] Furthermore, when the capacitance circuit CC is configured with multiple capacitors C as in the example of Fig. 5A, a switch circuit SW may be provided for each of the multiple capacitors C as shown in Fig. 5B. Each switch circuit SW may be configured with a switch having a small capacitance. In this case, the open / closed state of each switch SW is preferably controlled by the same control signal.

[0059] In each switch circuit such as the switch circuit SW1 in the capacitor array circuit 1 of Fig. 1, for example, either the terminal T12 or the terminal T13 is connected to the terminal T11. Therefore, each switch circuit such as the switch circuit SW1 constituting each basic circuit may be configured with a single switch of the c-contact (transfer contact) type (see Fig. 9) instead of a combination of two switches of the a-contact type or the b-contact type, such as the switch Q3a shown in Fig. 1.

[0060] The first switch Q1, the second switch Q2, and the switches Q3a, Q3b, Q4a, and Q4b constituting each basic circuit may be switches of any structure. These switches may be contact relays such as mechanical relays, or may be manual switches such as toggle switches if applicable. However, as described above, the first switch Q1, the second switch Q2, and the switches Q3a, Q3b, Q4a, and Q4b are repeatedly switched between open and closed states. Therefore, various contact relays whose open and closed states are controlled by signals or metal-oxide-semiconductor (MOS) switches are preferred. Metal-oxide-semiconductor field-effect transistors (MOSFETs), which are compact and capable of high-speed operation, are particularly preferred for the first switch Q1, the second switch Q2, and the switches Q3a, Q3b, Q4a, and Q4b.

[0061] 6 shows a capacitor array circuit 1a, which is a modification of the capacitor array circuit 1 of FIG. 1, in which the first switch Q1, the second switch Q2, and each switch constituting the switch circuit SW1 or SW2 of each basic circuit are configured with an N-channel MOSFET. Like the capacitor array circuit 1a, each switch constituting the capacitor array circuit of the embodiment may be configured with an N-channel MOSFET. Also, like the switches of the capacitor array circuit 1a, the first switch Q1, the second switch Q2, and the switches Q3a, Q3b, Q4a, and Q4b, which are configured with MOSFETs, may each be configured with a P-channel MOSFET.

[0062] The capacitor array circuit 1a of FIG. 6 includes a signal generating circuit 5 that generates signals to control the first switch Q1, the second switch Q2, and the switch circuits SW1 and SW2 of each basic circuit. The first switch Q1, the second switch Q2, the switch circuits SW1, and the switch circuits SW2 are controlled by gate signals G1 to G6 generated by the signal generating circuit 5, causing the capacitor array circuit 1a to repeatedly transition between a first state S1, a second state S2, a third state S3, and a fourth state S4 shown in FIGS. 3A to 3D. The signal generating circuit 5 is not particularly limited, and may be configured by a combination of any logic circuits or a semiconductor integrated circuit device such as a microcomputer. The capacitor array circuit 1 shown in FIG. 1 may also include means for generating signals to control the first switch Q1, the second switch Q2, and the switch circuits SW1 and SW2 of each basic circuit.

[0063] The open / closed states of the first switch Q1, the second switch Q2, and the switches Q3a, Q3b, Q4a, and Q4b, which are all made up of MOSFETs, are controlled by controlling the gate potential of the MOSFETs that make up each of these switches with predetermined gate signals G1 to G6. By controlling the gate potential and varying the drain-source resistance of each MOSFET, the open state (off state) and the closed state (on state) can be switched. Therefore, the open / closed states of the switches can be switched quickly and appropriately synchronized.

[0064] The switch circuits constituting each basic circuit, such as the first switch Q1, the second switch Q2, and the switch circuit SW1 constituting the capacitor array circuit of the embodiment, may be configured by an N-channel MOSFET 4n and a P-channel MOSFET 4p connected in parallel, as in the switch Q0 shown in FIG. 7. In the switch Q0 of FIG. 7, the drain of the N-channel MOSFET 4n is connected to the source of the P-channel MOSFET 4p, and the source of the N-channel MOSFET 4n is connected to the drain of the P-channel MOSFET 4p. The gate of the N-channel MOSFET 4n is connected to the gate of the P-channel MOSFET 4p via an inverting buffer 4i. Therefore, by simply inputting one control signal to the switch Q0, the open / closed states of the two N-channel and P-channel MOSFETs can be controlled.

[0065] <Dummy switch> 6, when the first switch Q1, the second switch Q2, and each switch constituting the switch circuit of each basic circuit are configured with MOSFETs, unintended charges may flow into the first node N1, the capacitance circuit CC1, and / or the capacitance circuit CC2. That is, when the MOSFET constituting each switch switches from the on state to the off state, a phenomenon known as clock feedthrough may cause charges on the gate side of the MOSFET to flow into the drain side and / or source side. Furthermore, when the MOSFET constituting each switch switches from the on state to the off state, a phenomenon known as charge injection may cause charges accumulated in the channel to be released to the drain and / or source.

[0066] Such an unintended flow of charge into the first node N1 or each capacitance circuit fluctuates the amount of charge stored in the first node N1, which is the basis for the current actually measured in the difference measurement of the above-mentioned embodiment, and as a result, may reduce the measurement accuracy. Therefore, in the capacitor array circuit of the embodiment, when the first switch Q1 and the like are configured with MOSFETs, preferably, dummy switches are connected in series to any or all of the MOSFETs configuring each switch.

[0067] 8 shows, as an example of a dummy switch, dummy switches Qd1 and Qd2 connected in series to a first switch Q1. As shown in FIG. 8, the dummy switch Qd1 is connected between one of the source and drain of the first switch Q1 and a first node N1, and the dummy switch Qd2 is connected between the other of the source and drain of the first switch Q1 and a first potential VB1. The dummy switches Qd1 and Qd2 are each formed of an N-channel MOSFET, the same as the MOSFET constituting the first switch Q1. The source and drain of the MOSFET constituting the dummy switch Qd1 are connected to each other, and the source and drain of the MOSFET constituting the dummy switch Qd2 are connected to each other. In FIG. 8, a gate signal G1 is a gate signal for the first switch Q1, and a gate signal Gd1 is a gate signal for each of the dummy switches Qd1 and Qd2.

[0068] The MOSFETs constituting the dummy switches Qd1 and Qd2 are controlled to be turned on when the MOSFET constituting the first switch Q1 is turned off, as indicated by the gate signals G1 and Gd1. Therefore, when the MOSFET constituting the first switch Q1 is turned off, the charge released to the source and / or drain can be drawn into the gate of each dummy switch Qd1 or Qd2 by turning on the MOSFETs constituting the dummy switches Qd1 and Qd2. This reduces fluctuations in the amount of charge at the first node N1 caused by the MOSFET constituting the first switch Q1 being turned off. That is, by connecting a dummy switch also made up of a MOSFET in series with the first switch Q1 made up of a MOSFET, it is possible to suppress a decrease in the accuracy of measuring the difference in capacitance.

[0069] The MOSFETs constituting the dummy switches such as the dummy switches Qd1 and Qd2 are not particularly limited, but preferably have the same structure as the MOSFETs constituting the series-connected switches such as the first switch Q1 (hereinafter also referred to as "target switches"). Furthermore, it is more preferable that the MOSFETs constituting the dummy switches have a channel size approximately half that of the MOSFETs constituting the target switches. This is because it is believed that an amount of charge approximately equal to the charge flowing out from one of the source and drain of the MOSFET constituting the target switch can be drawn into the gate side. Note that the dummy switches do not have to be connected to both the source and drain sides of the MOSFET constituting the target switch as in the example of FIG. 8, but may be connected to only one side.

[0070] Although FIG. 8 shows only the dummy switches Qd1 and Qd2 connected in series with the first switch Q1, one or both of the two dummy switches such as the dummy switches Qd1 and Qd2 may be connected in series with any or all of the switches constituting the capacitor array circuit of the embodiment. For example, the dummy switch provided for the second switch Q2 of the capacitor array circuit 1a of FIG. 6 is connected between the measurement terminal 3 and the second switch Q2 and / or between the first node N1 and the second switch Q2. The dummy switch provided for the switch Q3a of the capacitor array circuit 1a of FIG. 6 is connected to the first capacitance circuit CC1 side and / or the second potential VB2 side of the switch Q3a. The dummy switch provided for the switch Q3b is connected to the first capacitance circuit CC1 side and / or the third potential VB3 side of the switch Q3b. The dummy switch provided for the switch Q4a is connected to the second capacitance circuit CC2 side and / or the second potential VB2 side of the switch Q4a. The dummy switch provided for the switch Q4b is connected to the second capacitance circuit CC2 side and / or the third potential VB3 side of the switch Q4b.

[0071] <First application example> 9 shows a capacitor array circuit 1α, which is a first application example of the capacitor array circuit of the embodiment. The capacitor array circuit 1α includes three basic circuits 21, 22, and 23, each of which is configured as a series circuit of a capacitance circuit formed by a capacitor C and a switch circuit that switches the bias applied to the capacitance circuit. Each of the three basic circuits 21, 22, and 23 is connected to a first node N1. Of the three basic circuits, the first basic circuit 21 is configured by a first capacitance circuit CC1 and a switch circuit SW1, the second basic circuit 22 is configured by a second capacitance circuit CC2 and a switch circuit SW2, and the third basic circuit 23 is configured by a third capacitance circuit CC3 and a switch circuit SW3. In the capacitor array circuit 1α, the first capacitance circuit CC1, the second capacitance circuit CC2, and the third capacitance circuit CC3 are each configured by two capacitors C.

[0072] One end of each capacitor C constituting the first to third capacitance circuits CC1 to CC3 is all connected to the first node N1. The switch circuit SW1 is composed of two switches Q3 shown as contact c switches, and the common terminal of each switch Q3 is connected to the other end of each capacitor C constituting the first capacitance circuit CC1. Similarly, the switch circuit SW2 is composed of two switches Q4, and the common terminal of each switch Q4 is connected to the other end of each capacitor C constituting the second capacitance circuit CC2. The switch circuit SW3 is composed of two switches Q5, and the common terminal of each switch Q5 is connected to the other end of each capacitor C constituting the third capacitance circuit CC3. One of the two terminals other than the common terminal of each of the switches Q3 to Q5 is connected to the second potential VB2, and the other is connected to the third potential VB3. Note that although the switches Q3 to Q5 are shown as contact c switches, they may also be composed of two MOSFETs, like the switch circuit SW1 in FIG. 6. The first switch Q1, the second switch Q2, and the measurement terminal 3 are provided in the same manner as in the capacitor array circuit 1 of FIG.

[0073] Although not shown, the control terminals of the two switches Q3 are shorted, the control terminals of the two switches Q4 are shorted, and the control terminals of the two switches Q5 are shorted, that is, the two switches Q3 change their internal connection states in cooperation with each other, the two switches Q4 change their internal connection states in cooperation with each other, and the two switches Q5 change their internal connection states in cooperation with each other.

[0074] FIG. 10 shows a timing diagram similar to FIG. 2 illustrating the connection states of the switches in the capacitor array circuit 1α and the current i flowing through the measurement terminal 3. In FIG. 10, a high level in the chart for the switches Q3 to Q5 indicates that the other end of the capacitor C connected to each switch is connected to the second potential VB2, and a low level indicates that the other end of the capacitor C connected to each switch is connected to the third potential VB3. As shown in FIG. 10, in the capacitor array circuit 1α, during period P1, when the switch Q3 connects the two capacitors C in the first capacitance circuit CC1 to the second potential VB2, the switch Q4 connects the two capacitors C in the second capacitance circuit CC2 to the third potential VB3. During period P1, the first potential VB1 is applied to the first node N1, similar to the capacitor array circuit 1 in FIG. 1.

[0075] Thereafter, in period P3 after the application of the first potential VB1 to the first node N1 is stopped in period P2, when the switch Q3 connects the two capacitors C of the first capacitance circuit CC1 to the third potential VB3, the switch Q4 connects the two capacitors C of the second capacitance circuit CC2 to the second potential VB2. Then, in this state, the first node N1 is connected to the measurement terminal 3 in period P4.

[0076] 3A to 3D can be brought into the first state S1 to the fourth state S4 shown in Fig. 3A to 3D for the two capacitors C of the first capacitance circuit CC1, the two capacitors C of the second capacitance circuit CC2, and the first node N1. Therefore, the difference between the combined capacitance of the two capacitors C of the first basic circuit 21 of the capacitor array circuit 1α in Fig. 9 and the combined capacitance of the two capacitors C of the second basic circuit 22 can be measured by the principle of difference measurement in the embodiment described above for the capacitor array circuit 1 in Fig. 1.

[0077] In the capacitor array circuit 1α, the third basic circuit 23 is also connected to the first node N1. However, as shown in FIG. 10, the switch Q5 constituting the third basic circuit 3 does not change state over periods P1 to P4. Therefore, the capacitor C constituting the third basic circuit 23 does not affect the current i flowing through the measurement terminal 3 during period P4. Therefore, the difference between the combined capacitance of the two capacitors C in the first basic circuit 21 and the combined capacitance of the two capacitors C in the second basic circuit 22 can be measured using the principle of difference measurement of the embodiment. That is, three or more basic circuits may be connected to the first node N1. Even if three or more basic circuits are connected to the first node N1, the difference in capacitance between one or more capacitors between two arbitrarily selected basic circuits can be accurately measured without being affected by capacitors in basic circuits other than the one being measured. In this way, since the difference in capacitance between two capacitors can be measured even if a capacitor other than the one being measured is connected to the first node N1, the capacitor array circuit of the embodiment can be applied to various electric circuits.

[0078] <Second application example> 11 shows a capacitor array circuit 1β, which is a second application example of the capacitor array circuit of the embodiment. The second application example is an example in which the capacitor array circuit of the embodiment is used in a ladder circuit that determines the weights of input bits of a capacitive DA converter. As an example, FIG. 11 shows an example in which the capacitor array circuit is used in a 3-bit DA converter. Note that the terminals of the first switch Q1 and the second switch Q2 opposite to the first node N1 may be connected to a predetermined node or left open when the capacitive DA converter is in use.

[0079] The capacitor array circuit 1β includes four basic circuits 21, 22, 23, and 24. Each of the four basic circuits 21 to 24 is connected to a first node N1. Of the four basic circuits, the first basic circuit 21 is configured with a first capacitance circuit CC1 and a switch circuit SW1, the second basic circuit 22 is configured with a second capacitance circuit CC2 and a switch circuit SW2, the third basic circuit 23 is configured with a third capacitance circuit CC3 and a switch circuit SW3, and the fourth basic circuit 24 is configured with a fourth capacitance circuit CC4 and a switch circuit SW4.

[0080] In the capacitor array circuit 1β, each capacitance circuit constituting each basic circuit is designed to have the same capacitance value. n (n is an integer equal to or greater than 0) capacitors C. Specifically, in the example shown in FIG. 11, the first capacitance circuit CC1 is configured with 4 (=2 2 ) capacitors C, and the second capacitance circuit CC2 is composed of 2 (=2 1 ) capacitors C, and the third capacitance circuit CC3 and the fourth capacitance circuit CC4 are each composed of 1 (=2 0 ) capacitors C. In a 3-bit DA converter using the capacitor array circuit 1β of FIG. 11, the four capacitors C of the first capacitance circuit CC1 weight the third bit, which is the MSB, of the input digital value, the two capacitors C of the second capacitance circuit CC2 weight the second bit, and the one capacitor C of the third capacitance circuit CC3 weight the first bit, which is the LSB, of the input digital value. The one capacitor C of the fourth capacitance circuit CC4 functions as a dummy capacitance required for DA conversion.

[0081] One end of each capacitor C constituting the first to fourth capacitance circuits CC1 to CC4 is all connected to the first node N1. Each of switch circuits SW1, SW2, SW3, and SW4 is connected to a capacitor C in the basic circuit to which it belongs, and includes the same number of switches as the number of capacitors C in the basic circuit to which it belongs. Switch circuit SW1 is composed of four switches Q3, switch circuit SW2 is composed of two switches Q4, switch circuit SW3 is composed of one switch Q5, and switch circuit SW4 is composed of one switch Q6. The common terminal of each switch is connected to the other end of the capacitor C constituting the basic circuit to which it belongs. Of the two terminals other than the common terminal of each of switches Q3 to Q6, one is connected to the second potential VB2, and the other is connected to the third potential VB3. Note that switches Q3 to Q6 may be composed of two MOSFETs, like switch circuit SW1 in FIG. 6.

[0082] The switches Q3 to Q6 have control terminals Tc that receive control signals for the internal connection states of the switches Q3 to Q6. In each basic circuit, the control terminals Tc of the switches in each basic circuit are connected to each other. n The control terminals Tc of the four switches Q3 are connected to each other so as to switch collectively between application of the second potential VB2 and application of the third potential VB3 to the four capacitors C in the first basic circuit 21. That is, in the first basic circuit 21, the control terminals Tc of the four switches Q3 are short-circuited to each other so as to switch collectively between application of the second potential VB2 and application of the third potential VB3 to the four capacitors C in the first basic circuit 21. In the second basic circuit 22, the control terminals Tc of the two switches Q4 are short-circuited to each other so as to switch collectively between application of the second potential VB2 and application of the third potential VB3 to the two capacitors C in the second basic circuit 22. Therefore, the two switches Q4 constituting each basic circuit are connected to each other so as to switch collectively between application of the second potential VB2 and application of the third potential VB3 to the four capacitors C in the second basic circuit 22. n The capacitors C can be easily connected collectively to the second potential VB or to the third potential VB3.

[0083] In addition, when the switches Q3 to Q6 are configured with two MOSFETs as shown in FIG. 6, the control terminal Tc may be the gate terminal of each MOSFET. n In order to simultaneously switch between application of the second potential VB2 and application of the third potential VB3 to the capacitors C, the gate terminals of the MOSFETs connected to the second potential VB2 are shorted to each other, and the gate terminals of the MOSFETs connected to the third potential VB3 are shorted to each other.

[0084] 12A and 12B are timing diagrams illustrating an example of the connection state of each switch in the capacitor array circuit 1β and the current i flowing through the measurement terminal 3, in a manner similar to that of FIG. 10. In FIGS. 12A and 12B, a four-bit "CODE" indicates the internal connection state of each of the switches Q3 to Q6. The fourth bit, the third bit, the second bit, and the first bit indicate the connection states of the switches Q3, Q4, Q5, and Q6, respectively. A "1" in each bit indicates that the capacitor C connected to the switch corresponding to that bit is connected to the second potential VB2, and a "0" indicates that the capacitor C connected to the switch corresponding to that bit is connected to the third potential VB3.

[0085] 12A, the first potential VB1 is applied to the first node N1 during period P1. In the capacitor array circuit 1β, since only the fourth bit of CODE is "1" during period P1, the switch Q3 connects the four capacitors C of the first capacitance circuit CC1 to the second potential VB2. Meanwhile, the switches Q4 to Q6 connect the four capacitors C connected to the switches Q4 to Q6 to the third potential VB3.

[0086] Then, during period P3 after the application of the first potential VB1 to the first node N1 is stopped during period P2, only the fourth bit of CODE is "0," so switch Q3 connects the four capacitors C of the first capacitance circuit CC1 to the third potential VB3. Meanwhile, switches Q4 to Q6 connect a total of four capacitors C connected to switches Q4 to Q6 to the second potential VB2. Then, in this state, the first node N1 is connected to measurement terminal 3 during period P4.

[0087] That is, the four capacitors C in the first capacitance circuit CC1, the four capacitors C in the second capacitance circuit CC2 to the fourth capacitance circuit CC4, and the first node N1 can be brought into the first state S1 to the fourth state S4 shown in FIGS. 3A to 3D. Therefore, the difference between the combined capacitance of the four capacitors C in the first basic circuit 21 of the capacitor array circuit 1β and the combined capacitance of the four capacitors C in the second basic circuit 22 to the fourth basic circuit 24 can be measured using the principle of difference measurement in the embodiment described for the capacitor array circuit 1 in FIG. 1. The capacitor C in the first basic circuit 21 is responsible for weighting the third bit in a DA converter using the capacitor array circuit 1β, and therefore, the linearity at the time of switching the third bit can be evaluated.

[0088] 12B, when the switches Q3 to Q6 are switched, the capacitor C in the second basic circuit 22 performs weighting, and linearity at the time of switching of the second bit can be evaluated. That is, as shown in FIG. 12B, since only the third bit of CODE is "1" during period P1, the switch Q4 connects the two capacitors C of the second capacitance circuit CC2 to the second potential VB2. Meanwhile, the switches Q5 to Q6 connect a total of two capacitors C connected to the switches Q5 to Q6 to the third potential VB3.

[0089] Thereafter, in a period P3, because only the first and second bits of CODE are "1," the switch Q4 connects the two capacitors C of the second capacitance circuit CC2 to the third potential VB3. Meanwhile, the switches Q5 and Q6 connect a total of two capacitors C connected to the switches Q5 and Q6 to the second potential VB2. Then, in this state, in a period P4, the first node N1 is connected to the measurement terminal 3. Therefore, the difference between the combined capacitance of the two capacitors C of the second basic circuit 22 of the capacitor array circuit 1β and the combined capacitance of a total of two capacitors C of the third basic circuit 23 and the fourth basic circuit 24 can be measured using the principle of difference measurement in the embodiment described for the capacitor array circuit 1 in FIG. 1.

[0090] In the example of Fig. 12B, the fourth bit of CODE is always "0", so the capacitor C in the first basic circuit 21 does not affect the current flowing through the measurement terminal 3 during the period P4, just like the capacitor C in the third basic circuit 23 in Fig. 9. Therefore, the linearity when the second bit switches can be evaluated with high accuracy.

[0091] As described above, when measuring the difference in capacitance values ​​in the capacitor array circuit of the embodiment, even if a capacitor other than the target capacitor is connected to the first node N1, the current to be measured is not affected by the capacitor other than the target capacitor. Therefore, the capacitor array circuit of the embodiment can be used not only for the 3-bit DA converter shown in FIG. 11 but also for DA converters of any number of bits or AD converters of any number of bits incorporating a DA converter. In a DA converter of any number of bits, the difference between the capacitance value of one or more capacitors weighting a specific bit and the combined capacitance value of all capacitors and dummy capacitors weighting bits lower than the specific bit (e.g., capacitor C of the fourth basic circuit 24 in FIG. 11) can be measured. That is, one and the other of two capacitor groups each including the same number of capacitors among the multiple capacitors constituting the ladder circuit of the capacitive DA converter can be regarded as capacitors C10 and C20 of the capacitor array circuit 1 in FIG. 1, respectively. Then, the difference between the combined capacitance value of one of the two capacitor groups and the combined capacitance value of the other can be measured.

[0092] <Method for measuring the difference in capacitance value in the embodiment> The capacitance difference measurement method of the embodiment (hereinafter also simply referred to as the "measurement method of the embodiment") is preferably performed on the capacitor array circuit of the embodiment described above or a capacitor array circuit of an application example thereof. Therefore, the measurement method of the embodiment will be described using the capacitor array circuit 1, 1a, 1α, or 1β as an example, again referring to FIGS. 1 to 12B as appropriate. Note that the measurement method of the embodiment is primarily a method for performing the "difference measurement of the embodiment" described above. Therefore, the measurement method of the embodiment can include each of the processes and operations described with respect to the difference measurement of the embodiment, even if they are not described again below.

[0093] <Method for measuring the difference in capacitance value in the embodiment> The measurement method of the embodiment is a method for measuring the difference between the capacitance values ​​of a first capacitance circuit CC1 and a second capacitance circuit CC2, each of which is composed of one or more capacitors among a plurality of capacitors whose one ends are connected to each other at a first node N1 in a capacitor array circuit 1 shown in FIG. 1. In the capacitor array circuit 1 of FIG. 1, the first capacitance circuit CC1 is composed of one capacitor C10 (first capacitor), and the second capacitance circuit CC2 is composed of one capacitor C20 (second capacitor). In the measurement method of the embodiment, first, as shown in FIG. 3A, with the first node N1 and an ammeter Im connected to the measurement terminal of the capacitor array circuit 1 separated, a first potential VB1 is applied to one end of each of the capacitors C10 and C20, whose capacitance difference is to be measured, via the first node N1. The application of the first potential VB1 to one end of each of the capacitors C10 and C20 is performed by closing a first switch Q1 connected between the first node N1 and the first potential VB.

[0094] Furthermore, with the first node N1 and the ammeter Im separated, and with a first potential VB1 applied to one end of each of the capacitors C10 and C20, a second potential VB2 is applied to the other end of the capacitor C10, and a third potential VB3 lower than the second potential VB2 is applied to the other end of the capacitor C20. Specifically, the second potential VB2 is applied to the other end of the capacitor C10 by closing a switch Q3a disposed between the other end of the capacitor C10 and the second potential VB2. Furthermore, the third potential VB3 is applied to the other end of the capacitor C20 by closing a switch Q4b disposed between the other end of the capacitor C20 and the third potential VB3. A voltage that is the potential difference between the second potential VB2 and the third potential VB3 is applied to a series circuit SC of the capacitor C10 and the second capacitor C20, which are connected via the first node N1. The first state S1 in FIG. 3A is brought to the capacitors C10 and C20, whose capacitance difference is to be measured, and the first node N1. The above process is referred to as the "first step." Note that the first potential VB1 to the third potential VB3 can be generated using any voltage source inside or outside the capacitor array circuit 1.

[0095] After the first step, a second step is performed in which the first switch Q1 is opened to isolate the first node N1 from the first potential VB1, as shown in Fig. 3B, and the capacitor C10, the capacitor C20, and the first node N1 are brought into the second state S2 of Fig. 3B.

[0096] After the second step, a third step is performed in which the polarity of the voltage applied to the series circuit SC, which is made up of the capacitor C10 and the second capacitor C20 connected via the first node N1, is reversed. Specifically, the polarity of the voltage applied to the series circuit SC is reversed by applying a third potential VB3 to the other end of the capacitor C10, to which the second potential VB2 was applied in the first step, and by applying a second potential VB2 to the other end of the capacitor C20, to which the third potential VB3 was applied in the first step. The application of the third potential VB3 to the other end of the capacitor C10 is performed by opening the switch Q3a and closing the switch Q3b, which is disposed between the other end of the capacitor C10 and the third potential VB3. The application of the second potential VB2 to the other end of the capacitor C20 is performed by opening the switch Q4b and closing the switch Q4a, which is disposed between the other end of the capacitor C20 and the second potential VB2. By going through the third step, the capacitor C10, the capacitor C20, and the first node N1 are brought to the third state S3 of FIG. 3C.

[0097] After the third step, a fourth step is performed in which the first node N1 and the ammeter Im are connected via the second switch Q2. Specifically, by closing the second switch Q2, one end of the ammeter Im is connected to the first node N1 via the second switch Q2. The other end of the ammeter Im is connected to the first potential VB1. Therefore, in the fourth step, the first potential VB1 is applied to the first node N1 via the ammeter Im. By performing the fourth step, the capacitor C10, the capacitor C20, and the first node N1 are brought into the fourth state S4 of FIG. 3D. Note that the first switch Q1, the second switch Q2, the switch Q3a, the switch Q3b, the switch Q4a, and the switch Q4b may be operated manually or by generating appropriate control signals using a semiconductor integrated circuit device such as a microcomputer and inputting them to each switch.

[0098] In this way, by performing the first to fourth steps, the capacitors C10 and C20 and the first node N1 can be sequentially brought into states from the first state S1 to the fourth state S4 shown in Figures 3A to 3D. Therefore, by performing the fourth step, as described with reference to Figures 3A to 3D, a current i based on the charge Δq0 expressed by the above equation 7, i.e., Δq0 = Δq1 - Δq2 = (C2 - C1) × (VB2 - VB3), flows to the measurement terminal 3. Note that C1 is the capacitance value of the capacitor C10, and C2 is the capacitance value of the capacitor C20.

[0099] Then, the first to fourth steps are repeated, and a fifth step is performed in which the ammeter Im measures the average current (Io) of the current i flowing through it. The current value measured by the ammeter Im is the average of the charge Δq0 shown in equation 7 above over one cycle (1 / (repetition frequency: f)) of repeating steps 1 to 4, so the difference between the capacitance value of the capacitor C10 being measured and the capacitance value of the capacitor C20 can be obtained from the following equation: ΔC=(C2-C1)=2×Io / (f×(VB2-VB3))

[0100] In the measurement method of the embodiment, as described in the difference measurement of the embodiment, only the amount of charge present in the measurement circuit corresponding to the capacitance difference between the measurement targets can be input to and output from the measurement circuit via the ammeter. In the measurement method of the embodiment, the current value actually measured is the current value corresponding to the capacitance difference between the measurement targets. Therefore, the measurement accuracy of the capacitance difference is unlikely to be limited by the number of significant digits of the measurement system for measuring a current that is, for example, several orders of magnitude larger than the current corresponding to the capacitance difference. Therefore, the capacitance difference between the measurement targets can be measured with higher accuracy than conventional methods.

[0101] <Application example of the measurement method of the embodiment> When the measurement method of the embodiment is performed on the capacitor array circuit 1α illustrated in Fig. 9, the measurement method of the embodiment may further include, before the first step, selecting N (N is a natural number equal to or greater than 1) capacitors C as first capacitors and selecting the same number of capacitors C as N as second capacitors from among a plurality of capacitors C having one end connected to the first node N1. For example, in the capacitor array circuit 1α of Fig. 9, two capacitors C of the first capacitance circuit CC1 are selected as the first capacitors. Then, two capacitors C of the second capacitance circuit CC2 are selected as the second capacitors.

[0102] In this application example, in the first step, the first switch Q1 is closed to apply a first potential VB1 via the first node N1 to one end of all the capacitors C included in the first capacitor and one end of all the capacitors C included in the second capacitor. In the first step, a second potential VB2 is further applied to the other end of all the capacitors C included in the first capacitor, and a third potential VB3 is applied to the other end of all the capacitors C included in the second capacitor.

[0103] In this application example, in the third step, a third potential VB3 is applied to the other end of all of the capacitors C included in the first capacitor, and a second potential VB2 is applied to the other end of all of the capacitors C included in the second capacitor, thereby reversing the polarity of the voltage applied to the series circuit of all of the capacitors C included in the first capacitor and all of the capacitors C included in the second capacitor via the first node N1.

[0104] By performing the first to fourth steps in this manner, the first capacitor consisting of N capacitors C, the second capacitor consisting of N capacitors C, and the first node N1 can be sequentially brought into states from the first state S1 to the fourth state S4 shown in Figures 3A to 3D. Therefore, by repeating the first to fourth steps and performing the fifth step, the difference between the capacitance value of the first capacitor and the capacitance value of the second capacitor to be measured can be obtained.

[0105] Furthermore, the measurement method of the embodiment in this application example may include applying a third potential VB3 to the other ends of all capacitors C other than the capacitors C included in the first capacitor and the capacitors C included in the second capacitor among the multiple capacitors C connected to the first node N1 through the first step through the fourth step. For example, in the capacitor array circuit 1α of FIG. 9 , if the capacitor C of the first capacitance circuit CC1 is selected as the first capacitor and the capacitor C of the second capacitance circuit CC2 is selected as the second capacitor, the third potential VB3 is applied to the other ends of the two capacitors C of the third capacitance circuit CC3 through the first step through the fourth step. In this way, as described for the capacitor array circuit 1α of FIG. 9 , the difference in capacitance between the two capacitors C selected as the first capacitors and the two capacitors C selected as the second capacitors can be measured without being affected by the capacitors C not selected as the first capacitor or the second capacitor.

[0106] In this application example, the second potential VB2 may be applied to the other ends of all capacitors C other than the capacitor C included in the first capacitor and the capacitor C included in the second capacitor from the first step to the fourth step. In this case, the bias state of the capacitors not selected as the first capacitor or the second capacitor does not change from the first step to the fourth step. Therefore, the difference in the capacitance value of the measurement target can be determined without being affected by the capacitors not selected as the first capacitor or the second capacitor.

[0107] <Application of the measurement method of the embodiment to a DA converter> The application example of the measurement method of the above embodiment can also be used for the capacitor array circuit 1β used as a ladder circuit of a capacitive DA converter, which has been described with reference to Fig. 11. In this case, a number of capacitors C that is a power of 2 is selected for each of the first capacitor and the second capacitor in the application example of the measurement method of the embodiment.

[0108] For example, in the capacitor array circuit 1β of FIG. 11, the second capacitance circuit CC2 has a capacitance of 2 (=2 1 ) capacitors C are selected as the first capacitors. The total of the capacitors C of the third capacitance circuit CC3 and the capacitors C of the fourth capacitance circuit CC4 is 2 (=2 1 ) capacitors C are selected as the second capacitors. Specifically, the application of the second potential VB2 and the third potential VB3 to the two capacitors C of the second capacitance circuit CC2 is switched using switch Q4. The application of the second potential VB2 and the third potential VB3 to a total of two capacitors C, the capacitor C of the third capacitance circuit CC3 and the capacitor C of the fourth capacitance circuit CC4, is switched using switches Q5 and Q6.

[0109] Then, either the third potential VB3 or the second potential VB2 is applied to the other ends of the four capacitors C of the unselected first capacitance circuit CC1 via the switch Q3 throughout the first to fourth steps. This reduces the influence of the four capacitors C of the first capacitance circuit CC1, making it possible to evaluate the linearity of the switching of the second bit, weighted by the capacitor C of the second capacitance circuit CC2. The measurement method of the embodiment can be used to evaluate the linearity of the switching of any bit in a D / A converter with any number of bits, in addition to the 3-bit D / A converter illustrated in FIG. 11 .

[0110] <Measures to prevent deterioration of measurement accuracy due to charge release from the switch> As explained above with respect to the capacitor array circuit 1a in Fig. 6, when each switch of the capacitor array circuit of the embodiment is configured with a MOSFET, an unintended charge may flow into the first node N1 due to phenomena called clock feedthrough or charge injection. Furthermore, when the second switch Q2 switches to the on state, it is possible that the charge stored in the stray capacitance on the ammeter Im side may flow into the first node N1. In other words, the charge at the first node N1 may fluctuate due to the MOSFETs constituting each switch switching from the on state to the off state.

[0111] To prevent such a decrease in measurement accuracy due to the release of charge from the MOSFET, the measurement method of the embodiment may further include processing for substantially canceling fluctuations in the amount of charge stored at the first node N1. Specifically, the measurement method of the embodiment may include a current cancellation step that includes measuring a current based only on the amount of charge that fluctuates at the first node N1 due to the MOSFET's transition to the off state, and subtracting the current from the current measured in the fifth step. Referring again to FIG. 1, the current cancellation step will be described below using the capacitor array circuit 1 of FIG. 1 as an example.

[0112] First, in the current canceling step, with the first node N1 and the ammeter Im separated, the first switch Q1 is closed, a second potential VB2 is applied to the other end of the capacitor C10 (first capacitor), and a third potential VB3 is applied to the other end of the capacitor C20 (second capacitor). Alternatively, with the first node N1 and the ammeter Im separated, the first switch Q1 is closed, a third potential VB3 is applied to the other end of the capacitor C10, and a second potential VB2 is applied to the other end of the capacitor C20 (hereinafter, this procedure is also referred to as a "sixth step").

[0113] After the sixth step, a seventh step is performed in which the first switch Q1 is opened. After the seventh step, application of one of the second potential VB2 and the third potential VB3 to the other end of the capacitor C10 and application of the other of the second potential VB2 and the third potential VB3 to the other end of the capacitor C20 continue (hereinafter, this procedure is also referred to as an "eighth step"). That is, in the current cancellation step, unlike the third step described above, the polarity of the voltage applied to the series circuit SC of the capacitors C10 and C20 is not reversed.

[0114] After the eighth step, a ninth step is performed in which the first node N1 and the ammeter Im are connected by the second switch Q2. In the ninth step, a first potential VB1 is applied to the first node N1 via the ammeter Im. Then, by repeating steps six through nine, a second average current (Io2), which is the average current of the current i flowing through the ammeter Im, is measured by the ammeter Im. Here, because the polarity of the voltage applied to the series circuit SC of the capacitors C10 and C20 is not reversed in step eight, a current based on the charge stored in the first node N1 according to the difference between the capacitance values ​​of the capacitors C10 and C20 does not flow through the ammeter Im. That is, by operating the first switch Q1 and the second switch Q2 during steps six through nine, a current based only on the charge released from each switch to the first node N1 can be measured.

[0115] The current canceling step includes subtracting the second average current Io2 from the average current Io measured in step 5. As described above, the second average current Io2 is the average current of the current that flows based solely on the charges released into the first node N1 by the operation of the first switch Q1 and the second switch Q2, and therefore, it is possible to reduce errors caused by the switching of at least one of the first switch Q1 and the second switch Q2.

[0116] That is, the current cancellation step is based on the idea of ​​grasping the magnitude of the current caused by the switching of each switch and canceling the current value by that magnitude by performing the same procedures as steps 1 to 5 without changing the state of application of potential to the two capacitors whose capacitance difference is to be measured. Note that the current cancellation step may be combined with the measurement method of the embodiment of the application example described with reference to Figures 9 and 11. [Explanation of symbols]

[0117] 1, 1a, 1α, 1β capacitor array circuit 2 Basic circuit 21~24 1st~4th basic circuit 3 Measurement terminal 5 Signal generation circuit CC1~CC4 1st~4th capacitor circuit C capacitor C10 capacitor (first capacitor) C20 capacitor (second capacitor) i Current flowing through the measurement terminal Io, Io2 average current Im ammeter N1 First node Q1 First switch Q2 Second switch Q3a, Q3b, Q4a, Q4b, Q3~Q6 switches Qd1, Qd2 dummy switches S1~S4 1st to 4th states SC capacitance circuit in series SW1~SW4 switch circuit Tc switch control terminal VB1~VB3 1st~3rd potential

Claims

1. At least two basic circuits each consisting of a series circuit of a capacitance circuit consisting of at least one capacitor and a switch circuit that switches a bias applied to the capacitance circuit; a first switch connected to one end of each of the at least two basic circuits at a first node, the first switch being in a closed state to apply a first potential to the capacitance circuit; a measurement terminal for causing a current to flow in or out based on the charge stored in the first node; a second switch that connects or disconnects the first node and the measurement terminal; A capacitor array circuit comprising: the switch circuit constituting a first basic circuit which is one of the at least two basic circuits switches between application of a second potential and application of a third potential lower than the second potential to a first capacitance circuit which is the capacitance circuit constituting the first basic circuit; the switch circuit constituting a second basic circuit, which is any one of the at least two basic circuits other than the first basic circuit, switches between application of the second potential and application of the third potential to a second capacitance circuit, which is the capacitance circuit constituting the second basic circuit; A capacitor array circuit in which the polarity of the voltage applied to the series circuit of the first capacitance circuit and the second capacitance circuit via the first node is reversed when the first switch is in a closed state or an open state, thereby causing a current based on the charge stored in the first node to flow out or in from the measurement terminal.

2. 2. The capacitor array circuit according to claim 1, comprising three or more of said basic circuits each connected to said first node.

3. Each of the capacitance circuits constituting each of the three or more basic circuits is designed to have the same capacitance value. n (n is an integer equal to or greater than 0) capacitors, the switch circuit constituting each basic circuit includes switches in the same number as the capacitors individually connected to the capacitors in each basic circuit; The switch has a control terminal for receiving a control signal indicating an internal connection state, In each basic circuit, the control terminals are connected to each other in two n 3. The capacitor array circuit according to claim 2, wherein the capacitors are connected to each other so as to simultaneously switch between application of the second potential and application of the third potential to the capacitors.

4. 2. The capacitor array circuit according to claim 1, wherein the switch circuit, the first switch, and the second switch are each configured by an N-channel MOSFET, a P-channel MOSFET, or an N-channel MOSFET and a P-channel MOSFET connected in parallel.

5. 5. The capacitor array circuit according to claim 4, further comprising a MOSFET connected in series with at least one of the MOSFETs constituting said switch circuit, said first switch, and said second switch, and controlled to be in an on state when said at least one MOSFET is in an off state.

6. a generation circuit for generating signals that control the switch circuit, the first switch, and the second switch so as to repeatedly transition the capacitor array circuit through a first state, a second state, a third state, and a fourth state in order; In the first state, the first potential is applied to one end of each of the first capacitance circuit and the second capacitance circuit, the second potential is applied to the other end of the first capacitance circuit, the third potential is applied to the other end of the second capacitance circuit, and the measurement terminal and the first node are separated from each other; In the second state, the first switch is controlled from the first state to an open state, and application of the first potential to the first capacitance circuit and the second capacitance circuit is stopped; In the third state, the third potential is applied to the other end of the first capacitance circuit, and the second potential is applied to the other end of the second capacitance circuit; 6. The capacitor array circuit according to claim 1, wherein in the fourth state, the measurement terminal and the first node are connected.

7. A method for measuring a difference between a capacitance value of a capacitance circuit made up of one or more first capacitors among a plurality of capacitors connected to each other at one end at a first node, and a capacitance value of a capacitance circuit made up of one or more second capacitors among the plurality of capacitors, comprising: a first step of applying a first potential to the one end of the first capacitor and the one end of the second capacitor via the first node by closing a first switch while separating the first node from an ammeter, applying a second potential to the other end of the first capacitor, and applying a third potential lower than the second potential to the other end of the second capacitor; a second step of isolating the first node from the first potential by opening the first switch after the first step; a third step, after the second step, of applying the third potential to the other end of the first capacitor and applying the second potential to the other end of the second capacitor, thereby reversing the polarity of the voltage applied to the series circuit of the first capacitor and the second capacitor via the first node; a fourth step, after the third step, of connecting the first node and the ammeter with a second switch to apply the first potential to the first node via the ammeter; a fifth step of repeating the first step to the fourth step and measuring an average current flowing through the ammeter with the ammeter; Measurement methods including:

8. Before the first step, selecting N capacitors (N is a natural number equal to or greater than 1) as the first capacitors from the plurality of capacitors and selecting the same number of capacitors as the N as the second capacitors; applying the third potential or the second potential to the other ends of all capacitors other than the first capacitor and the second capacitor among the plurality of capacitors through the first step to the fourth step, in the first step, in a state in which the first node and the ammeter are separated, the first switch is closed to apply the first potential to the one ends of all of the first capacitors and the second capacitors via the first node, apply the second potential to the other ends of all of the first capacitors, and apply the third potential to the other ends of all of the second capacitors; 8. The measurement method according to claim 7, wherein in the third step, the polarity of the voltage applied to the series circuit of the first capacitors and the second capacitors via the first node is reversed by applying the third potential to the other ends of all the first capacitors and applying the second potential to the other ends of all the second capacitors.

9. 9. The method of claim 8, wherein N is a power of two.

10. a sixth step of closing the first switch while separating the first node from the ammeter, applying one of the second potential and the third potential to the other end of the first capacitor, and applying the other of the second potential and the third potential to the other end of the second capacitor; a seventh step of opening the first switch after the sixth step; an eighth step of, after the seventh step, continuing to apply one of the second potential and the third potential to the other end of the first capacitor and continuing to apply the other of the second potential and the third potential to the other end of the second capacitor; a ninth step, after the eighth step, of connecting the first node and the ammeter with a second switch to apply the first potential to the first node via the ammeter; repeating the sixth step to the ninth step to measure a second average current flowing through the ammeter with the ammeter; 10. The measurement method according to claim 7, further comprising: subtracting the second average current from the average current measured in the fifth step, thereby reducing an error caused by switching of at least one of the first switch and the second switch.

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