Rush current prevention circuit

Abstract

To provide a rush current prevention circuit that can appropriately prevent a rush current from flowing into an input capacitor using an N channel FET arranged on the upstream side of a load.SOLUTION: In a load drive circuit in which a load 8 and an input capacitor 7 are connected in parallel between a power supply line Lp and a ground line Lg that are connected to a battery 11. A rush current prevention circuit 601A prevents a rush current from flowing from the battery 11 into the input capacitor 7. A rush current prevention transistor 66 is composed of an N channel FET arranged on the power supply line Lp on the upstream side of the load 8, in which the drain is connected on the battery 11 side, and the source is connected on the load 8 side. A booster circuit (gate voltage supply unit) 30 supplies a gate voltage to the gate of the rush current prevention transistor 66. The booster circuit (gate voltage supply unit) 30 supplies the gate voltage so that the rush current prevention transistor 66 continues to be in a half on-state for a prescribed time or longer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an inrush current prevention circuit. [Background technology]

[0002] Conventionally, inrush current prevention circuits are known that prevent inrush current from flowing into an input capacitor at startup in a circuit that includes a load connected to a DC power supply and an input capacitor connected in parallel with the load.

[0003] For example, the inrush current prevention circuit disclosed in Patent Document 1 includes a field effect transistor (FET), a time constant circuit having a bias resistor and a first capacitor for generating a gate voltage of the FET, and a second capacitor connected in parallel between the drain and gate of the FET. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 4186739 Summary of the Invention [Problem to be solved by the invention]

[0005] In the circuit configuration of Patent Document 1, a P-channel FET is arranged in the power supply line upstream of the load, or an N-channel FET is arranged in the ground line downstream of the load. From the viewpoint of board layout, it is preferable to arrange the N-channel FET for preventing inrush current upstream of the load, but Patent Document 1 does not disclose such arrangement.

[0006] The present invention was created in light of these circumstances, and its purpose is to provide an inrush current prevention circuit that properly prevents inrush current from flowing into the input capacitor by using an N-channel FET placed upstream of the load. [Means for solving the problem]

[0007] The present invention provides an inrush current prevention circuit for preventing inrush current from flowing from a battery (11) to an input capacitor (7) in a load drive circuit in which a load (8) and an input capacitor (7) are connected in parallel between a power supply line (Lp) connected to the battery (11) and a ground line (Lg).

[0008] This inrush current prevention circuit includes an inrush current prevention transistor (66) and a gate voltage supply unit (30, 50). The inrush current prevention transistor is composed of an N-channel FET arranged on the power supply line upstream of the load, with its drain connected to the battery side and its source connected to the load side. The gate voltage supply unit supplies a gate voltage to the gate of the inrush current prevention transistor.

[0009] The gate voltage supply unit supplies a gate voltage so that the inrush current prevention transistor maintains the half-on state for a predetermined time or more, which is set based on the time required for the inrush current of the input capacitor to fall below an allowable value that will not cause damage to the element or malfunction due to noise.

[0010] The gate voltage supply unit of the first aspect is a boost circuit 30 that is provided between the power supply line and the gate of the inrush current prevention transistor and boosts the battery voltage in accordance with instructions from a boost control unit 23. The boost control unit controls the boost speed of the boost circuit so that the inrush current prevention transistor continues to be in a half-on state for a predetermined time or more.

[0011] By supplying the boost voltage from the boost control unit to the gate, the N-channel FET inrush current prevention transistor placed on the power supply line can be fully turned on. However, if the boost speed is fast, the inrush current prevention transistor will turn fully on all at once, causing an inrush current to flow into the input capacitor. Therefore, the boost control unit controls the boost speed to be slowed down, and by gradually flowing the charging current in the half-on state, it is possible to properly prevent inrush current to the input capacitor.

[0012] The gate voltage supply unit of the second aspect is a time constant circuit 50 including a resistor 53 having one end connected to the drain of the inrush current prevention transistor and the other end connected to the gate of the inrush current prevention transistor, and a time constant capacitor 54 connected to the other end of the resistor. The time constant circuit has physical properties of the resistor and the time constant capacitor set so that the inrush current prevention transistor remains in a half-on state for a predetermined time or more from the start of current flow until the steady state is reached.

[0013] To fully turn on an N-channel FET inrush current prevention transistor placed on the power supply line, a voltage higher than the battery voltage must be supplied to the gate using a boost circuit. However, it is possible to half-turn on the inrush current prevention transistor even if the gate voltage is lower than the battery voltage. Therefore, in the second aspect, by using a time constant circuit to maintain the half-turn on state of the inrush current prevention transistor, it is possible to appropriately prevent inrush current from flowing into the input capacitor.

[0014] Alternatively, after the input capacitor is charged in the half-on state, the inrush current prevention transistor may be fully turned on using a boost circuit. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1A is a circuit diagram of an inrush current prevention circuit according to the first embodiment. [Figure 2] 4 is a time chart showing the operation of the inrush current prevention circuit of the first embodiment. [Figure 3] FIG. 1B is a circuit diagram of an inrush current prevention circuit according to the first embodiment. [Figure 4] FIG. 1C is a circuit diagram of an inrush current prevention circuit according to the first embodiment. [Figure 5] FIG. 6 is a circuit diagram of an inrush current prevention circuit according to a second embodiment. [Figure 6] 6 is a time chart showing the operation of the inrush current prevention circuit of the second embodiment. [Figure 7] 6 is a time chart showing the operation of an inrush current prevention circuit of a comparative example. [Figure 8]FIG. 3A is a circuit diagram of an inrush current prevention circuit according to a third embodiment. [Figure 9] 10 is a time chart showing the operation of the inrush current prevention circuit of the third embodiment. [Figure 10] FIG. 3B is a circuit diagram of an inrush current prevention circuit according to a third embodiment. [Figure 11] FIG. 4A is a circuit diagram of an inrush current prevention circuit according to a fourth embodiment. [Figure 12] 10 is a time chart showing the operation of the inrush current prevention circuit of the fourth embodiment. [Figure 13] 1A and 1B are diagrams illustrating changes in the charging current of the input capacitor when the duty ratio of the start-up signal is (a) kept constant and (b) gradually increased. [Figure 14] FIG. 4B is a circuit diagram of an inrush current prevention circuit according to a fourth embodiment. [Figure 15] FIG. 5A is a circuit diagram of an inrush current prevention circuit according to an embodiment. [Figure 16] FIG. 5B is a circuit diagram of an inrush current prevention circuit according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] Several embodiments of the inrush current prevention circuit of the present invention will be described with reference to the drawings. Substantially identical configurations in several embodiments will be assigned the same reference numerals, and descriptions thereof will be omitted. As the following first to fifth embodiments, those having the same basic circuit configuration, purpose, and function will be grouped together as one embodiment. When there are several configuration examples within one embodiment, they will be listed with the letters A and B, such as "Embodiment 1A" and "Embodiment 1B."

[0017] First, referring to FIG. 1 of the 1A embodiment as a representative, the configuration of a load driving circuit to which the inrush current prevention circuit of each embodiment is applied will be described. The reference numerals of the inrush current prevention circuits of each embodiment are designated by the third and fourth digits following "60," indicating the embodiment. For example, the reference numeral of the inrush current prevention circuit of the 1A embodiment shown in FIG. 1 is "601A." However, in the initial description of common matters, the circuit will be collectively referred to as "inrush current prevention circuit 60X."

[0018] In the load drive circuit, a load 8 and an input capacitor 7 are connected in parallel between a power supply line Lp and a ground line Lg connected to a battery 11. The battery 11 is, for example, an in-vehicle battery having a voltage of about 12 V. Hereinafter, the voltage of the battery 11 will be referred to as "battery voltage Vb" (see FIG. 2, etc.). The load 8 is, for example, a three-phase brushless motor or a DC motor used in an electric power steering system (EPS) or an electric brake system, or a three-phase inverter circuit or an H-bridge circuit that is a power converter. The input capacitor 7 is, for example, an aluminum electrolytic capacitor.

[0019] The load drive circuit is configured as an EPS-ECU or brake ECU, and starts and stops upon receiving start and stop signals from a higher-level vehicle control device 10. The ECU is provided with a microcomputer 20 that performs various control calculations. A step-down circuit 14 steps down the battery voltage Vb to, for example, about 5 V and supplies it to the microcomputer 20. The microcomputer 20 issues a load drive signal to a power converter so that, for example, the motor of the load 8 operates at a desired rotation speed and torque.

[0020] In each embodiment, the microcomputer 20 functions as a boost control unit 23 that controls the boost circuit 30, or as an activation signal control unit 24 that outputs an activation signal, which is a pulse signal, to the activation transistor 41. Alternatively, the microcomputer 20 turns on / off a driver 35 provided on the output side of the boost circuit 30. In other embodiments, some of the functions of the microcomputer 20 may be substituted by an ASIC or the like.

[0021] In this load drive circuit, the inrush current prevention circuit 60X of each embodiment mainly prevents inrush current from flowing from the battery 11 to the input capacitor 7 when the ECU is started up. The inrush current prevention circuit 60X includes an inrush current prevention transistor 66 and a "gate voltage supply unit." The inrush current prevention transistor 66 is configured by an N-channel FET (field effect transistor) arranged on the power supply line Lp upstream of the load 8. Typically, a MOSFET is used as the FET.

[0022] The inrush current prevention transistor 66 has its drain connected to the battery 11 side and its source connected to the load 8 side. The N-channel FET is "half-on" when the gate-source voltage Vgs reaches or exceeds the threshold voltage Vth, and is "fully-on" when the gate-source voltage Vgs reaches a sufficiently high value. When the inrush current prevention transistor 66 is in the fully-on state, a relatively large charging current flows from the battery 11 to the input capacitor 7. On the other hand, when the inrush current prevention transistor 66 is in the half-on state, the charging current flowing from the battery 11 to the input capacitor 7 is suppressed.

[0023] The "gate voltage supply unit" supplies a gate voltage Vg to the gate of the inrush current prevention transistor 66. The specific configuration of the "gate voltage supply unit" differs depending on the embodiment. In the first embodiment, the "gate voltage supply unit" is the boost circuit 30. In the second embodiment, the "gate voltage supply unit" is the time constant circuit 50.

[0024] In this embodiment, the gate voltage supply unit supplies the gate voltage Vg so that "the inrush current prevention transistor 66 continues to be in the half-on state for a predetermined time or more." This predetermined time is set based on the time it takes for the inrush current of the input capacitor 7 to become "below an allowable value that does not cause damage to elements or malfunction due to noise." Next, the inrush current prevention circuit 60X of each embodiment will be described in order.

[0025] (First embodiment) A first embodiment will be described with reference to FIGS. 1 to 4. In the first embodiment, the gate voltage supply unit is a boost circuit 30. FIG. 1 shows the configuration of an inrush current prevention circuit 601A according to the most basic first embodiment. In the following description, "inrush current prevention circuit 601A" will be abbreviated as "circuit 601A", for example.

[0026] The boost circuit 30 is provided between the power supply line Lp and the gate of the inrush current prevention transistor 66, and boosts the voltage of the battery 11 in accordance with instructions from a boost control unit 23 configured, for example, within the microcomputer 20. The boost control unit 23 controls the target value of the boost voltage and the boost speed at which the voltage is changed to the target value. The boost control unit 23 controls the boost speed of the boost circuit 30 so that the inrush current prevention transistor 66 continues to be in a half-on state for a predetermined period of time or more.

[0027] 2 shows a timing chart of the first embodiment. When the microcomputer 20 is started up by a start signal from the vehicle control device 10 at time t0, the boost control unit 23 of the microcomputer 20 outputs a boost command to the boost circuit 30. Then, the boost voltage, i.e., the gate voltage Vg, starts to rise at a controlled boost rate. When the gate voltage Vg reaches the threshold voltage Vth at time th, the source voltage Vs rises from 0, and the inrush current prevention transistor 66 enters a half-on state.

[0028] The source voltage Vs rises following the gate voltage Vg and saturates when it reaches the battery voltage Vb. Meanwhile, the gate voltage Vg is boosted beyond the battery voltage Vb, turning the inrush current prevention transistor 66 fully on at time tf. Between time th and time tf, the gate-source voltage Vgs remains constant at the threshold voltage Vth, and the inrush current prevention transistor 66 remains half-on. The boost rate is controlled so that this duration is equal to or longer than a predetermined time Tho. The predetermined time Tho is set based on the time required for the inrush current of the input capacitor 7 to fall below an allowable value that will not cause damage to the elements or malfunction due to noise.

[0029] At time te, when the microcomputer 20 stops in response to a stop signal from the vehicle control device 10, the boost circuit 30 also stops operating, and the gate voltage Vg gradually decreases. The source voltage Vs decreases in tandem with the gate voltage Vg. When the gate-source voltage Vgs falls below the threshold due to the decrease in gate voltage Vg, the inrush current prevention transistor 66 turns off.

[0030] In the first embodiment, the inrush current prevention transistor 66, an N-channel FET arranged on the power supply line Lp, can be fully turned on by supplying a voltage boosted by the boost control unit 23 to the gate. However, if the boost speed is fast, the inrush current prevention transistor 66 will be fully turned on all at once, causing an inrush current to flow into the input capacitor 7. Therefore, the boost control unit 23 controls the boost speed to be reduced, and by allowing the charging current to flow little by little in the half-on state, it is possible to appropriately prevent an inrush current from flowing into the input capacitor 7.

[0031] 3 differs from the circuit 601A of the 1A embodiment in that a gate resistor 33 is connected between the boost circuit 30 and the gate of the inrush current prevention transistor 66, and a capacitor 34 is connected between the gate of the inrush current prevention transistor 66 and the ground line Lg. The RC circuit formed by the gate resistor 33 and the capacitor 34 conforms to the time constant circuit of the second embodiment, which will be described later.

[0032] 4 differs from the circuit 601A of the 1A embodiment in that a driver 35 is provided between the boost circuit 30 and the gate of the inrush current prevention transistor 66. When an on signal is input from the microcomputer 20 to the driver 35, the voltage boosted by the boost circuit 30 is applied to the gate of the inrush current prevention transistor 66 via the driver 35.

[0033] (Second embodiment) A second embodiment will be described with reference to Figures 5 and 6. In the second embodiment, the gate voltage supply unit is a time constant circuit 50. The inrush current prevention circuit 602 supplies a gate voltage to the gate of the inrush current prevention transistor 66 by the time constant circuit 50, and maintains the transistor in a half-on state.

[0034] A circuit 602 of the second embodiment shown in FIG. 5 includes a time constant circuit (i.e., RC circuit) 50 including a resistor 53 and a time constant capacitor 54. One end of the resistor 53 is connected to the drain of the inrush current prevention transistor 66, and the other end is connected to the gate of the inrush current prevention transistor 66. The time constant capacitor 54 is connected between the other end of the resistor 53, i.e., the end connected to the gate of the inrush current prevention transistor 66, and the ground line Lg. To distinguish it from the input capacitor 7, the capacitor 54 of the RC circuit will be referred to as the "time constant capacitor." The connection point between the resistor 53 and the time constant capacitor 54 is referred to as an RC connection point Jrc.

[0035] In the steady state after the transient state following the start of energization, the time constant capacitor 54 is fully charged. In the time constant circuit 50, the physical properties (i.e., resistance and capacitance) of the resistor 53 and the time constant capacitor 54 are set so that the inrush current prevention transistor 66 remains in the half-on state for a predetermined time or more from the start of energization until the steady state is reached.

[0036] The circuit 602 of the second embodiment also includes a startup transistor 41 that is turned on by a startup signal and is located between the drain of the inrush current prevention transistor 66 and one end of the resistor 53, i.e., the end opposite the RC connection point Jrc. The startup signal may be input from the vehicle control device 10 (long dashed arrow) or from the microcomputer 20 (short dashed arrow). The time when the startup transistor 41 is turned on by the input of the startup signal marks the start of current flow to the time constant circuit 50.

[0037] 6 shows a time chart of the second embodiment. At time t0, the start-up transistor 41 is turned on by a start-up signal from the vehicle control device 10 or the microcomputer 20. Then, at time th, when the gate voltage Vg charged in the time constant capacitor 54 reaches the threshold Vth, the inrush current prevention transistor 66 enters a half-on state. Unlike the first embodiment, the inrush current prevention transistor 66 does not transition from the half-on state to a full-on state. The half-on state continues for a predetermined time Tho or more until the start-up signal for the start-up transistor 41 is stopped at time te and the gate voltage Vg drops due to discharge.

[0038] To fully turn on the N-channel FET arranged on the power supply line Lp, a voltage higher than the battery voltage must be supplied to the gate using a boost circuit. However, even if the gate voltage is lower than the battery voltage, it is possible to half-turn on the inrush current prevention transistor 66. Therefore, in the second embodiment, the time constant circuit 50 is used to maintain the half-turn on state of the inrush current prevention transistor 66, thereby appropriately preventing inrush current from flowing into the input capacitor 7.

[0039] Here, as a modification of the second embodiment, an inrush current prevention circuit is assumed that does not include the startup transistor 41, but instead supplies a gate voltage to the inrush current prevention transistor 66 using only the time constant circuit 50. If there are no other switches on the power supply line Lp or ground line Lg of the load drive circuit, in the circuit of this modification, the inrush current prevention transistor 66 is always in a half-on state from the moment the battery 11 is connected.

[0040] This is not a problem in a system in which the load 8 is constantly driven without being stopped, but in a system in which the load 8 is repeatedly started and stopped, dark current always flows from the battery 11 while the load 8 is stopped. For this reason, in the second embodiment, it is preferable to provide a start-up transistor 41 that also serves as a dark current cut-off function.

[0041] (Comparison with comparative examples) Figure 7 shows, as a comparative example, the voltage change characteristics at the start of current flow in the inrush current prevention circuit disclosed in Figure 1 of Patent Document 1 (Japanese Patent No. 4186739), a conventional technology. In the comparative inrush current prevention circuit, an N-channel FET 5 is connected to the ground line downstream of the load. The drain of the FET is connected to the load 3, and the source is connected to the negative terminal of the battery 1. A bias resistor 7 and a first capacitor 6 are connected in parallel between the gate and the ground line. A second capacitor 9 is connected between the drain and gate. This inrush current prevention circuit prevents inrush current from flowing through the input capacitor 4 immediately after the ground line switch 2 is turned on.

[0042] After the switch 2 is turned on at time t0, the gate voltage of the FET 5 rises to a voltage VC determined by the first capacitor 6, the second capacitor 7, and the input capacitor 9, and the FET is turned half-on at time th. Subsequently, the gate voltage of the FET 5 further rises from VC, and the FET 5 is turned fully on at time tf. However, the time from time th to time tf is shorter than the predetermined time Tho in the first and second embodiments.

[0043] As described above, in the comparative example, FET 5 temporarily passes through the half-on state during the gate voltage rise, but this is merely a natural phenomenon. Unlike the first embodiment, the comparative example does not actively control the voltage rise rate to maintain the half-on state of FET 5 for a predetermined time Tho or more. Furthermore, unlike the second embodiment, the comparative example does not fully turn on FET 5 and maintain the half-on state for a predetermined time Tho or more.

[0044] In the comparative example (the prior art of Patent Document 1), it is thought that the N-channel FET is placed on the ground line to fully turn on without using a boost circuit. In contrast, the first and second embodiments of the present invention are fundamentally different from the concept of the comparative example in that the inrush current prevention transistor 66 placed upstream of the load is actively used in a half-on state.

[0045] (Third embodiment) A third embodiment will be described with reference to Figures 8 to 10. In the third embodiment, after the input capacitor is charged in the half-on state according to the second embodiment, the inrush current prevention transistor 66 of the N-channel FET is fully turned on using a boost circuit.

[0046] 8 differs from the circuit 602 (FIG. 5) of the second embodiment in that a boost circuit 30 is provided in parallel with the resistor 53 of the time constant circuit 50. A gate resistor 33 is connected between the boost circuit 30 and the RC connection point Jrc. The boost circuit 30 boosts the voltage of the battery 11 in accordance with instructions from the boost control unit 23 of the microcomputer 20.

[0047] As shown in the time chart of Figure 9, at time t0, a start signal from the vehicle control device 10 turns on the start transistor 41, and simultaneously starts the microcomputer 20. After that, at time th, the inrush current prevention transistor 66 turns on in a half-on state. At this time, the boost circuit 30 is off. When a boost start signal is input from the boost control unit 23 to the boost circuit 30 at time tf, the boost circuit 30 starts operating, and the inrush current prevention transistor 66 transitions from the half-on state to the full-on state.

[0048] The timing at which the boost control unit 23 issues a boost start signal will now be explained in more detail. For example, as indicated by the dashed line, a monitor circuit 27 may be provided to detect the charging voltage of the input capacitor 7, and the boost control unit 23 may determine that charging of the input capacitor 7 is complete based on the value detected by the monitor circuit 27 and output the boost start signal. Note that the monitor circuit 27 is not limited to a configuration that directly detects the inter-electrode voltage of the input capacitor 7, and may instead detect a current and convert it into a voltage. Alternatively, the boost control unit 23 may store characteristics related to the charging time of the input capacitor 7, and output the boost start signal after the time that is estimated to indicate completion of charging has elapsed from time t0.

[0049] At time te, the start-up transistor 41 is turned off in response to a stop signal from the vehicle control device 10. The timing at which each component stops after this varies depending on the circuit configuration. For example, after the boost circuits 30 simultaneously stop at time te, the inrush current prevention transistor 66 is turned off, and finally the microcomputer 20 stops.

[0050] 10, similar to the circuit 603A of the 3A embodiment, a boost circuit 30 is provided in parallel with the resistor 53 of the time constant circuit 50. A driver 35 is also provided between the boost circuit 30 and the RC junction Jrc. When an on signal is input from the boost control unit 23 to the driver 35, the boosted voltage from the boost circuit 30 is applied to the RC junction Jrc via the driver 35. Therefore, the inrush current prevention transistor 66 transitions from a half-on state to a full-on state.

[0051] (Fourth embodiment) A fourth embodiment will be described with reference to Figures 11 to 14. In the fourth embodiment, the start signal of the second embodiment is a pulse signal, and the start transistor 41 is intermittently driven. In a circuit 604A of the fourth embodiment shown in Figure 11, a start signal is input from the start signal control unit 24 of the microcomputer 20 to the start transistor 41 in the circuit 602 (Figure 5) of the second embodiment.

[0052] As shown in the timing chart of Figure 12, the start-up signal is input by the start-up signal control unit 24 as a pulse signal in which on-periods and off-periods are repeated at a predetermined duty ratio. The gate voltage Vg rises during the on-period of the start-up signal, and drops slightly during the off-period due to discharge, resulting in an overall rise. When the gate voltage Vg reaches the threshold voltage Vth at time th, the inrush current prevention transistor 66 enters a half-on state, and a charging current begins to flow to the input capacitor 7.

[0053] For example, the duty ratio is defined as the ratio of the on-period to the sum of the on-period and off-period. The higher the duty ratio, the shorter the half-on time from time t0 when the start signal is input until time th when the inrush current prevention transistor 66 reaches the half-on state. Furthermore, the charging time of the input capacitor 7 after reaching the half-on state also becomes shorter.

[0054] The start-up signal control unit 24 sets the duty ratio high when it is desired to shorten the charging time of the input capacitor 7. On the other hand, the start-up signal control unit 24 sets the duty ratio low when it is desired to lengthen the charging time of the input capacitor 7. In this way, the start-up signal control unit 24 adjusts the charging time of the input capacitor 7 by the duty ratio.

[0055] Next, referring to FIG. 13, we will explain the changes in the charging current flowing into the input capacitor 7 when the inrush current prevention transistor 66 is half-on when the duty ratio of the start signal is (a) constant and (b) gradually increased. When the duty ratio is constant as in (a), the peak value of the charging current is high immediately after reaching the half-on state, and the peak value of the charging current decreases as charging progresses. In contrast, in (b), the start signal control unit 24 changes the duty ratio of the start signal successively from low to high. Immediately after charging begins, the peak value of the charging current decreases because the duty ratio is low, and after charging progresses, the peak value of the charging current increases because the duty ratio is high. Therefore, the charging current (inrush current) flowing into the input capacitor 7 can be averaged.

[0056] 14 differs from the circuit 604A of the 4A embodiment in that it is provided with a monitor circuit 27 that detects the charging voltage of the input capacitor 7. The start-up signal control unit 24 changes the duty ratio of the start-up signal based on the charging voltage of the input capacitor 7 detected by the monitor circuit 27. When it is desired to shorten the charging time of the input capacitor 7, the start-up signal control unit 24 increases the duty ratio as indicated by the dashed line. When it is desired to lengthen the charging time of the input capacitor 7, the start-up signal control unit 24 decreases the duty ratio as indicated by the dashed line.

[0057] (Fifth embodiment) A fifth embodiment will be described with reference to FIGS. 15 and 16. The fifth embodiment serves both as an inrush current prevention circuit and a shutdown circuit for abnormal conditions. For example, when an abnormality such as a short circuit or a disconnection of the load 8 is detected, the shutdown circuit shuts off the power supply to the load 8. A circuit 605A of the fifth embodiment shown in FIG. 15 differs from the circuit 603A of the third embodiment (FIG. 8) in that a shutdown transistor 68 is provided between the RC connection point Jrc and the ground line Lg. The shutdown transistor 68 is configured, for example, by an N-channel FET. When a shutdown signal is input to the gate, the shutdown transistor 68 becomes conductive, preventing the gate voltage from being supplied to the inrush current prevention transistor 66, and the power supply from the battery 11 to the load 8 is shut off.

[0058] 16 differs from the circuit 603B (FIG. 9) of the 3B embodiment in that the circuit 605B of the 5B embodiment is switched to turn off the output of the driver 35 when an abnormality occurs. In this way, in the 5th embodiment, a fail-safe function is realized by configuring the inrush current prevention transistor 66 not to turn on when an abnormality occurs in the load 8 or the like.

[0059] (Other embodiments) (a) As the time constant circuit constituting the inrush current prevention circuits 604A, 604B of the fourth embodiment (FIGS. 11 and 14), an LC circuit including an inductor and a time constant capacitor may be provided instead of the RC circuit including the resistor 53 and the time constant capacitor 54. In the fourth embodiment in which the startup signal is input as a pulse signal, the LC circuit functions as a low-pass filter to remove high-frequency pulses above a predetermined frequency and maintain the inrush current prevention transistor 66 in a half-on state.

[0060] (b) The above-described embodiments may be combined within the scope of compatibility. For example, the third and fourth embodiments may be combined to start the start-up transistor 41 with a pulse start-up signal to set the inrush current prevention transistor 66 to a half-on state, and then transition to a full-on state using the boost circuit 30.

[0061] The present invention is not limited to the above-described embodiment, and can be embodied in various forms without departing from the spirit of the invention. [Explanation of symbols]

[0062] 11. Battery, 23... Boost control section, 30. Boost circuit (gate voltage supply section), 50... Time constant circuit (gate voltage supply section), 53: Resistor; 54: Time constant capacitor; 601A~605B...Circuit (rush current prevention circuit), 66... ​​Inrush current prevention transistor, 7 Input capacitor, 8 Load, Lp···Power line, Lg···Ground line.

Claims

1. In a load drive circuit in which a load (8) and an input capacitor (7) are connected in parallel between a power supply line (Lp) connected to a battery (11) and a ground line (Lg), an inrush current prevention circuit is provided for preventing an inrush current from flowing from the battery to the input capacitor, an inrush current prevention transistor (66) configured by an N-channel FET arranged on the power supply line upstream of the load, the drain of which is connected to the battery side and the source of which is connected to the load side; a gate voltage supply unit (30, 50) that supplies a gate voltage to the gate of the inrush current prevention transistor, The inrush current prevention circuit includes a gate voltage supply unit that supplies a gate voltage so that the inrush current prevention transistor maintains a half-on state for a predetermined period of time or more.

2. the gate voltage supply unit is a boost circuit (30) that is provided between the power supply line and the gate of the inrush current prevention transistor and that boosts the voltage of the battery in accordance with an instruction from a boost control unit (23); 2. The inrush current prevention circuit according to claim 1, wherein the boost control section controls the boosting speed of the boost circuit so that the inrush current prevention transistor continues to be in a half-on state for a predetermined period of time or more.

3. the gate voltage supply unit is a time constant circuit (50) including a resistor (53) having one end connected to the drain of the inrush current prevention transistor and the other end connected to the gate of the inrush current prevention transistor, and a time constant capacitor (54) connected to the other end of the resistor; 2. The inrush current prevention circuit according to claim 1, wherein the time constant circuit has physical property values ​​of the resistor and the time constant capacitor set so that the inrush current prevention transistor remains in a half-on state for a predetermined time or more from the start of current flow until the steady state is reached.

4. 4. The inrush current prevention circuit according to claim 3, further comprising a start-up transistor (41) that is made conductive by a start signal and is provided between the drain of the inrush current prevention transistor and the one end of the resistor.

5. a boost circuit (30) for boosting the voltage of the battery in accordance with an instruction from a boost control unit (23) is provided in parallel with the resistor of the time constant circuit; 5. The inrush current prevention circuit according to claim 4, wherein after the startup transistor is turned on by the startup signal and the inrush current prevention transistor is in a half-on state, the boost control unit drives the boost circuit to bring the inrush current prevention transistor into a full-on state.

6. The start signal is input by a start signal control unit (24) as a pulse signal in which an on period and an off period are repeated at a predetermined duty ratio, 5. The inrush current prevention circuit according to claim 4, wherein the start-up signal control section adjusts the charging time of the input capacitor according to the duty ratio.

7. 7. The inrush current prevention circuit according to claim 6, wherein the duty ratio is defined as the ratio of an on-period to the sum of an on-period and an off-period, and the start-up signal control unit changes the duty ratio in order from a low value to a high value.

8. 7. The inrush current prevention circuit according to claim 6, wherein the start signal control unit changes the duty ratio based on a charging voltage of the input capacitor detected by a monitor circuit (28).

9. 9. The inrush current prevention circuit according to claim 1, wherein the gate voltage supply unit cuts off the supply of gate voltage to the inrush current prevention transistor when an abnormality signal is received.

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