Quantum computer control device, quantum computer control system and quantum computer control method

Abstract

To provide a quantum computer control device capable of improving accuracy of time synchronization to the same extent as accuracy of clock synchronization.SOLUTION: A control device 100 for controlling a quantum bit comprises: a time counter 160 which indicates a time; a clock distributor 130 which inputs a reference clock and distributes a clock which is synchronized to the reference clock to constituents inside and outside of the control device; and a trigger signal distributor 140 which inputs a reference trigger signal and distributes a trigger signal to the constituents inside and outside of the control device on the basis of a time indicated by the time counter to which the time is set on the basis of the reference trigger signal. The reference trigger signal is sampled at the timing of the clock and a time obtained by adding latency of the reference trigger signal to the time indicated by the time counter is set to the time counter at the timing when the reference trigger signal is sampled.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a quantum computer control device, a quantum computer control system, and a quantum computer control method. [Background technology]

[0002] Quantum computers perform calculations by sequentially performing gate operations on individual quantum bits or on multiple linked quantum bits. A quantum computer control device is used to control these gate operations (see, for example, Patent Document 1).

[0003] Patent Document 1 discloses that an analog circuit, an oscillator circuit, and a baseband circuit for performing gate operation are contained within a single control device, and the analog circuit and oscillator circuit for the baseband circuit are integrated, thereby improving the usability, scalability, and robustness of the control device.

[0004] Currently, quantum computers can handle only a few dozen qubits, but this number is expected to increase in the future. As quantum computers become larger in scale, there is a need to combine multiple quantum computer control devices to control a single quantum computer. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2023-067604 Summary of the Invention [Problem to be solved by the invention]

[0006] Quantum computers perform calculations by sequentially performing gate operations on quantum bits, but the number of quantum bits required for a calculation can sometimes exceed the number of quantum bits that can be controlled by a single control device. In such cases, multiple control devices must be combined to form a control system to control a single quantum computer. Therefore, the time required for gate operations must be managed as a whole control system consisting of multiple control devices. For example, since the gate operation time for a superconducting quantum bit is approximately 10 ns to 150 ns, the control devices and control systems must be time-synchronized in units of at least 1 ns.

[0007] However, the most commonly used time synchronization methods have an accuracy of only a few microseconds at best, which is not sufficient for the accuracy required for quantum computing.

[0008] The present invention has been made to solve the above-mentioned problems, and aims to provide a quantum computer control device, a quantum computer control system, and a quantum computer control method that can improve the accuracy of time synchronization to the same level as the accuracy of clock synchronization. [Means for solving the problem]

[0009] To achieve the above object, the quantum computer control system (hereinafter also referred to as the control system) according to the present invention is a control system (2) including first and second control devices (100, 200) for controlling quantum bits, wherein the first control device comprises a first time counter (160) indicating time, a first clock distributor (130) that distributes a first clock to components inside and outside the first control device, and a first trigger signal distributor (140) that distributes a first trigger signal to components inside and outside the first control device based on the time indicated by the first time counter, and the second control device comprises a second time counter (260) that indicates time, and a first clock distributor (130) that is connected to the first clock distributor and distributes a first clock to components inside and outside the first control device. a second clock distributor (230) that distributes a second clock phase-synchronized with the first clock to components in the second control device; and a second trigger signal distributor (240) that is connected to the first trigger signal distributor, receives the first trigger signal distributed by the first trigger signal distributor after a certain latency, and distributes the second trigger signal to the components in the second control device based on the time indicated by the second time counter, wherein the second trigger signal distributor samples the first trigger signal at the timing of the second clock, and sets the time obtained by adding the latency to the time indicated by the first time counter at the timing of sampling the first trigger signal in the second time counter.

[0010] As described above, in the control system of the present invention, the second trigger signal distributor samples the first trigger signal at the timing of the second clock and sets the time indicated by the first time counter plus a latency at the timing of sampling the first trigger signal to the second time counter. By having the second trigger signal distributor sample the first trigger signal at the timing of the second clock, the latency can be quantized to the order of nanoseconds (~ns). Furthermore, by setting the time indicated by the first time counter plus a latency at the timing of sampling the first trigger signal to the second time counter, the error due to the latency can be corrected. This configuration can improve the accuracy of time synchronization to the same level as the accuracy of clock synchronization.

[0011] To achieve the above object, the control system according to the present invention is a control system (2) including first and second control devices (100, 200) for controlling quantum bits, wherein the first control device comprises a first time counter (160) indicating time, a first clock distributor (130) distributing a first clock to components inside and outside the first control device, and a first trigger signal distributor (140) distributing a first trigger signal to components inside and outside the first control device based on the time indicated by the first time counter, and the second control device comprises a second time counter (260) indicating time, and a second clock distributor (130) connected to the first clock distributor and distributing a second clock phase-synchronized with the first clock distributed by the first clock distributor to components inside the second control device. and a second trigger signal distributor (240) connected to the first trigger signal distributor, receiving the first trigger signal distributed by the first trigger signal distributor after a certain latency, and distributing a second trigger signal to components in the second control device based on the time indicated by the second time counter, wherein the first trigger signal distributor transmits the first trigger signal and a first timestamp to the second trigger signal distributor, and the second trigger signal distributor samples the first trigger signal at the timing of the second clock, and sets a second timestamp, which is the first timestamp plus the latency, in the second time counter at the timing of sampling the first trigger signal.

[0012] As described above, in the control system of the present invention, the first trigger signal distributor transmits a first trigger signal and a first timestamp to the second trigger signal distributor, and the second trigger signal distributor samples the first trigger signal at the timing of the second clock and sets a second timestamp, which is the first timestamp plus a latency, in the second time counter at the timing of sampling the first trigger signal. By having the second trigger signal distributor sample the first trigger signal at the timing of the second clock, latency can be quantized to the order of nanoseconds (~ns). Furthermore, by setting a second timestamp, which is the first timestamp plus a latency, in the second time counter at the timing of sampling the first trigger signal, latency errors can be corrected. This configuration can improve the accuracy of time synchronization to the same level as the accuracy of clock synchronization.

[0013] In the control system according to the present invention, the first control device may further include a latency measurement unit (114) that measures the latency required to transmit the trigger signal from the first trigger signal distributor to the second trigger signal distributor.

[0014] This configuration makes it possible to measure the latency required to transmit a trigger signal from the first trigger signal distributor to the second trigger signal distributor.

[0015] In the control system according to the present invention, the components within the first and second control devices may include first and second transceiver units (120, 220) for transmitting and receiving high-frequency radio signals for controlling the quantum bits, each of the first and second transceiver units comprising a baseband circuit (50) for processing a baseband signal and an RF circuit (60) for converting the baseband signal to a high-frequency radio signal, the baseband circuit comprising a digital processing circuit (52) for digitally processing the baseband signal and a digital-to-analog conversion circuit (54) for converting the baseband signal between a digital signal and an analog signal, and the first and second trigger signals may be sent to the digital-to-analog conversion circuit and used as triggers for conversion between a digital signal and an analog signal.

[0016] With this configuration, the first and second trigger signals are sent to the digital-to-analog conversion circuit and used as triggers for conversion between digital and analog signals, thereby improving the time precision of quantum bit gate operations.

[0017] In the control system according to the present invention, the first and second trigger signal distributors and the digital processing circuit may be configured as an FPGA (Field Programmable Gate Array).

[0018] This configuration allows the first and second trigger signal distributors and the like to be flexibly designed and configured.

[0019] In order to achieve the above object, a quantum computer control method (hereinafter also referred to as a control method) according to the present invention is a control method for controlling a quantum bit using first and second control devices (100, 200), and includes a first clock distribution step in the first control device for distributing a first clock to components inside and outside the first control device, and a first trigger signal distribution step in the second control device for distributing a first trigger signal to components inside and outside the first control device based on the time of the first control device, and a second clock in the second control device that is phase-synchronized with the first clock distributed in the first clock distribution step. and a second trigger signal distribution step of receiving the first trigger signal distributed in the first trigger signal distribution step after a certain latency and distributing a second trigger signal to the components in the second control device based on the time of the second control device, wherein the second trigger signal distribution step samples the first trigger signal at the timing of the second clock, and sets the time of the second control device to the time obtained by adding the latency to the time of the first control device at the timing of sampling the first trigger signal.

[0020] As described above, in the control method of the present invention, in the second trigger signal distribution step, the first trigger signal is sampled at the timing of the second clock, and the time of the first control device plus a latency at the timing of sampling the first trigger signal is set as the time of the second control device. By sampling the first trigger signal at the timing of the second clock in the second trigger signal distribution step, the latency can be quantized to the order of nanoseconds (up to ns). Furthermore, by setting the time of the second control device plus a latency at the timing of sampling the first trigger signal, the error due to the latency can be corrected. This configuration makes it possible to improve the accuracy of time synchronization to the same level as the accuracy of clock synchronization.

[0021] In order to achieve the above object, the control method according to the present invention is a control method for controlling quantum bits using first and second control devices (100, 200), and includes, in the first control device, a first clock distribution step of distributing a first clock to components inside and outside the first control device, and a first trigger signal distribution step of distributing a first trigger signal to components inside and outside the first control device based on the time of the first control device, and in the second control device, a second clock distribution step of distributing a second clock phase-synchronized with the first clock distributed in the first clock distribution step to components inside the second control device, and and a second trigger signal distribution step of receiving the first trigger signal distributed by the second clock after a certain latency and distributing the second trigger signal to components within the second control device based on the time of the second control device, wherein the first trigger signal distribution step transmits the first trigger signal and a first timestamp to the second control device, and the second trigger signal distribution step samples the first trigger signal at the timing of the second clock, and sets a second timestamp obtained by adding the latency to the first timestamp at the timing of sampling the first trigger signal as the time of the second control device.

[0022] As described above, the control method of the present invention includes a first trigger signal distribution step of transmitting a first trigger signal and a first timestamp to a second control device, a second trigger signal distribution step of sampling the first trigger signal at the timing of a second clock, and setting the second timestamp, which is the first timestamp plus a latency at the timing of sampling the first trigger signal, as the time of the second control device. By sampling the first trigger signal at the timing of the second clock in the second trigger signal distribution step, the latency can be quantized to the order of nanoseconds (~ns). Furthermore, by setting the second timestamp, which is the first timestamp plus a latency at the timing of sampling the first trigger signal, as the time of the second control device, the error due to the latency can be corrected. This configuration can improve the accuracy of time synchronization to the same level as the accuracy of clock synchronization.

[0023] The quantum computer control device (hereinafter also referred to as the control device) of the present invention is a control device (100) for controlling quantum bits in order to achieve the above-mentioned object, and comprises a time counter (160) that indicates time, a clock distributor (130) that inputs a reference clock and distributes a clock synchronized with the reference clock to components inside and outside the control device, and a trigger signal distributor (140) that inputs a reference trigger signal and distributes a trigger signal to components inside and outside the control device based on the time indicated by the time counter, which is set based on the reference trigger signal, and is characterized in that the trigger signal distributor samples the reference trigger signal at the timing of the clock, and sets the time indicated by the time counter at the timing of sampling the reference trigger signal plus the latency of the reference trigger signal in the time counter.

[0024] As described above, in the control device of the present invention, the clock distributor inputs a reference clock and distributes a clock synchronized with the reference clock to components inside and outside the control device. This allows the clock to be distributed as a reference clock not only to components inside the control device but also to clock distributors of other control devices. Furthermore, the trigger signal distributor inputs a reference trigger signal and distributes a trigger signal to components inside and outside the control device based on the time indicated by a time counter set based on the reference trigger signal. This allows the trigger signal to be distributed as a reference trigger signal not only to components inside the control device but also to trigger signal distributors of other control devices. Furthermore, the trigger signal distributor samples the reference trigger signal at the timing of the clock and sets the time indicated by the time counter at the timing of sampling the reference trigger signal plus the latency of the reference trigger signal in the time counter. By sampling the reference trigger signal at the timing of the clock, the trigger signal distributor can quantize the latency to the order of nanoseconds (~ns). Furthermore, by setting the time indicated by the time counter at the timing of sampling the reference trigger signal plus the latency of the reference trigger signal in the time counter, errors due to latency can be corrected. This configuration makes it possible to improve the accuracy of time synchronization to the same level as the accuracy of clock synchronization not only in a single control device but also in a control system consisting of multiple control devices.

[0025] In order to achieve the above-mentioned object, the control device according to the present invention is a control device (100) for controlling quantum bits, and comprises a time counter (160) that indicates time, a clock distributor (130) that inputs a reference clock and distributes a clock synchronized with the reference clock to components inside and outside the control device, and a trigger signal distributor (140) that inputs a reference trigger signal and a reference timestamp and distributes a trigger signal and a timestamp to components inside and outside the control device based on the time indicated by the time counter, which has been set based on the reference trigger signal and the reference timestamp, and is characterized in that the trigger signal distributor samples the reference trigger signal at the timing of the clock, and sets a timestamp in the time counter at the timing of sampling the reference trigger signal that is the sum of the timestamp and the latency of the reference trigger signal.

[0026] As described above, in the control device of the present invention, the clock distributor inputs a reference clock and distributes a clock synchronized with the reference clock to components inside and outside the control device. This allows the clock to be distributed as a reference clock not only to components inside the control device but also to clock distributors of other control devices. Furthermore, the trigger signal distributor inputs a reference trigger signal and a reference timestamp and distributes trigger signals and timestamps to components inside and outside the control device based on the time indicated by a time counter set based on the reference trigger signal and the reference timestamp. This allows the trigger signal to be distributed as a reference trigger signal not only to components inside the control device but also to trigger signal distributors of other control devices. Furthermore, the trigger signal distributor samples the reference trigger signal at the timing of the clock and sets a timestamp obtained by adding the latency of the reference trigger signal to the reference timestamp in the time counter at the timing of sampling the reference trigger signal. By sampling the reference trigger signal at the timing of the clock, the trigger signal distributor can quantize latency to the order of nanoseconds (~ns). Furthermore, by setting a timestamp obtained by adding the latency of the reference trigger signal to the timestamp in the time counter at the timing of sampling the reference trigger signal, errors due to latency can be corrected. This configuration makes it possible to improve the accuracy of time synchronization to the same level as the accuracy of clock synchronization not only in a single control device but also in a control system consisting of multiple control devices. [Effects of the Invention]

[0027] According to the present invention, it is possible to provide a quantum computer control device, a quantum computer control system, and a quantum computer control method that can improve the accuracy of time synchronization to the same level as the accuracy of clock synchronization. For example, if the clock synchronization accuracy in a control system is about ±5 ps, the time synchronization accuracy can also be about ±5 ps. This satisfies the time synchronization accuracy required for a quantum computer control system. Therefore, it is possible to control a quantum computer even with a large number of quantum bits, which exceeds the number of quantum bits that can be controlled by a single control device. [Brief explanation of the drawings]

[0028] [Figure 1] 1 is a diagram showing the configuration of a quantum computer control device and a quantum computer control system according to a first embodiment of the present invention. [Figure 2] 1 is a diagram illustrating a configuration of a transmitter / receiver unit of a quantum computer control device according to a first embodiment of the present invention. [Figure 3] FIG. 2 is a diagram for explaining clock synchronization in the quantum computer control device or control system according to the first embodiment of the present invention. [Figure 4] FIG. 2 is a diagram for explaining clock synchronization using a tree hierarchical structure in the quantum computer control device or control system according to the first embodiment of the present invention. [Figure 5] FIG. 2 is a diagram for explaining trigger synchronization in the quantum computer control device or control system according to the first embodiment of the present invention. [Figure 6] 1A shows a configuration for realizing time synchronization in a quantum computer control device or control system according to a first embodiment of the present invention, and FIG. 1B is a timing chart. [Figure 7] FIG. 2 is a diagram for explaining time synchronization using a master-slave hierarchical structure in the quantum computer control system according to the first embodiment of the present invention. [Figure 8]FIG. 1 is a diagram for explaining time synchronization using a master-slave method in a quantum computer control device or control system according to a first embodiment of the present invention. [Figure 9] 1 is a diagram showing a detailed configuration of a main part of a quantum computer control device according to a first embodiment of the present invention. [Figure 10] FIG. 1 is a diagram showing a rack configuration of a quantum computer control system according to a first embodiment of the present invention. [Figure 11] FIG. 10 is a diagram for explaining time synchronization using a master-slave method in a quantum computer control device or control system according to a second embodiment of the present invention. [Figure 12] FIG. 10 is a diagram showing a detailed configuration of a main part of a quantum computer control device according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0029] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0030] (First embodiment) Fig. 1 is a diagram showing the configuration of a control system 2 in a quantum computer 1 according to a first embodiment of the present invention. As shown in Fig. 1, the quantum computer 1 includes a quantum bit unit 3 and a control system 2 for controlling the quantum bit unit 3. The control system 2 includes a first control device 100 and a second control device 200.

[0031] The quantum bit section 3 may be configured to include, for example, several tens of superconducting quantum bits, or may be configured to include several thousand quantum bits handled by a medium-sized NISQ (Noisy Intermediate-Scale Quantum Computer), or may be configured to include even more quantum bits.

[0032] The first control device 100 includes a control unit 110 , a transmitting / receiving unit 120 , a clock distributor 130 , a trigger signal distributor 140 , a clock latency storage unit 152 , a trigger latency storage unit 154 , and a time counter 160 .

[0033] The control unit 110 is connected to each component in the first control device 100 and controls the overall operation of each component. The control unit 110 includes a clock latency measurement unit 112 and a trigger latency measurement unit 114.

[0034] The time counter 160 indicates the time of the first control unit 100 .

[0035] The clock distributor 130 distributes the first clock to components inside and outside the first control device 100 .

[0036] The trigger signal distributor 140 distributes the first trigger signal to components inside and outside the first control device 100 based on the time indicated by the time counter 160 or based on a trigger signal received from outside.

[0037] The clock latency measurement unit 112 is configured to measure, for example, the latency required to transmit a clock from the clock distributor 130 to another clock distributor 230. The clock latency storage unit 152 is configured to store information about the latency measured by the clock latency measurement unit 112.

[0038] The trigger latency measurement unit 114 is configured to measure, for example, the latency required for transmitting a trigger signal from the trigger signal distributor 140 to another trigger signal distributor 240. The trigger latency storage unit 154 is configured to store information about the latency measured by the trigger latency measurement unit 114.

[0039] The second control device 200 includes a control unit 210 , a transmitting / receiving unit 220 , a clock distributor 230 , a trigger signal distributor 240 , a clock latency storage unit 252 , a trigger latency storage unit 254 , and a time counter 260 .

[0040] The control unit 210 is connected to each component in the second control device 200 and controls the overall operation of each component. The control unit 210 includes a clock latency measurement unit 212 and a trigger latency measurement unit 214.

[0041] The time counter 260 indicates the time of the second control device 200 .

[0042] The clock distributor 230 is connected to the clock distributor 130 and distributes a second clock that is phase-synchronized with the first clock distributed by the clock distributor 130 to components inside or outside the second control device 200.

[0043] The trigger signal distributor 240 is connected to the trigger signal distributor 140, receives the first trigger signal distributed by the trigger signal distributor 140 after a certain latency, and distributes the second trigger signal to components inside or outside the second control device 200 based on the time indicated by the time counter 260 or based on the first trigger signal.

[0044] The trigger signal distributor 240 samples the first trigger signal at the timing of the second clock, and sets the time indicated by the time counter 260 or a predetermined time plus a latency at the timing of sampling the first trigger signal to the time counter 260.

[0045] The clock latency measurement unit 212 is configured to measure the latency required to transmit a clock from the clock distributor 230 to a clock distributor of another control device. The clock latency storage unit 252 is configured to store information about the latency measured by the clock latency measurement unit 212. The clock latency storage unit 252 may store information about the latency measured by the clock latency measurement unit 112.

[0046] The trigger latency measurement unit 214 is configured to measure, for example, the latency required to transmit a trigger signal from the trigger signal distributor 240 to a trigger signal distributor of another control device. The trigger latency storage unit 254 is configured to store information about the latency measured by the trigger latency measurement unit 214. The trigger latency storage unit 254 may also store information about the latency measured by the trigger latency measurement unit 114.

[0047] 2 is a diagram showing the configuration of the transceiver units 120 and 220. As shown in FIG. 2, the transceiver units 120 and 220 are each configured to transmit and receive high-frequency radio signals for controlling the quantum bit unit 3, and include a baseband circuit 50 that processes baseband signals and an RF circuit 60 that converts between the baseband signals and high-frequency radio signals. The baseband circuit 50 includes a digital processing circuit 52 that digitally processes the baseband signals, and a digital-to-analog conversion circuit (DAC / ADC circuit) 54 that converts the baseband signals between digital and analog signals. First and second trigger signals are sent to the DAC / ADC circuit 54 and are used as triggers for conversion between digital and analog signals.

[0048] During transmission, the digital processing circuit 52 performs digital processing such as framing of parallel data, data scrambling, encoding, and parallel-to-serial conversion. During transmission, the DAC / ADC circuit 54 performs serial-to-parallel conversion on the serial signal received from the digital processing circuit 52, and outputs the result after decoding, descrambling, data generation, and filtering. During reception, the same processing is performed in reverse order to that during transmission.

[0049] The RF circuit 60 includes an upconverter / downconverter 62 that includes a local oscillator, a mixer, and the like. During transmission, a local oscillation signal generated by the local oscillator and an analog signal output from the DAC / ADC circuit 54 are mixed in the mixer and upconverted. The RF signal obtained by the upconversion is provided to the quantum bit unit 3, where a gate operation is performed. During reception, the reverse operation to that performed during transmission is performed. The RF signal sent from the quantum bit unit 3 is downconverted by the RF circuit 60 and sent to the baseband circuit 50. In the baseband circuit 50, the DAC / ADC circuit 54 converts the signal into a digital signal, which is then sent to the control units 110 and 210 via the digital processing circuit 52.

[0050] The trigger signal distributors 140, 240 and the digital processing circuit 52 may be configured using FPGA.

[0051] (clock synchronization) Next, clock synchronization will be described.

[0052] 3 is a diagram for explaining clock synchronization in the control devices 100, 200 or the control system 2 of the quantum computer 1 according to the first embodiment. In the example shown in FIG. 3, the clock distributor 510 is connected to DAC / ADC circuits 520, 521, and 522. Under the control of the clock latency measurement unit 112, the clock distributor 510 calculates the amount of delay and corrects the amount of delay as follows.

[0053] (1) The external SYSREF signal is distributed from the clock distributor 510 to the DAC / ADC circuits 520, 521, and 522. (2) In the DAC / ADC circuits 520, 521, and 522, the internal SYSREF signal is synchronized with the external SYSREF signal. (3) Sending an internal SYSREF signal from the DAC / ADC circuits 520, 521, 522 to the clock distributor 510. (4) Measure the round trip delay in the clock distributor 510. (5) The clock distributor 510 transmits round trip delay information to the DAC / ADC circuits 520, 521, and 522. (6) In the DAC / ADC circuits 520, 521, and 522, the internal SYSREF signal is delayed by the round trip delay.

[0054] Information about the measured round trip delay and information about the delay amount (or latency) obtained from that information may be stored in the clock latency storage unit 152.

[0055] The clock synchronization described above is all performed automatically. With this configuration, the internal SYSREF signals of the DAC / ADC circuits 520, 521, and 522 can be synchronized with the external SYSREF signal with an accuracy of ±5 ps. Even if another clock distributor is interposed between the clock distributor 510 and the DAC / ADC circuits 520, 521, and 522, the delay amount can be corrected in the same way.

[0056] Next, the configuration of a clock distributor that can accommodate a larger number of DAC / ADC circuits will be described.

[0057] Figure 4 is a diagram for explaining clock synchronization using a tree-like hierarchical structure of clock distributors. A multi-qubit quantum computer requires a large number of DAC / ADC circuits in the control system 2. To distribute clocks to a large number of DAC / ADC circuits, clock distributors are connected in a tree structure, as shown in Figure 4.

[0058] 4, clock distributors 510, 511, and 512 distribute clocks synchronized with the clock distributed from clock distributor 500 to DAC / ADC circuits 520, 521, 522, 530, 540, etc. If the number of tree levels is n, the clock synchronization accuracy is ±√n×5 ps. For example, in NISQ (up to 1000 quantum bits), clock distributors are configured in 4 to 5 stages, and the clock synchronization accuracy in this case is ±10 to 5√5 ps.

[0059] (Time synchronization) Next, time synchronization will be described.

[0060] FIG. 5 is a diagram illustrating time synchronization in the control device 100, 200 or the control system 2 of the quantum computer 1 according to the first embodiment. In the example shown in FIG. 5, a master trigger signal distributor (hereinafter also referred to as the master) 600 is connected to slave trigger signal distributors (hereinafter also referred to as the slaves) 610, 615, and 616, and a trigger signal is distributed from the master trigger signal distributor 600 to the slave trigger signal distributors 610, 615, and 616. The slave trigger signal distributors 610, 615, and 616 sample the trigger signal at the timing of the clock in the control device 100 or 200. As described above, the clocks in all the control devices are synchronized with an accuracy of, for example, ±10 ps. Therefore, by sampling the trigger signal at the timing of the clock, the delay amount of the trigger signal can be quantized.

[0061] Under the control of the trigger latency measurement unit 114, the trigger signal distributor 600 calculates the delay amount and corrects the delay amount as follows.

[0062] (1) A trigger signal is distributed from the master trigger signal distributor 600 to the slave trigger signal distributors 610, 615, and 616. (2) A response signal is transmitted from the slave trigger signal distributors 610, 615, and 616 to the master trigger signal distributor 600. (3) Measure the round trip delay in the master trigger signal distributor 600. (4) The master trigger signal distributor 600 transmits round trip delay information to the slave trigger signal distributors 610, 615, and 616. (5) The slave trigger signal distributors 610, 615, and 616 calculate and store the latency (amount of delay) of the trigger signal from the round trip delay information. (6) The slave trigger signal distributors 610, 615, and 616 adjust the trigger signal from the master trigger signal distributor 600 by the amount of latency to perform time synchronization.

[0063] Information about the measured round trip delay and information about the delay amount (or latency) obtained from that information may be stored in the trigger latency storage units 154 and 254.

[0064] 6(a) shows a configuration for achieving time synchronization in the control device 100, 200 or control system 2 of the quantum computer 1 according to the first embodiment, and FIG. 6(b) is a timing chart. As shown in FIGS. 6(a) and 6(b), the trigger signal distributor 140 receives a reference trigger signal (signal b) and a clock (signal a) from the clock distributor 130, and transmits a trigger signal (signal c) to the trigger signal distributor 240 at clock timing (t1). The trigger signal distributor 240 samples the trigger signal (signal d) from the trigger signal distributor 140 at the timing of the clock (signal a') from the clock distributor 230, and sets the time indicated by the time counter 160 or a predetermined time plus the latency D of the trigger signal at timing (t2) when the trigger signal (signal d) is sampled in the time counter 260. In addition, the trigger signal distributor 240 either corrects the trigger signal (signal d) by the latency at the timing of sampling the trigger signal and outputs the trigger signal (signal e), or outputs the trigger signal based on the time indicated by the time counter 260.

[0065] In this way, by sampling the trigger signal from the master using a clock signal that is synchronized or phase-synchronized with high precision within all control devices, the delay amount of the trigger signal is quantized, the quantized delay amount (latency) is measured in advance, and the latency of the trigger signal sampled using the clock signal is adjusted. This makes it possible to achieve time synchronization with the same high level of precision as clock synchronization.

[0066] <Single> Next, the configuration of the master trigger signal distributor 141 and the slave trigger signal distributors 142, 143, and 144 in one control device 100 will be described.

[0067] FIG. 7 is a diagram illustrating time synchronization using a master-slave system in the quantum computer control device 100 according to the first embodiment. As shown in FIG. 7, three slave trigger signal distributors 142, 143, and 144 are connected to one master trigger signal distributor 141. In the example of FIG. 7, the master trigger signal distributor 141 and the slave trigger signal distributor 142 are arranged on one board 102, and two slave trigger signal distributors 143 and 144 are arranged on another board 103. The synctrig signal is distributed from the master trigger signal distributor 141 to the three slave trigger signal distributors 142, 143, and 144. In the case of a control system consisting of multiple control devices, the synctrig signal is also distributed to the master trigger signal distributors of the other control devices.

[0068] The specific steps are as follows: (1) One of the four trigger signal distributors is designated as the master in advance, and the other three are designated as slaves. (2) A command is issued from the integrated control computer PC to start master synchronization. (3) Upon receiving the command, the master starts synchronization by changing the synctrig signal from L to H (or H to L). (4) When the synctrig signal changes from L to H, the slave sets its own timestamp to a predetermined value. (5) At the same time, the master sets its own timestamp to a predetermined value.

[0069] This procedure ensures that the master and slave have the same timestamp when viewed in absolute time.

[0070] <Multiple units> Next, time synchronization among a plurality of control devices will be described.

[0071] 8 is a diagram illustrating time synchronization using a master-slave hierarchical structure in the control system 2 of the quantum computer 1 according to the first embodiment. In the example of FIG. 8, five masters 610...614 and three slaves 615, 616, and 617 are connected to one master trigger signal distributor 600, and five masters and three slaves are also connected to each connected master, forming a hierarchical structure. For example, masters 620...624 and slaves 625, 626, and 627 are connected to master 610, and masters 630...634 and slaves 635... are connected to master 614. A synctrig signal is transmitted and received between the trigger signal distributors.

[0072] <Unit> Next, a specific example of the configuration of one control device 100 will be described.

[0073] 9 is a diagram showing a detailed configuration of the main parts of the control device 100 of the quantum computer 1 according to the first embodiment. As shown in Fig. 9, the control device 100 includes, in a unit (housing) 101, two boards 102 and 103, an input terminal 104, and input / output terminals 105, 106, 107, 108, and 109.

[0074] The first board 102 includes a clock distributor 131, a clock generator 180, a multiplexer 182, two trigger signal distributors 141 and 142, and four DAC / ADC circuits 171, 172, 173, and 174. The clock distributor 131 is connected to the clock generator 180 and the input terminal 104 via the multiplexer 182. The clock distributor 131 is also connected to the trigger signal distributors 141 and 142 and the DAC / ADC circuits 171, 172, 173, and 174. The clock distributor 131 is also connected to the clock distributor 132 of the second board 103 and the input / output terminals 105, 106, 107, 108, and 109.

[0075] The trigger signal distributor 141 is connected to the input terminal 104, trigger signal distributors 142, 143, and 144, and input / output terminals 105, 106, 107, 108, and 109. The trigger signal distributor 141 is also connected to DAC / ADC circuits 171 and 172. The trigger signal distributor 142 is connected to DAC / ADC circuits 173 and 174.

[0076] The second board 103 includes a clock distributor 132, two trigger signal distributors 143 and 144, and DAC / ADC circuits 175, 176, 177, and 178. The clock distributor 132 is connected to the clock distributor 131. The clock distributor 132 is also connected to the trigger signal distributors 143 and 144 and the DAC / ADC circuits 175, 176, 177, and 178. The clock distributor 132 is also connected to input / output terminals 107, 108, and 109.

[0077] The trigger signal distributor 143 is connected to the clock distributor 132, the trigger signal distributor 141, and the DAC / ADC circuits 175 and 176. The trigger signal distributor 144 is connected to the clock distributor 132, the trigger signal distributor 141, and the DAC / ADC circuits 177 and 178.

[0078] A clock generated by clock generator 180 or a clock input from the outside via input terminal 104 is sent to clock distributor 131 via multiplexer 182. The clock is, for example, 160 MHz. Clock distributor 131 then transmits the clock to trigger signal distributors 141 and 142 and DAC / ADC circuits 171, 172, 173, and 174. Clock distributor 131 also distributes the clock to clock distributor 132 on second board 103, and transmits the clock to the outside via input / output terminals 105 and 106.

[0079] Trigger signal distributor 141 receives a clock from clock distributor 131, receives a trigger signal from input terminal 104, and transmits the trigger signal to trigger signal distributors 142, 143, and 144. Trigger signal distributor 141 also transmits a trigger signal to the outside from input / output terminals 105, 106, 107, 108, and 109, and transmits a TRIG signal to DAC / ADC circuits 171 and 172. Trigger signal distributor 142 receives a clock from clock distributor 131, receives a trigger signal from trigger signal distributor 141, and transmits a TRIG signal to DAC / ADC circuits 173 and 174.

[0080] The trigger signal distributor 143 receives the clock from the clock distributor 132 and the trigger signal from the trigger signal distributor 141, and transmits the TRIG signal to the DAC / ADC circuits 175 and 176. The trigger signal distributor 144 receives the clock from the clock distributor 132 and the trigger signal from the trigger signal distributor 141, and transmits the TRIG signal to the DAC / ADC circuits 177 and 178.

[0081] Here, the trigger signal is a signal that signals the start of synchronization, and is a synctrig signal that is input to trigger signal distributors 141, 142, 143, and 144. The trigger signal also drives a TRIG signal that sets the internal counters of DAC / ADC circuits 171, 172, 173, 174, 175, 176, 177, and 178 to 0.

[0082] <rack> Next, the tree structure of the unit (chassis) will be explained.

[0083] Fig. 10 is a diagram showing the rack configuration of the control system 2 according to the first embodiment. In the example shown in Fig. 10, the control system 2 has five racks 300, 310, 320, 330, and 340. The rack 300 houses units 301 to 309, the rack 310 houses units 311 to 319, the rack 320 houses units 321 to 329, the rack 330 houses units 331 to 339, and the rack 340 houses units 341 to 349. Each unit has one input terminal 104 and five input / output terminals 105 to 109, allowing the units to be connected to each other. A synctrig signal and a BSYNC signal are transmitted between the units (see Fig. 9).

[0084] In the first level of the tree structure, unit 325 of rack 320 is connected to four slave units 315, 323, 327, and 335. In the second level of the tree structure, unit 315 is connected to five units 305, 313, 314, 316, and 317; unit 335 is connected to four units 333, 334, 336, and 337; unit 323 is connected to three units 321, 322, and 324; and unit 327 is connected to three units 326, 328, and 329.

[0085] In the third level of the tree structure, unit 313 is connected to two units 303 and 311, unit 314 is connected to two units 304 and 312, unit 316 is connected to two units 306 and 318, unit 317 is connected to two units 307 and 319, unit 333 is connected to two units 331 and 343, unit 334 is connected to two units 332 and 344, unit 336 is connected to one unit 338, and unit 337 is connected to one unit 339.

[0086] At the fourth level of the tree structure, unit 311 is connected to one unit 301, unit 312 is connected to one unit 302, unit 318 is connected to one unit 308, unit 319 is connected to one unit 309, unit 331 is connected to one unit 341, and unit 332 is connected to one unit 342.

[0087] As described above, in the example shown in FIG. 10, the units have a four-stage tree structure, the synchronization accuracy of the master is ±10 ps, ​​and the synchronization accuracy of all clock distributors is ±5√5 ps.

[0088] As described above, in the control system 2 of the first embodiment, the trigger signal distributor 240 samples the trigger signal at the timing of the clock, and sets the time indicated by the time counter 160 or a predetermined time plus a latency as a new timestamp in the time counter 260 at the timing of sampling the trigger signal. By having the trigger signal distributor 240 sample the trigger signal at the timing of the clock, it is possible to quantize the latency to the order of nanoseconds (~ns). Furthermore, by setting the time indicated by the time counter 160 plus a latency at the timing of sampling the trigger signal in the time counter 260, it is possible to correct errors due to the latency. This configuration makes it possible to improve the accuracy of time synchronization to the same level as the accuracy of phase-synchronized clocks.

[0089] (Second embodiment) Next, a control device 100 and a control system 2 for a quantum computer 1 according to a second embodiment of the present invention will be described with reference to the drawings.

[0090] The control device 100 and control system 2 of the quantum computer 1 according to the second embodiment differ from the first embodiment, which is configured to transmit only trigger signals, in that timestamp information is transmitted from the master trigger signal distributor to the slave trigger signal distributor. The other configurations are the same as those of the first embodiment, and the same components are assigned the same reference numerals and detailed descriptions are omitted as appropriate.

[0091] The following describes the configuration of master trigger signal distributor 141 and slave trigger signal distributors 142, 143, and 144 in control device 100. In this specification, the master trigger signal distributor is also simply referred to as the master, and the slave trigger signal distributor is also simply referred to as the slave.

[0092] FIG. 11 is a diagram illustrating time synchronization using a master-slave system in the control device 100 of the quantum computer 1 according to the second embodiment. As shown in FIG. 11, three slave trigger signal distributors 142, 143, and 144 are connected to one master trigger signal distributor 141. In the example of FIG. 11, the master trigger signal distributor 141 and the slave trigger signal distributor 142 are arranged on one board 102, and two slave trigger signal distributors 143 and 144 are arranged on another board 103. Time stamp information is transmitted from the master trigger signal distributor 141 to the three slave trigger signal distributors 142, 143, and 144 via SPI (or Ethernet) along with the synctrig signal. In the case of a control system consisting of multiple control devices, the synctrig signal and time stamp information are also transmitted to the master trigger signal distributors of the other control devices.

[0093] The specific steps are as follows: (1) One of the four trigger signal distributors is designated as the master in advance, and the other three are designated as slaves. (2) A command is issued from the integrated control computer PC to start master synchronization. (3) Upon receiving the command, the master starts synchronization by changing the synctrig signal from L to H (or H to L). (4) The master notifies the slave via SPI of the timestamp when the master changes from L to H (or H to L). (5) The slave changes its own timestamp to a timestamp that takes into account the latency. In the case of a single unit, since it is in the same housing, there is almost no latency.

[0094] This procedure ensures that the master and slave have the same timestamp when viewed in absolute time.

[0095] Next, a specific example of the configuration of one control device 100 will be described.

[0096] Fig. 12 is a diagram showing a detailed configuration of the main parts of the control device 100 of the quantum computer 1 according to the second embodiment. In Fig. 12, a trigger signal distributor 141 receives a trigger signal from an input terminal 104 and transmits timestamp information together with the trigger signal via the SPI to trigger signal distributors 142, 143, and 144. In addition, the trigger signal distributor 141 transmits the timestamp information together with the trigger signal to the outside from input / output terminals 105 to 109.

[0097] The following describes time synchronization in a control system 2 consisting of multiple control devices. The basic configuration of the control system 2 is the same as that of the first embodiment shown in Fig. 1, the hierarchical structure of the master trigger signal distributor and the slave trigger signal distributor is the same as that of the first embodiment shown in Fig. 8, and the tree structure of the units (housings) is also the same as that of the first embodiment shown in Fig. 10.

[0098] As described above, in the control system 2 according to the second embodiment, the trigger signal distributor 140 of the control device 100 transmits a trigger signal and a timestamp to the trigger signal distributor 240 of another control device 200. The trigger signal distributor 240 samples the trigger signal at the clock timing and adds a latency to the timestamp at the timing of sampling the trigger signal, setting the new timestamp in the time counter. By having the trigger signal distributor 240 sample the trigger signal at the clock timing, the latency can be quantized to the order of nanoseconds (~ns). Furthermore, by setting the timestamp obtained by adding the latency to the timestamp at the timing of sampling the trigger signal in the time counter, the error due to the latency can be corrected. This configuration improves the accuracy of time synchronization to the same level as that of phase-synchronized clocks. [Industrial Applicability]

[0099] As described above, the present invention has the effect of being able to improve the accuracy of time synchronization to the same degree as the accuracy of clock synchronization, and is useful in quantum computer control devices, control systems, and control methods in general. [Explanation of symbols]

[0100] 1. Quantum computers 2. Control System 3 Quantum Bits 50 Baseband Circuit 52 Digital Processing Circuit 54 DAC / ADC circuit 60 RF circuits 62 Upconverter / Downconverter 100, 200 control device 101 units 102, 103 boards 104 Input terminal 105, 106, 107, 108, 109 input / output terminals 110, 210 control unit 112, 212 Clock latency measurement unit 114, 214 Trigger latency measurement section 120, 220 Transmitter / Receiver 130, 131, 132, 230, 500, 510, 511, 512 Clock distributor 140, 141, 142, 143, 144, 240, 600, 610, 615, 616 Trigger signal distributor 152, 252 clock latency storage 154, 254 Trigger latency memory 160, 260 Time Counter 171, 172, 173, 174, 175, 176, 177, 178, 520, 521, 522, 530, 540 DAC / ADC circuit 180 Clock Generator 182 Multiplexer 300, 310, 320, 330, 340 racks 301~309, 311~319, 321~329, 331~339, 341~349 Units (chassis)

Claims

1. A control system (2) including first and second control devices (100, 200) for controlling quantum bits, The first control device a first time counter (160) that indicates a time; a first clock distributor (130) that distributes a first clock to components inside and outside the first control device; a first trigger signal distributor (140) that distributes a first trigger signal to components inside and outside the first control device based on the time indicated by the first time counter; The second control device a second time counter (260) that indicates the time; a second clock distributor (230) connected to the first clock distributor and distributing a second clock synchronized with the first clock distributed by the first clock distributor to components in the second control device; a second trigger signal distributor (240) connected to the first trigger signal distributor, receiving the first trigger signal distributed by the first trigger signal distributor after a certain latency, and distributing a second trigger signal to components in the second control device based on the time indicated by the second time counter; Equipped with the second trigger signal distributor samples the first trigger signal at the timing of the second clock, and sets the second time counter to a time obtained by adding the latency to the time indicated by the first time counter at the timing of sampling the first trigger signal.

2. A control system (2) including first and second control devices (100, 200) for controlling quantum bits, The first control device a first time counter (160) that indicates a time; a first clock distributor (130) that distributes a first clock to components inside and outside the first control device; a first trigger signal distributor (140) that distributes a first trigger signal to components inside and outside the first control device based on the time indicated by the first time counter; The second control device a second time counter (260) that indicates the time; a second clock distributor (230) connected to the first clock distributor and distributing a second clock synchronized with the first clock distributed by the first clock distributor to components in the second control device; a second trigger signal distributor (240) connected to the first trigger signal distributor, receiving the first trigger signal distributed by the first trigger signal distributor after a certain latency, and distributing a second trigger signal to components in the second control device based on the time indicated by the second time counter; Equipped with the first trigger signal distributor transmits the first trigger signal and a first timestamp to the second trigger signal distributor; The second trigger signal distributor samples the first trigger signal at the timing of the second clock, and sets a second timestamp, which is the first timestamp plus the latency, in the second time counter at the timing of sampling the first trigger signal.

3. 3. The control system according to claim 1, wherein the first control device further comprises a latency measurement unit (114) that measures the latency required to transmit the trigger signal from the first trigger signal distributor to the second trigger signal distributor.

4. the components within the first and second controllers include first and second transceivers (120, 220), respectively, for transmitting and receiving high frequency radio signals for controlling the quantum bits; each of the first and second transceiver units includes a baseband circuit (50) that processes a baseband signal and an RF circuit (60) that converts the baseband signal to a high-frequency radio signal; the baseband circuit includes a digital processing circuit (52) that digitally processes the baseband signal, and a digital-to-analog conversion circuit (54) that converts the baseband signal between a digital signal and an analog signal; 3. The control system according to claim 1, wherein the first and second trigger signals are sent to the digital-to-analog conversion circuit and used as triggers for conversion between digital and analog signals.

5. 5. The measurement system according to claim 4, wherein the first and second trigger signal distributors and the digital processing circuit are implemented by an FPGA.

6. A control method for controlling a quantum bit using first and second control devices (100, 200), comprising: In the first control device, a first clock distribution step of distributing a first clock to components inside and outside the first control device; a first trigger signal distribution step of distributing a first trigger signal to components inside and outside the first control device based on the time of the first control device, In the second control device, a second clock distribution step of distributing a second clock synchronized with the first clock distributed in the first clock distribution step to components within the second control device; a second trigger signal distribution step of receiving the first trigger signal distributed in the first trigger signal distribution step after a certain latency and distributing a second trigger signal to components in the second control device based on a time of the second control device; Including, In the second trigger signal distribution step, the first trigger signal is sampled at the timing of the second clock, and the time of the first control device plus the latency at the timing of sampling the first trigger signal is set as the time of the second control device.

7. A control method for controlling a quantum bit using first and second control devices (100, 200), comprising: In the first control device, a first clock distribution step of distributing a first clock to components inside and outside the first control device; a first trigger signal distribution step of distributing a first trigger signal to components inside and outside the first control device based on the time of the first control device, In the second control device, a second clock distribution step of distributing a second clock synchronized with the first clock distributed in the first clock distribution step to components within the second control device; a second trigger signal distribution step of receiving the first trigger signal distributed in the first trigger signal distribution step after a certain latency and distributing a second trigger signal to components in the second control device based on a time of the second control device; Including, In the first trigger signal distribution step, the first trigger signal and a first timestamp are transmitted to the second control device; In the second trigger signal distribution step, the first trigger signal is sampled at the timing of the second clock, and a second timestamp obtained by adding the latency to the first timestamp at the timing of sampling the first trigger signal is set as the time of the second control device.

8. A control device (100) for controlling a quantum bit, comprising: a time counter (160) that indicates the time; a clock distributor (130) that receives a reference clock and distributes a clock synchronized with the reference clock to components inside and outside the control device; a trigger signal distributor (140) that receives a reference trigger signal and distributes the trigger signal to components inside and outside the control device based on the time indicated by the time counter, which is set based on the reference trigger signal; The control device is characterized in that the trigger signal distributor samples the reference trigger signal at the timing of the clock, and sets the time indicated by the time counter at the timing of sampling the reference trigger signal plus the latency of the reference trigger signal to the time counter.

9. A control device (100) for controlling a quantum bit, comprising: a time counter (160) that indicates the time; a clock distributor (130) that receives a reference clock and distributes a clock synchronized with the reference clock to components inside and outside the control device; a trigger signal distributor (140) that receives a reference trigger signal and a reference timestamp and distributes the trigger signal and the timestamp to components inside and outside the control device based on the time indicated by the time counter, which is set based on the reference trigger signal and the reference timestamp; The control device is characterized in that the trigger signal distributor samples the reference trigger signal at the timing of the clock, and sets a timestamp in the time counter at the timing of sampling the reference trigger signal, the timestamp being the timestamp plus the latency of the reference trigger signal.

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