Display device

Abstract

To provide a display device capable of applying overdrive with less costs and a simpler setup.SOLUTION: A display device comprises: pixels; scanning lines connected to multiple pixels lined up along a first direction; signal lines connected to multiple pixels lined up along a second direction that crosses the first direction; a first circuit for supplying a gate signal to the multiple scanning lines; a second circuit for supplying a pixel signal to the multiple signal lines; and a third circuit for generating a pixel signal corresponding to image data. The pixels are reset by a reset signal corresponding to a predetermined gradation value before a pixel signal is supplied, the third circuit applies overdrive to partial or entire pixels, and the magnitude of the difference between the gradation value of a pixel signal generated by overdrive and a predetermined gradation value is larger in a pixel signal supplied to a pixel connected to a scanning line in which supply timing of a gate signal in scanning is later.SELECTED DRAWING: Figure 16

Description

[Technical Field]

[0001] The present disclosure relates to a display device. [Background technology]

[0002] In order to increase the response speed, a display device is known that applies overdrive to drive the liquid crystal (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2019-40036 Summary of the Invention [Problem to be solved by the invention]

[0004] In the overdrive described in Cited Document 1, it was necessary to provide pixels with a gradation value corresponding to the difference in gradation value of each pixel between the latest image to be displayed and the image immediately preceding it. Therefore, a display device to which the overdrive described in Cited Document 1 is applied requires a storage area for storing the immediately preceding image, and the high cost of the storage device for securing the storage area was unavoidable. In addition, the gradation value control according to the difference in gradation value of each pixel between the latest image and the image immediately preceding it is complicated, and a display device capable of applying overdrive with a simpler mechanism has been desired.

[0005] The present disclosure has been made in view of the above-mentioned problems, and aims to provide a display device to which overdrive can be applied at lower cost and with a simpler mechanism. [Means for solving the problem]

[0006] A display device according to one aspect of the present disclosure includes pixels, scanning lines connected to a plurality of the pixels arranged along a first direction, signal lines connected to a plurality of the pixels arranged along a second direction intersecting the first direction, a first circuit that supplies gate signals to the plurality of the scanning lines, a second circuit that supplies pixel signals to the plurality of the signal lines, and a third circuit that generates the pixel signals according to image data, wherein the pixel signals are supplied to the pixels according to drive timings of switching elements that are driven according to the gate signals, and the pixels are reset by a reset signal corresponding to a predetermined gradation value before the pixel signals are supplied, and the first circuit the third circuit applies overdrive to some or all of the pixels, and the overdrive is a process of generating the pixel signal corresponding to a gradation value whose difference from the predetermined gradation value is greater than the reference gradation value, based on the difference between the gradation value indicated by pixel data included in the image data and the predetermined gradation value; the magnitude of the difference between the gradation value of the pixel signal generated by the overdrive and the predetermined gradation value is greater for the pixel signal supplied to the pixel connected to the scanning line whose timing of supplying the gate signal in the scanning is later. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a configuration diagram illustrating an example of a display system according to an embodiment. [Figure 2] FIG. 2 is a schematic diagram showing an example of the relative relationship between the display panel and the user's eyes. [Figure 3] FIG. 3 is a block diagram showing an example of the configuration of each of the image generating device and the display device in the display system shown in FIG. [Figure 4] FIG. 4 is a circuit diagram showing a display area according to the embodiment. [Figure 5] FIG. 5 is a schematic diagram illustrating an example of a display panel according to an embodiment. [Figure 6] FIG. 6 is a cross-sectional view that schematically shows a cross section of a display panel according to an embodiment. [Figure 7] FIG. 7 is a diagram for explaining the scanning performed to supply the gate signal. [Figure 8] FIG. 8 is a timing chart of signal control relating to updating of frame images. [Figure 9] FIG. 9 is a diagram showing the timing of the control signal without P1. [Figure 10] FIG. 10 is a graph for explaining the mechanism of overdrive. [Figure 11] FIG. 11 is a graph for explaining the relationship between overdrive and the difference in relative luminance before and after updating. [Figure 12] FIG. 12 is a graph showing an example of the response of the pixel Pix when the temperature of the liquid crystal molecules LM is lower than the temperature of the liquid crystal molecules LM assumed in the description with reference to FIG. [Figure 13] FIG. 13 is a block diagram showing a schematic configuration employed in a comparative example in which overdrive is applied that reflects the difference in relative luminance between images before and after updating. [Figure 14] FIG. 14 is a table showing the response time of a pixel Pix determined based on the relationship between the gradation value indicated by the pixel signal before updating and the gradation value indicated by the pixel signal after updating. [Figure 15] FIG. 15 is a graph showing an example of the gradation value indicated by the updated pixel signal when overdrive is applied in a case where the pixel Pix is ​​driven at the maximum brightness before updating the pixel signal. [Figure 16] FIG. 16 is a graph showing the relationship between "target gray scale" and "writing gray scale" for five lookup tables used as standards for applying overdrive. [Figure 17] FIG. 17 is a block diagram showing the input / output of the driver IC 115 and the main functional configuration included in the driver IC 115. [Figure 18] FIG. 18 is a block diagram showing the main functional configuration of the tone correction circuit 115c. [Figure 19] FIG. 19 is a block diagram showing the processing contents performed by each component of the tone correction circuit 115c shown in FIG. [Figure 20]FIG. 20 is a graph showing an example of the gradation value indicated by the pixel signal after updating when overdrive is applied in a case where the pixel Pix is ​​driven at the lowest luminance before updating the pixel signal. [Figure 21] FIG. 21 is a graph showing an example of the gradation value indicated by the updated pixel signal when overdrive is applied, in the case where the pixel Pix is ​​driven at an intermediate gradation between the minimum and maximum brightness before updating the pixel signal. [Figure 22] FIG. 22 is a diagram showing an example of the contents of each of the lookup tables LUT1, LUT2, LUT3, LUT4, and LUT5 when a pixel signal indicating a gradation value of "0" is used as the predetermined pixel signal. [Figure 23] FIG. 23 is a graph showing the lookup tables LUT1, LUT2, LUT3, LUT4, and LUT5 shown in FIG. [Figure 24] FIG. 24 is a diagram showing "L out" within a range where "L in" is 245 or more when the number of bits is not expanded. [Figure 25] FIG. 25 is a diagram showing "L out" within a range where "L in" is 245 or more when the number of bits is expanded. [Figure 26] FIG. 26 is a graph showing a lookup table that reflects the "writing grayscale" relative to the ideal "target grayscale" as an overdrive, and a lookup table that prioritizes suppressing uniformity of "L out." [Figure 27] FIG. 27 is a diagram showing "L out" within a range where "L in" is 240 or more, among the relationships between "L in" and "L out" in the lookup tables LUA and LUB shown in FIG. [Figure 28] FIG. 28 is a graph showing an example of a response when a reset is performed due to a halftone. DETAILED DESCRIPTION OF THE INVENTION

[0008] Each embodiment of the present disclosure will be described below with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the invention are naturally included within the scope of the present disclosure. Furthermore, to clarify the explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and are not intended to limit the interpretation of the present disclosure. Furthermore, in this specification and each drawing, elements similar to those described above with reference to the previous drawings will be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0009] Fig. 1 is a configuration diagram showing an example of a display system according to an embodiment. Fig. 2 is a schematic diagram showing an example of the relative relationship between a display panel and a user's eyes. In this embodiment, the display system 1 is a display system that changes the display in accordance with the user's movements. For example, the display system 1 is a VR system that stereoscopically displays VR (Virtual Reality) images showing three-dimensional objects in a virtual space and changes the stereoscopic display in accordance with the orientation (position) of the user's head, thereby creating a sense of virtual reality for the user.

[0010] 1, the display system 1 includes, for example, a display device 100 and an image generation device 200. The display device 100 and the image generation device 200 are connected by, for example, a cable 300. The cable 300 includes, for example, a cable such as a USB (Universal Serial Bus) or an HDMI (registered trademark) (High-Definition Multimedia Interface) cable. The display device 100 and the image generation device 200 may also be connected by wireless communication.

[0011] In the present disclosure, the display device 100 is used as a head-mounted display device that is fixed to a wearing member 400 and worn on the head of a user, for example. The display device 100 includes a display panel 110 for displaying an image generated by the image generation device 2. Hereinafter, the mode in which the display device 100 is fixed to the wearing member 400 is also referred to as an "HMD (Head Mounted Display)."

[0012] In the present disclosure, the image generating device 200 is exemplified by an electronic device such as a personal computer or a game console. The image generating device 200 generates a VR image according to the position and posture of the user's head and outputs the image to the display device 100. Note that the image generated by the image generating device 200 is not limited to a VR image.

[0013] The display device 100 is fixed at a position where the display panel 110 is placed in front of both eyes of the user when the user wears the HMD. In addition to the display panel 110, the display device 100 may be provided with an audio output device such as a speaker at a position corresponding to both ears of the user when the user wears the HMD. As will be described later, the display device 100 may also be provided with a sensor (for example, a gyro sensor, an acceleration sensor, a direction sensor, etc.) that detects the position and posture of the head of the user wearing the display device 100. The display device 100 may also be provided with the functions of the image generating device 200.

[0014] As shown in FIG. 2, the wearing member 400 has, for example, lenses 410 corresponding to two eyes E. When a user wears the HMD, the lenses 410 enlarge an image displayed on the display panel 110 and focus it on the user's eyes E. The user views the image displayed on the display panel 110 and enlarged by the lenses 410. Note that while FIG. 2 shows an example in which one lens is placed between the user's eyes E and the display panel 110, it may also be configured with, for example, multiple lenses corresponding to both of the user's eyes. It may also be configured such that the display panel 110 is placed at a position other than in front of the user's eyes.

[0015] In this embodiment, the display panel 110 is assumed to be a liquid crystal display panel of a horizontal electric field mode such as IPS (in-plane switching) including FFS (fringe field switching) using an image liquid crystal element.

[0016] In a display device 100 used in a VR system such as that shown in FIG. 1, an image displayed on a display panel 110 is enlarged and focused on a user's eye E, as shown in FIG. 2. This necessitates the development of higher-resolution display panels. Furthermore, enlarging the displayed image makes the gaps between pixels appear more like a grid. Therefore, using a liquid crystal display panel with a high pixel aperture ratio has the advantage of enabling image display with less of a grid-like appearance.

[0017] Fig. 3 is a block diagram showing an example of the configuration of the image generating device and the display device in the display system shown in Fig. 1. As shown in Fig. 3, the display device 100 includes two display panels 110, a sensor 120, an image separating circuit 150, and an interface 160.

[0018] The display device 100 includes two display panels 110. One of the two display panels 110 is used as the display panel 110 for the left eye, and the other is used as the display panel 110 for the right eye.

[0019] Each of the two display panels 110 has a display area 111 and a display control circuit 112. The display panel 110 has a light source device (not shown) that illuminates the display area 111 from behind.

[0020] In the display area 111, P0×Q0 pixels Pix are arranged in a two-dimensional matrix (row and column pattern) (P0 in the row direction (X direction) and Q0 in the column direction (Y direction)). In this embodiment, the pixel density in the display area 111 is set to, for example, 806 ppi. FIG. 3 shows a schematic representation of the arrangement of the multiple pixels Pix, and the detailed arrangement of the pixels Pix will be described later.

[0021] The display panel 110 has scan lines extending in the X direction and signal lines extending in the Y direction intersecting the X direction. In the display panel 110, pixels Pix are arranged in an area surrounded by the signal lines SL and the scan lines GL. Each pixel Pix has a switching element (TFT: thin film transistor) connected to the signal line SL and the scan line GL, and a pixel electrode connected to the switching element. A single scan line GL is connected to a plurality of pixels Pix arranged along the extension direction of the scan line GL. A single signal line SL is connected to a plurality of pixels Pix arranged along the extension direction of the signal line SL.

[0022] Of the two display panels 110, the display area 111 of one display panel 110 is for the right eye, and the display area 111 of the other display panel 110 is for the left eye. Here, an example is shown in which the display panel 110 has two display panels 110, one for the left eye and one for the right eye, but the display device 100 is not limited to a structure using two display panels 110. For example, there may be one display panel 110, and the display area of ​​the single display panel 110 may be divided into two so that an image for the right eye is displayed in the right half area and an image for the left eye is displayed in the left half area.

[0023] The display control circuit 112 includes a driver IC (Integrated Circuit) 115, a signal line connection circuit 113, and a scanning line drive circuit 114. The signal line connection circuit 113 is electrically connected to the signal lines SL. The driver IC 115 controls the ON / OFF of switching elements (e.g., TFTs) for controlling the operation (light transmittance) of the pixels Pix via the scanning line drive circuit 114. The scanning line drive circuit 114 is electrically connected to the scanning lines GL.

[0024] The sensor 120 detects information that allows estimation of the orientation of the user's head. For example, the sensor 120 detects information that indicates the movement of the display device 100, and the display system 1 estimates the orientation of the head of the user wearing the display device 100 on their head, based on the information that indicates the movement of the display device 100.

[0025] The sensor 120 detects information that enables estimation of the orientation of the HMD, for example, using at least one of the angle, acceleration, angular velocity, orientation, and distance of the display device 100. The sensor 120 may use, for example, a gyro sensor, an acceleration sensor, an orientation sensor, etc. The sensor 120 may detect, for example, the angle and angular velocity of the display device 100 using a gyro sensor. The sensor 120 may detect, for example, the direction and magnitude of acceleration acting on the display device 100 using an acceleration sensor.

[0026] Furthermore, the sensor 120 may detect the orientation of the display device 100 using, for example, a direction sensor. The sensor 120 may detect movement of the display device 100 using, for example, a distance sensor, a GPS (Global Positioning System) receiver, or the like. The sensor 120 may be any other sensor such as an optical sensor, or a combination of multiple sensors, as long as it is a sensor for detecting the orientation of the user's head, changes in line of sight, movement, etc. The sensor 120 is electrically connected to the control circuit 230, for example, as shown in FIG. 3 . A signal indicating the detection result of the sensor 120 is output to the control circuit 230.

[0027] Image separation circuit 150 receives left-eye image data and right-eye image data sent from image generation device 200 via cable 300, and sends the left-eye image data to display panel 110 that displays an image for the left eye, and sends the right-eye image data to display panel 110 that displays an image for the right eye. As will be described later, image data (for example, image data DP3 shown in FIG. 17, which will be described later) that forms the basis of pixel signals generated by driver IC 115 is the left-eye image data or right-eye image data.

[0028] Interface 160 includes a connector to which cable 300 (FIG. 1) is connected. A signal from image generation device 200 is input to interface 160 via connected cable 300. Note that a signal input from sensor 120 may be output to control circuit 230 of image generation device 200 via interface 160 and interface 240. Interface 160 may also be, for example, a wireless communication device, and may transmit and receive information to and from image generation device 200 via wireless communication.

[0029] The image generating device 200 includes an operation unit 210 , a storage unit 220 , a control circuit 230 , and an interface 240 .

[0030] The operation unit 210 accepts operations from a user. The operation unit 210 can use input devices such as a keyboard, buttons, or a touch screen. The operation unit 210 is electrically connected to the control circuit 230. The operation unit 210 outputs information according to the operation to the control circuit 230.

[0031] The storage unit 220 stores programs and data. The storage unit 220 temporarily stores processing results of the control circuit 230. The storage unit 220 includes a storage medium. The storage medium includes, for example, a ROM, a RAM, a memory card, an optical disk, or a magneto-optical disk. The storage unit 220 may store data of images to be displayed on the display device 100.

[0032] The storage unit 220 stores, for example, a control program 211, a VR application 212, etc. The control program 211 can provide, for example, functions related to various controls for operating the image generating device 200. The VR application 212 can provide a function for displaying a VR image on the display device 100. The storage unit 220 can store, for example, various pieces of information input from the display device 100, such as data indicating the detection results of the sensor 120.

[0033] The control circuit 230 includes, for example, an MCU (Micro Control Unit), a CPU (Central Processing Unit), etc. The control circuit 230 can comprehensively control the operation of the image generating device 200. Various functions of the control circuit 230 are realized based on the control of the control circuit 230.

[0034] The control circuit 230 includes, for example, a GPU (Graphics Processing Unit) that generates an image to be displayed. The GPU generates an image to be displayed on the display device 100. The control circuit 230 outputs the image generated by the GPU to the display device 100 via the interface 240. In this embodiment, a case will be described in which the control circuit 230 of the image generating device 200 includes a GPU, but this is not limiting. For example, the GPU may be provided in the display device 100 or the image separation circuit 150 of the display device 100. In this case, the display device 100 may acquire data from, for example, the image generating device 200, an external electronic device, etc., and the GPU may generate an image based on the data.

[0035] The interface 240 includes a connector to which a cable 300 (see FIG. 1) is connected. A signal from the display device 100 is input to the interface 240 via the cable 300. The interface 240 outputs a signal input from the control circuit 230 to the display device 100 via the cable 300. The interface 240 may be, for example, a wireless communication device, and may transmit and receive information to and from the display device 100 via wireless communication.

[0036] When the control circuit 230 executes the VR application 212, it causes the display device 100 to display an image according to the movement of the user (display device 100). When the control circuit 230 detects a change in the user (display device 100) while an image is being displayed on the display device 100, it changes the image displayed on the display device 100 to an image in the changed direction. When starting to create an image, the control circuit 230 creates an image based on a reference viewpoint and a reference line of sight in the virtual space, and when it detects a change in the user (display device 100), it changes the viewpoint or line of sight when creating the displayed image from the reference viewpoint or reference line of sight direction according to the movement of the user (display device 100), and causes the display device 100 to display an image based on the changed viewpoint or line of sight.

[0037] For example, the control circuit 230 detects a movement of the user's head to the right based on the detection result of the sensor 120. In this case, the control circuit 230 changes the image currently being displayed to an image that would appear if the user were to change their line of sight to the right. The user can view an image to the right of the image being displayed on the display device 100.

[0038] For example, when the control circuit 230 detects movement of the display device 100 based on the detection result of the sensor 120, it changes the image in accordance with the detected movement. When the control circuit 230 detects that the display device 100 has moved forward, it changes the currently displayed image to an image that would appear if the display device 100 had moved forward. When the control circuit 230 detects that the display device 100 has moved backward, it changes the currently displayed image to an image that would appear if the display device 100 had moved backward. The user can view an image in the direction of their own movement from the image displayed on the display device 100.

[0039] Fig. 4 is a circuit diagram showing a display area according to an embodiment. Hereinafter, the above-mentioned scanning lines GL collectively refer to the plurality of scanning lines G1, G2, and G3. The above-mentioned signal lines SL collectively refer to the plurality of signal lines S1, S2, and S3. In the example shown in Fig. 4, the scanning lines GL and the signal lines SL are orthogonal to each other, but this is not limiting. For example, the scanning lines GL and the signal lines SL do not have to be orthogonal to each other.

[0040] As shown in FIG. 4, in the present disclosure, the pixel Pix includes, for example, a pixel PixR for displaying red (first color: R), a pixel PixG for displaying green (second color: G), and a pixel PixB for displaying blue (third color: B). In the display area 111, switching elements TrD1, TrD2, and TrD3, signal lines SL, and scanning lines GL of the pixels PixR, PixG, and PixB are formed. The signal lines S1, S2, and S3 are wirings for supplying pixel signals to the pixel electrodes PE1, PE2, and PE3 (see FIG. 6). The scanning lines G1, G2, and G3 are wirings for supplying gate signals for driving the switching elements TrD1, TrD2, and TrD3. The pixel signals are signals generated by the driver IC 115 based on image data input to the display panel 110. The pixel signals determine the orientation of liquid crystal molecules LM at the positions of the pixels PixR, PixG, and PixB included in each pixel Pix. That is, the pixel signal determines the degree of transmission of light from the backlight at the position of each pixel Pix. In other words, the pixel signal is generated so that an image to be displayed in accordance with image data can be reproduced by the display output of the display panel 110.

[0041] The pixels PixR, PixG, and PixB each include a switching element TrD1, TrD2, and TrD3, and a capacitance of a liquid crystal layer LC. The switching elements TrD1, TrD2, and TrD3 are configured with thin-film transistors, and in this example, are configured with n-channel MOS (Metal Oxide Semiconductor) TFTs. A sixth insulating film 16 (see FIG. 6) is provided between the pixel electrodes PE1, PE2, and PE3, which will be described later, and the common electrode COM, and these form the storage capacitance Cs shown in FIG. 4.

[0042] The color filters CFR, CFG, and CFB shown in Fig. 4 have color regions colored in three colors, for example, red (first color: R), green (second color: G), and blue (third color: B), arranged periodically. A set of color regions of the three colors R, G, and B is associated with each of the pixels PixR, PixG, and PixB shown in Fig. 4 described above. The pixels PixR, PixG, and PixB corresponding to the three color regions are defined as a set of pixels Pix. Note that the color filter may include color regions of four or more colors.

[0043] Fig. 5 is a schematic diagram showing an example of a display panel according to an embodiment, and Fig. 6 is a cross-sectional view showing a cross section of the display panel according to an embodiment.

[0044] 5, the display panel 110 has sides 110e1, 110e2, 110e3, and 110e4 at the substrate edges. The areas between the display area 111 and the sides 110e1, 110e2, 110e3, and 110e4 at the substrate edges of the display panel are called peripheral areas.

[0045] The scanning line driving circuit 114 is disposed in a peripheral region between a side 110e1 at an edge of the substrate of the display panel 110 and the display region 111. The signal line connecting circuit 113 is disposed in a peripheral region between a side 110e4 at an edge of the substrate of the display panel 110 and the display region 111. The driver IC 115 is disposed in a peripheral region between a side 110e4 at an edge of the substrate of the display panel 110 and the display region 111. In this embodiment, the sides 110e3 and 110e4 at the edges of the substrate of the display panel 110 are parallel to the X direction. The sides 110e1 and 110e2 at the edges of the substrate of the display panel 110 are parallel to the Y direction.

[0046] In the example shown in FIG. 5, the signal lines SL extend parallel to the Y direction, and the scanning lines GL extend parallel to the X direction. As shown in FIG. 5, in the present disclosure, the direction in which the scanning lines GL extend is perpendicular to the direction in which the signal lines SL extend, so that, for example, each of the pixels PixR, PixG, and PixB is rectangular. In the example shown in FIG. 5, each of the pixels PixR, PixG, and PixB is rectangular, but is not limited to a rectangle. For example, each of the pixels PixR, PixG, and PixB may be a parallelogram. Note that each of the pixels PixR, PixG, and PixB may also be referred to as a pixel PixS.

[0047] Next, the cross-sectional structure of the display panel 110 will be described with reference to FIG. 6. In FIG. 6, the array substrate SUB1 has a first insulating substrate 10, such as a glass substrate or a resin substrate, as its base. The array substrate SUB1 includes a first insulating film 11, a second insulating film 12, a third insulating film 13, a fourth insulating film 14, a fifth insulating film 15, a sixth insulating film 16, signal lines S1 to S3, pixel electrodes PE1 to PE3, a common electrode COM, a first alignment film AL1, and the like, on the side of the first insulating substrate 10 facing the counter substrate SUB2. In the following description, the direction from the array substrate SUB1 toward the counter substrate SUB2 will be referred to as "upward" or simply "upward."

[0048] The first insulating film 11 is located on the first insulating substrate 10. The second insulating film 12 is located on the first insulating film 11. The third insulating film 13 is located on the second insulating film 12. The signal lines S1 to S3 are located on the third insulating film 13. The fourth insulating film 14 is located on the third insulating film 13 and covers the signal lines S1 to S3.

[0049] If necessary, wiring may be disposed on the fourth insulating film 14. This wiring will be covered by the fifth insulating film 15. In this embodiment, wiring is omitted. The first insulating film 11, the second insulating film 12, the third insulating film 13, and the sixth insulating film 16 are formed of a light-transmitting inorganic material such as silicon oxide or silicon nitride. The fourth insulating film 14 and the fifth insulating film 15 are formed of a light-transmitting resin material and have a thickness greater than that of the other insulating films formed of inorganic materials. However, the fifth insulating film 15 may also be formed of an inorganic material.

[0050] The common electrode COM is located on the fifth insulating film 15. The common electrode COM is covered with a sixth insulating film 16. The sixth insulating film 16 is formed of an inorganic material having light-transmitting properties, such as silicon oxide or silicon nitride.

[0051] The pixel electrodes PE1 to PE3 are located on a sixth insulating film 16 and face the common electrode COM via the sixth insulating film 16. The pixel electrodes PE1 to PE3 and the common electrode COM are formed of a light-transmitting conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The pixel electrodes PE1 to PE3 are covered with a first alignment film AL1. The first alignment film AL1 also covers the sixth insulating film 16.

[0052] The counter substrate SUB2 is based on a second insulating substrate 20 having light transparency, such as a glass substrate or a resin substrate. The counter substrate SUB2 is provided with a light-shielding layer BM, color filters CFR, CFG, CFB, an overcoat layer OC, a second alignment film AL2, etc. on the side of the second insulating substrate 20 facing the array substrate SUB1.

[0053] 6, the light-shielding layer BM is located on the side of the second insulating substrate 20 facing the array substrate SUB1. The light-shielding layer BM defines the size of the openings facing the pixel electrodes PE1 to PE3. The light-shielding layer BM is made of a black resin material or a light-shielding metal material.

[0054] The color filters CFR, CFG, and CFB are located on the side of the second insulating substrate 20 facing the array substrate SUB1, with their respective edges overlapping the light-shielding layer BM. The color filter CFR faces the pixel electrode PE1. The color filter CFG faces the pixel electrode PE2. The color filter CFB faces the pixel electrode PE3. In one example, the color filters CFR, CFG, and CFB are formed from resin materials colored blue, red, and green, respectively.

[0055] The overcoat layer OC covers the color filters CFR, CFG, and CFB. The overcoat layer OC is made of a light-transmitting resin material. The second alignment film AL2 covers the overcoat layer OC. The first alignment film AL1 and the second alignment film AL2 are made of, for example, a material that exhibits horizontal alignment.

[0056] As described above, the counter substrate SUB2 includes the light-shielding layer BM, color filters CFR, CFG, CFB, etc. The light-shielding layer BM is disposed in an area facing wiring portions such as the scanning lines G1, G2, G3, signal lines S1, S2, S3, contact portions PA1, PA2, PA3, and switching elements TrD1, TrD2, TrD3 shown in FIG.

[0057] 6, the counter substrate SUB2 includes three color filters CFR, CFG, and CFB, but may include four or more color filters including color filters of colors other than blue, red, and green, such as white, transparent, yellow, magenta, cyan, etc. Furthermore, these color filters CFR, CFG, and CFB may be included on the array substrate SUB1.

[0058] In addition, in FIG. 6, the color filters CF are provided on the counter substrate SUB2, but the color filters CF may be provided on the array substrate SUB1, which is a so-called COA (Color filter on Array) structure.

[0059] The array substrate SUB1 and counter substrate SUB2 are arranged such that the first alignment film AL1 and the second alignment film AL2 face each other. A liquid crystal layer LC is sealed between the first alignment film AL1 and the second alignment film AL2. The liquid crystal layer LC is made of a negative-type liquid crystal material with negative dielectric anisotropy or a positive-type liquid crystal material with positive dielectric anisotropy.

[0060] The array substrate SUB1 faces the backlight unit IL, and the counter substrate SUB2 faces the display surface. Various types of backlight unit IL are applicable, but detailed explanation of their structures will be omitted.

[0061] The first optical element OD1 including the first polarizer PL1 is disposed on the outer surface of the first insulating substrate 10 or on the surface facing the backlight unit IL. The second optical element OD2 including the second polarizer PL2 is disposed on the outer surface of the second insulating substrate 20 or on the surface facing the viewing position. The first polarization axis of the first polarizer PL1 and the second polarization axis of the second polarizer PL2 are in a crossed Nicol positional relationship in the XY plane, for example. The first optical element OD1 and the second optical element OD2 may include other optically functional elements such as retardation plates.

[0062] For example, if the liquid crystal layer LC is made of a negative liquid crystal material, and no voltage is applied to the liquid crystal layer LC, the liquid crystal molecules LM are initially aligned in the XY plane with their long axes aligned along the X direction. On the other hand, when a voltage is applied to the liquid crystal layer LC, that is, when an electric field is formed between the pixel electrodes PE1 to PE3 and the common electrode COM, the alignment state of the liquid crystal molecules LM changes under the influence of the electric field. When the liquid crystal layer LC is on, the polarization state of incident linearly polarized light changes depending on the alignment state of the liquid crystal molecules LM as it passes through the liquid crystal layer LC.

[0063] Hereinafter, the supply of gate signals and pixel signals performed in this embodiment will be described in more detail with reference to FIG.

[0064] 7 is a diagram for explaining scanning performed to supply gate signals. In the explanation from FIG. 7 onward, it is assumed that the scanning lines GL are arranged in the order of scanning lines G1, G2, G3, . . ., GB, . . ., GC, . . ., GD, . . ., GE from one end to the other in the Y direction. In addition, the interval between scanning line G1 and scanning line GB, the interval between scanning line GB and scanning line GC, the interval between scanning line GC and scanning line GD, and the interval between scanning line GD and scanning line GE are intervals DS, which can be considered to be equal. It is assumed that the number of scanning lines GL arranged at intervals DS is equal.

[0065] Hereinafter, when the word "scanning" is used without special mention, it refers to the supply of gate signals from the scanning line driving circuit 114 for displaying and outputting one frame image. The supply of gate signals during scanning is performed for each scanning line GL. Specifically, gate signals are supplied to each scanning line GL at different timings. More specifically, the scanning lines GL to which gate signals are supplied are switched sequentially from one end to the other in the Y direction. That is, during scanning, a gate signal is supplied to scanning line G1, a gate signal is supplied to scanning line G2, a gate signal is supplied to scanning line G3, ..., a gate signal is supplied to scanning line GB, ..., a gate signal is supplied to scanning line GC, ..., a gate signal is supplied to scanning line GD, ..., and a gate signal is supplied to scanning line GE, in this order. When a gate signal is supplied to a certain scanning line GL, a pixel signal is supplied from the signal line connection circuit 113 via a signal line SL, and the pixel signal is supplied to each of the pixels Pix connected to that certain scanning line GL. That is, during scanning, the pixel signal supplied to the pixel Pix connected to the scanning line GL to which the gate signal is supplied is supplied to each signal line SL.

[0066] Hereinafter, the term "pixel row" refers to multiple pixels Pix that share the same scanning line GL. Therefore, one pixel row is multiple pixels Pix connected to one scanning line GL. The multiple pixels Pix included in one pixel row are lined up in the X direction.

[0067] Next, signal control relating to updating of frame images to be displayed will be described with reference to FIG.

[0068] FIG. 8 is a timing chart of signal control related to updating a frame image. Hereinafter, when a frame period FT is referred to, it refers to the period related to the display output of one frame image. The frame period FT includes the update period of one frame image and the display output period of the updated frame image. Specifically, as shown in FIG. 8, the frame period FT includes a first period P1, a second period P2, a third period P3, and a fourth period P4. The first period P1, the second period P2, and the third period P3 correspond to the update period of one frame image. The fourth period P4 corresponds to the display output period of the updated frame image.

[0069] The first period P1 is a period in which all pixels Pix are reset. Specifically, during the first period P1, gate signals are supplied to all scanning lines GL, and predetermined pixel signals are supplied to all signal lines SL. Here, the predetermined pixel signals function as reset signals. Details of the predetermined pixel signals will be described later.

[0070] Scanning is performed during the second period P2. Therefore, during the second period P2, the scanning lines GL to which the gate signals are supplied are switched sequentially from one end to the other end in the Y direction, and pixel signals supplied to the pixels Pix connected to the scanning line GL to which the gate signals are supplied are supplied to each signal line SL.

[0071] The scanning line driving circuit 114 is implemented to alternately perform a process of supplying gate signals to all scanning lines GL collectively in a first period P1 and a process of scanning in a second period P2. Scanning in the second period P2 is achieved by, for example, a so-called shift register. Supplying gate signals collectively in the first period P1 is achieved by, for example, a switch for connecting a gate signal supply line to all scanning lines GL without using a shift register.

[0072] Furthermore, the reset signal supplied from the signal line connection circuit 113 during the first period P1 may be generated by the driver IC 115 and supplied to the signal line SL via the signal line connection circuit 113, or the reset signal may be supplied to the signal line SL by another method. For example, the display panel 110 may be provided with a switch that can collectively switch between connection and disconnection of the signal line SL and a potential line to which a potential that functions as a reset signal is supplied, and the switch may be turned ON during the first period P1 to connect the potential line and the signal line SL, and the switch may be turned OFF during periods other than the first period P1 to disconnect the potential line and the signal line SL.

[0073] In FIG. 8, targets to which gate signals are supplied during scanning are illustrated vertically as "scan targets." In FIG. 8, scan lines G1, GB, GC, GD, and GE are representatively shown as scan targets among the multiple scan lines GL. However, in reality, all scan lines GL arranged from one end to the other in the Y direction are included in the scan targets. Also, in FIG. 8, the scan transition line SC indicates the relationship between time and the switching of targets to which gate signals are supplied during scanning. A gate signal is supplied to the scan target at a timing corresponding to the intersection of the scan target and the scan transition line SC. Therefore, the gate signal is supplied to scan line G1 immediately after the start of the second period P2. The gate signal is supplied to scan line GB after the first response time T1B has elapsed since the start of the second period P2. The gate signal is supplied to scan line GC after the first response time T1C has elapsed since the start of the second period P2. The first response time T1C is longer than the first response time T1B. Furthermore, the timing at which the gate signal is supplied to the scanning line GD is the timing after the first response time T1D has elapsed from the start of the second period P2. The first response time T1D is longer than the first response time T1C. Furthermore, the timing at which the gate signal is supplied to the scanning line GE is the timing after the first response time T1E has elapsed from the start of the second period P2. The first response time T1E is longer than the first response time T1D.

[0074] Hereinafter, the term "first response time T1" will collectively refer to the time from the start of the second period P2 until the gate signal is supplied, including first response times T1B, T1C, T1D, and T1E. As indicated by the differences between first response time T1B, first response time T1C, first response time T1D, and first response time T1E, the length of the first response time T1 depends on the arrangement of each scanning line GL. The first response time T1 is shorter for scanning lines GL arranged closer to one end in the Y direction and longer for scanning lines GL arranged closer to the other end in the Y direction.

[0075] The third period P3 functions as an interval between the second period P2 and the fourth period P4. The third period P3 is set in the frame period FT because it takes a certain amount of time for the liquid crystal molecules LM in the pixels Pix to respond to the supplied pixel signals.

[0076] As described above, the timing of supplying gate signals to each scanning line GL during the second period P2 is different, and therefore the time from when a pixel signal is supplied to the pixel Pix connected to each scanning line GL through the third period P3 to the start of the fourth period P4 is different for each pixel row.

[0077] Hereinafter, the second response time T2 will be used to comprehensively refer to the time from the supply timing of the gate signal, i.e., the supply timing of the pixel signal, to the fourth period P4. In FIG. 8, second response times T21, T2B, T2C, T2D, and T2E are shown as examples of the second response time T2. The second response time T21 is the second response time T2 of the pixel row that shares the scan line G1. The second response time T2B is the second response time T2 of the pixel row that shares the scan line GB. The second response time T2B is shorter than the second response time T21. The second response time T2C is the second response time T2 of the pixel row that shares the scan line GC. The second response time T2C is shorter than the second response time T2B. The second response time T2D is the second response time T2 of the pixel row that shares the scan line GD. The second response time T2D is shorter than the second response time T2C. The second response time T2E is the second response time T2 of the pixel rows that share the scan line GE. The second response time T2E is shorter than the second response time T2D.

[0078] During the fourth period P4, the backlight is turned on. That is, since the response of the liquid crystal molecules LM according to the pixel signals supplied during the second period P2 is completed through the third period P3, the degree of transmission of light from the backlight is individually controlled for each pixel Pix during the fourth period P4, thereby displaying and outputting an image.

[0079] In Fig. 8, the backlight is turned on or off using a square wave indicating ON / OFF switching in the "BL" column. As indicated by the "OFF" square wave, the backlight is not turned on during the first period P1, the second period P2, and the third period P3. As indicated by the "ON" square wave, the backlight is turned on during the fourth period P4.

[0080] Note that frame period FTb shown in FIG. 8 is the frame period immediately before frame period FT shown in FIG. 8. Frame period FTa shown in FIG. 8 is the frame period immediately after frame period FT shown in FIG. 8. During frame period FTa and frame period FTb, signal control similar to that during frame period FT is performed. In the embodiment, a predetermined number of frame periods occur within a predetermined time (for example, 1 second) according to a predetermined refresh rate. The predetermined number of frame periods can be any number, for example, 90 times, or any other number, preferably 90 or more times as appropriate for the use of the HMD.

[0081] Here, the technical significance of the first period P1 being before the second period P2 in the frame period FT will be explained. As a premise for this technical significance, overdrive performed in a liquid crystal display will be explained with reference to FIG.

[0082] FIG. 10 is a graph illustrating the mechanism of overdrive. The horizontal axis in FIG. 10 and in FIGS. 11 and 12 (described later) indicates the elapsed time since a pixel signal is supplied to a pixel Pix. The vertical axis in FIG. 10 and in FIGS. 11 and 12 (described later) indicates the relative luminance, in percentage, of the display output performed at the position of the pixel Pix in response to the pixel signal supplied to the pixel Pix. The graphs in FIG. 10 and in FIGS. 11 and 12 (e.g., graph LC1) reflect the response speed of the pixel Pix in response to the difference in luminance of the pixel Pix before and after the supply of the pixel signal. For example, FIG. 10 graphs the response speed of the pixel Pix when the luminance of the display output by the pixel Pix driven in response to the supplied pixel signal is considered to be 100% luminance, and the luminance of the display output by the pixel Pix before the supply of the pixel signal is 0%.

[0083] FIG. 9 illustrates the timing of control signals without P1. As shown in FIG. 9, when P1, which was included in the frame period FT in the description with reference to FIG. 8, is absent and the pixel voltage of the previous frame FTb is maintained even after the P4 period, the first response time T1 extends the response of the second response time T2 of the previous frame FTb and continues until just before the second response time T2 of the frame FT. In FIG. 9, as in the description with reference to FIG. 8, the second response time T2 varies for each pixel row. Therefore, the backlight illumination period, as viewed from the timing of pixel signal supply, varies for each pixel row. Specifically, the shorter the second response time T2 of a pixel row, the earlier the backlight illumination period occurs in relation to the timing of pixel signal supply. FIG. 10 illustrates fourth periods P4E, P4D, and P4C as examples of such "deemed backlight illumination periods."

[0084] The fourth period P4E is a "deemed backlight on period" for pixel rows that share the scan line GE. Therefore, the fourth period P4E occurs after the second response time T2E (see FIG. 8) has elapsed since the supply of the pixel signal. The fourth period P4D is a "deemed backlight on period" for pixel rows that share the scan line GD. Therefore, the fourth period P4D occurs after the second response time T2D (see FIG. 8) has elapsed since the supply of the pixel signal. The fourth period P4C is a "deemed backlight on period" for pixel rows that share the scan line GC. Therefore, the fourth period P4C occurs after the second response time T2C (see FIG. 8) has elapsed since the supply of the pixel signal. Note that the fourth periods P4E, P4D, and P4C are actually the same fourth period P4.

[0085] Assume that a pixel signal is supplied to update the luminance of a pixel Pix from 0% to 100% in response to an update of a frame image. In this case, the simplest signal processing is to supply a pixel signal indicating 100% luminance to the pixel Pix. Here, the response of the pixel Pix using this simplest signal processing can be represented by the graph LC1 shown in FIG. 10. In graph LC1, the timing at which the luminance reaches 100% occurs after the fourth period P4C, and is not in time for any of the fourth periods P4E, P4D, and P4C. Therefore, with this simplest signal processing, the response of the pixel Pix does not arrive in time for the end of the fourth period P4, and the pixel Pix cannot achieve the 100% luminance expected by the pixel signal. In other words, the luminance reproduction in the display output is insufficient.

[0086] Therefore, overdrive is applied to LCD displays. Overdrive here refers to supplying a pixel signal to a pixel Pix that corresponds to a relative luminance difference greater than the relative luminance difference between the pixel Pix before and after updating. The degree of the "relative luminance difference greater than the relative luminance difference between the pixel Pix before and after updating" applied by overdrive generally increases for pixels Pix with shorter second response times T2.

[0087] For example, a relative luminance difference of slightly more than 100% is applied to pixels Pix included in pixel rows that share a scanning line GC (see FIGS. 7 and 8) by overdrive. By applying this relative luminance difference, the response of the pixel Pix becomes as shown by graph LC2 in FIG. 10. In graph LC2, the timing at which the luminance reaches 100% occurs at timing TM2 during the fourth period P4C, which is within the fourth period P4C. Furthermore, timing TM2 coincides approximately with the midpoint between the start and end of the fourth period P4C. This ensures that the average luminance of the pixel Pix during the fourth period P4C is approximately 100%, thereby achieving more precise luminance control.

[0088] Furthermore, a relative luminance difference of nearly 110% is applied to pixels Pix included in pixel rows that share the same scan line GD (see FIGS. 7 and 8) by overdrive. By applying this relative luminance difference, the response of the pixel Pix becomes as shown by graph LC3 in FIG. 10. In graph LC3, the timing at which the pixel Pix reaches 100% luminance occurs at timing TM3 during the fourth period P4D, which is within the fourth period P4D. Furthermore, timing TM3 coincides approximately with the midpoint between the start and end of the fourth period P4D. This ensures that the average luminance of the pixel Pix during the fourth period P4D is nearly 100%, enabling more precise luminance control.

[0089] Furthermore, a relative luminance difference of approximately 150% is applied to pixels Pix included in pixel rows that share a scanning line GE (see Figures 7 and 8) by overdrive. By applying this relative luminance difference, the response of the pixel Pix becomes as shown by graph LC4 in Figure 10. In graph LC4, the timing at which the luminance reaches 100% occurs at timing TM4 during the fourth period P4E, which is within the fourth period P4E. Furthermore, timing TM4 coincides approximately with the midpoint between the start and end of the fourth period P4E. This ensures that the average luminance of the pixel Pix during the fourth period P4E is approximately 100%, thereby achieving more precise luminance control.

[0090] In this way, overdrive can achieve more accurate luminance reproduction. The basic concept of overdrive has been explained above with reference to Fig. 10, but when actually applying overdrive, more complex factors must be taken into consideration, such as the difference in relative luminance before and after updating. Below, the relationship between overdrive and the difference in relative luminance before and after updating will be explained with reference to Fig. 11.

[0091] FIG. 11 is a graph illustrating the relationship between overdrive and the difference in relative luminance before and after updating. In the explanations of FIG. 11 and FIG. 12 described below, it is assumed that pixel Pix will exhibit 100% luminance, i.e., luminance LU2, during the fourth period P4X after updating the pixel signal. The fourth period P4X is a "deemed backlight illumination period" for pixel rows that share a certain scanning line GL. The fourth period P4X occurs after the second response time T2X has elapsed since the supply of the pixel signal. The second response time T2X is the second response time T2 for the pixel row.

[0092] In addition, in the explanation with reference to FIG. 11 and FIG. 12 described later, the brightness of 0% represented on the vertical axis (relative brightness) is defined as brightness LU1. Brightness LU3 is shown as an example of high brightness that significantly exceeds 100%. Brightness LU3 is a brightness that exceeds 150% and is less than 160%. Brightness LU21 is shown as an example of brightness that exceeds brightness LU2 and is significantly lower than brightness LU3. Brightness LU22 is shown as an example of brightness that is lower than brightness LU2 and is significantly higher than brightness LU1.

[0093] For example, when the luminance of pixel Pix before updating the pixel signal is luminance LU1 and the simplest signal processing is applied without overdrive, the response of pixel Pix can be represented by graph LC51 shown in FIG. 11. In graph LC51, the timing at which 100% luminance is reached occurs after the fourth period P4X, and is too late for the fourth period P4X. Therefore, by applying overdrive in this case and supplying a pixel signal corresponding to luminance LU21 to pixel Pix, the response of pixel Pix becomes as shown in graph LC52. In graph LC51, the timing at which 100% luminance is reached occurs at timing TMX during the fourth period P4X, and is enough to reach the fourth period P4X.

[0094] Furthermore, when the luminance of pixel Pix before the pixel signal is updated is luminance LU3 and the simplest signal processing is applied without overdrive, the response of pixel Pix can be represented by graph LC53 in FIG. 11. In graph LC53, the timing at which 100% luminance is reached occurs after the fourth period P4X, and is too late for the fourth period P4X. Therefore, by applying overdrive in this case and supplying a pixel signal corresponding to luminance LU22 to pixel Pix, the response of pixel Pix becomes as shown in graph LC54. In graph LC54, the timing at which 100% luminance is reached occurs at timing TMX during the fourth period P4X, and is enough to reach the fourth period P4X.

[0095] For the above reasons, if the first period P1 were not present as in the example shown in FIG. 9, a pixel signal corresponding to luminance LU22 or luminance LU21, rather than luminance LU2, would need to be applied to the pixel Pix so that it reaches 100% luminance. Whether luminance LU22, luminance LU21, or another gradation is used must be determined based on the luminance difference before and after the update (image data TFb and TF) and the pixel response speed, and a means for doing so must be provided. As described with reference to FIG. 11, when the luminance of pixel Pix before the pixel signal update is luminance LU1, which is lower than luminance LU2, a luminance LU21, which is higher than luminance LU2, is supplied as the pixel signal for update. Furthermore, when the luminance of pixel Pix before the pixel signal update is luminance LU3, which is higher than luminance LU2, a luminance LU22, which is lower than luminance LU2, is supplied as the pixel signal for update. Thus, when applying overdrive, even though the pixel Pix is ​​caused to produce brightness LU2 during the fourth period P4X after the pixel signal is updated, the pixel signal supplied for updating must be different depending on whether the brightness of the pixel Pix before the pixel signal is updated is relatively high or low compared to brightness LU2.

[0096] Furthermore, the response of the pixel Pix to the updated pixel signal is also affected by factors other than the relative brightness before and after the update, such as the temperature of the liquid crystal.

[0097] Fig. 12 is a graph showing an example of the response of the pixel Pix when the temperature of the liquid crystal molecules LM is lower than the temperature of the liquid crystal molecules LM assumed in the description with reference to Fig. 11. Generally, when the temperature of the liquid crystal molecules LM is lower, the response of the liquid crystal molecules LM becomes slower. In other words, when the temperature of the liquid crystal molecules LM is lower, the response of the pixel Pix becomes slower.

[0098] 12 shows that a decrease in the temperature of the liquid crystal molecules LM causes the response of the pixel Pix to become like graph LC61 when control similar to graph LC51 shown in FIG. 11 is applied. Similarly, a decrease in the temperature of the liquid crystal molecules LM causes the response of the pixel Pix to become like graph LC62 when control similar to graph LC52 shown in FIG. 11 is applied. Furthermore, a decrease in the temperature of the liquid crystal molecules LM causes the response of the pixel Pix to become like graph LC63 when control similar to graph LC53 shown in FIG. 11 is applied. Furthermore, a decrease in the temperature of the liquid crystal molecules LM causes the response of the pixel Pix to become like graph LC64 when control similar to graph LC54 shown in FIG. 11 is applied.

[0099] In graphs LC62 and LC64, even though overdrive is applied, the timing at which 100% brightness is reached occurs at timing TMY, which is later than the fourth period P4X, and is not in time for the fourth period P4X. In this way, if the decrease in temperature of the liquid crystal molecules LM cannot be correctly reflected in the conditions for applying overdrive, the response of the pixel Pix may not be in time even if overdrive is applied.

[0100] Furthermore, the impact on luminance when the pixel Pix's response is delayed even with overdrive depends on the luminance of the pixel Pix before the update. Specifically, when the luminance of the pixel Pix before the pixel signal update is lower than the luminance LU2, e.g., luminance LU1, the luminance of the pixel Pix occurring during the fourth period P4X is lower than the originally expected luminance of the pixel Pix. On the other hand, when the luminance of the pixel Pix before the pixel signal update is higher than the luminance LU2, e.g., luminance LU3, the luminance of the pixel Pix occurring during the fourth period P4X is higher than the originally expected luminance of the pixel Pix. Such variations in luminance reproduction depending on the relative luminance of the pixel Pix before and after the update result in variations in the luminance distribution, where the luminance of some parts of the displayed image is lower than expected, while the luminance of other parts is higher than expected. Note that if overdrive is not applied, such variations in the luminance distribution would be even more pronounced.

[0101] In this way, even if overdrive is applied, the difficulty of reproducing ideal luminance is not small when considering changes in the response of the pixel Pix due to external factors such as the temperature of the liquid crystal molecules LM.

[0102] In addition, since FIG. 10 applies overdrive that reflects the difference in relative luminance of the image before and after updating, a configuration is required to hold information indicating the luminance of pixel Pix before the pixel signal is updated.

[0103] FIG. 13 is a block diagram showing a schematic configuration employed in a comparative example in which overdrive reflecting the difference in relative luminance between images before and after updating is applied. As described with reference to FIGS. 11 and 12, applying overdrive reflecting the difference in relative luminance between images before and after updating requires information indicating the luminance of pixel Pix before the pixel signal is updated. The information indicating the luminance of pixel Pix before the pixel signal is updated is image data corresponding to the image displayed in the frame period immediately preceding the frame period FT in which the pixel signal is updated (frame period FTb in FIG. 9). Therefore, as shown in “Comparative Example 1” and “Comparative Example 2” in FIG. 13, a full-screen frame memory 1152 is provided within a driver IC 1151. Note that when the configurations of “Comparative Example 1” and “Comparative Example 2” shown in FIG. 13 are employed, a driver IC 1151 is provided instead of the driver IC 115 of the display panel 110.

[0104] In both "Comparative Example 1" and "Comparative Example 2," a lookup table for applying overdrive is stored in the gradation conversion LUT 1153, and a pixel signal OPX after overdrive is applied is output by the gradation conversion LUT 1153. The gradation conversion LUT 1153 outputs a pixel signal OPX according to the input pixel data PixD and the stored lookup table. Note that the row number NL is information indicating which pixel row the pixel Pix belongs to and which pixel data PixD corresponds to.

[0105] In "Comparative Example 1," the input path of pixel data PixD branches and is stored in a full-screen frame memory 1152. In the frame period FT following the frame period in which pixel data PixD is stored (frame period FTb), the full-screen frame memory 1152 outputs previous pixel data LBD1 indicating the pixel signal at the time of frame period FTb to the gradation conversion LUT 1153. The gradation conversion LUT 1153 determines the relative high / low relationship between the luminance of pixel Pix before and after updating by referring to the previous pixel data LBD1 and the latest pixel data PixD. Therefore, in "Comparative Example 1," the previous pixel data LBD1 is a signal containing information indicating the luminance of pixel Pix before the pixel signal is updated, and is a signal that constitutes image data corresponding to the image displayed in the frame period (frame period FTb in FIG. 8) immediately before the frame period FT in which pixel signal OPX is provided to pixel Pix.

[0106] In "Comparative Example 2," the output path of the pixel signal OPX branches and is stored in a full-screen frame memory 1152. In the frame period FT following the frame period in which the pixel signal OPX was output (frame period FTb), the full-screen frame memory 1152 outputs a previous pixel signal LBD2 indicating the pixel signal at the time of frame period FTb to the gradation conversion LUT 1153. The gradation conversion LUT 1153 determines the relative level of brightness of the pixel Pix before and after updating by referring to the previous pixel signal LBD2 and the latest pixel data PixD. Therefore, in "Comparative Example 2," the previous pixel signal LBD2 is a signal that includes information indicating the brightness of the pixel Pix before the pixel signal was updated, and is a signal that constitutes image data corresponding to the image displayed in the frame period (frame period FTb in FIG. 8) immediately before the frame period FT in which the pixel signal OPX is provided to the pixel Pix.

[0107] Regardless of whether the configuration of "Comparative Example 1" or "Comparative Example 2" described above is adopted, the single-screen frame memory 1152 must have a storage capacity corresponding to the data capacity of one piece of image data to be displayed during one frame period.

[0108] In contrast, in the embodiment, since the first period P1 is included in the frame period FT as shown in FIG. 8, the full-screen frame memory 1152 described with reference to FIG. 13 is not required. This is because all pixels Pix are reset by a predetermined pixel signal during the first period P1. This means that the pre-update pixel signal required to determine the updated pixel signal provided to the pixel Pix during the second period P2 after the first period P1 is unified to the predetermined pixel signal. Here, the predetermined pixel signal does not depend on the image displayed in the frame period immediately preceding the frame period FT in which the updated pixel signal is provided to the pixel Pix (frame period FTb in FIG. 8). Therefore, in the embodiment, the full-screen frame memory 1152 is not required.

[0109] Next, an example of a predetermined pixel signal that is applied to all pixels Pix during the first period P1 in the embodiment will be described with reference to FIG.

[0110] FIG. 14 is a table showing the response time of a pixel Pix determined by the relationship between the gradation value indicated by the pixel signal before update and the gradation value indicated by the pixel signal after update. In FIG. 14, "start gradation" indicates the gradation value indicated by the pixel signal before update. Also, "end gradation" indicates the gradation value indicated by the pixel signal after update. The level of luminance of the pixel Pix corresponds to the level of gradation value indicated by the pixel signal. Therefore, the level relationship between the "start gradation" and the "end gradation" corresponds to the level of luminance of the pixel Pix before and after the update described above. Note that in the explanations with reference to FIGS. 14 to 21, the pixel signal is an 8-bit signal and the gradation value is any value within the range of 0 to 255, but this is merely an example and the number of bits of the pixel signal in the embodiment is not limited to this.

[0111] The table in FIG. 14 shows the response time of pixel Pix, where the value at the intersection of the "start gradation" and "end gradation" is determined by the relationship between the gradation value indicated by the pixel signal before update and the gradation value indicated by the pixel signal after update. For example, if the "start gradation" is "0" and the "end gradation" is "255," the value at the intersection of the "start gradation" and "end gradation" is 3.2. This indicates that when the gradation value indicated by the pixel signal before update is "0" and the gradation value indicated by the pixel signal after update is "255," the response time of pixel Pix is ​​3.2 milliseconds (ms). The same interpretation can be used for the other values ​​at the intersection of the "start gradation" and "end gradation."

[0112] In this embodiment, a pixel signal indicating a gradation value of "255," for example, is adopted as the predetermined pixel signal provided to all pixels Pix during the first period P1. Therefore, at the time of the second period P2, pixel signals indicating a gradation value of "255" have already been supplied to all pixels Pix. Therefore, the pixel signal before the update relative to the updated pixel signal supplied during the second period P2 is a pixel signal indicating a gradation value of "255." Therefore, in this example, it is sufficient to consider the response time of the pixel Pix represented within the attention range TAR in FIG. 14, whose "start gradation" is "255." Note that a gradation value of 255 in an 8-bit pixel signal is synonymous with the pixel Pix receiving the pixel signal being driven at maximum brightness. Therefore, adopting a pixel signal indicating a gradation value of "255" as the predetermined pixel signal is synonymous with the pixel Pix being driven at maximum brightness before the pixel signal is updated.

[0113] FIG. 15 is a graph showing an example of the gradation values ​​indicated by the updated pixel signal when overdrive is applied and the pixel Pix is ​​driven at maximum luminance before the pixel signal is updated. The "target gradation" in FIG. 15 and in FIGS. 16, 20, 21, 23, and 26 (described later) indicates the gradation value to be reflected in the pixel Pix during the fourth period P4. That is, the "target gradation" corresponds to "100%" of the "relative luminance" in FIGS. 10 to 12. The luminance LU2 in FIGS. 11 and 12 corresponds to the "target gradation." The "write gradation" indicates the gradation value indicated by the pixel signal actually applied to the pixel Pix during the fourth period P4 by overdrive to set the pixel Pix to the "target gradation." The luminances LU21 and LU22 in FIGS. 11 and 12 correspond to the "target gradation."

[0114] As described as an example with reference to Fig. 14, in the embodiment, for example, a pixel signal indicating a gradation value of "255" is adopted as the predetermined pixel signal. The predetermined gradation value BE1 in Fig. 15 and Fig. 16 is given for the purpose of indicating the gradation value of "255" as the predetermined pixel signal.

[0115] First, if the pixel Pix responds quickly enough without applying overdrive, the "target gradation" and the "writing gradation" can be the same. Therefore, in this case, the relationship between the "target gradation" and the "writing gradation" is as shown in graph LC71 in FIG.

[0116] On the other hand, in overdrive when a pixel signal indicating a gradation value of "255" is used as the predetermined pixel signal, the pixel Pix is ​​driven to its maximum brightness during the first period P1. Therefore, the pixel signal supplied during the second period P2 becomes a pixel signal that drives the pixel Pix to exhibit a luminance equal to or lower than that before the update. Therefore, in this case, overdrive is applied so that the "write gradation" is equal to or lower than the "target gradation," as shown in the relationship between luminance LU2 and luminance LU22 in FIG. 11. Specifically, as shown in graph LC75 in FIG. 15, the pixel signal after update is determined so that the "write gradation" is lower than the "target gradation," excluding the gradation values ​​of "0" and "255."

[0117] As described with reference to FIG. 8, during scanning, the timing at which a pixel signal is supplied to the pixel Pix and the second response time T2 differ for each pixel row. Therefore, by applying an overdrive corresponding to the second response time T2 for each pixel row, the brightness of the pixel Pix can be controlled with higher precision than by applying the same overdrive to all pixel rows. Therefore, in the embodiment, a mechanism is provided for individually adjusting the relationship between the "target grayscale" and the "write grayscale" for each pixel row. This mechanism will be described with reference to FIGS. 16 to 19.

[0118] 16 is a graph showing five lookup tables used as standards for applying overdrive in relation to "target gradation" and "write gradation." Hereinafter, when we refer to "LUT of pixel signal supplied to pixel Pix," we mean the LUT that is referenced to derive "write gradation" from "target gradation" when applying overdrive to the pixel signal supplied to pixel Pix during the second period P2.

[0119] FIG. 16 shows graphs LC71, LC72, LC73, LC74, and LC75. Graph LC71 shows the relationship between the "target gradation" and the "write gradation" associated by the LUT of pixel signals supplied to pixels Pix included in pixel rows sharing the scan line G1. Graph LC72 shows the relationship between the "target gradation" and the "write gradation" associated by the LUT of pixel signals supplied to pixels Pix included in pixel rows sharing the scan line GB. Graph LC73 shows the relationship between the "target gradation" and the "write gradation" associated by the LUT of pixel signals supplied to pixels Pix included in pixel rows sharing the scan line GC. Graph LC74 shows the relationship between the "target gradation" and the "write gradation" associated by the LUT of pixel signals supplied to pixels Pix included in pixel rows sharing the scan line GD. Graph LC75 shows the relationship between the "target gradation" and the "write gradation" associated by the LUT of pixel signals supplied to pixels Pix included in pixel rows sharing the scan line GE.

[0120] In this manner, in the embodiment, overdrive is applied to pixel rows having shorter second response times T2 described with reference to Fig. 8, which causes the "writing grayscale" to fall below the "target grayscale" to a greater extent. In the example shown in Fig. 16, for a total of five scanning lines GL, namely scanning lines G1, GB, GC, GD, and GE, the "writing grayscale" can be derived from the "target grayscale" by directly referencing the corresponding LUT.

[0121] Here, the difference between the gradation value of a predetermined pixel signal, "255," and the gradation value of the "target gradation" is defined as the first difference. Furthermore, the difference between the gradation value of a predetermined pixel signal, "255," and the gradation value of the "write gradation" is defined as the second difference. Based on this premise, we will focus on the relationship between the first difference and the second difference for each of graphs LC71, LU72, LU73, LU74, and LU75. However, we will exclude the portions where the "target gradation" is "0" or "255."

[0122] First, in graph LC71, where overdrive is not substantially applied, the first difference and the second difference are equal. In contrast, in graphs LC72, LU73, LU74, and LU75, where overdrive is applied, the second difference is larger than the first difference. Here, the gradation value of the "target gradation" is the gradation value of pixel data included in image data, such as pixel data PixD (see Figures 18 and 19). Therefore, overdrive can be said to be a process in which, using "the difference between the gradation value indicated by pixel data included in image data and a predetermined gradation value determined by a reset signal," such as the first difference, as a reference, a gradation value whose difference from the predetermined gradation value is greater than the reference is treated as a "write gradation," and a pixel signal corresponding to the "write gradation" is generated.

[0123] Furthermore, in graph LC75, the magnitude of the second difference relative to the first difference is larger than those of graphs LC72, LU73, and LU74. In addition, in graph LC74, the magnitude of the second difference relative to the first difference is larger than those of graphs LC72 and LU73. In addition, in graph LC73, the magnitude of the second difference relative to the first difference is larger than those of graph LC72. Such relative relationships of the magnitude of the second differences correspond to delays in the supply timing of gate signals during the second period P2 to the scanning lines GL to which graphs LC72, LU73, LU74, and LU75 are respectively applied. The scanning line GL corresponding to graph LC75 is the scanning line GE. The scanning line GL corresponding to graph LC74 is the scanning line GD. The scanning line GL corresponding to graph LC73 is the scanning line GC. The scanning line GL corresponding to graph LC72 is the scanning line GB. The scanning line GL corresponding to graph LC71 is the scanning line G1. The timing of supplying the gate signal to the scanning line GE during the second period P2 is later than that to the scanning lines GD, GC, GB, and G1. The timing of supplying the gate signal to the scanning line GD during the second period P2 is later than that to the scanning lines GC, GB, and G1. The timing of supplying the gate signal to the scanning line GC during the second period P2 is later than that to the scanning lines GB and G1. The timing of supplying the gate signal to the scanning line GB during the second period P2 is later than that to G1. In this way, the second difference, such as "the magnitude of the difference between the gradation value of the pixel signal generated by overdrive and the predetermined gradation value by the reset signal," is larger for pixel signals supplied to pixels Pix connected to scanning lines GL that have a later timing of supplying the gate signal in the scan.

[0124] Moreover, graphs LC72, LU73, LU74, and LU75 show the relationship between the gradation value (target gradation) indicated by the pixel data and the gradation value (written gradation) of the pixel signal when overdrive is applied.

[0125] Note that pixel signals supplied to pixels Pix included in pixel rows that share a scanning line GL for which no directly corresponding LUT is provided are derived by interpolation processing. Interpolation processing refers to a process of deriving a "write gradation" from a "target gradation" and generating a pixel signal by referencing the LUTs that directly correspond to two scanning lines GL that are arranged closer to the scanning line GL for which no directly corresponding LUT is provided, among the scanning lines GL for which a directly corresponding LUT is provided.

[0126] Hereinafter, the driver IC 115 having a mechanism for generating pixel signals to which overdrive has been applied based on input image data, including interpolation processing, will be described with reference to FIGS.

[0127] Fig. 17 is a block diagram showing the input / output of the driver IC 115 and the main functional configuration included in the driver IC 115. As shown in Fig. 17, the driver IC 115 has an I / F circuit 115a, a row counter 115b, a gradation correction circuit 115c, a DAC 115d, and a timing controller 115e. I / F stands for interface. DAC stands for digital-to-analog converter.

[0128] In response to input of image data DP3, the I / F circuit 115a generates pixel data PixD, a row count signal, and an operation control signal for the timing controller. The pixel data PixD is pixel data included in the image data DP3. The image data includes multiple pixel data corresponding to a matrix arrangement. A display output from the display panel 110 is achieved by assigning pixel signals corresponding to each of the multiple pixel data to different pixels Pix. The gradation value indicated by the pixel data PixD indicates the gradation value as the "target gradation." The row count signal is a signal for identifying the pixel row of the pixel Pix that is the target of the pixel data PixD. The row count signal is output each time the pixel row of the pixel Pix that is the target of the pixel data PixD changes. The operation control signal for the timing controller is a signal for synchronization control between the signal line connection circuit 113 and the scanning line drive circuit 114 by the timing controller 115e.

[0129] The row counter 115b counts the row count signal and outputs a row number NL. The row number NL indicates the scanning line GL to which the pixel Pix to which the pixel data PixD is assigned is connected. That is, the row number NL identifies which scanning line GL the pixel row including the pixel Pix belongs to.

[0130] For example, when the row count signal is provided to the row counter 115b only once, the value of the row number NL is 1. The row number NL having a value of 1 means that the scanning line GL to which the pixel Pix to which the pixel data PixD is assigned is connected is the scanning line G1 shown in FIGS. 7 and 8. Here, assuming that the number of scanning lines GL is Nv as shown in FIG. 7, when the row count signal has been provided to the row counter 115b Nv times, the value of the row number NL becomes Nv, and the scanning line GL to which the pixel Pix to which the pixel data PixD is assigned is identified as the scanning line GE shown in FIGS. 7 and 8. Similarly, when the row count signal has been provided to the row counter 115b (¼Nv) times, the value of the row number NL becomes (¼Nv), and the scanning line GL to which the pixel Pix to which the pixel data PixD is assigned is identified as the scanning line GB shown in FIGS. 7 and 8. Furthermore, when the row count signal has been provided to the row counter 115b (1 / 2Nv) times, the value of the row number NL becomes (1 / 2Nv), and the scanning line GL to which the pixel Pix to which the pixel data PixD is assigned is connected is identified as the scanning line GC shown in Figures 7 and 8. Furthermore, when the row count signal has been provided to the row counter 115b (3 / 4Nv) times, the value of the row number NL becomes (3 / 4Nv), and the scanning line GL to which the pixel Pix to which the pixel data PixD is assigned is connected is identified as the scanning line GD shown in Figures 7 and 8.

[0131] Note that if a row count signal is further provided to the row counter 115b after the value of the row number NL has reached Nv, this indicates that one frame period has ended and the next frame period has begun. In this case, the value of the row number NL is reset to the initial value STA. The initial value STA shown in FIG. 7 indicates a value of 1.

[0132] The gradation correction circuit 115c generates a pixel signal Ot based on the pixel data PixD and the row number NL. A more specific configuration of the gradation correction circuit 115c will be described with reference to FIGS.

[0133] Fig. 18 is a block diagram showing the main functional configuration of the gradation correction circuit 115c. Fig. 19 is a block diagram showing the processing contents performed by each component of the gradation correction circuit 115c shown in Fig. 18. The gradation correction circuit 115c has a first calculation unit 115p, an LUT reference unit 115q, and a second calculation unit 115r.

[0134] The first calculation unit 115p calculates lutl according to the following formula (1). As described above, Nv in formula (1) is the number of scanning lines GL. The minimum value of lutl calculated by formula (1) is lutl=1 when NL=1. The maximum value of lutl calculated by formula (1) is lutl=1+{4×(Nv-1) / Nv} when NL=Nv, which is greater than or equal to 4 and less than 5. lutl=1+{4×(NL-1) / Nv}···(1)

[0135] Furthermore, the first calculation unit 115p calculates i according to the following formula (2). floor() in formula (2) indicates an operation to round down the decimal point of the value in parentheses. As described above, since lutl that can be calculated by formula (1) is greater than or equal to 1 and less than 5, the value of i calculated by formula (2) is either 1, 2, 3, or 4. i=floor(lutl) (2)

[0136] Furthermore, the first calculation unit 115p calculates di according to the following formula (3). di is a value greater than or equal to 0 and less than 1. If lutl is a natural number, lutl=i holds, and di=0. If lutl is not a natural number, di is a value greater than 0 and less than 1. di=lutl-i···(3)

[0137] The first calculation unit 115p outputs information indicating the value of i calculated via equations (1) and (2) and information indicating the value (i+1) obtained by adding 1 to the i to the LUT reference unit 115q. The first calculation unit 115p also outputs information indicating the value of di calculated via equations (1), (2), and (3) to the second calculation unit 115r.

[0138] The LUT reference unit 115q holds multiple lookup tables. The LUT reference unit 115q shown in FIG. 19 holds five lookup tables: lookup tables LUT1, LUT2, LUT3, LUT4, and LUT5. The lookup table LUT1 is a LUT that indicates the relationship between a "target gradation" and a "writing gradation," as represented, for example, by the graph LC71 described with reference to FIG. 16. That is, the lookup table LUT1 is a LUT for pixel signals supplied to pixels Pix included in pixel rows that share the scanning line G1. The lookup table LUT2 is a LUT that indicates the relationship between a "target gradation" and a "writing gradation," as represented, for example, by the graph LC72 described with reference to FIG. 16. That is, the lookup table LUT2 is a LUT for pixel signals supplied to pixels Pix included in pixel rows that share the scanning line GB. The lookup table LUT3 is a LUT that indicates the relationship between a "target gradation" and a "writing gradation," as represented, for example, by the graph LC73 described with reference to FIG. 16. That is, the lookup table LUT3 is a LUT for pixel signals supplied to pixels Pix included in pixel rows that share the scanning line GC. The lookup table LUT4 is a LUT that shows the relationship between a "target gradation" and a "writing gradation," which can be expressed, for example, as the graph LC74 described with reference to FIG. 16. That is, the lookup table LUT4 is a LUT for pixel signals supplied to pixels Pix included in pixel rows that share the scanning line GD. The lookup table LUT5 is a LUT that shows the relationship between a "target gradation" and a "writing gradation," which can be expressed, for example, as the graph LC75 described with reference to FIG. 16. That is, the lookup table LUT5 is a LUT for pixel signals supplied to pixels Pix included in pixel rows that share the scanning line GE.

[0139] The LUT reference unit 115q references the lookup table (LUTi) corresponding to the value of i and the lookup table (LUTi+1) corresponding to the value of (i+1) among the multiple lookup tables it holds. For example, when i=1, the lookup table corresponding to the value of i is the lookup table LUT1. In this case, the lookup table corresponding to the value of (i+1) is the lookup table LUT2.

[0140] The LUT reference unit 115q identifies a "writing gradation" when the gradation value indicated by the pixel data PixD is set as the "target gradation" in the lookup table (LUTi) corresponding to the value of i, and sets the value of the identified "writing gradation" as the first candidate Ot1. Also, the LUT reference unit 115q identifies a "writing gradation" when the gradation value indicated by the pixel data PixD is set as the "target gradation" in the lookup table (LUTi+1) corresponding to the value of (i+1), and sets the value of the identified "writing gradation" as the second candidate Ot2. The LUT reference unit 115q outputs information indicating the first candidate Ot1 and information indicating the second candidate Ot2 to the second calculation unit 115r.

[0141] The second calculation unit 115r calculates the pixel signal Ot based on the following equation (4): The pixel signal Ot is a value that reflects the value of the "write gradation" of the overdrive for the pixel Pix included in the pixel row that shares the scanning line GL in the arrangement indicated by the value of the row number NL and in the arrangement to which the pixel data PixD is given. Ot={Ot1×(1-di)}+Ot2×di···(4)

[0142] Note that when di is 0, the "Ot2 × di" component on the right side of equation (4) becomes 0, and the calculation is performed using only the "Ot1 × (1-di)" component. Therefore, in this case, interpolation processing is not performed in effect, and the value of the pixel signal Ot reflects the "written gradation" when the gradation value indicated by the pixel data PixD is set as the "target gradation" in the lookup table (LUTi) corresponding to the value of i.

[0143] On the other hand, when di is not 0, the value of the pixel signal Ot reflects the components "Ot2 × di" and "Ot1 × (1 - di)." That is, in this case, the value of the pixel signal Ot is a value derived by interpolation based on both the "writing gradation" derived from the lookup table (LUTi) corresponding to the value of i and the "writing gradation" derived from the lookup table (LUTi+1) corresponding to the value of (i+1).

[0144] 17, the gradation correction circuit 115c outputs the generated pixel signal Ot to the DAC 115d. The DAC 115d generates an analog electrical signal corresponding to the value indicated by the pixel signal Ot and outputs it to the signal line connection circuit 113. A signal corresponding to the analog electrical signal is provided to the signal line SL from the signal line connection circuit 113 and functions as a pixel signal output during the second period P2. This pixel signal is a pixel signal that reflects the value of the "write gradation" of the overdrive.

[0145] In response to a timing controller operation control signal provided from the I / F circuit 115a, the timing controller 115e controls the operation of the signal line connection circuit 113 and the operation of the scanning line drive circuit 114 so as to synchronize the timing at which a pixel signal corresponding to pixel data PixD is supplied to the signal line SL with the timing at which a gate signal is supplied to the scanning line GL of the row number NL corresponding to the pixel data PixD, thereby enabling the pixel Pix to be driven by a pixel signal to which overdrive has been applied.

[0146] 17 to 19, the driver IC 115 holds a lookup table (e.g., lookup tables LUT2, LUT3, LUT4, LUT5, etc.) that indicates the relationship between the gradation value (target gradation) indicated by pixel data and the gradation value (write gradation) of the pixel signal when overdrive is applied, and generates a pixel signal to be supplied to the pixel to which overdrive is applied by referring to the lookup table. The driver IC 115 also holds a plurality of lookup tables (e.g., lookup tables LUT2, LUT3, LUT4, LUT5, etc.), each of which corresponds to a plurality of scanning lines (e.g., scanning lines GB, GC, GD, GE) that have different gate signal supply timings during scanning.

[0147] In the above explanation with reference to Figures 16 to 19, it has been assumed that the graphs LC71, LC72, LC73, LC74, and LC75 shown in Figure 16 correspond to the lookup tables LUT1, LUT2, LUT3, LUT4, and LUT5 shown in Figure 19. That is, the lookup tables LUT1, LUT2, LUT3, LUT4, and LUT5 in the explanation were based on the assumption that a pixel signal indicating a gradation value of "255" was adopted as the predetermined pixel signal. However, the predetermined pixel signal that can be adopted in the embodiments is not limited to a pixel signal indicating a gradation value of "255."

[0148] Fig. 20 is a graph showing an example of the gradation value indicated by the updated pixel signal when overdrive is applied and the pixel Pix is ​​driven at the lowest luminance before updating the pixel signal. That is, Fig. 20 shows a case where a pixel signal indicating the lowest gradation value (0) is adopted as the predetermined pixel signal. In the example shown in Fig. 20, a pixel signal indicating a gradation value of "0" is adopted as the predetermined pixel signal. The predetermined gradation value BE2 in Fig. 20 is added for the purpose of indicating a gradation value of "0" as the predetermined pixel signal.

[0149] First, if the pixel Pix responds quickly enough without applying overdrive, the "target gradation" and the "writing gradation" can be the same. Therefore, in this case, the relationship between the "target gradation" and the "writing gradation" is as shown in graph LC81 in FIG.

[0150] On the other hand, when a pixel signal indicating a gradation value of "0" is used as the predetermined pixel signal, overdrive drives the pixel Pix to its minimum luminance during the first period P1. Therefore, the pixel signal supplied during the second period P2 drives the pixel Pix to achieve a luminance equal to or greater than the pre-update luminance. Therefore, overdrive in this case is applied so that the "write gradation" is equal to or greater than the "target gradation," as shown in the relationship between luminance LU2 and luminance LU21 in FIG. 11 . Specifically, as shown in graph LC85 in FIG. 20 , the updated pixel signal is determined so that the "write gradation" exceeds the "target gradation," excluding the gradation values ​​of "0" and "255." Setting the predetermined reset gradation value shown in FIG. 20 to 0 or a gradation value close to 0 ensures that the liquid crystal reaches the intended minimum transmittance at gradation 0 within the limited response time T2. Because gradation value 0 cannot be set lower by overdrive to shorten the response time, the example shown in FIG. 20 is a suitable example for easily achieving higher contrast. Here, a gradation value of "0" can be said to be the gradation value at which the degree of light transmittance of a pixel (e.g., pixel PixR, pixel PixG, pixel PixB) to which a pixel signal corresponding to that gradation value is applied is lowest. If the lowest degree of light transmittance is 0% and the highest degree of light transmittance is 100%, setting a gradation value at which the degree of light transmittance of the pixel is lower than 10% as a predetermined gradation value makes it easier to ensure pixel response. This is because pixel response time tends to be logarithmic with respect to changes in transmittance. Generally, the contrast of an LCD display is about 1000:1, and the degree of light transmittance of a pixel with the lowest transmittance is about 0.1%. Here, the time required for the degree of light transmittance to transition between 0.1% and 1%, the time required for the transition between 1% and 10%, and the time required for the transition between 10% and 100% are all approximately the same. Among these, the time it takes to transition to 0.1% is more important from the perspective of ensuring the contrast of the LCD display. Therefore, by setting the gradation value at which the degree of light transmission through the pixel falls below 10% as the specified gradation value, it can be said that it is easier to guarantee the pixel's response.

[0151] Fig. 21 is a graph showing an example of the gradation value indicated by the updated pixel signal when overdrive is applied and the pixel Pix is ​​driven at an intermediate gradation between the minimum and maximum luminance before updating the pixel signal. Fig. 21 shows a case where a pixel signal indicating a value of "127" in an 8-bit signal with a maximum value of 255 is used as the predetermined pixel signal. The predetermined gradation value BE3 in Fig. 21 is given for the purpose of indicating the gradation value as the predetermined pixel signal.

[0152] First, if the pixel Pix responds quickly enough without applying overdrive, the "target gradation" and the "writing gradation" can be the same. Therefore, in this case, the relationship between the "target gradation" and the "writing gradation" is as shown in graph LC91 in FIG.

[0153] On the other hand, in overdrive when a pixel signal indicating a gradation value of "127" is used as the predetermined pixel signal, the pixel Pix is ​​driven to a luminance corresponding to an intermediate gradation during the first period P1. Therefore, the relationship between the "target gradation" and the "write gradation" of the pixel signal supplied during the second period P2 changes depending on whether the pixel data PixD exceeds or falls below the gradation value of "127." When the pixel data PixD exceeds the gradation value of "127," the pixel signal supplied during the second period P2 in accordance with the pixel data PixD drives the pixel Pix to exhibit a luminance higher than that before the update. When the pixel data PixD falls below the gradation value of "127," the pixel signal supplied during the second period P2 in accordance with the pixel data PixD drives the pixel Pix to exhibit a luminance lower than that before the update. Note that when the pixel data PixD has a gradation value of "127," there is no need to apply overdrive in the first place. Therefore, when the pixel data PixD has a gradation value of "127," the pixel signal becomes a pixel signal corresponding to the gradation value of "127." Therefore, in this case, overdrive is applied so that the "writing gradation" is equal to or less than the "target gradation" when the "target gradation" is equal to or less than "127," as shown in the relationship between luminance LU2 and luminance LU22 in FIG. 11, and so that the "writing gradation" is equal to or greater than the "target gradation" when the "target gradation" is equal to or greater than "127," as shown in the relationship between luminance LU2 and luminance LU21 in FIG. 11. Specifically, the updated pixel signal is determined, for example, as shown in graph LC95 in FIG. 21.

[0154] 20 and 21 show only one type of graph corresponding to the application of overdrive, but even when the predetermined pixel signal described with reference to FIGS. 20 and 21 is used, as described with reference to FIGS. 16 to 19, overdrive may be applied according to the second response time T2 for each pixel row, taking into account that the timing at which the pixel signal is supplied to the pixel Pix during scanning and the second response time T2 differ for each pixel row. In other words, the lookup tables LUT1, LUT2, LUT3, LUT4, and LUT5 described with reference to FIG. 19 may be any as long as they correspond to the predetermined pixel signal. Below, a more detailed example of the case where a pixel signal indicating a gradation value of "0" is used as the predetermined pixel signal, as shown in FIG. 20, will be described with reference to FIGS. 22 to 27.

[0155] Fig. 22 is a diagram showing an example of the contents of each of the lookup tables LUT1, LUT2, LUT3, LUT4, and LUT5 when a pixel signal indicating a gradation value of "0" is used as the predetermined pixel signal. "L in" in Fig. 22 and Fig. 27 corresponds to the "target gradation." "L out" in Fig. 22 and Fig. 27 corresponds to the "write gradation" of each of the lookup tables LUT1, LUT2, LUT3, LUT4, and LUT5.

[0156] Fig. 23 is a graph showing the lookup tables LUT1, LUT2, LUT3, LUT4, and LUT5 shown in Fig. 22. The lookup table LUT1 shown in Fig. 22 is graphed as graph LC101 shown in Fig. 23. The lookup table LUT2 shown in Fig. 22 is graphed as graph LC102 shown in Fig. 23. The lookup table LUT3 shown in Fig. 22 is graphed as graph LC103 shown in Fig. 23. The lookup table LUT4 shown in Fig. 22 is graphed as graph LC104 shown in Fig. 23. The lookup table LUT5 shown in Fig. 22 is graphed as graph LC105 shown in Fig. 23.

[0157] In the examples shown in FIGS. 22 and 23, unlike the example described with reference to FIG. 16, the number of bits of the "writing gradation" is expanded beyond the number of bits of the "target gradation". Specifically, in the examples shown in FIGS. 22 and 23, the number of bits of the "writing gradation" is 10 bits, and takes any value within a range from 0 to 1023. Note that the number of bits of the "target gradation" in the examples shown in FIGS. 22 and 23 is 8 bits, similar to the example described with reference to FIG. 16. That is, in the examples shown in FIGS. 22 and 23, the number of bits is expanded when applying overdrive to derive the "writing gradation" from the "target gradation". Hereinafter, when the term "expansion of the number of bits" is used, it refers to expanding the number of bits of the "writing gradation" beyond the number of bits of the "target gradation".

[0158] FIG. 24 is a diagram illustrating "L out" within a range where "L in" is 245 or greater when no bit extension is performed. As shown in FIG. 24, when no bit extension is performed, the application of overdrive may eliminate the apparent difference in gradation values. For example, in the example shown in FIG. 24, in the lookup table LUT5, "L out" within the range where "L in" is 245 to 247 is unified to "253." In addition, in the lookup table LUT5, "L out" within the range where "L in" is 248 to 251 is unified to "254." In addition, in the lookup table LUT5, "L out" within the range where "L in" is 252 to 255 is unified to "255." Such unified "L out" values ​​may cause gradation collapse in the display output image if a response delay or the like described with reference to FIG. 12 occurs. In the example shown in FIG. 24, the lookup tables LUT2, LUT3, and LUT4 other than the lookup table LUT5 also have unification of "L out", although this is not as pronounced as in the lookup table LUT5.

[0159] Fig. 25 is a diagram showing "L out" within a range where "L in" is equal to or greater than 245 when the number of bits is expanded. As shown in Figs. 22, 23, and 25, expanding the number of bits can prevent "L out" from becoming unified in each lookup table. In other words, expanding the number of bits can more easily prevent the apparent gradation values ​​from becoming unified as described with reference to Fig. 24, and the possibility of gradation collapse due to such unification.

[0160] In the examples shown in Figures 22, 23, and 25, the occurrence of unification of "L out" has already been suppressed, but if the occurrence of unification of "L out" occurs even after expanding the number of bits, it is possible to intentionally shift the relationship between "L in" and "L out" slightly to suppress the unification of "L out", giving priority to the application of the "write gradation" to the "target gradation" that is ideal as overdrive.

[0161] Fig. 26 is a graph showing a lookup table that reflects the "writing grayscale" relative to the ideal "target grayscale" as an overdrive, and a lookup table that prioritizes suppressing uniformity of "L out." Lookup table LUB shown in Fig. 26 shows a lookup table that reflects the "writing grayscale" relative to the ideal "target grayscale" as an overdrive. Also, lookup table LUA shows a lookup table that prioritizes suppressing uniformity of "L out."

[0162] FIG. 27 shows the relationship between "L in" and "L out" in the lookup tables LUA and LUB shown in FIG. 26, showing "L out" within a range where "L in" is 240 or greater. As shown in FIG. 27, in lookup table LUB, "L out" within a range where "L in" is 240 or 241 is unified to "1020." Also, in lookup table LUB, "L out" within a range where "L in" is 242 to 245 is unified to "1021." Also, in lookup table LUB, "L out" within a range where "L in" is 246 to 254 is unified to "1022." Instead of such a lookup table LUB, a lookup table in which "L out" values ​​do not intentionally overlap, such as lookup table LUB, may be employed. This makes it possible to more reliably unify the apparent gradation values ​​and prevent the possibility of gradation collapse due to such unification, as described with reference to FIG. 24.

[0163] In the LUTs described with reference to Figures 22, 23, 25, 26, and 27, the number of bits of the gradation value (L_out) of a pixel signal is greater than the number of bits of the gradation value (L_in) indicated by the pixel data. Furthermore, the gradation value (L_out) of a pixel signal in the LUTs described with reference to Figures 22, 23, and 27 differs when the gradation value (L_in) indicated by the pixel data differs.

[0164] As described above, according to the embodiment, the pixel circuit includes pixels (pixels Pix including pixels PixR, PixG, and PixB), scanning lines (scanning lines GL) connected to a plurality of pixels arranged along a first direction (X direction), signal lines (signal lines SL) connected to a plurality of pixels arranged along a second direction (Y direction) intersecting the first direction, a first circuit (scanning line driving circuit 114) that supplies gate signals to the plurality of scanning lines, a second circuit (signal line connecting circuit 113) that supplies pixel signals to the plurality of signal lines, and a third circuit (driver IC 115) that generates pixel signals according to image data. The pixel signals are supplied to the pixels in accordance with the drive timing of switching elements (switching elements TrD1, TrD2, and TrD3) that are driven in accordance with the gate signals, and are reset by a reset signal corresponding to a predetermined gradation value before the pixel signals are supplied. The first circuit performs scanning by varying the supply timing of the gate signals for each of the plurality of scanning lines when the pixel signals are supplied to the pixels. The third circuit applies overdrive to some or all of the pixels. Overdrive is a process that uses the difference between a gradation value indicated by pixel data included in image data and a predetermined gradation value as a reference and generates a pixel signal corresponding to a gradation value whose difference from the predetermined gradation value is greater than the reference value. The magnitude of the difference between the gradation value of a pixel signal generated by overdrive and the predetermined gradation value is greater for pixel signals supplied to pixels connected to scanning lines whose gate signal is supplied later in the scan.

[0165] This eliminates the need for a configuration such as the single-screen frame memory 1152 described with reference to Fig. 13, allowing overdrive to be achieved at lower cost. Also, by resetting each pixel with a reset signal before supplying a pixel signal to each pixel for display output corresponding to image data, the "previous pixel information (grayscale value)" required for generating a pixel signal for applying overdrive can be unified to the grayscale value of the reset signal. Therefore, overdrive can be applied with a simpler mechanism than the complex mechanism in which the "previous pixel information (grayscale value)" fluctuates depending on the previous image.

[0166] In addition, the third circuit (driver IC 115) holds a lookup table (e.g., lookup tables LUT2, LUT3, LUT4, LUT5, etc.) that shows the relationship between the gradation value indicated by the pixel data and the gradation value of the pixel signal when overdrive is applied, and generates a pixel signal to be supplied to the pixel to which overdrive is applied by referring to the lookup table, thereby enabling overdrive to be applied using a simpler mechanism.

[0167] Furthermore, the third circuit (driver IC 115) holds multiple lookup tables (e.g., lookup tables LUT2, LUT3, LUT4, LUT5, etc.), and each of the multiple lookup tables corresponds to each of multiple scanning lines (e.g., scanning lines GB, GC, GD, GE) that have different gate signal supply timings during scanning, thereby achieving more accurate overdrive according to the gate signal supply timing during scanning.

[0168] Furthermore, as described with reference to FIG. 22 and other figures, by making the number of bits of the gradation value of the pixel signal in the lookup table larger than the number of bits of the gradation value indicated by the pixel data, it becomes easier to suppress gradation collapse.

[0169] Furthermore, as described with reference to FIGS. 22 and 27, the gradation values ​​of pixel signals in the lookup table are different when the gradation values ​​indicated by the pixel data are different, thereby more reliably suppressing gradation collapse.

[0170] Furthermore, in an HMD intended for displaying and outputting VR images as in the embodiment, there is a tendency for a faster response to be required in the display area 111. In response to this tendency, according to the embodiment, by applying overdrive, it is possible to achieve a high-speed response at a level that is sufficient to meet the requirement.

[0171] Furthermore, when resetting with the highest grayscale (e.g., 255) as described with reference to FIG. 16, even if a response delay occurs as described with reference to FIG. 12, all pixels will uniformly output a grayscale value higher than the intended grayscale value. When resetting with the lowest grayscale (e.g., 0) as described with reference to FIG. 20, even if a response delay occurs as described with reference to FIG. 12, all pixels will uniformly output a grayscale value lower than the intended grayscale value. Even when resetting with an intermediate grayscale as shown in FIG. 21, when comparing a grayscale brighter than the reset grayscale with a grayscale darker than the reset grayscale, the grayscale difference due to overdrive is in the opposite direction (brighter than the reset grayscale, and darker than the reset grayscale). Therefore, even if a response delay or advance occurs, there is no mixture of brightness differences due to overdrive in different directions, and brightness variations can be suppressed. FIG. 28 is a graph showing an example of a response when resetting with an intermediate grayscale. Pattern 1 shows an example where the response arrives in time for the fourth period P4. Pattern 2 shows an example where the response arrives too late for the fourth period P4. As shown in pattern 2, even if a delay or advance in response occurs, a mixture of brightness differences due to overdrive in different directions does not occur.

[0172] The number of lookup tables referenced for overdrive is not limited to five as shown in Fig. 19 etc., but may be two or more. The value "4" in equation (1) is the value obtained by subtracting 1 from the value (5) indicating the total number of LUTs, namely, five lookup tables LUT1, LUT2, LUT3, LUT4, and LUT5. Therefore, if the number of LUTs used is n, then "4" in equation (1) should be replaced with (n-1).

[0173] Furthermore, two or more of the first, second, and third circuits may be packaged together. For example, a circuit that integrates the functions of two or more of the signal line connection circuit 113, the scanning line driving circuit 114, and the driver IC 115 may be employed. In other words, it is not essential that the first, second, and third circuits are physically independent from each other.

[0174] Although the embodiment is directed to an HMD for VR images, the use of the display device according to the present disclosure is not limited to this. For example, the display device may be a display device that displays and outputs a single image using a single display panel 110.

[0175] Furthermore, which pixel row the pixels Pix in which overdrive is applied can be changed as appropriate depending on various factors such as the required response speed and the response characteristics of the display panel. For example, the LUT may be defined to apply overdrive to all pixels Pix including scan line G1. Conversely, if the response is sufficient without applying overdrive up to scan lines GB and GC, overdrive may be applied to pixels Pix on and after scan line GC. In either case, with overdrive, the pixel signal supplied to a pixel Pix connected to a scan line GL whose gate signal is supplied later in the scanning process tends to have a larger second difference than the first difference.

[0176] Furthermore, other effects and advantages brought about by the aspects described in this embodiment that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present disclosure. [Explanation of symbols]

[0177] 100 display device 110 Display panel 113 Signal line connection circuit 114 Scanning line driving circuit 115 Driver IC G1, G2, G3, GB, GC, GD, GE, GL scan lines LUT1, LUT2, LUT3, LUT4, LUT5 lookup tables Pix, PixB, PixG, PixR pixels SL signal line

Claims

1. Pixels and a scanning line connected to a plurality of the pixels arranged along a first direction; signal lines connected to a plurality of the pixels arranged along a second direction intersecting the first direction; a first circuit for supplying gate signals to the plurality of scan lines; a second circuit that supplies pixel signals to the plurality of signal lines; a third circuit that generates the pixel signal according to image data; The pixel is the pixel signal is supplied in accordance with a drive timing of a switching element that is driven in accordance with the gate signal; Before the pixel signal is supplied, the pixel is reset by a reset signal corresponding to a predetermined gradation value, the first circuit performs scanning to make different supply timings of the gate signals for each of the plurality of scanning lines when the pixel signals are supplied to the pixels; the third circuit applies overdrive to some or all of the pixels; the overdrive is a process of generating the pixel signal corresponding to a gradation value whose difference from the predetermined gradation value is greater than the reference gradation value indicated by pixel data included in the image data, using the reference gradation value as a difference between the predetermined gradation value and the gradation value indicated by pixel data included in the image data; a difference between the gradation value of the pixel signal generated by the overdrive and the predetermined gradation value is larger for the pixel signal supplied to the pixel connected to the scanning line whose timing of supplying the gate signal in the scanning is later; Display device.

2. The third circuit is a lookup table indicating a relationship between a gradation value indicated by the pixel data and a gradation value of the pixel signal when the overdrive is applied; generating a pixel signal to be supplied to the pixel to which the overdrive is applied by referring to the lookup table; The display device according to claim 1 .

3. the third circuit holds a plurality of the look-up tables; each of the plurality of lookup tables corresponds to each of the plurality of scanning lines having different supply timings of the gate signal in the scanning; The display device according to claim 2 .

4. the number of bits of the gradation value of the pixel signal in the lookup table is greater than the number of bits of the gradation value indicated by the pixel data; The display device according to claim 3 .

5. the gradation value of the pixel signal in the lookup table is different when the gradation value indicated by the pixel data is different; The display device according to claim 4 .

6. the predetermined gradation value is a gradation value at which the degree of light transmission in the pixel is lower than 10%; The display device according to claim 1 .

Images