Photoelectric conversion device and apparatus

Abstract

To provide a technique advantageous for suppressing a peak value of current consumption.SOLUTION: A photoelectric conversion device comprises a pixel array that has a plurality of pixels arranged to form a plurality of rows and a plurality of columns, and a read-out circuit that has a plurality of column circuits reading out signals from the pixel array. Each pixel includes: a photoelectric conversion element that accumulates electric charges according to incident light; a charge voltage conversion part; a transfer part that transfers the electric charges from the photoelectric conversion element to the charge voltage conversion part; a first amplification transistor that amplifies the voltage of the charge voltage conversion part; a first current source that supplies a first current to the first amplification transistor; a holding part that holds output of the first amplification transistor; and a second amplification transistor that amplifies the voltage supplied from the holding part. Each column circuit includes a second current source that supplies a second current to the second amplification transistor. The first current is smaller than the second current.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and an apparatus. [Background technology]

[0002] Patent Document 1 describes a global shutter CMOS image sensor in which each pixel has a memory for storing a signal. In the global shutter system, charge accumulation operations start and end simultaneously in all pixels. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-51548 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in a global shutter CMOS image sensor, the operation of writing signals corresponding to the charges accumulated in the photoelectric conversion elements into memory is performed simultaneously in all pixels, which can result in a very large peak value of current consumption.

[0005] An object of the present invention is to provide an advantageous technique for suppressing the peak value of current consumption. [Means for solving the problem]

[0006] One aspect of the present invention relates to a photoelectric conversion device including a pixel array having a plurality of pixels arranged to form a plurality of rows and a plurality of columns, and a readout circuit having a plurality of column circuits that read out signals from the pixel array, wherein in the photoelectric conversion device, each pixel includes a photoelectric conversion element that accumulates an electric charge corresponding to incident light, a charge-voltage conversion unit, a transfer unit that transfers an electric charge from the photoelectric conversion element to the charge-voltage conversion unit, a first amplifying transistor that amplifies the voltage of the charge-voltage conversion unit, a first current source that supplies a first current to the first amplifying transistor, a holding unit that holds an output of the first amplifying transistor, and a second amplifying transistor that amplifies the voltage supplied from the holding unit, and each column circuit includes a second current source that supplies a second current to the second amplifying transistor, and the first current is smaller than the second current. [Effects of the Invention]

[0007] According to the present invention, an advantageous technique for suppressing the peak value of current consumption is provided. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram schematically illustrating an example of the configuration of a photoelectric conversion device according to an embodiment. [Figure 2] FIG. 1 is a functional block diagram showing an example of the configuration of a photoelectric conversion device according to an embodiment. [Figure 3] 3 is a circuit diagram showing an example of the configuration of one pixel and a portion of one column circuit in the photoelectric conversion device illustrated in FIGS. 1 and 2. FIG. [Figure 4] Diagram showing the three operating modes. [Figure 5] FIG. 10 is a diagram illustrating a write operation in a period B. [Figure 6] FIG. 10 is a diagram illustrating a read operation in a period C. [Figure 7] FIG. 1 is a diagram showing a configuration in which a pixel array is divided into a plurality of blocks. [Figure 8] FIG. 10 is a diagram illustrating a partial global shutter mode. [Figure 9] FIG. 1 is a diagram illustrating an example of the configuration of an apparatus according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0010] FIG. 1 illustrates an exemplary configuration of a photoelectric conversion device 10 according to an embodiment. FIG. 2 illustrates a functional block diagram of the photoelectric conversion device 10 illustrated in FIG. 1. The photoelectric conversion device 10 may be configured, for example, as an image sensor that captures an optical image to generate image data and outputs the image data. Alternatively, the photoelectric conversion device 10 may be configured, for example, as a sensor that captures an optical image to generate image data and outputs information obtained by processing the image data. In the exemplary configuration illustrated in FIG. 1, the photoelectric conversion device 10 may be configured by stacking three substrates 100, 200, and 300. Each of the first substrate 100, the second substrate 200, and the third substrate 300 may have a semiconductor layer and a wiring structure. However, this is merely an example, and the photoelectric conversion device 10 may be configured with a single substrate, two substrates, or four or more substrates.

[0011] The first substrate 100 may include a first array 110 in which a plurality of first pixel components 30 are arranged to form a plurality of rows and a plurality of columns, a first control circuit 20, and a first vertical scanning circuit 120. The second substrate 200 may include a second array 210 in which a plurality of second pixel components 40 are arranged to form a plurality of rows and a plurality of columns, a second control circuit 21, a second vertical scanning circuit 220, and a bias generation circuit 230. One first component 30 and one second pixel component 40 may form one pixel (a pixel PIX, described below). In other words, the first substrate 100 and the second substrate 200 may form a pixel array PA in which a plurality of pixels are arranged to form a plurality of rows and a plurality of columns.

[0012] The first vertical scanning circuit 120 may be configured to, for example, control the accumulation of charges in the photoelectric conversion elements of each of the multiple pixels, the transfer of charges from the photoelectric conversion elements to the charge-voltage converters, the resetting of the charge-voltage converters, and the output of signals corresponding to the voltages of the charge-voltage converters. The first control circuit 20 may be configured to control the first vertical scanning circuit 120. The second vertical scanning circuit 220 may be configured to, for example, control the write operation of writing signals to the storage units of each of the multiple pixels and the read operation of signals from the storage units. The second control circuit 21 may be configured to control the second vertical scanning circuit 220 and the bias generation circuit 230. The bias generation circuit 230 may be configured to generate bias voltages and the like for controlling the first current sources (described below) in each pixel. The first vertical scanning circuit 120 and the second vertical scanning circuit 220 constitute a control unit CNT that controls the multiple pixels.

[0013] The third substrate 300 may include a readout circuit 310 including a plurality of column circuits 50 that read out signals from the pixel array PA, a column control circuit 320 that controls the plurality of column circuits 50 of the readout circuit 310, a bias generation circuit 330, a ramp generator 340, and a third control circuit 22. The third control circuit 22 controls the column control circuit 320, the bias generation circuit 330, and the ramp generator 340. Each column circuit 50 is arranged to read out signals from pixels constituting a corresponding column among the plurality of columns of the pixel array PA. The bias generation circuit 330 may be configured to generate a bias voltage or the like for controlling a second current source (described later) in each pixel. The ramp generator 340 may be configured to generate a ramp signal RAMP (described later) used for AD conversion and supply it to the plurality of column circuits 50.

[0014] Fig. 3 shows an example of the configuration of one pixel PIX and a portion of one column circuit 50 in the photoelectric conversion device 10 illustrated in Fig. 1 and Fig. 2. One pixel PIX can be configured by one first component 30 and one second pixel component 40.

[0015] The first component 30, which may be disposed on the first substrate 100, may include, for example, two photoelectric conversion elements 115 and 116. Alternatively, it may include only one photoelectric conversion element or three or more photoelectric conversion elements. The first component 30 may include a charge-voltage conversion unit FD, transfer units 113 and 114 that individually transfer the charges accumulated in the photoelectric conversion elements 115 and 116 to the charge-voltage conversion unit FD, and a first reset unit 112 that resets the charge-voltage conversion unit FD. The charge-voltage conversion unit FD is a capacitance that converts charges into voltage and may include, for example, a floating diffusion formed in a diffusion region of a semiconductor layer as well as parasitic capacitance. The first component 30 may also include a first amplification transistor 111 that amplifies the voltage of the charge-voltage conversion unit FD. The first component 30 may also include a selection transistor 117, although the first selection transistor 117 is optional.

[0016] The second component 40, which may be disposed on the second substrate 200, may include, for example, a first current source CS1, a first current source switch transistor 218 (first control transistor), a holding unit HLD, and sample and hold switches 213, 214, and 215. The second component 40 may also include a second amplification transistor 211, a second selection transistor 219, and a second reset unit 212.

[0017] The column circuit 50 (readout circuit 310) that may be disposed on the third substrate 300 may include a second current source switch transistor 315 (second control transistor), a second current source CS2, a readout line 316, and a comparator circuit 311.

[0018] The photoelectric conversion elements 115 and 116 have an anode and a cathode. The anodes of the photoelectric conversion elements 115 and 116 may be connected to a ground potential SGND for the photoelectric conversion elements 115 and 116 or a predetermined potential. The cathodes of the photoelectric conversion elements 115 and 116 may be connected to one of the sources or drains of the transistors constituting the transfer units 113 and 114. Transfer signals TXA and TXB are supplied from the first vertical scanning circuit 120 to the gates of the transistors constituting the transfer units 113 and 114, respectively. The other of the sources or drains of the transistors constituting the transfer units 113 and 114 may be connected to the charge-voltage conversion unit FD.

[0019] One of the source or drain of the transistor constituting the first reset unit 112 is connected to the charge-voltage conversion unit FD, and the other may be connected to a power supply potential SVDD for the photoelectric conversion elements 115 and 116. A first reset signal RES is supplied to the gate of the transistor constituting the first reset unit 112 from the first vertical scanning circuit 120. The gate of the first amplification transistor 111 is connected to the charge-voltage conversion unit FD, and one of the source or drain of the first amplification transistor 111 is connected to the power supply potential SVDD, and the other may be connected to one of the source or drain of the first selection transistor 117. The other of the source or drain of the first selection transistor 117 may be connected from the first substrate 100 to a read node VREADP on the second substrate 200 via the first connection unit 1-1. A first selection signal SEL is supplied to the gate of the first selection transistor 117 from the first vertical scanning circuit 120. The first amplification transistor 111 and the first current source CS1 constitute a first source-follower amplifier circuit.

[0020] The read node VREADP may be connected to the first current source CS1 via the first current source switch transistor 218. A block selection signal BLK may be supplied to the gate of the first current source switch transistor 218 from the first vertical scanning circuit 120. The first current source CS1 may include, for example, a series connection of the first current source transistor 217 and the first cascode transistor 216, but may also be configured as a single current source transistor or have other configurations. Control voltages VBIAS1 and VGATE1 may be supplied to the gates of the first current source transistor 217 and the first cascode transistor 216, respectively, from the bias generation circuit 230. One of the source or drain of the first current source switch transistor 218 may be connected to the read node VREADP, and the other may be connected to, for example, the first cascode transistor 216. One of the source or drain of the first current source transistor 217 is connected to the first cascode transistor 216, and the other is connected to the ground potential AGND for the analog circuit.

[0021] The read node VREADP may be connected to one of the sources or drains of the sampling switches 213, 214, and 215. The other of the sources or drains of the sampling switches 213, 214, and 215 may be connected to one end of the memories (hold capacitors) CN, CA, and CAB. The other ends of the memories CN, CA, and CAB may be connected to a ground potential MGND for the memories. Control signals SWN, SWA, and SWAB may be supplied to the gates of the sampling switches 213, 214, and 215 from the second vertical scanning circuit 220. One of the sources or drains of the transistors constituting the second reset unit 212 may be connected to a power supply potential MVDD for the memories, and the other may be connected to the read node VREADP.

[0022] The gate of the second amplification transistor 211 is connected to a read node VREADP, one of the source or drain is connected to a power supply potential MVDD for memory, and the other may be connected to one of the source or drain of a second selection transistor 219. The other of the source or drain of the second selection transistor 219 may be connected to an output node VLOUT from the second substrate 200 to the third substrate 300 via a second connection part 2-1. A second selection signal SELM may be supplied to the gate of the second selection transistor 219 from the second vertical scanning circuit 220.

[0023] The output node VLOUT includes a readout line (vertical signal line) 316 arranged to extend in the column direction, and is connected to the pixel PIX (of the second amplification transistor 211) of the row selected by the second selection signal SELM among the pixels PIX arranged in one column.

[0024] The output node VLOUT may be connected to a second current source CS2 via a second current source switch transistor 315. A block selection signal BLKM may be supplied to the gate of the second current source switch transistor 315 from the column control circuit 320. The second current source CS2 may include, for example, a series connection of a second current source transistor 314 and a second cascode transistor 313, but may also be configured as a single current source transistor or have other configurations. The second amplification transistor 211 and the second current source CS2 form a second source follower amplifier circuit. Control voltages VBIAS2 and VGATE2 may be supplied to the gates of the second current source transistor 314 and the second cascode transistor 313, respectively, from the bias generation circuit 330. One of the source and drain of the second current source switch transistor 315 may be connected to the output node VLOUT, and the other may be connected to, for example, the second cascode transistor 313. One of the source and drain of the second current source transistor 314 is connected to the second cascode transistor 313, and the other is connected to the ground potential AGND. The ground potential AGND of the third substrate 300 can be connected to the ground potential AGND of the second substrate 200 via the second connection part 2-2.

[0025] Furthermore, the output node VLOUT may be connected to one differential input terminal of a comparator circuit 311, which is connected to a ground potential AVDD power supply for analog circuits and a power supply potential AGND for analog circuits. A ramp signal RAMP may be supplied to the other differential input terminal of the comparator circuit 311 from a ramp generator 340. Note that, based on the comparison result output from the comparator circuit 311, the image signal is converted from an analog signal to a digital signal.

[0026] In the above example, the power supply potentials SVDD, MVDD, AVDD and the ground potentials SGND, MGND, AGND are separated from one another to reduce the effect of fluctuations in the power supply potential on other circuits. However, without being limited to the above example, a common power supply potential and a common ground potential may also be used.

[0027] In the above example, the cascode transistors 216 and 313 are provided to suppress current changes due to fluctuations in the drain voltages of the current source transistors 217 and 314. However, if the current changes due to fluctuations in the drain voltages of the current source transistors 217 and 314 are small, the cascode transistors 216 and 313 are not necessary.

[0028] The photoelectric conversion device 10 may be configured to control multiple pixels PIX using a partial global shutter (PGS) system. Alternatively, the vertical drive circuit 30 may have a partial global shutter mode in which multiple pixels PIX are controlled using the partial global shutter (PGS) system, and a global shutter mode in which multiple pixels PIX are controlled using the global shutter (GS) system. The mode control may be performed, for example, by a mode command signal sent externally to a main control unit (not shown). The partial global shutter (PGS) system is a system in which multiple pixels PIX constituting a pixel array PA are divided into multiple blocks as shown in FIG. 7, and each block is driven using the global shutter system. Each block may include pixels arranged in the same row and pixels arranged in different rows. In other words, each block may include any number of pixels PIX whose positions are specified by two or more rows and two or more columns.

[0029] FIG. 4(a) schematically shows the operation of the photoelectric conversion device 10 in global shutter (GS) mode. Period A is an accumulation period during which the photoelectric conversion elements 115 and 116 accumulate electric charges. Period B is a write period during which signals (noise level, optical signal level) corresponding to the electric charges accumulated by the photoelectric conversion elements 115 and 116 are written to the holding unit HLD (memories CN, CA, CAB). Period C is a read period during which signals are read out from the holding units HLD of the multiple pixels PIX constituting the pixel array PA in units of one or a predetermined number of rows. In global shutter mode, the operation during period A is performed simultaneously for all pixels PIX, and the operation during period B is performed simultaneously for all pixels PIX. Furthermore, in global shutter mode, the operation during period C is performed to sequentially read out signals from the pixel array in units of one or a predetermined number of rows.

[0030] FIG. 5 illustrates a write operation during period B. The accumulation period is until just before time t1, and period B, i.e., the write period, is from time t1 to time t10. First, just before time t1, the first reset signal RES is at a high level, the transistors constituting the first reset unit 112 are on, and the charge-voltage converter FD is set (reset) to a voltage corresponding to the power supply potential SVDD. Just before time t1, the second reset signal RESC is also at a high level, the transistors constituting the second reset unit 212 are on, and the read node VREADP is set (reset) to a voltage corresponding to the power supply potential MVDD. Just before time t1, the control signals SWN, SWA, and SWAB are also at a high level, the sampling switches 213, 214, and 215 are on, and one ends of the memories CN, CA, and CAB are set (reset) to a voltage corresponding to the power supply potential SVDD.

[0031] Next, at time t1, the second reset signal RESC changes from high to low, and the transistors constituting the second reset unit 212 change from on to off. Also at time t1, the control signals SWN, SWA, and SWAB change from high to low, and the sampling switches 213, 214, and 215 change from on to off. That is, the memories CN, CA, and CAB hold the voltages they had just before time t1. Furthermore, at time t1, the first selection signal SEL and the block selection signal BLK change from low to high, and the first selection transistor 117 and the first current source switch transistor 218 change from off to on. This causes a current to flow through the first amplification transistor 111. In this state, the first amplification transistor 111 outputs a voltage (level) corresponding to the voltage of the charge-voltage conversion unit FD to the read node VREADP.

[0032] Then, at time t2, the first reset signal RES changes from high level to low level, and the voltage of the charge-voltage converter FD is maintained at the voltage at the time of reset if there is no noise, but in reality it becomes a noise level according to the noise.

[0033] Subsequently, from time t2 to time t3, the control signal SWN is set to high level, turning on the sampling switch 213, thereby causing a state in which a noise signal voltage (hereinafter referred to as an N signal) corresponding to the noise level is written to the memory CN. Then, at time t3, the control signal SWN signal changes from high level to low level, causing the sampling switch 213 to change from on to off, causing the memory CN to hold the N signal.

[0034] Next, from time t4 to time t5, the first transfer signal TXA is set to high level, turning on the transistor that constitutes the first transfer unit 113 and transferring the charge of the first photoelectric conversion element 115 to the charge-voltage converter FD. From time t5 to time t6, the control signal SWA is set to high level, causing the sampling switch 214 to change from off to on. This causes a state in which a first optical signal voltage (hereinafter referred to as the SA signal) corresponding to the charge of the first photoelectric conversion element 115 is written to the memory CA. Then, at time t6, the control signal SWA changes from high level to low level, causing the sampling switch 214 to change from on to off, causing the memory CA to hold the SA signal.

[0035] From time t7 to time t8, the first transfer signal TXA and the second transfer signal TXB are set to high level, and the transistors constituting the first transfer unit 113 and the transistors constituting the second transfer unit 114 are turned on. As a result, the charges of the first photoelectric conversion element 115 and the second photoelectric conversion element 116 are transferred to the charge-voltage conversion unit FD, and the charges of the first photoelectric conversion element 115 and the second photoelectric conversion element 116 are added together in the charge-voltage conversion unit FD.

[0036] From time t9 to time t10, the control signal SWAB is set to high level, turning on the sampling switch 215. This causes a state in which a second optical signal voltage (hereinafter referred to as an SAB signal) corresponding to the charges of the first photoelectric conversion element 115 and the second photoelectric conversion element 116 is written to the memory CAB. Then, at time t10, the control signal SWB changes from high level to low level, causing the sampling switch 215 to change from high level to low level. This causes the sampling switch 215 to change from on to off, causing the memory CAB to hold the SAB signal. In this way, the N signal, SA signal, and SAB signal of each pixel PIX are held in the memories CN, CA, and CAB, respectively.

[0037] 6 illustrates the readout operation during period C. Period B ends by time t21. The period from time t21 to time t30 is the readout period (one horizontal scanning period) of signals from the pixels PIX in the first row. FIG. 6 shows the readout periods of signals from the pixels PIX in the first and second rows.

[0038] At time t21, the selection signal SELM(1) (the number in parentheses indicates the row number) for the first row changes from low to high, and the second selection transistor 219 of the pixels PIX in the first row changes from off to on. Also at time t21, the block selection signal BLKM changes from low to high, and the second current source switch transistor 315 changes from off to on. This allows current to flow through the second amplification transistor 211 of the pixels PIX in the first row, and signals can be read out from the pixels PIX in the first row.

[0039] Then, from time t21 to time t22, the second reset signal RESC is set to a high level, and the voltage of the read node VREADP is set to a voltage corresponding to the power supply potential MVDD. Note that the voltage of the read node VREADP may be set to another voltage. Thereafter, from time t23 to time t24, the control signal SWN is set to a high level, and the sampling switch 213 is turned on. As a result, the N signal held in the memory CN is supplied to the gate of the second amplification transistor 211, and the second amplification transistor 211 outputs a voltage corresponding to the N signal to the output node VLOUT. The comparator circuit 311 compares the voltage of the output node VLOUT with the ramp signal RAMP and outputs the comparison result. A subsequent circuit (not shown) can be configured to output the time from the start of the comparison operation by the comparator circuit 311 to the inversion of the comparison result (the count value by the counter) as digital data corresponding to the N signal.

[0040] Subsequently, from time t24 to time t25, the second reset signal RESC is again set to high level, and the voltage of the read node VREADP is set to a voltage corresponding to the power supply potential MVDD. Such an operation can reduce the influence on the signal read from the selected memory that is caused by the state before the signal is read from the selected memory.

[0041] From time t26 to time t27, the control signal SWA is set to high level, turning on the sampling switch 214. As a result, the SA signal held in the memory CA is supplied to the gate of the second amplification transistor 211, and the second amplification transistor 211 outputs a voltage corresponding to the SA signal to the output node VLOUT. The comparator circuit 311 compares the voltage of the output node VLOUT with the ramp signal RAMP and outputs the comparison result. A subsequent circuit (not shown) can operate to output the time from the start of the comparison operation by the comparator circuit 311 to the inversion of the comparison result (the count value by the counter) as digital data corresponding to the SA signal.

[0042] Furthermore, from time t27 to time t28, the second reset signal RESC is again set to high level, and the voltage of the read node VREADP is set to a voltage corresponding to the power supply potential MVDD. From time t29 to time t30, the control signal SWAB is set to high level, turning on the sampling switch 215. As a result, the SAB signal held in the memory CAB is supplied to the gate of the second amplification transistor 211, and the second amplification transistor 211 outputs a voltage corresponding to the SAB signal to the output node VLOUT. The comparator circuit 311 compares the voltage of the output node VLOUT with the ramp signal RAMP and outputs the comparison result. A subsequent circuit (not shown) can operate to output the time from the start of the comparison operation by the comparator circuit 311 to the inversion of the comparison result (the count value by the counter) as digital data corresponding to the SAB signal.

[0043] At time t30, the selection signal SELM(1) for the first row changes from high to low, causing the second selection transistors 219 of the pixels PIX in the first row to change from on to off. Meanwhile, at time t30, the selection signal SELM(2) for the second row changes from low to high, causing the second selection transistors 219 of the pixels PIX in the second row to change from off to on. From time t30 to time t39, the readout operation of signals from the pixels PIX in the second row is performed in the same manner as the readout operation of signals from the pixels PIX in the first row. Thereafter, the signals of the pixels in the third through final rows are read out in the same manner.

[0044] The block selection signal BLKM can change from high level to low level at the timing when the period C ends.

[0045] In the above example, an N signal, an SA signal, and an SAB signal are read out from each pixel, but this is merely an example. For example, an N signal, an SA signal, and an SB signal may be read out from each pixel (the SB signal is the optical signal level read out from the photoelectric conversion element 116). Alternatively, an N signal and an SAB signal may be read out from each pixel. Alternatively, an N signal, an SB signal, and an SAB signal may be read out from each pixel.

[0046] Note that the configuration and operation of the above photoelectric conversion device are merely examples for easy understanding, and the overall configuration of the photoelectric conversion device, the configuration of each pixel, the driving method of each pixel, etc. can be appropriately changed.

[0047] In this embodiment, the first current source CS1 (first current source transistor 217) is configured or controlled to supply a first current to the first amplification transistor 111. Further, the second current source CS2 (second current source transistor 314) is configured or controlled to supply a second current to the second amplification transistor 211. Here, it is preferable that the magnitude of the first current is smaller than the magnitude of the second current. This can be adjusted, for example, by the voltage levels of the control voltages VBIAS1 and VBIAS2 generated by the bias generation circuits 230 and 330. For example, when the first current source transistor 217 and the second current source transistor 314 are composed of NMOS transistors, by setting VBIAS1 < VBIAS2, the magnitude of the first current can be made smaller than the magnitude of the second current. The magnitude of the first current preferably satisfies at least one of the conditions of less than 90%, less than 80%, less than 70%, less than 60%, less than 50%, less than 40%, less than 30%, less than 20%, less than 10% of the magnitude of the second current. Alternatively, the magnitude of the first current preferably satisfies at least one of the conditions of less than 1 / 2, less than 1 / 4, less than 1 / 8, less than 1 / 16, less than 1 / 32, less than 1 / 64, less than 1 / 128, less than 1 / 256, less than 1 / 512 of the magnitude of the second current.

[0048] Hereinafter, the advantages of making the magnitude of the first current smaller than the magnitude of the second current will be described. One first amplification transistor 111 to which one first current source CS1 (first current source transistor 217) supplies a first current has as the target for writing a signal at one time only one of the memories CN, CA, and CAB. Therefore, the magnitude of the current required for one first current source CS1 (first current source transistor 217) is relatively small.

[0049] On the other hand, one second amplification transistor 211 to which the second current source CS2 (second current source transistor 314) supplies the second current needs to drive the load (capacitance) of the readout line 316 extending in the column direction and the multiple second selection transistors 219 connected thereto. Therefore, the current (magnitude) required for one second current source CS2 (second current source transistor 314) is relatively large. Therefore, the first current (magnitude) may be smaller than the second current (magnitude). In the global shutter mode, the first current sources CS1 (first current source transistors 217) of the multiple pixels PIX constituting the pixel array PA operate simultaneously during period B (write period). Therefore, making the first current (magnitude) smaller than the second current (magnitude) is useful for suppressing the peak value of current consumption. Suppressing the peak value of current consumption stabilizes the power supply potential and ground potential, which is advantageous for reducing noise. Suppressing the peak value of current consumption is also advantageous for reducing power consumption.

[0050] 4(b) and 4(c) schematically show the operation of the photoelectric conversion device 10 in partial global shutter (PGS) mode. FIGS. 4(b) and 4(c) show an example in which the pixels PIX constituting the pixel array PA are divided into a plurality (N) of blocks, i.e., blocks BLK1 to BLKN. First, the period A (accumulation period) will be described. In the partial global shutter (PGS) mode, a period A (accumulation period) is determined for each block. In the example of FIGS. 4(b) and 4(c), N periods A (accumulation periods) are determined corresponding to the N blocks BLK1 to BLKN, respectively. Here, the first vertical scanning circuit 120 can be configured to control the pixels PIX so that the period during which the pixels PIX perform the accumulation operation is the same within each block but different between the blocks. The first vertical scanning circuit 120 controls the pixels PIX so that the timing at which the pixels PIX start the accumulation operation is the same within each block but different between the blocks. Furthermore, the first vertical scanning circuit 120 controls the pixels PIX so that the timing of ending the accumulation operation for the pixels PIX is the same within each block but different between the blocks. On the other hand, the first vertical scanning circuit 120 controls the pixels PIX so that the length of the accumulation operation period for the pixels PIX is the same for all blocks, in other words, the same for all pixels PIX.

[0051] In the example shown in Fig. 4(b), the readout circuit 310 starts period C (readout period) before period A (accumulation period) and period B (write period) end in all of the multiple pixels PIX. From another perspective, in the example shown in Fig. 4(b), the readout operation in a certain block (operation in period C) is performed in parallel with the operation in period A or period B (operation in period A or B) in another block. In the example shown in Fig. 4(b), the readout circuit 310 performs, for example, the readout operation of signals from each block in response to the end of the write operation in each block.

[0052] 4(c), the readout circuit 310 starts a period C (readout period) after the period A (accumulation period) and the period B (writing period) have ended for all of the pixels PIX. The example shown in FIG. 4(c) is advantageous for suppressing the peak value of current consumption in the photoelectric conversion device 10.

[0053] The partial global shutter (PGS) mode can be realized, for example, by providing a first selection signal SEL and a block selection signal BLK for each block so that each block can be individually controlled. Specifically, a plurality of first selection signals SEL1, SEL2, . . . SELN and a plurality of block selection signals BLK1, BLK2, . . . BLKN may be provided and driven as illustrated in FIG. 8.

[0054] The peak current consumption of the first current source CS1 during period A in partial global shutter (PGS) mode is I PGS , the peak value of the current consumption of the first current source CS1 during period A of the global shutter (GS) mode is I GS Then, I PGS =I GS / N, where N is the number of blocks. In the partial global shutter mode, the control voltages VBIAS1 and VBIAS2 generated by the bias generation circuits 230 and 330 may also be adjusted so that the (magnitude of) the first current is smaller than the (magnitude of) the second current.

[0055] In the above example, the multiple pixels PIX that make up the pixel array PA are divided into N blocks, and the accumulation period and writing period are controlled for each block, but the accumulation period and writing period may also be controlled in units of a predetermined number of blocks, two or more.

[0056] The size of the block (eg, the number of rows) may be determined such that the number of rows on which write operations are performed per unit time is greater than the number of rows on which read operations are performed per unit time.

[0057] In response to the first current flowing from the first current source CS1 being smaller than the second current flowing from the second current source CS2, the W / L ratio of the first amplification transistor 111 may be made smaller than the W / L ratio of the second amplification transistor 211. Alternatively, in response to the first current flowing from the first current source CS1 being smaller than the second current flowing from the second current source CS2, the area of ​​(the active region of) the first amplification transistor 111 may be made smaller than the area of ​​(the active region of) the second amplification transistor 211.

[0058] The W / L ratio and the area of ​​a transistor are explained below. The current I that flows between the source and drain of a transistor is expressed by the following equation (1).

[0059] I=β(W / L)·(Vgs-Vth)···Formula (1) where β is the gain coefficient, W is the channel width, L is the channel length, Vgs is the gate-source voltage, and Vth is the threshold voltage.

[0060] The channel width W and channel length L are determined by the configuration of the transistor. As shown in equation (1), the current I flowing between the source and drain of the transistor is proportional to the W / L ratio, which is the ratio of the channel width W to the channel length L of the transistor. In addition, by making the first current flowing from the first current source CS1 smaller than the second current flowing from the second current source CS2, the current that the first amplification transistor 111 can flow can be made smaller than the current that the second amplification transistor 211 can flow.

[0061] Therefore, the W / L ratio of the first amplification transistor 111 may be made smaller than the W / L ratio of the second amplification transistor 211 in response to the first current flowing from the first current source CS1 being smaller than the second current flowing from the second current source CS2. Furthermore, when the channel length L of the first amplification transistor 111 and the channel length L of the second amplification transistor 211 are equal, the channel width W of the first amplification transistor 111 may be made smaller than the channel width W of the second amplification transistor 211. In other words, the area of ​​(the active region of) the first amplification transistor 111 may be made smaller than the area of ​​(the active region of) the second amplification transistor 211. Reducing the area of ​​(the active region of) the first amplification transistor 111 is advantageous for reducing the pixel size.

[0062] In order to make the first current passed by the first current source CS1 smaller than the second current passed by the second current source CS2, the W / L ratio of the first current source transistor 217 may be smaller than the W / L ratio of the second current source transistor 314. When the channel length L of the first current source transistor 217 and the channel length L of the second current source transistor 314 are equal, the channel width W of the first current source transistor 217 may be smaller than the channel width W of the second current source transistor 314. In other words, the area of ​​(the active region of) the first current source transistor 217 may be smaller than the area of ​​(the active region of) the second current source transistor 314. [Application example] One application example of the photoelectric conversion device 10 is an imaging device that generates an image (image data) by capturing an optical image. Other application examples of the photoelectric conversion device include a distance measuring device (a device that measures distance using focus detection or TOF (Time Of Flight)), a photometric device (a device that measures the amount of incident light), etc.

[0063] Hereinafter, an apparatus EQ incorporating a photoelectric conversion device 10 will be described with reference to FIG. 18. The apparatus EQ may include at least one of the photoelectric conversion device 10 configured as an image sensor, an optical device 1040, a control device 1050, a processing device 1060, a display device 1070, a storage device 1080, and a mechanical device 1090. The optical device 1040 is, for example, a lens, a shutter, or a mirror. The control device 1050 controls the semiconductor chip 210. The control device 1050 is, for example, a semiconductor device such as an ASIC.

[0064] The processing device 1060 processes the signal output from the semiconductor chip 210. The processing device 1060 is a semiconductor device such as a CPU or ASIC for configuring an analog front end (AFE) or a digital front end (DFE). The display device 1070 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor chip 210. The storage device 1080 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor chip 210. The storage device 1080 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0065] The mechanical device 1090 has a moving part or a propulsion part such as a motor or an engine. In the device EQ, the signal output from the semiconductor chip 210 is displayed on the display device 1070, or transmitted to the outside by a communication device (not shown) included in the device EQ. For this purpose, the device EQ may further include a storage device 1080 and a processing device 1060 in addition to the storage circuit and arithmetic circuit included in the semiconductor chip 210. The mechanical device 1090 may be controlled based on the signal output from the semiconductor chip 210.

[0066] The device EQ is also suitable for electronic devices such as information terminals with a photographing function (e.g., smartphones and wearable terminals) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 1090 in the camera can drive components of the optical device 1040 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 1090 in the camera can move the semiconductor chip 210 for vibration isolation operations.

[0067] Furthermore, the equipment EQ may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 1090 in transportation equipment may be used as a moving device. The equipment EQ as transportation equipment is suitable for transporting semiconductor chips 210 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 1060 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 1090 as a moving device based on information obtained by the semiconductor chip 210. Alternatively, the equipment EQ may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot. [Disclosures] The present specification and drawings include the following disclosure. (Item 1) A photoelectric conversion device comprising: a pixel array having a plurality of pixels arranged to form a plurality of rows and a plurality of columns; and a readout circuit having a plurality of column circuits that read out signals from the pixel array, Each pixel includes a photoelectric conversion element that accumulates a charge corresponding to incident light, a charge-voltage conversion unit, a transfer unit that transfers a charge from the photoelectric conversion element to the charge-voltage conversion unit, a first amplifying transistor that amplifies a voltage of the charge-voltage conversion unit, a first current source that supplies a first current to the first amplifying transistor, a holding unit that holds an output of the first amplifying transistor, and a second amplifying transistor that amplifies the voltage supplied from the holding unit, each column circuit includes a second current source that supplies a second current to the second amplifying transistor; the first current is less than the second current; A photoelectric conversion device characterized by: (Item 2) a control unit that controls the plurality of pixels; the control unit causes the transfer unit to transfer charges from the photoelectric conversion elements to the charge-voltage converters and causes the plurality of pixels to simultaneously perform a writing operation of writing the output of the first amplification transistors to the holding unit; 2. The photoelectric conversion device according to item 1, (Item 3) a control unit that divides the plurality of pixels into a plurality of blocks and controls the plurality of pixels; the control unit controls the plurality of pixels so that a period during which the transfer unit transfers charges from the photoelectric conversion element to the charge-voltage conversion unit and the holding unit writes the output of the first amplification transistor to the holding unit is the same within each block and different among the plurality of blocks. 2. The photoelectric conversion device according to item 1, (Item 4) the read circuit performs a signal read operation from each block in response to completion of the write operation in each block; 4. The photoelectric conversion device according to item 3, (Item 5) the readout circuit starts a readout operation of signals from the plurality of pixels after the write operation in all of the plurality of blocks is completed. 4. The photoelectric conversion device according to item 3, (Item 6) Each pixel further includes a first control transistor; the first amplifying transistor, the first current source, and the first control transistor are connected in series; the control unit performs the write operation by turning on the first control transistor; 6. The photoelectric conversion device according to any one of items 3 to 5, characterized in that: (Item 7) the first current source includes a first current source transistor, and the second current source includes a second current source transistor; a voltage is supplied to a gate of the first current source transistor and a gate of the second current source transistor so that the first current is smaller than the second current; 7. The photoelectric conversion device according to any one of items 1 to 6, wherein: (Item 8) a W / L ratio, which is a ratio of a channel width W to a channel length L of the first amplification transistor, is smaller than a W / L ratio of the second amplification transistor; 8. The photoelectric conversion device according to any one of items 1 to 7, characterized in that: (Item 9) The area of ​​the first amplification transistor is smaller than the area of ​​the second amplification transistor. 8. The photoelectric conversion device according to any one of items 1 to 7, characterized in that: (Item 10) the first current source includes a series connection of a first current source transistor and a first cascode transistor; 10. The photoelectric conversion device according to any one of items 1 to 9, characterized in that: (Item 11) the second current source includes a series connection of a second current source transistor and a second cascode transistor; 11. The photoelectric conversion device according to any one of items 1 to 10, characterized in that: (Item 12) the readout circuit is disposed on a substrate different from a substrate on which at least second amplification transistors of the plurality of pixels are disposed. 12. The photoelectric conversion device according to any one of items 1 to 11, characterized in that: (Item 13) Each column circuit includes a readout line; the second amplification transistor of each pixel constituting one column of the plurality of pixels is connected to the readout line of a corresponding column circuit of the plurality of column circuits; 13. The photoelectric conversion device according to any one of items 1 to 12, characterized in that: (Item 14) Each pixel further includes a select transistor; the second amplification transistor of each pixel constituting one column of the plurality of pixels is connected to the readout line of a corresponding column circuit of the plurality of column circuits via the selection transistor; Item 14. The photoelectric conversion device according to item 13, (Item 15) The plurality of pixel components are disposed on two or more substrates. 15. The photoelectric conversion device according to any one of items 1 to 14, wherein: (Item 16) The photoelectric conversion device according to any one of items 1 to 15, a processing device that processes a signal output from the photoelectric conversion device; An apparatus characterized by comprising:

[0068] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0069] 10: photoelectric conversion device, 50: column circuit, 113, 114: transfer section, 115, 116: photoelectric conversion element, 111: first amplification transistor, 211: second amplification transistor, 120: first vertical scanning circuit, 220: second vertical scanning circuit, 310: readout circuit, CS1: first current source, CS2: second current source, PIX: pixel, FD: charge-voltage conversion section, HLD: holding section, CNT: control section

Claims

1. A photoelectric conversion device comprising: a pixel array having a plurality of pixels arranged to form a plurality of rows and a plurality of columns; and a readout circuit having a plurality of column circuits that read out signals from the pixel array, Each pixel includes a photoelectric conversion element that accumulates a charge corresponding to incident light, a charge-voltage conversion unit, a transfer unit that transfers a charge from the photoelectric conversion element to the charge-voltage conversion unit, a first amplification transistor that amplifies a voltage of the charge-voltage conversion unit, a first current source that supplies a first current to the first amplification transistor, a holding unit that holds an output of the first amplification transistor, and a second amplification transistor that amplifies the voltage supplied from the holding unit, each column circuit includes a second current source that supplies a second current to the second amplifying transistor; the first current is less than the second current; A photoelectric conversion device characterized by:

2. a control unit that controls the plurality of pixels; the control unit causes the transfer unit to transfer charges from the photoelectric conversion elements to the charge-voltage converters and causes the plurality of pixels to simultaneously perform a writing operation of writing the output of the first amplification transistors to the holding unit; 2. The photoelectric conversion device according to claim 1.

3. a control unit that divides the plurality of pixels into a plurality of blocks and controls the plurality of pixels; the control unit controls the plurality of pixels so that a period during which the transfer unit transfers charges from the photoelectric conversion element to the charge-voltage conversion unit and the holding unit writes the output of the first amplification transistor to the holding unit is the same within each block and different among the plurality of blocks.

2. The photoelectric conversion device according to claim 1.

4. the read circuit performs a signal read operation from each block in response to completion of the write operation in each block; 4. The photoelectric conversion device according to claim 3.

5. the readout circuit starts a readout operation of signals from the plurality of pixels after the write operation in all of the plurality of blocks is completed.

4. The photoelectric conversion device according to claim 3.

6. Each pixel further includes a first control transistor; the first amplifying transistor, the first current source, and the first control transistor are connected in series; the control unit causes the write operation to be performed by turning on the first control transistor; 4. The photoelectric conversion device according to claim 3.

7. the first current source includes a first current source transistor, and the second current source includes a second current source transistor; a voltage is supplied to a gate of the first current source transistor and a gate of the second current source transistor so that the first current is smaller than the second current; 2. The photoelectric conversion device according to claim 1.

8. a W / L ratio, which is a ratio of a channel width W to a channel length L of the first amplification transistor, is smaller than a W / L ratio of the second amplification transistor; 2. The photoelectric conversion device according to claim 1.

9. an area of ​​the first amplification transistor is smaller than an area of ​​the second amplification transistor; 2. The photoelectric conversion device according to claim 1.

10. the first current source includes a series connection of a first current source transistor and a first cascode transistor; 2. The photoelectric conversion device according to claim 1.

11. the second current source includes a series connection of a second current source transistor and a second cascode transistor; 11. The photoelectric conversion device according to claim 10.

12. the readout circuit is disposed on a substrate different from a substrate on which at least the second amplification transistors of the plurality of pixels are disposed; 2. The photoelectric conversion device according to claim 1.

13. Each column circuit includes a readout line; the second amplification transistor of each pixel constituting one column of the plurality of pixels is connected to the readout line of a corresponding column circuit of the plurality of column circuits; 2. The photoelectric conversion device according to claim 1.

14. Each pixel further includes a select transistor; the second amplification transistor of each pixel constituting one column of the plurality of pixels is connected to the readout line of a corresponding column circuit of the plurality of column circuits via the selection transistor; 14. The photoelectric conversion device according to claim 13.

15. The plurality of pixel components are disposed on two or more substrates.

2. The photoelectric conversion device according to claim 1.

16. The photoelectric conversion device according to any one of claims 1 to 15, a processing device that processes a signal output from the photoelectric conversion device; An apparatus characterized by comprising:

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