Control device, control method, and program

Abstract

To enable prompt return from a low power consumption mode with a simpler configuration than conventional techniques.SOLUTION: A control device for controlling data acquisition from a signal using a clock that is output from an oscillator, includes: a clock mask control unit which masks a clock during a prestored mask period when operation of the oscillator is started; a sampling timing control unit which corrects a sampling timing based on the mask period; and a reception control unit which acquires received data and outputs it based on a reception signal whose input has been started during the mask period and the corrected sampling timing.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed technology relates to a control technology for performing control to acquire data from a signal using a clock. [Background technology]

[0002] Some electronic devices have a function such as a low power consumption mode that reduces power consumption when operation is not required, and returns from the low power consumption mode when operation becomes required. For example, Patent Document 1 discloses a technology in which a device returns to normal mode when it receives a signal (serial signal) synchronized with a clock signal by start-stop synchronous communication in standby mode (corresponding to the above-mentioned "low power consumption mode") Furthermore, Patent Document 1 discloses a configuration having a function such as a free-running mode in which, in order to quickly return from standby mode to normal mode, a clock signal is generated by an internal logic circuit during the time from startup of the oscillator circuit (crystal oscillator) until the oscillation operation is considered to be stable, and the internal circuit operates in synchronization with the clock signal from the internal logic circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-285823 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the technology described in Patent Document 1 requires a configuration for realizing a function such as a self-propelled mode, which results in a problem of a complex configuration.

[0005] The present disclosure is intended to solve the above-mentioned problems, and aims to quickly return from a low power consumption mode using a configuration simpler than conventional techniques. [Means for solving the problem]

[0006] The control device of the present disclosure includes: A control device that performs control to acquire data from a signal using a clock output by an oscillator, a clock mask control unit that masks the clock for a mask period that is stored in advance after the oscillator starts operating; a sampling timing control unit that corrects the sampling timing based on the mask period; a reception control unit that acquires and outputs reception data based on a reception signal that has started to be accepted during the mask period and the corrected sampling timing; Equipped with It is characterized by the following. [Effects of the Invention]

[0007] The present disclosure provides the advantage of enabling a quick return from a low power consumption mode with a configuration simpler than conventional techniques. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating an example of a basic configuration of a control device 100 according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram showing an example of the configuration of a control device 100A in the case where the control device 100 shown in FIG. 1 is applied to a microcontroller. [Figure 3] FIG. 3 is a diagram illustrating the timing of the reception operation in the normal mode. [Figure 4] FIG. 4 is a diagram illustrating the timing of the reception operation when clock mask control is performed but sampling timing control is not performed in a state of recovery from the low power consumption mode. [Figure 5] FIG. 5 is a diagram illustrating the timing of the reception operation in a state where the control device 100, 100A according to the present disclosure is restored from the low power consumption mode. [Figure 6]FIG. 6 is a flowchart showing an example of processing by the control device 100, 100A according to the first embodiment of the present disclosure. [Figure 7] FIG. 7 is a diagram illustrating a first example of a hardware configuration for realizing the functions according to the configuration of the present disclosure. [Figure 8] FIG. 8 is a diagram illustrating a second example of a hardware configuration for realizing the functions according to the configuration of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] In order to explain the present disclosure in more detail, embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0010] Embodiment 1 In the first embodiment, a basic form of the present disclosure will be described.

[0011] An example configuration of a control device according to a first embodiment of the present disclosure will be described. FIG. 1 is a diagram illustrating an example of a basic configuration of a control device 100 according to a first embodiment of the present disclosure. The control device 100 controls asynchronous communication in a microcontroller (not shown). Specifically, the control device 100 performs control to sample the signal using a clock output by an oscillator of the microcontroller. The control device 100 acquires and outputs data using the reception control unit 130. A microcontroller is a control device that is incorporated into, for example, electronic devices. The microcontroller has a function of operating in a normal mode, which operates in the same way as a general microcontroller, and a function of a low-power mode for reducing power consumption. The low power consumption mode, such as STOP or standby, temporarily stops the oscillation of most internal clocks, putting the microcontroller into a state of low power consumption compared to when it is operating in normal mode. When the microcontroller is in a low power consumption state, it returns from the low power consumption state upon receiving an external communication line (such as UART) and starts (resumes) communication (reception). To return from the low power consumption mode, for example, a serial signal is input from the outside using start-stop synchronous communication. At this time, in the microcontroller, a change in the external communication line triggers the internal oscillator to start up and supply a clock for communication operations, but there is a time lag before the oscillator can stably supply the clock at the desired frequency. This time lag places a limit on the allowable baud rate of the UART during communication (reception) when returning from a low-power state. That is, in a typical microcontroller, the clock is unstable at startup, so a time lag occurs during the unstable period, and the accuracy on the receiving side decreases. In response to this, the control device 100 masks the clock so as not to use the clock during a period in which oscillation is unstable, and further advances the sampling timing based on the mask period. The sampling timing is the timing at which data is sampled for a signal. The control device 100 shown in FIG. 1 includes a clock mask control unit 110, a sampling timing control unit 120, and a reception control unit .

[0012] When the oscillator starts operating, the clock mask control unit 110 masks the clock for a mask period that is stored in advance. Specifically, the clock mask control unit 110 masks the clock output during a mask period that is set and stored in advance after the oscillator starts operating and starts outputting the clock. More specifically, the clock mask control unit 110 masks the clock output during the mask period, which is a pre-set and stored time from when the oscillator starts operating and starts outputting the clock, by outputting a mask clock for the clock signal output from the oscillator. The oscillator starting to operate includes the oscillator restarting its operation from a state in which it has temporarily stopped oscillating the clock in the low power consumption mode.

[0013] The sampling timing control section 120 corrects the sampling timing based on the mask period. Specifically, when the mask period ends, the sampling timing control section 120 corrects the sampling timing based on the mask period and the clock, and outputs a sampling clock indicating the corrected sampling timing. For example, the sampling timing control section 120 advances the sampling timing, which is the timing of data sampling, by a time proportional to the clock stabilization period (mask period), which is the period from immediately after the start of the recovery operation until the clock becomes stable. Alternatively, the sampling timing control section 120 advances the sampling timing by, for example, a clock stabilization period (mask period) that is a period from immediately after the start of the recovery operation until the clock becomes stable. This ensures a margin of roughly the same magnitude whether the clock frequency on the sending side is faster or slower than the clock frequency of the receiving microcomputer, thereby improving the allowable baud rate.

[0014] When a received signal is input, the reception control unit 130 samples the received signal and outputs it as received data. The reception control unit 130 acquires and outputs reception data based on the reception signal that has started to be input during the mask period and the corrected sampling timing. Specifically, the reception control unit 130 receives the received signal during the mask period, and acquires and outputs the received data based on the received signal that began to be received during the mask period and the corrected sampling clock corrected by the sampling timing control unit 120.

[0015] In addition to the above configuration, the control device 100 may also include a control unit (not shown), a storage unit (not shown), and a communication unit (not shown). A control unit (not shown) controls the entire control device 100 and each of its components. The control unit (not shown) starts up the control device 100 in accordance with, for example, an external command. A storage unit (not shown) stores each piece of data used by the control device 100. The storage unit (not shown), for example, stores output (output data) from each component in the control device 100, and outputs the data for each component to the connected component. A communication unit (not shown) communicates with an external device, for example, between the control device 100 (100A) and a peripheral device. The control unit (not shown), the storage unit (not shown), and the communication unit (not shown) are the same in the embodiments described below.

[0016] Next, a configuration example of a control device 100A in which the control device 100 shown in FIG. 1 is applied to a microcontroller will be described. FIG. 2 is a diagram showing an example of the configuration of a control device 100A in the case where the control device 100 shown in FIG. 1 is applied to a microcontroller. The control device 100A performs control to acquire data from a signal using a clock output by an oscillator. The control device 100A shown in FIG. 2 is an MCU (microcontroller) incorporating the control device 100 shown in FIG. The microcontroller has the same configuration as the microcontroller already described, and has the function of operating in a normal mode, and also has the function of a low power consumption mode for reducing power consumption.

[0017] An example of the internal configuration of the control device 100A will be described. The control device 100A shown in Figure 2 is configured to include an internal oscillator 101, a clock mask control unit 110A, a sampling timing control unit 120A, a counter 125, a reception control unit 130A, a reception data generation circuit 140, a CPU 150, a transmission data generation circuit 160, and a data bus 170. The control device 100A of the present disclosure only needs to include the clock mask control unit 110A, the sampling timing control unit 120A, and the reception control unit 130A among the above-mentioned components, and may also be configured to include some or all of the components other than the clock mask control unit 110A, the sampling timing control unit 120A, and the reception control unit 130A. An example of the internal configuration of the control device 100A will be described below.

[0018] The internal oscillator 101 has a clock oscillation circuit that outputs a clock signal of a preset frequency. In a low power consumption mode in which clock oscillation is temporarily stopped, the built-in oscillator 101 starts outputting a clock when a received signal is input from the outside.

[0019] Clock mask control section 110A has the same functions as clock mask control section 110 already described. When the internal oscillator 101 (oscillator) starts operating, the clock mask control section 110A masks the clock during a mask period that is stored in advance. The clock mask control section 110A masks the clock output during a mask period that is set and stored in advance after the built-in oscillator 101 starts outputting the clock. The clock mask control unit 110A outputs a masking clock for the clock signal output from the built-in oscillator 101 during a mask period, which is a pre-set and stored time, from when the built-in oscillator 101 starts outputting the clock. The internal oscillator 101 starting to operate includes the internal oscillator 101 restarting operation from a state in which clock oscillation has been temporarily stopped in the low power consumption mode.

[0020] The sampling timing control section 120A corrects the sampling timing based on the mask period. Specifically, when the mask period ends, the sampling timing control section 120A corrects the sampling timing based on the mask period and the clock, and outputs a sampling clock indicating the corrected sampling timing. For example, the sampling timing control section 120A advances the sampling timing, which is the timing of data sampling, by a time proportional to the clock stabilization period (mask period), which is the period from immediately after the start of the recovery operation until the clock becomes stable. Alternatively, the sampling timing control section 120A advances the sampling timing by, for example, a clock stabilization period (mask period) that is a period from immediately after the start of the recovery operation until the clock becomes stable. This ensures a margin of roughly the same magnitude whether the clock frequency on the sending side is faster or slower than the clock frequency of the receiving microcomputer, thereby improving the allowable baud rate. 2 outputs a sampling clock using a counter 125. The sampling timing control section 120A outputs the sampling clock when the count value of the counter 125 reaches a preset value that is stored in advance. Furthermore, when the control device 100A returns from the low power consumption mode, the sampling timing control section 120A corrects the sampling timing by advancing the set value in time in accordance with the length of the mask period. The sampling timing control section 120A outputs a sampling clock based on the corrected set value of the sampling timing and the count value of the counter 125.

[0021] The counter 125 operates under the control of the sampling timing control section 120A. The counter 125 counts up the count value when the mask period ends. Specifically, for example, the counter 125 starts counting up the count value when the masking clock during the mask period falls, and thereafter counts up in accordance with the receiving operation clock. After counting up to a preset and stored maximum count value, the counter 125 then resets the count value to the initial value. In other words, once the counter 125 starts counting, it repeatedly counts up from the initial value to the maximum count value. 2 is included in the sampling timing control section 120A, but it does not have to be included in the sampling timing control section 120A and may be configured as a separate component. In this case, the sampling timing control section 120A receives the count value from the counter 125 and outputs a sampling clock when the count value reaches a set value.

[0022] When a received signal is input, the reception control unit 130A samples the received signal and outputs it as received data. The reception control unit 130A acquires and outputs reception data based on the reception signal that has started to be input during the mask period and the corrected sampling timing. The reception control unit 130A receives a reception signal during the mask period, and outputs reception data based on the reception signal that began to be received during the mask period and the sampling clock corrected by the sampling timing control unit 120A. The reception control unit 130A outputs the received data to the CPU 150 via the data bus 170.

[0023] The received data generating circuit 140 is a circuit that, when a received signal is input, samples the received signal to obtain and output received data. The reception data generation circuit 140 operates under the control of the reception control unit 130 A. For example, when returning from the low power consumption mode, the reception data generation circuit 140 samples the reception signal that has started to be input during a mask period, upon receiving a sampling clock output from the sampling timing control unit, and outputs the sampled signal as reception data. 2 is configured as being included in the reception control unit 130A, it does not have to be included in the reception control unit 130A and may be configured as a separate component. In this case, the reception control unit 130A receives and outputs the reception data output from the reception data generation circuit 140.

[0024] The CPU 150 is a central processing unit. The CPU 150 performs main arithmetic processing related to the control device 100A as a microcontroller. The CPU 150 is communicably connected to the reception data generation circuit 140 of the reception control unit 130A via a data bus 170. The CPU 150 is also communicably connected to the transmission data generation circuit 160. For example, when the CPU 150 receives received data, it performs arithmetic processing using the received data, and outputs the result of the arithmetic processing as transmission data via the transmission data generation circuit 160 to the outside of the control device 100A.

[0025] The transmission data generation circuit 160 is connected via a data bus 170 to the CPU 150 and the reception data generation circuit 140 of the reception control unit 130A so as to be able to communicate with each other. The transmission data generating circuit 160 is also connected to the outside of the control device 100A so as to be able to communicate with the outside. The transmission data generating circuit 160 outputs, for example, the transmission data output from the CPU 150 to the outside of the control device 100A.

[0026] Here, the timing of the receiving operation will be explained. First, an example of the timing of the reception operation in the normal mode will be described. FIG. 3 is a diagram illustrating the timing of the reception operation in the normal mode. FIG. 3 shows the changes over time of the internal oscillator clock 1000, the received signal 4000, the counter 5000, the sampling timing 6000, and the received data 7000.

[0027] Typically, the received signal 4000 of data transmitted and received in asynchronous communication is composed of an L-level start bit, 7 or 8 data bits consisting of H and L levels, a parity bit added immediately after the data bits, and 1 or 2 H-level stop bits. The number of data bits, the type and presence of parity bits, and the length of stop bits can be individually set depending on the device. FIG. 3 shows an example in which the data bit length is 8 bits, there is no parity bit, and the stop bit length is 1 bit.

[0028] In FIG. 3, the clock frequency of the internal oscillator is eight times that of the received signal (see internal oscillator clock 1000 and received signal 4000). When the received signal 4000 is input (at timing T r_s ), data sampling starts after detecting the L level of the start bit at the falling edge (received signal 4000). When the falling edge of the received signal 4000 is detected, the counter operates (timing T C_S , counter 5000). After starting, sampling is performed when the counter value is 3 (timing T S_S , sampling timing 6000). If the sampled received signal is at L level, it is determined to be a start bit, and thereafter, when the counter value is 3, sampling is performed from the data bit to the stop bit (see counter 5000, sampling timing 6000, and received data 7000).

[0029] Next, an example of the timing of the reception operation when returning from the low power consumption mode will be described. FIG. 4 is a diagram illustrating the timing of the reception operation when clock mask control is performed but sampling timing control is not performed when returning from the low power consumption mode. FIG. 5 is a diagram illustrating the timing of the reception operation in a state where the control device 100, 100A according to the present disclosure is restored from the low power consumption mode. In Figures 4 and 5, the received data (received signal including received data) in asynchronous communication is shown to be "START bit", "Data 0 bit", "Data 1 bit", "Data 2 bit", "Data 3 bit", "Data 3 bit", "Data 4 bit", "Data 5 bit", "Data 6 bit", "Data 7 bit", and "STOP bit", and the received data is sampled and captured using a clock supplied from the built-in oscillator 101. At this time, it is assumed that the microcontroller (control device 100A) is in a low power consumption mode, and returns from the low power consumption mode (at timing T r_s ), and at the same time, a clock begins to be supplied from the built-in oscillator 101. Since the clock of the built-in oscillator 101 is unstable immediately after recovery, the clock mask control units 110, 110A supply the reception control units 130, 130A with a masked clock for the period until it stabilizes. Note that the period until the oscillator clock stabilizes varies depending on the oscillator configuration, and therefore the clock mask period is determined by counting a length determined in advance based on the characteristics of the built-in oscillator 101 using a separate clock. As shown in FIG. 4, the control devices 100 and 100A input a received signal during a mask period, which is a period of a clock mask (a masking clock) (at timing T r_s ). Here, if the sampling timing for the received signal is kept the same as the sampling timing shown in FIG. s_s, the count value is set to 3), Data bit 5 is missed as shown in FIG. Therefore, the control devices 100 and 100A correct the sampling timing based on the mask period. For example, as shown in FIG. 5, if the sampling timing is advanced by the mask period of the clock signal (timing T s_s , count value setting value = 1), all data of "Data 0bit", "Data 1bit", "Data 2bit", "Data 3bit", "Data 3bit", "Data 4bit", "Data 5bit", "Data 6bit", and "Data 7bit" can be imported normally.

[0030] Next, an example of the processing by the control device will be described. FIG. 6 is a flowchart showing an example of processing by the control device 100, 100A according to the first embodiment of the present disclosure. The control device 100 and the control device 100A differ in that the control device 100A includes other components in addition to the components shown in the control device 100. However, since the processing of the common components shown in the control device 100 and the control device 100A is similar, an example of the processing of the control device 100A will be described here as a representative. The process shown in Fig. 6 is a control method performed by a control device. For example, by causing a computer to execute the control method included in Fig. 6 using a program, the computer can be made to function as an information processing device.

[0031] For example, when the control device 100A shown in Fig. 2 receives a signal from the outside in the low power consumption mode, it starts the process shown in Fig. 6. (Start)

[0032] The control device 100A then executes clock mask control processing (step ST1100). In the clock mask control process, when the operation of the built-in oscillator 101 starts, the clock mask control section 110A of the control device 100A masks the clock during a mask period that is stored in advance. Specifically, for example, when the clock mask control unit 110A receives a control signal to start the operation of the built-in oscillator 101, it obtains a pre-stored mask period and outputs a mask clock during the mask period. The clock mask control unit 110A also outputs a reception operation clock masked by the mask clock to the sampling timing control unit 120A. The clock mask control unit 110A also outputs the reception operation clock to the reception control unit 130A.

[0033] Next, the control device 100A executes a sampling timing control process (step ST1200). In the sampling timing control process, the sampling timing control section 120A of the control device 100A corrects the sampling timing based on the mask period. Specifically, for example, when the sampling timing control unit 120A receives a reception operation clock, it acquires a pre-stored mask period and calculates a corrected set value by advancing and correcting the set value of the count value based on the mask period. When the count value counted by the counter 125 reaches the set value, the sampling timing control unit 120A outputs a sampling clock indicating the sampling timing. The sampling timing control unit 120A outputs the sampling clock to the reception control unit 130A.

[0034] Next, the control device 100A executes a reception control process (step ST1300). In the reception control process, the reception control unit 130A of the control device 100A acquires and outputs reception data based on the reception signal that has started to be accepted during the mask period and the corrected sampling timing. Specifically, for example, the reception control unit 130A samples the reception signal at the timing of the sampling clock using the reception signal input during the mask period, the reception operation clock output by the clock mask control unit 110A, and the sampling clock output by the sampling timing control unit 120A, and acquires the reception data. The reception control unit 130A outputs the reception data to the CPU 150.

[0035] After outputting the received data to the CPU 150, the control device 100A ends the processing shown in FIG. 6. (End)

[0036] As described above, in this embodiment, by advancing the timing of data sampling based on the period in which the built-in oscillator is stable, asynchronous communication can be performed at a high baud rate even when the built-in oscillator is unstable immediately after returning from standby.

[0037] This embodiment shows an example of the following configuration. A control device that performs control to acquire data from a signal using a clock output by an oscillator, a clock mask control unit that masks the clock for a pre-stored mask period when the oscillator starts operating; a sampling timing control unit that corrects the sampling timing based on the mask period; a reception control unit that acquires and outputs reception data based on the reception signal that has started to be input during the mask period and the corrected sampling timing; Equipped with A control device characterized by: As a result, the present disclosure has an effect of providing a control device that enables quick recovery from a low power consumption mode with a configuration simpler than conventional techniques.

[0038] This embodiment shows an example of the following configuration. A control method executed by a control device that performs control to acquire data from a signal using a clock output by an oscillator, comprising: a clock mask control step in which a clock mask control unit of the control device masks the clock for a pre-stored mask period when the operation of the oscillator is started; a sampling timing control step in which a sampling timing control unit of the control device corrects the sampling timing based on the mask period; a reception control step in which a reception control unit of the control device acquires and outputs reception data based on the reception signal whose input has started during the mask period and the corrected sampling timing; A control method comprising: As a result, the present disclosure has the effect of providing a control method that enables quick recovery from a low power consumption mode with a configuration that is simpler than conventional techniques.

[0039] This embodiment shows an example of the following configuration. Computer, A control device that performs control to acquire data from a signal using a clock output by an oscillator, a clock mask control unit that masks the clock for a pre-stored mask period when the oscillator starts operating; a sampling timing control unit that corrects the sampling timing based on the mask period; a reception control unit that acquires and outputs reception data based on the reception signal that has started to be input during the mask period and the corrected sampling timing; Equipped with a control device characterized by: A program to run as. As a result, the present disclosure has the effect of providing a program that enables a device to quickly return from a low power consumption mode with a configuration that is simpler than conventional techniques.

[0040] This embodiment further shows an example of the following configuration. an internal oscillator that starts clock output when a received signal is input from an external device in a low power consumption mode in which clock oscillation is temporarily stopped; Furthermore, A control device characterized by: As a result, the present disclosure has the effect of providing a control device as a microcontroller that enables quick recovery from a low power consumption mode with a configuration simpler than conventional techniques. Furthermore, the present disclosure achieves the same effects as those described above by applying the above configuration to the above method or the above program.

[0041] Here, a hardware configuration for realizing the functions of the present disclosure will be described. FIG. 7 is a diagram illustrating a first example of a hardware configuration for realizing the functions according to the configuration of the present disclosure. FIG. 8 is a diagram illustrating a second example of a hardware configuration for realizing the functions according to the configuration of the present disclosure. The control device 100 or the control device 100A of the present disclosure is realized by the hardware shown in FIG. 7 or FIG. 8, respectively.

[0042] As shown in FIG. 7, each of the control device 100 and the control device 100A includes, for example, a processor 10001, a memory 10002, and a communication circuit 10004. The processor 10001 and the memory 10002 are, for example, installed in a computer. The functions of the present disclosure are realized by software, firmware, or a combination of software and firmware. The software or firmware is written as a program and stored in the memory 10002. That is, the memory 10002 stores programs for causing the computer to function as the built-in oscillator 101 (part), the clock mask control units 110, 110A, the sampling timing control units 120, 120A, the reception control units 130, 130A, and a control unit (not shown). The processor 10001 reads and executes the programs stored in the memory 10002, thereby realizing the functions of the built-in oscillator 101 (part), the clock mask control units 110, 110A, the sampling timing control units 120, 120A, the reception control units 130, 130A, and a control unit (not shown). The program causes a computer to execute the procedures or methods of the above-mentioned components. Furthermore, a storage unit (not shown) is realized by the memory 10002 or another memory (not shown). Furthermore, the communication circuit 10004 realizes a communication unit (not shown).

[0043] The processor 10001 is, for example, a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor, a microcontroller, or a digital signal processor (DSP). Memory 10002 may be a non-volatile or volatile semiconductor memory such as RAM (Random Access Memory), ROM (Read Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable Read Only Memory) or flash memory, or a magnetic disk such as a hard disk or flexible disk, or an optical disk such as a CD (Compact Disc) or DVD (Digital Versatile Disc), or a magneto-optical disk. The processor 10001 and the memory 10002 or the communication circuit 10004 are connected in a state where data can be transmitted between them.

[0044] Alternatively, the functions of the built-in oscillator 101 (part), clock mask control unit 110, 110A, sampling timing control unit 120, 120A, reception control unit 130, 130A, and a control unit not shown in the figure in the control unit 100 or control unit 100A may be realized by a dedicated processing circuit 20001, as shown in Figure 8.

[0045] The processing circuit 20001 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), a PLD (Programmable Logic Device), an FPGA (Field-Programmable Gate Array), an SoC (System-on-a-Chip), or a system LSI (Large-Scale Integration), or may be a combination of these. Furthermore, the memory 20002 or another memory not shown implements a storage unit not shown. Memory 20002 may be a non-volatile or volatile semiconductor memory such as RAM (Random Access Memory), ROM (Read Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable Read Only Memory) or flash memory, or a magnetic disk such as a hard disk or flexible disk, or an optical disk such as a CD (Compact Disc) or DVD (Digital Versatile Disc), or a magneto-optical disk. Furthermore, the communication circuit 20004 realizes a communication unit (not shown). The processing circuit 20001 and the memory 20002 or the communication circuit 20004 are connected in a state where data can be transmitted between them. In addition, in the control device 100 or the control device 100A, the functions of the built-in oscillator 101 (part), the clock mask control unit 110, 110A, the sampling timing control unit 120, 120A, the reception control unit 130, 130A, and a control unit not shown may be realized by separate processing circuits, or may be realized together by a processing circuit.

[0046] Alternatively, in the control device 100 or the control device 100A, some of the functions of the built-in oscillator 101 (part), the clock mask control unit 110, 110A, the sampling timing control unit 120, 120A, the receiving control unit 130, 130A, and a control unit not shown may be realized by the processor 10001 and the memory 10002, and the remaining functions may be realized by the processing circuit 20001. In this way, each of the functions of the above components can be realized by the cooperation of hardware, software, firmware, or a combination of these.

[0047] It should be noted that within the scope of this disclosure, the components in the embodiments may be freely combined, any component in each embodiment may be modified, or any component in the embodiments may be omitted.

[0048] The present disclosure is suitable for use in microcontrollers because it enables quick recovery from a low power consumption mode with a configuration simpler than conventional techniques. [Explanation of symbols]

[0049] 100,100A control device, 101 built-in oscillator, 110,110A clock mask control unit, 120,120A sampling timing control unit, 125 counter, 130,130A reception control unit, 140 reception data generation circuit, 150 CPU, 160 transmission data generation circuit, 170 data bus, 1000 built-in oscillator clock, 2000 clock unstable period mask, 3000 reception operation clock, 4000 reception signal, 5000 counter, 6000 sampling timing, 7000 reception data, 10001 processor, 10002 memory, 10004 communication circuit, 20001 processing circuit, 20002 memory, 20004 communication circuit.

Claims

1. A control device that performs control to acquire data from a signal using a clock output by an oscillator, a clock mask control unit that masks the clock for a pre-stored mask period when the oscillator starts operating; a sampling timing control unit that corrects the sampling timing based on the mask period; a reception control unit that acquires and outputs reception data based on the reception signal that has started to be input during the mask period and the corrected sampling timing; Equipped with A control device characterized by:

2. an internal oscillator that starts clock output when a received signal is input from an external device in a low power consumption mode in which clock oscillation is temporarily stopped; Furthermore, 2. The control device according to claim 1.

3. A control method executed by a control device that performs control to acquire data from a signal using a clock output by an oscillator, comprising: a clock mask control step in which a clock mask control unit of the control device masks the clock for a pre-stored mask period when the operation of the oscillator is started; a sampling timing control step in which a sampling timing control unit of the control device corrects the sampling timing based on the mask period; a reception control step in which a reception control unit of the control device acquires and outputs reception data based on the reception signal whose input has started during the mask period and the corrected sampling timing; A control method comprising:

4. Computer, A control device that performs control to acquire data from a signal using a clock output by an oscillator, a clock mask control unit that masks the clock for a pre-stored mask period when the oscillator starts operating; a sampling timing control unit that corrects the sampling timing based on the mask period; a reception control unit that acquires and outputs reception data based on the reception signal that has started to be input during the mask period and the corrected sampling timing; Equipped with a control device characterized by: A program to run as.

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