Semiconductor device and method of manufacturing semiconductor device

Abstract

To provide a technique for efficiently forming a structure in which a recessed part is provided on a top face of a first electrode layer and a second electrode layer covers the first electrode layer.SOLUTION: A semiconductor device comprises: a semiconductor substrate; a trench; a gate insulator film which covers an inner face of the trench; a gate electrode which is provided inside of the trench and insulated from the semiconductor substrate by the gate insulator film; an inter-layer insulator film which covers a top face of the gate electrode; a first electrode layer which consists of an Al alloy and covers a top face of the semiconductor substrate and the inter-layer insulator film; and a second electrode which consists of a Ni-containing metal and covers the first electrode layer. A top face of the inter-layer insulator film is positioned lower than the top face of the semiconductor substrate. On a top face of the first electrode layer, there is provided a recessed part in which a portion of an upper part in a range where the trench is formed is recessed with respect to a portion of the upper part in a range where the trench is not formed. The second electrode layer is in contact with the first electrode layer inside of the recessed part.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device having a trench and a method for manufacturing a semiconductor device having a trench.

[0002] Patent Document 1 discloses a technique for forming a Ni metal layer on the surface of an Al-Si metal layer after forming recesses in the surface of the Al-Si metal layer. This technique provides an anchor effect with the Ni metal layer filled in the recesses, thereby preventing the Ni metal layer from peeling off from the Al-Si metal layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-219828 Summary of the Invention [Problem to be solved by the invention]

[0004] In the technology of Patent Document 1, Si particles are formed on the outermost surface of an Al-Si metal layer by baking the Al-Si metal layer. Then, the Si particles are removed by etching to form micropores on the surface of the Al-Si metal layer. Then, zincate treatment is performed to enlarge the micropores, forming recesses. Thus, the technology of Patent Document 1 requires multiple steps to form recesses on the surface of the Al-Si metal layer. This specification proposes a semiconductor device structure and a manufacturing method thereof that can efficiently form a structure in which recesses are provided on the surface of a first electrode layer made of an Al alloy, and the surface of the first electrode layer is covered with a second electrode layer made of a metal containing Ni. [Means for solving the problem]

[0005] The semiconductor device disclosed in this specification includes a semiconductor substrate, a trench provided on an upper surface of the semiconductor substrate, a gate insulating film covering the inner surface of the trench, a gate electrode provided inside the trench and insulated from the semiconductor substrate by the gate insulating film, an interlayer insulating film provided inside the trench and covering an upper surface of the gate electrode, a first electrode layer made of an Al alloy and covering the upper surface of the semiconductor substrate and the interlayer insulating film, and a second electrode layer made of a metal containing Ni and covering the first electrode layer. The upper surface of the interlayer insulating film is located below the upper surface of the semiconductor substrate. The upper surface of the first electrode layer is provided with a recess, in which an upper portion of the area where the trench is formed is recessed relative to an upper portion of an area where the trench is not formed. The second electrode layer is in contact with the first electrode layer within the recess.

[0006] In this semiconductor device, the upper surface of the interlayer insulating film provided inside the trench is located lower than the upper surface of the semiconductor substrate. Therefore, a concave shape is formed by the upper surface of the semiconductor substrate, the side surface of the trench, and the upper surface of the interlayer insulating film. The first electrode layer covers the upper surface of the semiconductor substrate and the interlayer insulating film, and therefore a recess is formed on the upper surface of the first electrode layer following the concave shape. That is, the upper surface of the first electrode layer has a recess in which the upper portion of the area where the trench is formed is recessed relative to the upper portion of the area where the trench is not formed. The second electrode layer covers the first electrode layer and contacts the first electrode layer within the recess. Therefore, peeling of the second electrode layer from the first electrode layer is suppressed by an anchor effect. Furthermore, in the manufacturing process of this semiconductor device, the gate electrode and the interlayer insulating film are formed so that the upper surface of the interlayer insulating film is located lower than the upper surface of the semiconductor substrate, and then the first electrode layer is formed, thereby forming a recess in the upper surface of the first electrode layer. Therefore, by forming the second electrode layer so as to cover this recess, an anchor effect can be obtained. In this way, in this semiconductor device, the recessed structure of the first electrode layer can be formed with almost no increase in the number of steps compared to a general manufacturing process, and the semiconductor device can be manufactured efficiently. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 3] 3A to 3C are diagrams for explaining a manufacturing process of a semiconductor device according to an embodiment; [Figure 4] 3A to 3C are diagrams for explaining a manufacturing process of a semiconductor device according to an embodiment; [Figure 5] 3A to 3C are diagrams for explaining a manufacturing process of a semiconductor device according to an embodiment; [Figure 6] 3A to 3C are diagrams for explaining a manufacturing process of a semiconductor device according to an embodiment; [Figure 7] 3A to 3C are diagrams for explaining a manufacturing process of a semiconductor device according to an embodiment; [Figure 8] 3A to 3C are diagrams for explaining a manufacturing process of a semiconductor device according to an embodiment; [Figure 9] 3A to 3C are diagrams for explaining a manufacturing process of a semiconductor device according to an embodiment; [Figure 10] 3A to 3C are diagrams for explaining a manufacturing process of a semiconductor device according to an embodiment; [Figure 11] FIG. 10 is a plan view of a semiconductor device according to a first modified example. [Figure 12] FIG. 10 is a plan view of a semiconductor device according to a second modification. [Figure 13] FIG. 11 is a plan view of a semiconductor device according to a third modified example. DETAILED DESCRIPTION OF THE INVENTION

[0008] In the semiconductor device disclosed in the present specification, an example may further include an insulating layer covering the upper surface of the semiconductor substrate around the area where the trench is formed, and a length from the upper surface of the semiconductor substrate to the upper surface of the interlayer insulating film in a thickness direction of the semiconductor substrate may be greater than a thickness of the insulating layer.

[0009] With this configuration, a recessed shape having sufficient depth is formed by the upper surface of the semiconductor substrate, the side surface of the trench, and the upper surface of the interlayer insulating film, and therefore a recessed portion having sufficient depth is provided in the upper surface of the first electrode layer, which can effectively prevent the second electrode layer from peeling off from the first electrode layer.

[0010] (Example) The semiconductor device 10 of the embodiment shown in FIGS. 1 and 2 has a semiconductor substrate 12 made of SiC (i.e., silicon carbide). The semiconductor substrate 12 may be made of other semiconductor materials (e.g., Si, GaN, etc.). As shown in FIG. 1, two source electrodes 20 and four electrode pads 28 are provided on the top surface of the semiconductor device 10. The areas of the top surface of the semiconductor device 10 outside the source electrodes 20 and the electrode pads 28 are covered with a protective insulating layer 30. The semiconductor substrate 12 incorporates a MOSFET (metal-oxide-semiconductor field effect transistor). The source electrode 20 is an electrode that functions as the source of the MOSFET. The electrode pads 28 are, for example, electrode pads that control the gate voltage of the MOSFET or electrode pads that detect the temperature of the MOSFET.

[0011] As shown in FIG. 2, trenches 40 are provided on the upper surface 12a of the semiconductor substrate 12. As shown in FIGS. 1 and 2, the trenches 40 are provided on the upper surface 12a below the source electrode 20. When the semiconductor substrate 12 is viewed in the thickness direction as shown in FIG. 1, the trenches 40 extend in a lattice pattern. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, and a direction parallel to the upper surface 12a and perpendicular to the x-direction is referred to as the y-direction. The trenches 40 are composed of multiple trenches 40a extending linearly along the x-direction on the upper surface 12a and multiple trenches 40b extending linearly along the y-direction on the upper surface 12a. As shown in FIG. 2, a gate insulating film 42 and a gate electrode 44 are disposed within the trench 40. The inner surface of the trench 40 is covered with the gate insulating film 42. The gate electrode 44 is insulated from the semiconductor substrate 12 by the gate insulating film 42.

[0012] The semiconductor substrate 12 has an n-type source layer 50, a p-type body layer 52, an n-type drift layer 54, and an n-type drain layer 56. The source layer 50 is in contact with the source electrode 20 and the gate insulating film 42. The body layer 52 is disposed around the source layer 50. The body layer 52 is in contact with the source electrode 20 at a position adjacent to the source layer 50. The body layer 52 is in contact with the gate insulating film 42 below the source layer 50. The drift layer 54 is disposed below the body layer 52. The drift layer 54 is in contact with the gate insulating film 42 below the body layer 52. The drift layer 54 is separated from the source layer 50 by the body layer 52. The drain layer 56 is an n-layer having a higher n-type impurity concentration than the drift layer 54. The drain layer 56 is disposed below the drift layer 54. A drain electrode 38 is disposed on the lower surface 12b of the semiconductor substrate 12. The drift layer 54 is in contact with the drain electrode 38. The gate electrode 44, the gate insulating film 42, the source layer 50, the body layer 52, the drift layer 54, and the drain layer 56 constitute the above-mentioned MOSFET. In this manner, the MOSFET is provided below the source electrode 20. Hereinafter, the region of the semiconductor substrate 12 where the MOSFET is provided will be referred to as an element region 14. Furthermore, the region of the semiconductor substrate 12 surrounding the element region 14 will be referred to as an outer periphery region 16. As shown in FIG. 1 , the element region 14 is disposed below the source electrode 20.

[0013] 2, the upper surface of the gate electrode 44 is covered with an interlayer insulating film 43. The interlayer insulating film 43 is disposed in the trench 40. The gate electrode 44 is insulated from the source electrode 20 by the interlayer insulating film 43. The upper surface of the interlayer insulating film 43 is located lower than the upper surface 12a of the semiconductor substrate 12. Therefore, a recessed shape 46 is formed by the upper surface of the interlayer insulating film 43, the side surface of the trench 40, and the upper surface 12a of the semiconductor substrate 12. The depth of the recessed shape 46 (the length from the upper surface 12a of the semiconductor substrate 12 to the upper surface of the interlayer insulating film 43 in the thickness direction of the semiconductor substrate) is, for example, approximately 500 nm.

[0014] A peripheral insulating layer 32 is disposed on the upper surface 12a of the semiconductor substrate 12 in the peripheral region 16. The peripheral insulating layer 32 is made of silicon oxide. The thickness T of the peripheral insulating layer 32 is smaller than the depth D of the recessed shape 46.

[0015] The source electrode 20 has a first electrode layer 21 and a second electrode layer 22. The first electrode layer 21 is made of an AlSi alloy. However, the first electrode layer 21 may be made of other Al alloys (e.g., AlCu alloy, AlSiCu alloy, AlMg alloy, AlSiMg alloy, etc.). The second electrode layer 22 is made of simple Ni. However, the second electrode layer 22 may be made of other metals containing Ni (e.g., Ni alloy).

[0016] The first electrode layer 21 is distributed across the element region 14 and the peripheral region 16. The first electrode layer 21 contacts the upper surface 12a of the semiconductor substrate 12 and the upper surface of the interlayer insulating film 43 within the element region 14. As described above, the upper surface of the interlayer insulating film 43 and the upper surface 12a of the semiconductor substrate 12 form a recessed shape 46. A recess 21a extending along the recessed shape 46 is formed on the upper surface of the first electrode layer 21 within the element region 14. That is, in the recess 21a, the upper portion of the area where the trench 40 is formed is recessed relative to the upper portion of the upper surface 12a of the semiconductor substrate 12 (i.e., the area where the trench 40 is not formed). The recess 21a extends in a lattice pattern similar to the trench 40 extending in a lattice pattern in FIG. 1 . The first electrode layer 21 covers the peripheral insulating layer 32 within the peripheral region 16. The first electrode layer 21 contacts the upper surface of the peripheral insulating layer 32.

[0017] The protective insulating layer 30 is made of polyimide. As shown in FIG. 2, the protective insulating layer 30 covers the upper surfaces of the first electrode layer 21 and the peripheral insulating layer 32 in the peripheral region 16. In other words, the protective insulating layer 30 has an opening 30a, and the source electrode 20 is disposed in the opening 30a. As shown in FIG. 1, the opening 30a is rectangular, with two sides extending along the x direction and the remaining two sides extending along the y direction. When the semiconductor substrate 12 is viewed along the thickness direction as shown in FIG. 1, the trench 40 is disposed in the opening 30a. Therefore, the recess 21a provided in the upper surface of the first electrode layer 21 is disposed in the opening 30a.

[0018] The second electrode layer 22 is disposed in the opening 30a of the protective insulating layer 30. The second electrode layer 22 covers the upper surface of the first electrode layer 21 across the element region 14 and the peripheral region 16. The second electrode layer 22 is in contact with the upper surface of the first electrode layer 21 and also fills the recess 21a. That is, the second electrode layer 22 is in contact with the first electrode layer 21 on the inner surface of the recess 21a. Because the second electrode layer 22 fills the recess 21a, the second electrode layer 22 is less likely to peel off from the first electrode layer 21 due to an anchor effect. In particular, since the recess shape 46 has a sufficient depth, the recess 21a also has a sufficient depth, and therefore a significant anchor effect is obtained.

[0019] When the semiconductor device 10 is in use, the semiconductor substrate 12 repeatedly generates heat. This causes repeated thermal stress to be applied to the interface between the second electrode layer 22 and the first electrode layer 21. Repeated thermal stress applied to the interface may cause the second electrode layer 22 to peel off from the first electrode layer 21. In response to this, in this embodiment, recesses 21a are formed in a lattice pattern on the upper surface of the first electrode layer 21. The recesses 21a extend in an intersecting manner along the x and y directions, which can effectively suppress peeling of the second electrode layer 22 from the first electrode layer 21. For example, peeling of the second electrode layer 22 may tend to progress along a specific direction. When the recesses 21a extend in a lattice pattern, when peeling progresses along a specific direction, at least one of the recesses 21a extending in the x and y directions can stop the progress of the peeling.

[0020] Next, a description will be given of a method for manufacturing the semiconductor device 10. First, as shown in Fig. 3, a source layer 50, a body layer 52, a drift layer 54, and a drain layer 56 are formed in the semiconductor substrate 12 by a known method. Next, as shown in Fig. 3, a trench 40 is formed by selectively etching the top surface of the semiconductor device 10.

[0021] 4, a gate insulating film 42 is deposited using a CVD (Chemical Vapor Deposition) technique so as to cover the upper surface 12a of the semiconductor substrate 12 and the inner surface of the trench 40. Thereafter, polysilicon is deposited on the surface of the gate insulating film 42 to form a gate electrode 44.

[0022] Next, the gate electrode 44 is etched. As a result, as shown in FIG. 5 , the gate electrode 44 is removed from the upper surface 12a of the semiconductor substrate 12. The gate electrode 44 is left in the trench 40. Here, the gate electrode 44 is etched so that the upper surface of the remaining gate electrode 44 is located lower than the upper surface 12a of the semiconductor substrate 12. The gate electrode 44 is etched so that the upper surface of the remaining gate electrode 44 is located higher than the lower end of the source layer 50.

[0023] 6, an interlayer insulating film 43 is formed inside the trench 40 and on the upper part of the semiconductor substrate 12 (on the upper surface of the gate insulating film 42 covering the upper surface 12a). Next, an NSG (Non-doped Silicate Glass) film 60 and a BPSG (Boro-Phospho Silicate Glass) film 62 are formed on the upper surface of the interlayer insulating film 43. Thereafter, a resist layer 90 is formed on the BPSG film 62 by patterning. The resist layer 90 is formed so as to cover the BPSG film 62 in the peripheral region 16.

[0024] Next, as shown in FIG. 7 , the BPSG film 62, the NSG film 60, the interlayer insulating film 43, and the gate insulating film 42 are removed by etching via the resist layer 90. Here, the etching is performed so that the interlayer insulating film 43 remains inside the trench 40. The etching is also performed so that the upper surface of the interlayer insulating film 43 is positioned below the upper surface 12a of the semiconductor substrate 12. The side surfaces of the trench 40 are exposed above the interlayer insulating film 43. This forms a recessed shape 46 composed of the upper surface 12a of the semiconductor substrate 12, the side surfaces of the trench 40, and the upper surface of the interlayer insulating film 43. After etching, the resist layer 90 is removed. The BPSG film 62, the NSG film 60, the interlayer insulating film 43, and the gate insulating film 42 remaining in the peripheral region 16 become the peripheral insulating layer 32. The above-described steps are performed so that the depth of the recessed shape 46 is greater than the thickness of the peripheral insulating layer 32.

[0025] Next, as shown in FIG. 8, a first electrode layer 21 is formed over the entire upper region of the semiconductor substrate 12 by sputtering or the like. At this time, the recessed shapes 46 are filled with the first electrode layer 21. As a result, in the element region 14, recesses 21a are formed on the upper surface of the first electrode layer 21 following the recessed shapes 46. Next, a mask layer 92 is formed on the first electrode layer 21 so that the upper surface of the first electrode layer 21 in the range where the trenches 40 are not formed (the outer peripheral edge of the first electrode layer 21) is exposed, and the first electrode layer 21 is etched through the mask layer 92. As a result, the outer peripheral edge of the first electrode layer 21 is removed as shown in FIG. 9. After etching the first electrode layer 21, the mask layer 92 is removed.

[0026] 10, a protective insulating layer 30 is formed on the peripheral insulating layer 32 and the first electrode layer 21, and an opening 30a is formed in the protective insulating layer 30. Here, the opening 30a is formed so as to surround the element region 14. In other words, the opening 30a is formed so that the recess 21a is disposed within the opening 30a.

[0027] Next, as shown in FIG. 2, the second electrode layer 22 is formed by plating on the upper surface of the first electrode layer 21 in the opening 30a. The second electrode layer 22 fills the recess 21a. Therefore, the second electrode layer 22 contacts the first electrode layer 21 in the recess 21a. This makes the second electrode layer 22 less likely to peel off from the first electrode layer 21 due to an anchor effect. In addition, a drain electrode 38 is formed on the lower surface 12b of the semiconductor substrate 12. Through the above steps, the semiconductor device 10 is completed.

[0028] As described above, this manufacturing method forms a recess 46 consisting of the upper surface 12a of the semiconductor substrate 12, the side surface of the trench 40, and the upper surface of the interlayer insulating film 43, thereby forming a recess 21a in the upper surface of the first electrode layer 21 when the first electrode layer 21 is formed. Therefore, by forming the second electrode layer 22 so as to cover the recess 21a, it is possible to make the second electrode layer 22 less likely to peel off from the first electrode layer 21. Furthermore, because the trench 40 and the interlayer insulating film 43 are necessary elements in a trench-gate semiconductor device, this manufacturing method can form the recess 21a without increasing the number of steps in the manufacturing process of a typical semiconductor device. Therefore, this manufacturing method can efficiently manufacture a semiconductor device 10 in which the second electrode layer 22 is less likely to peel off from the first electrode layer 21.

[0029] In the above-described embodiment, the depth D of the recessed shape 46 is greater than the thickness T of the peripheral insulating layer 32. When the depth D of the recessed shape 46 is greater in this way, the recessed portion 21a becomes deeper. This makes it possible to more effectively prevent the second electrode layer 22 from peeling off from the first electrode layer 21. In other embodiments, the depth D of the recessed shape 46 may be equal to or less than the thickness T of the peripheral insulating layer 32.

[0030] In the above-described embodiment, the trenches 40 extend in a lattice pattern across substantially the entire device region 14 when the semiconductor substrate 12 is viewed in the thickness direction. However, as shown in FIG. 11 , for example, trenches 40 b (see FIG. 1 ) may not be provided, and multiple trenches 40 a extending parallel to one another in the x direction may be provided at intervals in the y direction. Even with this configuration, recesses 21 a are formed in the upper surface of the first electrode layer 21 above the trenches 40 a, thereby suppressing peeling of the second electrode layer 22 due to the anchor effect. Alternatively, as shown in FIG. 12 , multiple trenches 40 b extending in the y direction may be provided only in a region near the end of the device region 14 in the x direction. Alternatively, as shown in FIG. 13 , multiple trenches 40 a extending in the x direction may be provided only in a region near the end of the device region 14 in the y direction. The outer periphery of the second electrode layer 22 is more likely to peel off from the first electrode layer 21 than other portions. According to the configurations of FIGS. 12 and 13, the lattice-shaped recesses 21a are formed in at least a part of the outer periphery of the first electrode layer 21, and therefore the lattice-shaped recesses 21a can effectively provide an anchor effect.

[0031] Furthermore, in the above-described embodiment, a silicide layer made of, for example, an alloy of Ni and Si may be further provided on the upper surface 12a of the semiconductor substrate 12. The silicide layer can be formed by forming a Ni layer on the upper surface 12a of the semiconductor substrate 12 and then heat-treating the semiconductor substrate 12 before the step of forming the first electrode layer 21. Furthermore, a barrier metal made of, for example, a stacked film of Ti and TiN may be provided so as to cover the upper surface of the interlayer insulating film 43, the side surfaces of the trench 40, and the upper surface of the silicide layer (or the upper surface 12a of the semiconductor substrate 12 if no silicide layer is provided).

[0032] In the above-described embodiment, a MOSFET is formed in the element region 14. However, other switching elements (for example, IGBTs) may be formed in the element region 14.

[0033] Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of those objectives itself has technical utility. [Explanation of symbols]

[0034] 10: semiconductor device, 12: semiconductor substrate, 12a: upper surface, 12b: lower surface, 14: element region, 16: peripheral region, 20: source electrode, 21: first electrode layer, 21a: recess, 22: second electrode layer, 30: protective insulating layer, 30a: opening, 32: peripheral insulating layer, 38: drain electrode, 40: trench, 42: gate insulating film, 43: interlayer insulating film, 44: gate electrode

Claims

1. A semiconductor device (10), a semiconductor substrate (12); a trench (40) provided in the upper surface (12a) of the semiconductor substrate; a gate insulating film (42) covering the inner surface of the trench; a gate electrode (44) provided inside the trench and insulated from the semiconductor substrate by the gate insulating film; an interlayer insulating film (43) provided inside the trench and covering an upper surface of the gate electrode; a first electrode layer (21) made of an Al alloy and covering the upper surface of the semiconductor substrate and the interlayer insulating film; a second electrode layer (22) made of a metal containing Ni and covering the first electrode layer; Equipped with an upper surface of the interlayer insulating film is located below the upper surface of the semiconductor substrate; a recess (21 a) is provided on the upper surface of the first electrode layer, in which an upper portion of an area where the trench is formed is recessed relative to an upper portion of an area where the trench is not formed; the second electrode layer is in contact with the first electrode layer within the recess; Semiconductor device.

2. The semiconductor device further includes a peripheral insulating layer (32) covering the upper surface of the semiconductor substrate around the area where the trench is formed, 2. The semiconductor device according to claim 1, wherein a length from the upper surface of said semiconductor substrate to the upper surface of said interlayer insulating film in a thickness direction of said semiconductor substrate is greater than a thickness of said peripheral insulating layer.

3. A method for manufacturing a semiconductor device (10), comprising: forming a trench (40) in an upper surface (12a) of a semiconductor substrate (12); forming a gate insulating film (42) in the trench to cover the inner surface of the trench; forming a gate electrode (44) in the trench, the gate electrode being insulated from the semiconductor substrate by the gate insulating film; a step of forming an interlayer insulating film (43) covering an upper surface of the gate electrode in the trench, the step of forming the interlayer insulating film so that the upper surface of the interlayer insulating film is located lower than the upper surface of the semiconductor substrate; a step of forming a first electrode layer (21) made of an Al alloy so as to cover the upper surface of the semiconductor substrate and the interlayer insulating film, the step of forming the first electrode layer so as to form a recess (21a) on the upper surface of the first electrode layer, the upper portion of which is recessed relative to the upper portion of which is not formed with the trench; a step of forming a second electrode layer (22) made of a metal containing Ni so as to cover the first electrode layer, the step of forming the second electrode layer so as to be in contact with the first electrode layer within the recess; A manufacturing method comprising the steps of:

4. the step of forming the interlayer insulating film forming an insulating layer in the trench and on the top surface of the semiconductor substrate; etching the insulating layer so that the insulating layer covering the upper surface of the semiconductor substrate within the range in which the trench is formed is removed, the insulating layer covering the upper surface of the semiconductor substrate around the range in which the trench is formed remains as a peripheral insulating layer, the insulating layer within the trench remains as the interlayer insulating film, and the length from the upper surface of the semiconductor substrate to the upper surface of the interlayer insulating film in the thickness direction of the semiconductor substrate is greater than the thickness of the peripheral insulating layer; The method of claim 3, comprising:

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