Method of manufacturing semiconductor device and jig set

Abstract

To reduce influences of variance of warpage caused by heating an insulation circuit board.SOLUTION: A method of manufacturing a semiconductor device includes a preparation step, a positioning step and a height control step. The preparation step is a step of preparing an insulation circuit board and a cooling unit 3 including a cooling surface 30a. The positioning step is a step of storing the entire insulation circuit board within the cooling surface 30a via a joint member through a fixed region which is opened correspondingly to a size of the insulation circuit board in a planar view of a positioning jig 51 which is disposed on the cooling surface 30a of the cooling unit 3. The height control step is a step of pressing a top face of the insulation circuit board toward the cooling surface 30a via the fixed region with a pressing surface in a lower end of a control portion 52a forming a shape included in the fixed region of the positioning jig 51 in a planar view included in a height control jig 52 while pressing the positioning jig 51 to the cooling surface 30a.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device and a jig set. [Background technology]

[0002] In manufacturing a semiconductor device, a positioning jig is used to bond a semiconductor chip to a predetermined area on an insulating circuit board and to bond the insulating circuit board to a predetermined area on a heat sink, and a weight is placed on the positioning jig (see, for example, Patent Documents 1 and 2).

[0003] As an example of using a jig in manufacturing, a curved pressing member applies pressure to an insulating substrate with a conductive pattern via an inner block to solder the insulating substrate with a conductive pattern and a copper base (see, for example, Patent Document 3). Also, soldering is performed while the outer surfaces of both metal plates in the laminate are supported by a jig (see, for example, Patent Document 4). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2023-74141 [Patent Document 2] Japanese Patent Publication No. 2022-139492 [Patent Document 3] Japanese Patent Application Laid-Open No. 2013-157377 [Patent Document 4] Japanese Patent Application Laid-Open No. 2008-147218 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a method for manufacturing a semiconductor device and a jig set that reduce the influence of variations in warpage caused by heating of an insulating circuit board. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a preparation step of preparing an insulating circuit board and a cooling unit including a cooling surface; a positioning step of placing the entire insulating circuit board on the cooling surface of the cooling unit via a bonding member through a fixing area of ​​a positioning jig placed on the cooling surface of the cooling unit, the fixing area having an opening corresponding to the size of the insulating circuit board in a plan view; and a height control step of pressing the positioning jig against the cooling surface with a pressing surface at a lower end of a control portion included in a height control jig and having a shape that is included in the fixing area of ​​the positioning jig in a plan view, pressing the upper surface of the insulating circuit board against the cooling surface through the fixing area.

[0007] In the height control step, the height control jig may be pressed against the cooling surface separately from the positioning jig. In the height control step, a positioning weight may be placed on the positioning jig to load the positioning jig against the cooling surface.

[0008] In the height control step, a height control weight may be disposed on the height control jig to load the height control jig against the cooling surface. Furthermore, after the preparing step and before the positioning step, the method may further include a board setting step of inverting the height control jig, setting the fixing region of the positioning jig on the control portion of the height control jig, and setting the upper surface of the insulating circuit board on the pressing surface of the control portion through the fixing region of the positioning jig set on the height control jig; a cooling unit setting step of setting the bonding member on the upward-facing lower surface of the insulating circuit board set on the pressing surface of the height control jig and setting the cooling surface of the cooling unit on the positioning jig so as to cover the fixing region; and a re-inverting step of further inverting the height control jig, the positioning jig, the insulating circuit board, and the cooling unit.

[0009] According to another aspect of the present invention, there is provided a jig set used for positioning an insulating circuit board on a cooling surface of a cooling unit, the jig set including: a positioning jig that is placed on the cooling surface and has a fixing area that is opened to correspond to the size of the insulating circuit board in a plan view, and the insulating circuit board is entirely housed on the cooling surface through the fixing area via a bonding member; a height control jig that has a control portion that is shaped to be included in the fixing area of ​​the positioning jig and includes a pressing surface at a lower end of the control portion that presses an upper surface of the insulating circuit board against the cooling surface through the fixing area; and a positioning weight that loads the positioning jig against the cooling surface.

[0010] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Effects of the Invention]

[0011] The above-described semiconductor device manufacturing method and jig set can reduce the influence of variations in warping due to heating of the insulating circuit board, and can suppress variations in solder flow and solder thickness. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a perspective view of a semiconductor device. [Figure 2] FIG. 1 is a plan view of a semiconductor device. [Figure 3] FIG. 2 is a perspective view of a semiconductor unit included in the semiconductor device. [Figure 4] FIG. 2 is a perspective view of a cooling unit in which a semiconductor unit is disposed. [Figure 5] 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6] 1A to 1C are diagrams for explaining a semiconductor device assembly process (semiconductor unit setting) included in the semiconductor device manufacturing method of the present embodiment. [Figure 7]10A and 10B are diagrams for explaining a semiconductor device assembly step (setting of a cooling unit) included in the semiconductor device manufacturing method of the present embodiment. [Figure 8] 10A to 10C are diagrams for explaining the assembly process (re-inversion of the entire semiconductor device) of the semiconductor device included in the method for manufacturing the semiconductor device of the present embodiment. [Figure 9] 1 is a plan view of a positioning jig used in a semiconductor device assembly process included in the semiconductor device manufacturing method of the present embodiment. [Figure 10] 1 is a plan view of a height control jig used in a semiconductor device assembly process included in a semiconductor device manufacturing method according to the present embodiment. [Figure 11] 10A to 10C are diagrams for explaining the assembly process (soldering) of a semiconductor device included in the method for manufacturing a semiconductor device of a reference example. DETAILED DESCRIPTION OF THE INVENTION

[0013] FIG. 1 is a perspective view of a semiconductor device. Hereinafter, the embodiments will be described with reference to the drawings. In the present embodiment, the front surface (upper) refers to the surface (direction) of the semiconductor device 1 in FIG. 1 facing upward. For example, the sealing surfaces of the sealing members 28a, 28b, and 28c that seal the storage area surrounded by the inner walls 21a1, 21b1, 21c1, and 21d1 of the case 2 are the front surface (upper). The back surface (lower) refers to the surface (direction) facing downward in the semiconductor device 1 in FIG. 1. For example, it is the back surface (lower) of the case 2. The front surface (upper) and the back surface (lower) refer to the same directionality in cases other than FIG. 1.

[0014] The semiconductor device 1 of the present embodiment will be described with reference to Fig. 1. Fig. 1 is a perspective view of the semiconductor device 1 of the first embodiment. Note that in Fig. 1, only the main components are labeled with reference numerals. Although not shown, an output side region, an intermediate region, and an input side region are defined on the sealing surface of each of the sealing members 28a, 28b, and 28c.

[0015] As shown in FIG. 1, the semiconductor device 1 includes a semiconductor unit (not shown), a case 2 that houses the semiconductor unit, and a cooling unit 3 (not shown in FIG. 1, see FIG. 4) that has the semiconductor unit disposed on the back surface of the case 2. Details of the semiconductor unit will be described later. The case 2 has a generally rectangular shape in a plan view and includes long sides 21a and 21c and short sides 21b and 21d. The case 2 includes inner walls 21a1 and 21c1 along the long sides 21a and 21c. The inner walls 21a1 and 21c1 are partitioned by partitions 21e and 21f, respectively. The partitions 21e and 21f are arranged parallel to the short sides 21b and 21d and perpendicular to the long sides 21a and 21c. The three storage areas surrounded by the inner walls 21a1, 21b1, 21c1, and 21d1 each store a semiconductor unit, and are sealed by sealing members 28a, 28b, and 28c, respectively.

[0016] Sealing members 28a, 28b, and 28c seal the semiconductor units arranged in three storage areas surrounded by inner walls 21a1, 21b1, 21c1, and 21d1. Sealing members 28a, 28b, and 28c are made of a thermosetting resin mixed with a filler. Examples of thermosetting resins include epoxy resin, phenolic resin, maleimide resin, and polyester resin. The filler is an insulating ceramic with high thermal conductivity. Examples of such fillers include silicon oxide, aluminum oxide, boron nitride, and aluminum nitride. The filler content is 10% by volume or more and 70% by volume or less of the entire sealing members 28a, 28b, and 28c.

[0017] The case 2 also includes positive terminals 22a, 22b, and 22c and negative terminals 23a, 23b, and 23c along the long side 21a. The case 2 also includes a U terminal 24a, a V terminal 24b, and a W terminal 24c along the long side 21c on the front surface of the case 2. The positive terminal 22a, the negative terminal 23a, and the U terminal 24a are disposed with a sealing member 28a interposed therebetween. The case 2 also includes a control terminal 25a between the U terminal 24a and an inner wall 21c1 adjacent to the sealing member 28a. The positive terminal 22b, the negative terminal 23b, and the V terminal 24b are disposed with a sealing member 28b interposed therebetween. The case 2 also includes a control terminal 25b between the V terminal 24b and an inner wall 21c1 adjacent to the sealing member 28b. Positive electrode terminal 22c, negative electrode terminal 23c, and W terminal 24c are provided with sealing member 28c sandwiched therebetween. Furthermore, case 2 is provided with control terminal 25c between inner wall 21c1 adjacent to sealing member 28c and W terminal 24c. Note that the other ends of control terminals 25a, 25b, and 25c are each electrically connected to the gate electrodes of the semiconductor chips of the semiconductor units housed in case 2. Furthermore, the other ends of U terminal 24a, V terminal 24b, and W terminal 24c are each electrically connected to the emitter electrodes (or source electrodes) of the semiconductor chips of the semiconductor units.

[0018] Fig. 2 is a plan view of the semiconductor device. The case 2 includes a frame 20, positive terminals 22a, 22b, and 22c, negative terminals 23a, 23b, and 23c, U, V, and W terminals 24a, 24b, and 24c, control terminals 25a, 25b, and 25c, printed circuit boards 26a, 26b, and 26c, storage areas 27a, 27b, and 27c, and semiconductor units 4a, 4b, and 4c. Note that the reference numerals for the control terminals 25a, 25b, and 25c are omitted in Fig. 2.

[0019] The frame portion 20 has a flat plate shape. The storage areas 27a, 27b, and 27c are storage areas surrounded by inner walls 21a1, 21b1, 21c1, and 21d1, respectively. The storage areas 27a, 27b, and 27c store the semiconductor units 4a, 4b, and 4c. The shapes of the storage areas 27a, 27b, and 27c in a plan view correspond to the shapes of the insulating circuit boards of the semiconductor units 4a, 4b, and 4c, which will be described later. In the present embodiment, the storage areas 27a, 27b, and 27c have one inner wall surface (for example, the inner wall surface of the inner wall 21a1) shorter than the other inner wall surface (for example, the inner wall surface of the inner wall 21b1). However, this is not limiting and the storage areas may have a substantially rectangular shape.

[0020] The frame 20 is formed by injection molding, in which the positive terminals 22a, 22b, and 22c, the negative terminals 23a, 23b, and 23c, the U, V, and W terminals 24a, 24b, and 24c, the control terminals 25a, 25b, and 25c, and the printed circuit boards 26a, 26b, and 26c are placed in a mold and then filled with a thermoplastic resin containing a filler. Examples of such resins include polyphenylene sulfide (PPS) resin, polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, polyamide (PA) resin, and acrylonitrile butadiene styrene (ABS) resin. The filler is silicon oxide, aluminum oxide, boron nitride, or aluminum nitride. In particular, the frame 20 is made of a PPS resin containing one of these fillers.

[0021] Positive electrode terminals 22a, 22b, and 22c are integrally molded along long side 21a of frame 20, corresponding to storage areas 27a, 27b, and 27c (inner wall 21a1), respectively. Positive electrode terminals 22a, 22b, and 22c have internal connection portions 22a1, 22b1, and 22c1 at their ends. Internal connection portions 22a1, 22b1, and 22c1 are flat and protrude from inner wall 21a1 into storage areas 27a, 27b, and 27c, respectively, parallel to inner walls 21b1 and 21d1.

[0022] The negative electrode terminals 23a, 23b, and 23c are integrally formed along the long side 21a of the frame 20, corresponding to the storage areas 27a, 27b, and 27c (inner wall 21a1). The negative electrode terminals 23a, 23b, and 23c are adjacent to the positive electrode terminals 22a, 22b, and 22c, respectively. The negative electrode terminals 23a, 23b, and 23c protrude outward further than the positive electrode terminals 22a, 22b, and 22c. The negative electrode terminals 23a, 23b, and 23c have internal terminals 23a1, 23b1, and 23c1 at their ends. The internal terminals 23a1, 23b1, and 23c1 are flat and protrude from the inner wall 21a1 into the storage areas 27a, 27b, and 27c parallel to the inner walls 21b1 and 21d1, respectively. The internal terminals 23a1, 23b1, and 23c1 are also adjacent to the internal connection portions 22a1, 22b1, and 22c1, respectively.

[0023] The U, V, and W terminals 24a, 24b, and 24c are integrally molded on the front surface of the frame 20 along the long side 21c, corresponding to the storage areas 27a, 27b, and 27c (inner wall 21c1), respectively. The U, V, and W terminals 24a, 24b, and 24c have U, V, and W connecting portions 24a1, 24b1, and 24c1 at their ends. The U, V, and W connecting portions 24a1, 24b1, and 24c1 are flat and protrude from approximately the center of the inner wall 21c1 into the storage areas 27a, 27b, and 27c, respectively, parallel to the inner walls 21b1 and 21d1. The U, V, and W connecting portions 24a1, 24b1, and 24c1 face the internal terminals 23a1, 23b1, and 23c1, respectively, across the storage areas 27a, 27b, and 27c.

[0024] Each of the control terminals 25a, 25b, and 25c is rod-shaped and has a circular or rectangular cross section. A plurality of such control terminals 25a, 25b, and 25c are formed along and extending upward near the inner wall 21c1 of the storage areas 27a, 27b, and 27c on the front surface of the frame 20.

[0025] The positive electrode terminals 22a, 22b, 22c, the negative electrode terminals 23a, 23b, 23c, the U, V, W terminals 24a, 24b, 24c, and the control terminals 25a, 25b, 25c are made of a material with excellent conductivity. Examples of such materials include copper, aluminum, and alloys containing at least one of these. To improve corrosion resistance, the surfaces of the positive electrode terminals 22a, 22b, 22c, the negative electrode terminals 23a, 23b, 23c, the U, V, W terminals 24a, 24b, 24c, and the control terminals 25a, 25b, 25c may be plated with a material such as nickel. Specifically, nickel-phosphorus alloys and nickel-boron alloys may be used in addition to nickel.

[0026] The printed circuit boards 26a, 26b, and 26c are flat and are provided at the corners of the storage areas 27a, 27b, and 27c, respectively, on the inner wall 21c1 corresponding to the U, V, and W connection portions 24a1, 24b1, and 24c1 of the storage areas 27a, 27b, and 27c. The printed circuit boards 26a, 26b, and 26c have a multilayer structure in which an insulating layer and a circuit layer made of a conductive material are laminated on the insulating layer. The insulating layer is primarily composed of glass epoxy resin or phenolic resin. The conductive material of the circuit layer is primarily composed of copper, for example. The surfaces of the printed circuit boards 26a, 26b, and 26c are further covered with a highly heat-resistant resist film material, and a plurality of electrodes electrically connected to the circuit layer are arranged on the front surface. The printed circuit boards 26a, 26b, and 26c also have a plurality of through-holes formed therein. The control terminals 25a, 25b, and 25c are inserted into the through holes, respectively. In this case, the control terminals 25a, 25b, and 25c are fixed to the through holes with solder and electrically connected to the printed circuit boards 26a, 26b, and 26c. Alternatively, the control terminals 25a, 25b, and 25c may be press-fitted into the through holes. The control terminals 25a, 25b, and 25c are inserted into the through holes within the frame 20. Such printed circuit boards 26a, 26b, and 26c are also integrally formed with the frame 20.

[0027] The semiconductor unit 4a housed in the case 2 and the printed circuit board 26a are wired together by a bonding wire. At the inner wall 21c1 of the case 2 housing the semiconductor unit 4a, the gate electrode of the semiconductor chip of the semiconductor unit 4a and the printed circuit board 26a are electrically connected by a bonding wire. Similarly, at the inner wall 21c1 of the case 2 housing the semiconductor unit 4b, the printed circuit board 26b and the gate electrode of the semiconductor unit 4b are electrically connected by a bonding wire. Furthermore, the printed circuit board 26c and the gate electrode of the semiconductor unit 4c are electrically connected by a bonding wire.

[0028] Next, semiconductor units 4a, 4b, and 4c will be described. Fig. 3 is a perspective view of a semiconductor unit included in a semiconductor device. Semiconductor unit 4 includes an insulating circuit board 41, lead frames 45a, 45b, 45c, and 45d, and semiconductor chips 46a, 46b, 46c, and 46d arranged on the front surface of insulating circuit board 41 via a predetermined bonding member. Semiconductor units 4a, 4b, and 4c have the same structure as semiconductor unit 4.

[0029] The insulating circuit board 41 includes an insulating plate 42, conductive circuit patterns 43a, 43b, and 43c provided on the front surface of the insulating plate 42, and a metal plate 44 provided on the back surface of the insulating plate 42. The corners of the insulating plate 42 and the metal plate 44 may be rounded or C-chamfered. The size of the metal plate 44 is smaller than the size of the insulating plate 42 in a plan view, and is formed inside the insulating plate 42. The insulating plate 42 is made of a material that has insulating properties, low thermal resistance, and excellent thermal conductivity. The insulating plate 42 is made of ceramics. Ceramics include aluminum oxide, aluminum nitride, and silicon nitride.

[0030] The conductive circuit patterns 43a, 43b, and 43c are made of a material with excellent conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. The conductive circuit patterns 43a, 43b, and 43c can also be plated with a material with excellent corrosion resistance. Examples of such materials include nickel or an alloy containing nickel. Specific examples include nickel, nickel-phosphorus alloy, and nickel-boron alloy. The number, arrangement, and shape of the conductive circuit patterns 43a, 43b, and 43c shown in FIG. 3 are merely examples, and the number, arrangement, and shape can be selected appropriately according to the design.

[0031] The metal plate 44 is made of a metal with excellent thermal conductivity. Examples of such materials include copper, aluminum, and alloys containing at least one of these. To improve corrosion resistance, a material such as nickel may be formed on the surface of the metal plate 44 by plating or the like. Specific examples of such materials include nickel-phosphorus alloys and nickel-boron alloys in addition to nickel.

[0032] Such an insulating circuit board 41 is formed, for example, as follows. First, the metal plate 44, the insulating plate 42, and the conductive plate are stacked in this order, and then heated and pressed in the stacking direction to compress and bond them together. This compression bonding is performed in an activated gas atmosphere or in a vacuum. Then, the conductive plate is masked with a photosensitive resist mask to match a predetermined pattern, and the pattern is formed by etching. The photosensitive resist mask is then removed to form the conductive circuit patterns 43a, 43b, and 43c.

[0033] The lead frames 45a, 45b, 45c, and 45d are made of a material with excellent conductivity. Examples of such materials include copper, aluminum, and alloys containing at least one of these. To improve corrosion resistance, nickel or other materials may be plated on the surfaces of the lead frames 45a, 45b, 45c, and 45d. Specifically, nickel, nickel-phosphorus alloys, nickel-boron alloys, and other materials may be used. Each of the lead frames 45a, 45b, 45c, and 45d includes a joint with the semiconductor chip 46a, 46b, 46c, or 46d, a joint with the conductive circuit pattern 43a, or 43c, and a wiring portion connecting these joints. The joints of the lead frames 45a, 45b, 45c, and 45d with the corresponding semiconductor chip 46a, 46b, 46c, or 46d are joined to the negative electrodes on the front surfaces of the semiconductor chips via a bonding member. The joints of the lead frames 45a, 45b, 45c, and 45d with the corresponding conductive circuit patterns 43a and 43c are joined to the conductive circuit patterns 43a and 43b via joining materials. The wiring portions electrically connect the joints on the semiconductor chip side to the joints on the conductive circuit patterns. Each wiring portion is positioned parallel to the front surface of the insulating circuit board 41.

[0034] The semiconductor chips 46a, 46b, 46c, and 46d are power devices made of silicon. The semiconductor chips 46a, 46b, 46c, and 46d are RC (Reverse Conducting)-IGBTs (Integrated Gate Bipolar Transistors). The RC-IGBTs are configured with an IGBT, which is a switching element, and an FWD, which is a diode element, integrated into a single chip. Each of the semiconductor chips 46a, 46b, 46c, and 46d has, for example, a collector electrode (positive electrode) as a main electrode on the back surface and a gate electrode (control electrode) and an emitter electrode (negative electrode) as main electrodes on the front surface. Alternatively, the two semiconductor chips 46a and 46b (or the two semiconductor chips 46c and 46d) may each include a switching element and a diode element. In this case, the switching element may be a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT, or the like. Each of the semiconductor chips 46a, 46b (or 46c, 46d) has, for example, a drain electrode (positive electrode, collector electrode in an IGBT) as a main electrode on the back surface, and a gate electrode (control electrode) and a source electrode (negative electrode, emitter electrode in an IGBT) as main electrodes on the front surface. The diode element is a FWD such as an SBD (Schottky Barrier Diode) or a PiN (P-intrinsic-N) diode. Alternatively, the semiconductor chips 46a, 46b, 46c, 46d may be a power MOSFET mainly composed of silicon carbide. In a power MOSFET, the body diode may function as the FWD. Each of the semiconductor chips 46a, 46b, 46c, 46d has, for example, an input electrode (drain electrode) as a main electrode on the back surface, and an output electrode (source electrode) and a control electrode (gate electrode) as main electrodes on the front surface. Such semiconductor chips 46a and 46b (or semiconductor chips 46c and 46d) each have a cathode electrode as a main electrode on the back surface and an anode electrode as a main electrode on the front surface.The backsides of the semiconductor chips 46a, 46b, 46c, and 46d are bonded to the predetermined conductive circuit patterns 43a and 43c using a bonding material. The bonding material is solder or a sintered body. The solder is a lead-free solder primarily composed of a predetermined alloy. The predetermined alloy may be, for example, at least one of a tin-silver-copper alloy, a tin-zinc-bismuth alloy, a tin-copper alloy, and a tin-silver-indium-bismuth alloy. The solder may contain additives such as nickel, germanium, cobalt, or silicon. The sintering material used for sintering is, for example, powder of silver, iron, copper, aluminum, titanium, nickel, tungsten, or molybdenum. The illustrated example shows a case where a set of semiconductor chips 46a, 46b, 46c, and 46d is arranged on the insulating circuit board 41 shown in FIG. 3. However, this example is not limiting, and multiple sets may be arranged as needed.

[0035] FIG. 4 is a perspective view of a cooling unit in which a semiconductor unit is disposed. The cooling unit 3 includes a flat, substantially rectangular top plate 30 in a plan view. The top plate 30 of the cooling unit 3 is rectangular and has a larger area than the combined area of ​​the storage areas 27a, 27b, and 27c of the case 2 in a plan view. The top plate 30 of the cooling unit 3 is made of a metal with excellent thermal conductivity. Examples of such materials include aluminum, iron, silver, copper, or an alloy containing at least one of these. Examples of such alloys include metal composites such as aluminum-silicon nitride (Al-SiC) or magnesium-silicon nitride (Mg-SiC). To improve corrosion resistance, the surface of the top plate 30 may be plated with a material such as nickel. Examples of nickel-based materials include nickel-phosphorus alloys and nickel-boron alloys. The top plate 30 may be substantially rectangular, and as shown in FIG. 4, mounting holes for inserting screws may be formed along the corners and sides of the top plate 30, and portions with mounting holes may also be provided.

[0036] The cooling unit 3 may include a plurality of fins formed on the surface opposite the cooling surface 30a of the top plate 30, and a housing that houses the plurality of fins and is provided on the surface opposite the cooling surface 30a. In such a cooling unit 3 called a closed fin type, a refrigerant is circulated inside the housing to cool the semiconductor units 4 on the top plate 30. Alternatively, the cooling unit 3 may not include a housing, but may include a plurality of fins formed on the surface opposite the cooling surface 30a of the top plate 30. In such a cooling unit 3 called an open fin type, air passes between the plurality of fins to cool the semiconductor units 4 on the top plate 30.

[0037] The semiconductor units 4a, 4b, and 4c are arranged on the top plate 30 of the cooling unit 3 via bonding members so as to correspond to the storage areas 27a, 27b, and 27c, respectively. The bonding members (not shown) may be, for example, solder, brazing filler metal, or thermal interface material (TIM). Lead-free solder is used as the solder. The brazing filler metal is primarily composed of, for example, at least one of an aluminum alloy, a titanium alloy, a magnesium alloy, a zirconium alloy, and a silicon alloy. The TIM may be, for example, an elastomer sheet, RTV (Room Temperature Vulcanization) rubber, a gel, or a phase change material. The case 2 is arranged on the top plate 30 on which the semiconductor units 4a, 4b, and 4c are arranged so that the semiconductor units 4a, 4b, and 4c are accommodated in the storage areas 27a, 27c, and 27b. The case 2 is bonded to the top plate 30 with a predetermined adhesive.

[0038] In the semiconductor unit 4a housed in the housing region 27a, the internal terminal 23a1 is electrically connected to the conductive circuit pattern 43b via a block portion (not shown). The internal connection portion 22a1 is electrically connected to the conductive circuit pattern 43c via a block portion. Furthermore, the U connection portion 24a1 is electrically connected to the conductive circuit pattern 43a via a block portion. Similarly, in the semiconductor unit 4b housed in the housing region 27b, the internal terminal 23b1 is electrically connected to the conductive circuit pattern 43b via a block portion. The internal connection portion 22b1 is electrically connected to the conductive circuit pattern 43c via a block portion. Furthermore, the V connection portion 24b1 is electrically connected to the conductive circuit pattern 43a via a block portion. Similarly, in the semiconductor unit 4c housed in the housing region 27c, the internal terminal 23c1 is electrically connected to the conductive circuit pattern 43b via a block portion. The internal connection portion 22c1 is electrically connected to the conductive circuit pattern 43c via a block portion. Furthermore, the W connection portion 24c1 is electrically connected to the conductive circuit pattern 43a via the block portion. The block portion is made of a material with excellent conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. The thickness of the block portion corresponds to the gap between each connection portion and each circuit pattern. To improve corrosion resistance, a material such as nickel may be formed on the surface of the block portion by plating. Specific examples of such materials include nickel-phosphorus alloys and nickel-boron alloys in addition to nickel.

[0039] Next, a method for manufacturing such a semiconductor device 1 will be described with reference to Fig. 5. Fig. 5 is a flowchart showing the method for manufacturing a semiconductor device according to this embodiment. First, a preparation step P1 is performed in which components required for the semiconductor device 1 are prepared. In the preparation step P1, a semiconductor chip, an insulating circuit board, a case 2, raw materials for a sealing member, a lead frame, and a cooling unit 3 including a top plate 30 are prepared as examples of the required components.

[0040] Next, an assembly process P2 for the semiconductor units 4a, 4b, and 4c is performed. In the assembly process P2, first, the semiconductor chips 46a, 46b, 46c, and 46d are arranged, for example, via solder plates, at predetermined locations on the conductive circuit patterns 43a and 43c of the insulating circuit board 41. Furthermore, the lead frames 45a, 45b, 45c, and 45d are also arranged via solder plates. Next, the solder plates are heated to melt the solder plates, and then cooled. The semiconductor chips 46a, 46b, 46c, and 46d and the lead frames 45a, 45b, 45c, and 45d are joined to the insulating circuit board 41 with solder, which serves as a joining material. This completes the assembly of the semiconductor units 4a, 4b, and 4c, which have a structure similar to that of the semiconductor unit 4 shown in FIG. 4. Furthermore, in the insulating circuit board 41, the linear expansion coefficient of the insulating plate 42 is smaller than that of the conductive circuit patterns 43a, 43b, and 43c and the metal plate 44 formed on the insulating plate 42. Furthermore, the volume of metal plate 44 formed on the back surface of insulating plate 42 is larger than the conductive circuit patterns 43a, 43b, and 43c formed on the front surface of insulating plate 42. For this reason, heating and cooling in assembly process P2 causes insulating circuit board 41 included in semiconductor unit 4 to warp downward in a convex shape, with the back surface of insulating plate 42 facing downward.

[0041] Next, an assembly process P3 of the semiconductor device 1 is performed. The assembly process P3 is a process of attaching the semiconductor units 4a, 4b, and 4c to the cooling unit 3 and storing the semiconductor units 4a, 4b, and 4c provided in the cooling unit 3 in the case 2. The assembly process P3 includes a process P3a of inverting the assembly jig set, a process P3b of setting the semiconductor units, a process P3c of setting the cooling unit 3, a process P3d of re-inverting the entire assembly, and a process P3e of soldering the semiconductor units to the cooling surface 30a of the cooling unit 3. The details of the processes P3a, P3b, P3c, P3d, and P3e will be described later.

[0042] Next, a wiring step P4 is carried out in which the semiconductor units 4a, 4b, and 4c housed in the case 2 are wired to the printed circuit boards 26a, 26b, and 26c using bonding wires. Then, a sealing step P5 is carried out in which the storage areas 27a, 27b, and 27c of the case 2 are filled with the raw material of the sealing members and sealed with the sealing members 28a, 28b, and 28c.

[0043] Next, a process P3a for inverting the assembly jig set and a process P3b for setting the semiconductor unit will be specifically described. Fig. 6 is a diagram for explaining the semiconductor device assembly process (setting the semiconductor unit) included in the semiconductor device manufacturing method of the present embodiment.

[0044] In process P3a, the assembly jig set 5 is set and then turned upside down. The assembly jig set 5 is set with a positioning jig 51, a height control jig 52, a height control weight 53, and a positioning weight 54, in that order from the bottom up. Each jig will be described later. The assembly jig set 5 set in this manner is then turned upside down, with the positioning jig 51 positioned on the top layer.

[0045] In step P3b, an assembly jig set 5 that has been inverted upside down in step P3a is used. FIG. 6 shows the assembly jig set 5 after step P3b and the semiconductor unit 4 set in the assembly jig set 5. The inverted assembly jig set 5 includes, from top to bottom, a positioning jig 51, a height control jig 52, a height control weight 53, and a positioning weight 54. The positioning jig 51 and the height control jig 52 are preferably made of a heat-resistant material with a small linear expansion coefficient, such as a carbon material. The height control weight 53 and the positioning weight 54 are made of a material that is heavier than the positioning jig 51 and the height control jig 52.

[0046] The positioning jig 51 is a jig for positioning the semiconductor unit 4 with respect to the top plate 30. That is, the positioning jig 51 determines the positions of the semiconductor units 4a, 4b, and 4c on the top plate 30 so that they correspond to the storage areas 27a, 27b, and 27c, respectively. Such a positioning jig 51 may be rectangular in plan view, or may be frame-shaped including a fixing area 51a that is an opening area shaped to correspond to the outer shape of the semiconductor unit 4 (see FIG. 9, which will be described later). Furthermore, the positioning jig 51 may have a recess into which a guide of a positioning weight 54, which will be described later, fits, formed at a position corresponding to the guide.

[0047] The height control jig 52 controls the height of the semiconductor unit 4 by pressing the semiconductor unit 4 from the upper side (the semiconductor chips 46a, 46b, 46c, and 46d side) to the lower side (the metal plate 44 side). The height control jig 52 may have the same external shape as the positioning jig 51 in a plan view. The height control jig 52 also includes a control portion 52a including a pressing surface 52b that presses the upper side of the semiconductor unit 4 (see FIG. 8 , which will be described later). For example, the control portion 52a may correspond to the opening shape of the fixing region 51a of the positioning jig 51 in a plan view. The height control jig 52 may have through holes, through which guides of a positioning weight 54, which will be described later, are inserted, formed at positions corresponding to the guides. As described above, the entire assembly jig set 5 is upside down in FIG. 6 . The height control weight 53 is a weight that loads the height control jig 52 . The positioning weight 54 is a weight that loads the positioning jig 51 .

[0048] For example, the positioning weight 54 and the positioning jig 51 are connected by a guide. A clearance, which will be described later, between the jigs can be maintained depending on the length of this guide. The positioning weight 54 can directly load the positioning jig 51 via this guide. Between the positioning weight 54 and the positioning jig 51, the height control weight 53 and the height control jig 52 are inserted into the guide. The height control weight 53 can directly load the height control jig 52 along the guide.

[0049] Next, a specific description will be given of step P3c of setting the cooling unit 3. Fig. 7 is a diagram for explaining the assembly step (setting of the cooling unit) of the semiconductor device included in the manufacturing method of the semiconductor device of the present embodiment.

[0050] In process P3c, the solidified solder 31 in a plate shape is placed on the back surface (metal plate 44) side (upper side in FIG. 7) of the semiconductor unit 4, and the cooling unit 3 is placed on the top side of the assembly jig set 5 that has been turned upside down so that the cooling surface 30a of the top plate 30 of the cooling unit 3 faces downward. The cooling surface 30a may also be referred to as the placement surface.

[0051] Next, the step P3d of re-inverting the entire structure will be described in detail. Figure 8 is a diagram for explaining the step of assembling a semiconductor device (re-inverting the entire structure) included in the method for manufacturing a semiconductor device according to this embodiment.

[0052] In process P3d, the entire assembly jig set 5 and cooling unit 3 are turned upside down from the state after process P3c. The semiconductor unit 4 is then placed on the cooling surface 30a of the top plate 30 via the solder 31. The installation position of the semiconductor unit 4 relative to the cooling surface 30a is fixed by the positioning jig 51 and the positioning weight 54. The height control jig 52 moves downward along the guide under the load of the height control weight 53. The control portion 52a of the height control jig 52 then contacts the semiconductor unit 4 at the pressing surface 52b, which is the lower end of the control portion 52a. That is, the control portion 52a contacts the portion of the semiconductor unit 4 that protrudes above the cooling surface 30a due to warping, at the pressing surface 52b. The height control jig 52 can control the height of the semiconductor unit 4 by pressing the semiconductor unit 4 downward with the pressing surface 52b due to the load of the height control weight 53. The height control by the height control jig 52 will be described later.

[0053] Here, as shown in Figure 8, the thickness of the control portion 52a of the height control jig 52 is greater than the thickness of the portion through which the guide of the height control jig 52 is inserted, and the pressing surface 52b can be positioned below the upper surface of the positioning jig 51.

[0054] The amount of clearance 60, which is a gap provided to allow the height control jig 52 to move up and down along the guide, is set to a length that can absorb variations in warpage of the semiconductor units 4. The amount of such clearance 60 is 0.60 mm or more and 0.70 mm or less, for example, 0.65 mm.

[0055] FIG. 9 is a plan view of a positioning jig used in the semiconductor device assembly process included in the semiconductor device manufacturing method of this embodiment. FIG. 9 illustrates the positioning jig 51 arranged on the cooling unit 3 as shown in FIG. 8 , viewed from above to below along the Z axis. Also, FIG. 9 does not illustrate the height control jig 52, height control weight 53, and positioning weight 54. The positioning jig 51 is a rectangular frame having a fixing region 51a corresponding to the shape of the semiconductor unit 4. The semiconductor unit 4 can be fitted into the fixing region 51a. The fixing region 51a may also be referred to as an opening region. For example, recesses in which guides are provided may be formed at the four corners of the positioning jig 51. The cross-sectional view II in FIG. 9 corresponds to FIGS. 6 to 8.

[0056] Fig. 10 is a plan view of a height control jig used in the assembly process of a semiconductor device included in the semiconductor device manufacturing method of the present embodiment. Fig. 10 shows height control jig 52 arranged on cooling unit 3 as shown in Fig. 8, viewed from above to below the Z axis. Height control weight 53 and positioning weight 54 are not shown in Fig. 10.

[0057] As shown in FIG. 10 , the area of ​​height control jig 52 in a plan view may be larger than the area of ​​positioning jig 51 in a plan view. Furthermore, control portion 52a has the shape of fixing region 51a of positioning jig 51 in a plan view. Furthermore, height control jig 52 may have storage portions 52c at positions corresponding to lead frames 45a, 45b, 45c, and 45d. Storage portion 52c stores lead frames 45a, 45b, 45c, and 45d. When height control jig 52 presses semiconductor unit 4 from above, storage portion 52c stores lead frames 45a, 45b, 45c, and 45d, allowing height control jig 52 to appropriately apply the load of height control weight 53 to insulating circuit board 41. Therefore, height control jig 52 can appropriately control the height of insulating circuit board 41.

[0058] Here, a reference example of a semiconductor device manufacturing method will be described. FIG. 11 is a diagram for explaining the semiconductor device assembly process (soldering) included in the semiconductor device manufacturing method of the reference example. Note that in FIG. 11, the semiconductor unit 4 is shown in a simplified form. In the reference example, when performing the semiconductor device assembly process P3, the assembly jig set 5 of the embodiment is not used, and an inner frame jig 500 integrally formed from a carbon material or the like is used as a positioning jig. The inner frame jig 500 has four side walls surrounding the sides of a space in which the semiconductor unit 4 is to be placed on a predetermined region on the cooling surface 30a of the top plate 30, and a ceiling portion covering the upper surface of the space. In addition, a weight 510 is placed on the upper side of the inner frame jig 500.

[0059] In assembly process P3 of the reference example, the semiconductor unit 4 is set on the cooling surface 30a of the cooling unit 3 via the plate-shaped solidified solder 31. Then, the inner frame jig 500 is set on the cooling surface 30a, covering the semiconductor unit 4, and process P3e is performed. When the insulating circuit board 41 of the semiconductor unit 4 is joined to the cooling surface 30a of the cooling unit 3 with the solder 31 in process P3e, warping may occur in the insulating circuit board 41 due to heating. Here, FIG. 11(A) shows the warpage w1 and height h of the semiconductor unit 4 before joining the semiconductor unit 4 to the top plate 30 with the solder 31. The warpage w1 of the semiconductor unit 4 is the maximum value of the height of each point on the top surface of the semiconductor unit 4 from the cooling surface 30a. The warpage w1 of the semiconductor unit 4 may also be referred to as the warpage of the insulating circuit board 41. The warpage of the semiconductor unit 4 corresponds to the height of the semiconductor unit 4 or the height of the insulating circuit board 41. The height h is the length from the cooling surface 30a to the ceiling of the inner frame jig 500 when the inner frame jig 500 is placed on the cooling surface 30a. <hである。

[0060] The amount of warping caused by heat varies among individual insulating circuit boards 41. For this reason, if inner frame jig 500 with fixed dimensions is used for different insulating circuit boards 41, the following problems may occur.

[0061] FIG. 11(B-1) illustrates an example in which the amount of warpage w2 of the semiconductor unit 4 (or the insulating circuit board 41) is greater than the height h (w2>h). When w2>h, the warpage of the semiconductor unit 4 causes the inner frame jig 500 to be lifted, creating a gap between the inner frame jig 500 and the cooling surface 30a. This causes the molten solder 31 to flow out of the inner frame jig 500 through this gap. This increases the likelihood that, for example, the thickness of the solder 31 cannot be maintained locally sufficiently, resulting in a decrease in the heat dissipation performance of the semiconductor unit 4. It also increases the likelihood that the flowed-out solder 31 will adhere to the surrounding area.

[0062] FIG. 11(B-2) illustrates the case where the warpage amount w3 of the semiconductor unit 4 (or the insulating circuit board 41) is smaller than the height h (w3 < h). When w3 < h, a gap (gap amount = h - w3) occurs between the inside of the middle frame jig 500 and the semiconductor unit 4 (insulating circuit board 41). Then, the semiconductor unit 4 (insulating circuit board 41) tilts (that is, the insulating circuit board 41 plays freely inside the middle frame jig 500), and variations occur in the thickness (solder thickness) of the solder 31 used for bonding. As a result, variations also occur in the heat dissipation performance of the semiconductor unit 4, and the possibility of causing a decrease in the heat dissipation performance of the semiconductor unit 4 increases. Thus, the middle frame jig 500 with fixed dimensions cannot follow the variations in the heating warpage of the insulating circuit board 41.

[0063] Therefore, in the manufacturing method of the semiconductor device 1 of the present embodiment (particularly, step P3e), as illustrated in FIG. 8, instead of the middle frame jig 500, two divided jigs, that is, the positioning jig 51 and the height control jig 52 are used, so that it becomes possible to follow the variations in the heating warpage of the insulating circuit board 41. According to the assembly jig set 5 including the positioning jig 51 and the height control jig 52, a jig structure capable of following the variations in the heating warpage of the insulating circuit board 41 is realized.

[0064] The positioning jig 51 positions the semiconductor unit 4 (insulating circuit board 41) and suppresses the solder flow. The height control jig 52 controls the height of the semiconductor unit 4 (insulating circuit board 41) by the load of the height control weight 53. Furthermore, by dividing the weight into two, that is, the height control weight 53 and the positioning weight 54 instead of using one weight, the positioning jig 51 is loaded by the positioning weight 54, and the occurrence of a gap between the cooling surface 30a and the positioning jig 51 can be preferably suppressed.

[0065] In this way, assembly jig set 5 including positioning jig 51 and height control jig 52 can realize a jig structure that can absorb variations in thermal warpage of insulating circuit board 41. This reduces solder flow below insulating circuit board 41 and reduces variations in solder thickness below insulating circuit board 41.

[0066] For example, if the warpage of the insulating circuit board 41 is relatively large, the positioning jig 51 comes into contact with the cooling surface 30a, so no gap occurs. The positioning weight 54 can directly load the positioning jig 51 via a guide. This reduces the possibility of a gap occurring between the positioning jig 51 and the cooling surface 30a, and reduces poor solder flow.

[0067] Furthermore, when the warpage of the insulating circuit board 41 is relatively small, the height control jig 52 comes into contact with the semiconductor unit 4 (insulating circuit board 41), and the height control jig 52 allows the height control weight 53 to apply a load to the semiconductor unit 4 (insulating circuit board 41). This prevents the inclination of the semiconductor unit 4 (insulating circuit board 41) (difference in height of the periphery), reducing variations in the solder thickness.

[0068] As described above, the manufacturing method of the semiconductor device 1 includes, for example, a preparation step, a positioning step, and a height control step. The preparation step is a step of preparing the insulating circuit board 41 and the cooling unit 3 including the cooling surface 30a. The positioning step is a step of fitting the entire insulating circuit board 41 to the cooling surface 30a of the cooling unit 3 via a bonding material through a fixing area 51a of a positioning jig 51 arranged on the cooling surface 30a of the cooling unit 3, the fixing area 51a having an opening corresponding to the size of the insulating circuit board 41 in a plan view. The bonding material is, for example, solder 31. The height control step is a step of pressing the positioning jig 51 against the cooling surface 30a while pressing the upper surface of the insulating circuit board 41 against the cooling surface 30a through the fixing area 51a with a pressing surface at the lower end of a control portion 52a included in the height control jig 52 and having a shape that is included in the fixing area 51a of the positioning jig 51 in a plan view. This reduces the effect of variations in warpage of the insulating circuit board 41 due to heating.

[0069] For example, the height control step includes pressing a height control jig 52 against the cooling surface 30a, separate from the positioning jig 51. This allows the height of the insulating circuit board 41 to be appropriately controlled, reducing variations in the solder thickness and reducing deterioration in the heat dissipation performance of the semiconductor unit 4.

[0070] The height control step also includes placing a positioning weight (positioning weight 54) on the positioning jig 51 and applying a load to the positioning jig 51 against the cooling surface 30a. This prevents a gap from occurring between the positioning jig 51 and the cooling surface 30a, reducing defects due to solder flow.

[0071] The height control step also includes placing a height control weight 53 on the height control jig 52 and applying a load to the cooling surface 30a of the height control jig 52. This allows the height of the insulating circuit board 41 to be more appropriately controlled, and reduces the possibility that the heat dissipation performance of the semiconductor unit 4 will be reduced due to variations in solder thickness.

[0072] Furthermore, the manufacturing method of the semiconductor device 1 may include the following substrate setting step, cooling unit setting step, and re-inversion step after the preparation step and before the positioning step. The substrate setting process is a process in which the height control jig 52 is inverted, the fixing area 51a of the positioning jig 51 is set on the control part 52a of the height control jig 52, and the upper surface of the insulating circuit board 41 is set on the pressing surface 52b of the control part 52a through the fixing area 51a of the positioning jig 51 set on the height control jig 52. The cooling unit setting process is a process in which a joining member (solder 31) is set on the upward-facing underside of the insulating circuit board 41 set on the pressing surface 52b of the height control jig 52, and the cooling surface 30a of the cooling unit 3 is set on the positioning jig 51, covering the fixed area 51a. The re-inversion step is a step in which the height control jig 52, the positioning jig 51, the insulating circuit board 41, and the cooling unit 3 are further inverted. This allows the positioning jig 51 to be appropriately positioned on the cooling surface 30a, and also allows the insulating circuit board 41 to be placed on the cooling surface 30a so that height control by the height control jig 52 can be effectively performed. Therefore, when the case 2 is attached to the cooling surface 30a on which the semiconductor unit 4 (insulating circuit board 41) is placed, the semiconductor unit 4 can be reliably stored in the storage areas 27a, 27b, and 27c of the case 2.

[0073] As described above, the assembly jig set 5 used to position the insulating circuit board 41 on the cooling surface 30a of the cooling unit 3 includes a positioning jig 51, a height control jig 52, and a positioning weight (positioning weight 54). The positioning jig 51 is placed on the cooling surface 30a and has a fixing area 51a that is opened to correspond to the size of the insulating circuit board 41 in a plan view. The entire insulating circuit board 41 is accommodated on the cooling surface 30a through the fixing area 51a via a bonding member. The height control jig 52 has a control portion 52a that is shaped to be included in the fixing area 51a of the positioning jig 51, and includes a pressing surface 52b at the bottom of the control portion 52a that presses the upper surface of the insulating circuit board 41 toward the cooling surface 30a through the fixing area 51a. The positioning weight (positioning weight 54) loads the positioning jig 51 toward the cooling surface 30a. This reduces the influence of variations in warpage of the insulating circuit board 41 due to heating, and reduces the deterioration of the heat dissipation performance of the semiconductor unit 4 (insulating circuit board 41). [Explanation of symbols]

[0074] 1. Semiconductor device 2 cases 3 Cooling Unit 4, 4a, 4b, 4c Semiconductor unit 5 Assembly jig set 20 Frame 21a, 21c Long side 21a1,21b1,21c1,21d1 Inner wall 21b, 21d Short side 21e, 21f Partition 22a,22b,22c Positive terminal 22a1, 22b1, 22c1 Internal connection 23a,23b,23c Negative terminal 23a1,23b1,23c1 Internal terminal 24a U terminal 24a1 U connection part 24b V terminal 24b1 V connection 24c W terminal 24c1 W connection part 25a, 25b, 25c control terminals 26a, 26b, 26c Printed circuit board 27a, 27b, 27c Storage area 28a, 28b, 28c Sealing member 30 Top plate 30a Cooling surface (placement surface) 31 Solder 41 Insulated circuit board 42 Insulating plate 43a, 43b, 43c Conductive circuit patterns 44 Metal plate 45a, 45b, 45c, 45d Lead frame 46a, 46b, 46c, 46d Semiconductor chips 51 Positioning jig 51a Fixed area (opening area) 52 Height control jig 52a Control section 52b Pressing surface 52c Storage area 53 Height control weight 54 Positioning weight 60 Clearance

Claims

1. providing an insulating circuit board and a cooling unit including a cooling surface; a positioning step of placing the entire insulating circuit board on the cooling surface of the cooling unit via a bonding member through a fixing area of ​​a positioning jig that is disposed on the cooling surface of the cooling unit and that has an opening corresponding to the size of the insulating circuit board in a plan view; a height control step in which, while pressing the positioning jig against the cooling surface, a pressing surface at a lower end of a control portion included in the height control jig and having a shape that is included in the fixing region of the positioning jig in a plan view presses the upper surface of the insulating circuit board against the cooling surface through the fixing region; A method for manufacturing a semiconductor device having the above structure.

2. In the height control step, the height control jig is pressed against the cooling surface separately from the positioning jig. The method for manufacturing a semiconductor device according to claim 1 .

3. In the height control step, a positioning weight is placed on the positioning jig, and the positioning jig is loaded onto the cooling surface. The method for manufacturing a semiconductor device according to claim 1 .

4. In the height control step, a height control weight is disposed on the height control jig, and the height control jig is loaded against the cooling surface. The method for manufacturing a semiconductor device according to claim 1 .

5. After the preparing step and before the positioning step, a substrate setting process of inverting the height control jig, setting the fixing region of the positioning jig onto the control portion of the height control jig, and setting the upper surface of the insulating circuit board onto the pressing surface of the control portion through the fixing region of the positioning jig set on the height control jig; a cooling unit setting step of setting the bonding member on the upwardly facing underside of the insulating circuit board set on the pressing surface of the height control jig, and setting the cooling surface of the cooling unit on the positioning jig to cover the fixing area; a re-inversion step of further inverting the height control jig, the positioning jig, the insulating circuit board, and the cooling unit; The method for manufacturing a semiconductor device according to claim 1 , further comprising:

6. A jig set used for positioning an insulating circuit board on a cooling surface of a cooling unit, comprising: a positioning jig that is placed on the cooling surface and has a fixing area that is opened to correspond to the size of the insulating circuit board in a plan view, and the insulating circuit board is entirely housed on the cooling surface through the fixing area via a joining member; a height control jig having a control portion shaped to be included in the fixing region of the positioning jig, the control portion including a pressing surface at a lower end thereof that presses the upper surface of the insulating circuit board toward the cooling surface through the fixing region; a positioning weight that loads the positioning jig toward the cooling surface; A jig set having:

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