Fan-out type wafer level package unit

Abstract

To provide a structure of a fan-out type wafer level package unit.SOLUTION: In a fan-out type wafer level package unit 1, each conductive line 50 is configured by filling metal paste in a plurality of first recesses 31 in a first dielectric layer 30 and a plurality of second recesses 41 in a second dielectric layer 40, one end of the conductive line 50 is electrically connected to a plurality of die pads 21 of a die 20, and the other end forms one solder pad 51 in a plurality of openings 61 of an outer protective layer 60 and is exposed to the outside. At least one of solder pads is located at the periphery of a die area of a second surface 20b of the die 20. The die 20 is electrically connected to the outside through each die pad 21, each conductive line 50, and each solder pad.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a structure of a die package unit, and particularly to a structure of a fan-out type wafer level package unit. [Background technology]

[0002] Lightweight, thin, compact, highly efficient, and reliable packaging technologies are a trend in the semiconductor industry, with fan-out wafer-level packaging (FOWLP) being a traditional packaging technology. In FOWLP, an advanced packaging technology, the redistribution layer (RDL) is crucial because each conductive line in the RDL provides electrical extension and interconnection in the XY plane to multiple die pads on the die, allowing for relatively dispersed solder pads around the die, thereby effectively improving the design space and reliability of each conductive line. However, the key issue is how to ensure that each conductive line in the RDL provides electrical extension and interconnection in the XY plane while maintaining or achieving a certain level of lightness, thinness, and compactness. However, the conductive lines in the RDL technology used in traditional FOWLP packaging are formed using chemical plating or electroplating. In addition to the relatively high material and manufacturing costs, the manufacturing processes in the prior art also do not meet environmental protection requirements or are unfavorable to environmental protection, so further improvements are needed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-140973 Summary of the Invention [Problem to be solved by the invention]

[0004] The primary objective of the present invention is to provide a FOWLP unit structure, which includes a substrate, a die, a first dielectric layer, a second dielectric layer, a plurality of conductive lines, and an outer protective layer. Each of the conductive lines is formed by filling a plurality of first recesses in the first dielectric layer and a plurality of second recesses in the second dielectric layer with a metal paste. One end of each conductive line electrically connects to a plurality of die pads on the die. The other end of each conductive line is exposed to the outside through a plurality of openings in the outer protective layer, and a solder pad is formed in each of the openings. At least one of the solder pads is located around the die area on the second surface of the die, forming a FOWLP unit. The die is electrically connected to the outside through each of the die pads, each of the conductive lines, and each of the solder pads, which effectively solves the relatively high manufacturing costs and environmentally unfriendly problems associated with conventional FOWLP technology when manufacturing conductive lines. [Means for solving the problem]

[0005] To achieve the above objectives, the present invention provides a FOWLP unit. The FOWLP unit includes a substrate, a die, a first dielectric layer, a second dielectric layer, several conductive lines, and an external protective layer. The die is separated from a wafer, and the die has a first surface and an opposing second surface. The first surface of the die is fixedly mounted on the substrate, and the second surface of the die has a plurality of die pads, and the vertical extent of the second surface of the die is defined as a die area. The first dielectric layer is mounted on the substrate and the second surface of the die. The first dielectric layer has a plurality of first recesses extending horizontally. Each of the die pads of the die is exposed to the outside through each of the first recesses. The second dielectric layer is mounted on the first dielectric layer, and the second dielectric layer has a plurality of second recesses extending horizontally. Each of the second recesses communicates with each of the first recesses. Each of the conductive lines is formed by filling a metal paste into each of the first recesses and each of the second recesses, and each of the conductive lines is electrically connected to each of the die pads of the die. The outer protective layer is disposed on the second dielectric layer, and the outer protective layer has a plurality of openings, at least one of which is located around the die area on the second surface of the die. Each of the conductive lines is exposed to the outside through each of the openings, and each of the openings forms a solder pad. The die is electrically connected to the outside through each of the die pads, each of the conductive lines, and each of the solder pads located around the die area on the second surface of the die, thereby forming the FOWLP unit. The manufacturing method for the FOWLP unit 1 includes the following steps: Step S1: providing a substrate; Step S2: placing a plurality of dies separated from at least one wafer on the substrate with a gap therebetween. Wherein, each die has a first surface and an opposite second surface, the first surface of each die is mounted on the substrate 10, the second surface of each die has a plurality of die pads on it, and the vertical range of the second surface of the die is defined as a die area. Step S3: Dispose a first dielectric layer on the substrate and the second surface of each die.Step S4: A plurality of first recesses are formed on the first dielectric layer, extending horizontally, and each of the die pads of each die can be exposed to the outside through each of the first recesses. Step S5: A second dielectric layer is disposed on the first dielectric layer. Step S6: A plurality of second recesses are formed on the second dielectric layer, extending horizontally, and each of the second recesses is connected to each of the first recesses. Step S7: A metal paste is filled into each of the first recesses and each of the second recesses, and the thickness of the metal paste is made higher than the surface of the second dielectric layer. Step S8: The metal paste, now higher than the surface of the second dielectric layer, is polished to make the surface of the metal paste flat with the surface of the second dielectric layer, thereby forming a plurality of conductive lines. Step S9: An outer protective layer is disposed on the second dielectric layer. Step S10: A plurality of openings are formed in the outer protective layer, at least one of which is formed around the die region on the second surface of the die. Thereby, each of the conductive lines can be exposed to the outside through each of the openings, and one solder pad is formed within each of the openings.Step S11: A dividing operation is performed to divide and form a plurality of FOWLP units.

[0006] In one best embodiment of the present invention, the substrate includes a silicon substrate, a glass substrate or a ceramic substrate.

[0007] In one best embodiment of the present invention, the metal paste includes silver paste, nano-silver paste, copper paste or nano-copper paste.

[0008] In one preferred embodiment of the present invention, the first surface of the die is further fixed to the substrate using a die attach film (DAF).

[0009] In one best embodiment of the present invention, one solder ball is further provided on each of the openings, and each of the solder balls is electrically connected to each of the solder pads in each of the openings, so that the FOWLP unit can be electrically connected to one printed circuit board (PCB) through each of the solder balls. [Effects of the Invention]

[0010] The manufacturing process of the present invention is not only relatively simple, but also cost-effective, and can effectively improve the use efficiency and reliability of the FOWLP unit and solve the problem of environmental unfriendliness. Furthermore, the conductive lines 50 in the RDL of the present invention can provide electrical extension and interconnection in the XY plane, while still maintaining or achieving the specific effects of light weight, thinness, and small size of the FOWLP unit 1 to some extent. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 10 is a side cross-sectional view of the FOWLP unit of the present invention being installed on a printed circuit board. [Figure 2] FIG. 1 is a side cross-sectional view of the die of the present invention being mounted on a substrate. [Figure 3] FIG. 2 is a cross-sectional side view of the placement of a first dielectric layer of the present invention over the substrate and the second surface of the die. [Figure 4] FIG. 2 is a cross-sectional side view of the second dielectric layer of the present invention being placed over the first dielectric layer. [Figure 5] 10 is a side cross-sectional view of injecting a metal paste into the first recess and the second recess of the present invention. FIG. [Figure 6] 6 is a side cross-sectional view of polishing the metal paste on the surface of the second dielectric layer of FIG. 5. FIG. [Figure 7] 1 is a side cross-sectional view of forming a plurality of openings in the outer protective layer of the present invention. [Figure 8] FIG. 2 is a side cross-sectional view of the FOWLP unit of the present invention. DETAILED DESCRIPTION OF THE INVENTION [Example]

[0012] As shown in FIG. 1, the present invention provides a fan-out wafer level packaging (FOWLP) unit 1, which includes a substrate 10, a die 20, a first dielectric layer 30, a second dielectric layer 40, several conductive lines 50, and an outer protective layer 60.

[0013] As shown in FIG. 2, the substrate 10 includes, but is not limited to, a silicon (Si) substrate, a glass substrate, or a ceramic substrate.

[0014] 2, the die 20 is separated from a wafer, and has a first surface 20a and an opposing second surface 20b. The first surface 20a of the die 20 is fixedly mounted on the substrate 10, and the second surface 20b of the die 20 has a plurality of die pads 21, and the vertical range of the die on the second surface 20b is defined as a die area 1a. The die 20 shown in FIG. 2 will be described using two die pads 21 as an example.

[0015] 3, a first dielectric layer 30 is disposed on the substrate 10 and the second surface 20b of the die 20. The first dielectric layer 30 has a plurality of first recesses 31 extending horizontally, wherein each of the die pads 21 of the die 20 is exposed to the outside through each of the first recesses 31.

[0016] 4, the second dielectric layer 40 is disposed on the first dielectric layer 30, and the second dielectric layer 40 has a plurality of second recesses 41 extending horizontally. Each of the second recesses 41 communicates with each of the first recesses 31.

[0017] Each conductive line 50 is formed by filling a metal paste 50a into each first recess 31 and each second recess 41. As shown in Figure 6, each conductive line 50 is electrically connected to each die pad 21 of the die 20. The metal paste 50a can be, but is not limited to, silver paste, nano silver paste, copper paste, or nano copper paste. The nano silver paste has low cost, high conductivity, and can be sintered at a low temperature.

[0018] 7, the outer protective layer 60 is disposed on the second dielectric layer 40, and the outer protective layer 60 has a plurality of openings 61, at least one of which is located around the die area 1a on the second surface 20b of the die 20. As shown in FIG. 7, each of the conductive lines 50 is exposed to the outside through each of the openings 61, and one solder pad 51 is formed within each of the openings 61. In the following description, the number of openings 61 provided in the outer protective layer 60 in FIG. 7 is four.

[0019] As shown in FIG. 7, the die 20 is electrically connected to the outside through the die pads 21, the conductive lines 50, and the solder pads 51 around the die area 1a located on the second surface 20b of the die 20, thereby forming the FOWLP unit 1.

[0020] The method for manufacturing the FOWLP unit 1 of the present invention includes the following steps.

[0021] Step S1: As shown in FIG. 2, a substrate 10 is provided.

[0022] Step S2: As shown in Figure 2, a plurality of dies 20 obtained by dividing at least one wafer are fixedly mounted on the substrate 10 at intervals. In Figure 2, the dies 20 mounted on the substrate 10 are described by taking one of the dies 20 as an example. As shown in Figure 2, each die 20 has a first surface 20a and an opposite second surface 20b. The first surface 20a of each die 20 is mounted on the substrate 10, and the second surface 20b of each die 20 has a plurality of die pads 21 on it. The vertical range of the second surface 20b of the die is defined as a die area 1a.

[0023] Step S3: As shown in FIG. 3, a first dielectric layer 30 is disposed on the substrate 10 and the second surface 20b of each of the dies 20.

[0024] Step S4: As shown in FIG. 3, a plurality of first recesses 31 are formed on the first dielectric layer 30, extending horizontally, and the die pads 21 of the dies 20 are exposed to the outside through the first recesses 31.

[0025] Step S5: As shown in FIG. 4, a second dielectric layer 40 is disposed on the first dielectric layer 30.

[0026] Step S6: As shown in FIG. 4, a plurality of second recesses 41 are formed on the second dielectric layer 40 to extend horizontally, and each of the second recesses 41 communicates with each of the first recesses 31.

[0027] Step S7: As shown in FIG. 5, fill one metal paste 50a into each of the first recesses 31 and each of the second recesses 41, and if the thickness of the metal paste 50a is higher than the surface of the second dielectric layer 40, it indicates that the metal paste 50a has completely filled each of the first recesses 31 and each of the second recesses 41.

[0028] Step S8: As shown in FIG. 6, the metal paste 50a, which is now higher than the surface of the second dielectric layer 40, is polished so that the surface of the metal paste 50a is flush with the surface of the second dielectric layer 40, thereby forming a plurality of conductive lines 50.

[0029] Step S9: As shown in FIG. 7, an outer protective layer 60 is disposed on the second dielectric layer 40.

[0030] 7, the outer protective layer 60 is formed with a plurality of openings 61, at least one of which is formed around the die area 1a on the second surface 20b of the die 20. This allows each of the conductive lines 50 to be exposed to the outside through each of the openings 61, and each of the openings 61 has one solder pad 51 formed therein.

[0031] Step S11: As shown in Fig. 7, a dividing operation is performed to divide and form a plurality of FOWLP units 1. Each of the FOWLP units 1 shown in Fig. 7 will be described by taking one FOWLP unit 1 as an example.

[0032] The manufacturing process from step S3 to step S10 of the FOWLP unit 1 is considered to be the most important step in fabricating the RDL of the FOWLP unit 1. Among them, step S4 forms a plurality of horizontally extending first recesses 31 on the first dielectric layer 30, and step S6 forms a plurality of horizontally extending second recesses 41 on the second dielectric layer 40. In step S7, a metal paste 50a is filled into each of the first recesses 31 and each of the second recesses 41. In step S8, the metal paste 50a, which is elevated above the surface of the second dielectric layer 40, is polished to make the surface of the metal paste 50a flush with the surface of the second dielectric layer 40, thereby forming a plurality of conductive lines 50. Steps S4 to S8 are all manufacturing processes that are easy to carry out precisely, so the manufacturing process can be relatively simplified, and each conductive line 50 in the RDL can produce the effect of electrical extension and interconnection in the XY plane direction, while the FOWLP unit 1 can still maintain or achieve a certain degree of light weight, thinness, and small size.

[0033] As shown in FIG. 2, the first surface 20a of the die 20 is further fixed onto the substrate 10 using a die attach film 70.

[0034] As shown in FIG. 8, one solder ball 80 is further provided on each of the openings 61, but is not limited thereto, and each of the solder balls 80 is electrically connected to each of the solder pads 51 in each of the openings 61.

[0035] As shown in FIG. 1, the FOWLP unit 1 can be electrically connected to and installed on a single printed circuit board 2 through the solder balls 80, but is not limited thereto.

[0036] Comparing the FOWLP unit 1 of the present invention with the conventional FOWLP unit technology, it has the following advantages:

[0037] (1) Steps S3 to S10 of the manufacturing method of the present invention are all simple and easy to perform precisely, which can particularly effectively reduce the thickness of the FOWLP unit 1. Therefore, the manufacturing process of the present invention is not only relatively simple, but also cost-effective, and can effectively improve the usage efficiency and reliability of the FOWLP unit 1.

[0038] (2) The method for forming the conductive lines 50 of the present invention can effectively solve the problems of relatively high manufacturing costs and environmental disadvantages that arise when manufacturing the conductive lines using the conventional FOWLP.

[0039] The above description is a preferred embodiment showing the technical features of the present invention, and those skilled in the art can make changes and modifications without departing from the spirit of the present invention, and these changes and modifications are included in the scope of the claims of the present invention. [Explanation of symbols]

[0040] 1 Fan-out type wafer level package unit 1a Die Area 10 Substrate 20 Die 20a Front page 20b Second side 21 Die pad 30 First dielectric layer 31 First Recess 40 Second dielectric layer 41st Nirecess 50 Conductive Line 50a metal paste 60 outer protective layer 61 Aperture 70 Die attach film 80 solder balls 2. Printed circuit board

Claims

1. a substrate, a die, a first dielectric layer, a second dielectric layer, several conductive lines, and an outer protective layer; The die is separated from a wafer, and the die has a first surface and an opposite second surface, the first surface of the die is fixedly mounted on the substrate, the second surface of the die has a plurality of die pads on it, and the vertical range of the die on the second surface is defined as a die area; the first dielectric layer is disposed on the substrate and the second surface of the die, the first dielectric layer having a plurality of first recesses extending horizontally, and each of the die pads of the die is exposed to the outside through each of the first recesses; the second dielectric layer is disposed on the first dielectric layer, the second dielectric layer having a plurality of second recesses extending horizontally, each second recess communicating with each first recess; Each of the conductive lines is formed by filling a metal paste into each of the first recesses and each of the second recesses, and each of the conductive lines is electrically connected to each of the die pads of the die; and the outer protective layer is disposed on the second dielectric layer, the outer protective layer has a plurality of openings, at least one of which is located around the die area on the second surface of the die, wherein each of the conductive lines is exposed to the outside through each of the openings, and each of the openings forms a solder pad; the die is electrically connected to the outside through each of the die pads, each of the conductive lines, and each of the solder pads around the die area located on the second surface of the die, thereby forming the FOWLP unit; The method for manufacturing the FOWLP unit includes the following steps: Step S1: Provide a substrate; Step S2: Place a plurality of dies separated from at least one wafer on the substrate at intervals, where each die has a first surface and an opposite second surface, the first surface of each die is placed on the substrate, the second surface of each die has a plurality of die pads, and the vertical range of the die on the second surface is defined as a die area; Step S3: disposing a first dielectric layer on the substrate and the second surface of each of the dies; Step S4: forming a plurality of first recesses extending horizontally on the first dielectric layer, and exposing the die pads of the dies to the outside through the first recesses; Step S5: disposing a second dielectric layer on the first dielectric layer; Step S6: forming a plurality of second recesses on the second dielectric layer, the second recesses extending in a horizontal direction, and each second recess is connected to each first recess; Step S7: filling one metal paste into each of the first recesses and each of the second recesses, and making the thickness of the metal paste higher than the surface of the second dielectric layer; Step S8: polishing the metal paste that is higher than the surface of the second dielectric layer so that the surface of the metal paste is flat with the surface of the second dielectric layer, thereby forming a plurality of conductive lines; Step S9: placing an outer protective layer on the second dielectric layer; Step S10: forming a plurality of openings in the outer protective layer, at least one of which is formed around the die area on the second surface of the die, so that each of the conductive lines can be exposed to the outside through each of the openings, and forming one solder pad in each of the openings; and Step S11: A dividing operation is performed to divide and form a plurality of FOWLP units, forming a fan-out type wafer level package unit.

2. 2. The structure of the FOWLP unit as claimed in claim 1, wherein the substrate comprises a silicon (Si) substrate, a glass substrate or a ceramic substrate.

3. 2. The structure of claim 1, wherein the metal paste comprises silver paste, nano-silver paste, copper paste, or nano-copper paste.

4. 2. The structure of claim 1, wherein the first surface of the die is further attached to the substrate using a die attach film.

5. 2. The structure of the FOWLP unit according to claim 1, further comprising a solder ball provided on each of said openings, each of said solder balls being electrically connectable with each of said solder pads in each of said openings.

6. 6. The structure of claim 5, wherein the fan-out type wafer level package unit can be electrically connected to one printed circuit board through each of the solder balls.

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