Power unit

Abstract

To provide a power unit which includes a voltage doubler rectifying / smoothing circuit by which fixed output voltage is obtained irrespective of input voltage and setting of the output voltage can be easily changed.SOLUTION: A transformer comprises a winding 26 for voltage generation where a ground terminal 26g is connected with a first ground line 36, and in an oscillation terminal 26s, rectangular wave voltage Vs oscillating in a positive direction and a negative direction based on the first ground line 36 is generated. A power unit comprises an auxiliary switch 56 inserted into a position in series with a coupling capacitor 32a of a voltage doubler rectifying / smoothing circuit 32. The power unit comprises a switch control circuit 58 which performs control for holding the auxiliary switch 56 in an off state at least in a specific period of a period Tb in which the rectangular wave voltage Vs oscillates in the negative direction. Rise of both end voltage Vc of the coupling capacitor 32a to the fixed or higher level is inhibited and output voltage Vo3 generated in a smoothing capacitor 32d of the voltage doubler rectifying / smoothing circuit 32 is held at a target value Vr by the control of the switch control circuit 58.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power supply device equipped with a voltage doubler rectifying and smoothing circuit that rectifies the voltage generated by a winding of a transformer to generate a DC voltage. [Background technology]

[0002] <Conventional power supply device 10> Conventionally, there has been a power supply device, such as the power supply device 10 shown in FIG. 25, that includes a main DC-DC converter 12 that outputs a constant output voltage Vo1 to an external load 16 (such as a user device) and an auxiliary DC-DC converter 14 that outputs output voltages Vo2 and Vo3 to internal loads 18a and 18b (such as a control circuit within the power supply device 10).

[0003] The main DC-DC converter 12 is a device that converts the input voltage Vi supplied from the input power supply 20 into a constant output voltage Vo1, and operates to maintain the output voltage Vo1 at a constant value (target value). The main DC-DC converter 12 may be either a switching regulator or a series regulator.

[0004] The auxiliary DC-DC converter 14 is a switching regulator and includes a switching element 22 that interrupts the input voltage Vi to generate an interrupted input voltage, and a transformer 28 having an input winding 24 and a voltage generation winding 26 (output winding).The auxiliary DC-DC converter 14 further includes a rectifying and smoothing circuit 30 that rectifies and smooths the square-wave voltage Vs generated in the voltage generation winding 26 to generate an output voltage Vo2, a voltage doubler rectifying and smoothing circuit 32 that rectifies and smooths the square-wave voltage Vs to generate an output voltage Vo3, and a drive circuit 34 that turns the switching element 22 on and off so that the output voltage Vo2 becomes a constant value (target value).

[0005] The output side circuit of the auxiliary DC-DC converter 14, sandwiching the transformer 28, has a first ground line 36 which serves as the reference potential for the output voltages Vo1 and Vo2, and a second ground line 38 which serves as the reference potential for the output voltage Vo3. In the case of the auxiliary DC-DC converter 14, the second ground line 38 is the line through which the output voltage Vo1 of the main DC-DC converter 12 is output, and a certain voltage difference Vg21 (=Vo1) occurs with respect to the first ground line 36.

[0006] The voltage generating winding 26 of the transformer 28 has an amplitude terminal 26s and a ground terminal 26g, and the ground terminal 26g is connected to a first ground line 36. The rectifying and smoothing circuit 30 is connected between the amplitude terminal 26s and the first ground line 36, and the voltage doubler rectifying and smoothing circuit 32 is connected between the amplitude terminal 26s and a second ground line 38.

[0007] The rectifying and smoothing circuit 30, which is composed of a diode 30a and a capacitor 30b, generates an output voltage Vo2 by peak-holding the positive peak value +Va [Va>0] of the square-wave voltage Vs during a period Ta when the switching element 22 is off and the square-wave voltage Vs is oscillating in the positive direction. The output voltage Vo2 is maintained at a constant value by the operation of the drive circuit 34, so the positive peak value +Va remains constant. Conversely, the negative peak value -Vb [Vb>0] generated during a period Tb when the switching element 22 is on and the square-wave voltage Vs is oscillating in the negative direction fluctuates approximately in proportion to the input voltage Vi.

[0008] The voltage doubler rectifying and smoothing circuit 32 includes a coupling capacitor 32a having one end connected to the amplitude terminal 26s of the voltage generating winding 26, a potential setting diode 32b having an anode connected to the second ground line 38 and a cathode connected to the other end of the coupling capacitor 32a, and a rectifying diode 32c having an anode connected to the other end of the coupling capacitor 32a.The voltage doubler rectifying and smoothing circuit 32 also includes a smoothing capacitor 32d having one end on the high-voltage side connected to the cathode of the rectifying diode 32b and one end on the low-voltage side connected to the second ground line 38, and an output voltage Vo3 is generated across the smoothing capacitor 32d.

[0009] Next, the operation of the voltage doubler rectifying and smoothing circuit 32 and its peripheral circuitry will be described with reference to Figures 26(a) and 26(b). Here, when the potential of the first ground line 36 is used as the reference potential, the voltage at the anode of the rectifying diode 32c is referred to as the pre-rectification voltage Ve1, and the voltage at the cathode of the rectifying diode 32c is referred to as the post-rectification voltage Ve2. The following description will be made assuming that the forward voltage of each diode is sufficiently small. This assumption also applies to the description of each embodiment of the present invention described below.

[0010] First, the operation during period Tb(k) will be explained. Just before the end of period Ta(k-1), which precedes period Tb(k), the voltage Vc across coupling capacitor 32a is slightly lower than its steady-state value.

[0011] When period Ta(k-1) ends and period Tb(k) begins, square wave voltage Vs decreases from +Va to -Vb at a predetermined slope, and during this time, potential setting diode 32b turns on and rectifier diode 32c turns off, causing a current to flow in the circuit shown by the dashed arrow in Figure 26(a). When square wave voltage Vs reaches -Vb, the current stops flowing, and the voltage Vc across coupling capacitor 32a at the end of period Tb(k) becomes Vb + Vg21.

[0012] When period Tb(k) ends and period Ta(k) begins, square-wave voltage Vs rises from -Vb to +Va at a predetermined slope. During this time, potential-setting diode 32b turns off and rectifier diode 32c turns on, causing current to flow through the circuit shown by the dashed arrows in FIG. 26(b). When square-wave voltage Vs reaches +Va, current stops flowing (or becomes very small), pre-rectification voltage Vel becomes Vc+Va, rectification voltage V2 becomes Ve1, and output voltage V03 becomes Va+Vc-Vg21=Va+Vb. Power is then supplied to internal load 18b, and just before period Ta(k) ends, output voltage V03 drops slightly from Va+Vb, and end-to-end voltage Vc also drops slightly from Vb+Vg21.

[0013] After the period Ta(k), the same operation is repeated in the order of the period Tb(k+1), the period Ta(k+1), the period Tb(k+2), and so on, thereby generating a DC output voltage Vo3≈Va+Vb.

[0014] The problem here is that when the input voltage Vi fluctuates, the output voltage Vo3 fluctuates because the negative peak value -Vb included in the equation, output voltage Vo3 ≈ Va + Vb, fluctuates approximately in proportion to the input voltage Vi.

[0015] This problem will be explained using operating waveforms and specific numerical examples. Figure 27(a) shows the operating waveforms when the input voltage Vi is relatively low. The square-wave voltage Vs has a positive peak value +Va of 5V, a negative peak value -Vb of -10V, and a voltage difference Vg21 of 30V, so the output voltage Vo3 = Va + Vb = 5V + 10V = 15V. Figure 27(b) shows the operating waveforms when the input voltage Vi is relatively high (approximately doubled). The negative peak value -Vb changes from -10V to -20V, and the output voltage Vo3 = Va + Vb = 5V + 15V = 25V.

[0016] In this way, the auxiliary DC-DC converter 14 of the power supply device 10 causes the output voltage Vo3 supplied to the internal load 18b to fluctuate depending on the input voltage Vi, so some kind of countermeasure is necessary, especially when the range of the input voltage Vi is wide.

[0017] Note that the smoothing capacitor 32d of the voltage doubler rectifying and smoothing circuit 32 may have one end on the low voltage side connected to the first ground line 36. In this case, the basic operation is the same, and the voltage difference between the one end on the high voltage side of the smoothing capacitor 32d and the second ground line 38 becomes equal to the output voltage Vo3, and a voltage equal to the sum of the output voltages Vo1 and Vo3 is generated across the smoothing capacitor 32d. <Conventional power supply device 40> 28, there has been a power supply device that includes a main DC-DC converter 42 that outputs a constant output voltage Vo1 to an external load 16 (such as a user device), and that is configured so that this main DC-DC converter 42 also outputs output voltages Vo2 and Vo3 to internal loads 18a and 18b (such as a control circuit within the power supply device 40). In the following description of power supply device 40, components that are similar to those of the above-described power supply device 10 will be assigned the same reference numerals.

[0018] The main DC-DC converter 42 is a switching regulator and includes a switching element 22 that interrupts the input voltage Vi to generate an interrupted input voltage, and a transformer 46 having an input winding 24, an output winding 44, and a voltage generating winding 26. The converter also includes a rectifying and smoothing circuit 48 that rectifies and smooths the square-wave voltage Vss generated in the output winding 44 to generate an output voltage Vo1, and a drive circuit 50 that turns the switching element 22 on and off so that the output voltage Vo1 remains at a constant value (target value). The converter also includes a rectifying and smoothing circuit 30 that rectifies and smooths the square-wave voltage Vs generated in the voltage generating winding 26 to generate an output voltage Vo2, and a voltage doubler rectifying and smoothing circuit 52 that rectifies and smooths the square-wave voltage Vs to generate an output voltage Vo3.

[0019] The output side circuit of the main DC-DC converter 42, sandwiching the transformer 46, has a first ground line 36 that serves as the reference potential for the output voltages Vo1 and Vo2, and a second ground line 38 that serves as the reference potential for the output voltage Vo3. In the case of the main DC-DC converter 42, the second ground line 38 is the line on which the output voltage Vo1 is generated, and a constant voltage difference Vg21 (=Vo1) is generated with respect to the first ground line 36.

[0020] The output winding 44 of the transformer 46 has terminals 44s and 44g, with the terminal 44g connected to the first ground line 36. A rectifying and smoothing circuit 48 is connected between the amplitude terminal 44a and the first ground line 36. The rectifying and smoothing circuit 48 is composed of a diode 48a and a capacitor 48b. During a period Tb when the switching element 22 is off and the square-wave voltage Vss is oscillating in the positive direction, the rectifying and smoothing circuit 48 peak-holds the positive peak value +Vaa [Vaa>0] of the square-wave voltage Vss to generate an output voltage Vo1. The output voltage Vo1 is maintained at a constant value by the operation of the drive circuit 50, so the positive peak value +Vaa remains constant. Conversely, during a period Ta when the switching element 22 is on and the square-wave voltage Vss is oscillating in the negative direction, the negative peak value −Vbb [Vbb>0] fluctuates approximately proportional to the input voltage Vi.

[0021] The voltage generating winding 26 of the transformer 46 has an amplitude terminal 26s and a ground terminal 26g, and the ground terminal 26g is connected to a first ground line 36. The rectifying and smoothing circuit 30 is connected between the amplitude terminal 26s and the first ground line 36, and the voltage doubler rectifying and smoothing circuit 52 is connected between the amplitude terminal 26s and a second ground line 38.

[0022] The rectifying and smoothing circuit 30, comprised of a diode 30a and a capacitor 30b, peak-holds the negative peak value −Vb [Vb>0] of the square-wave voltage Vs during a period Tb when the switching element 22 is off and the square-wave voltage Vs is oscillating in the negative direction, generating a negative output voltage Vo2. The output voltage Vo2 is approximately proportional to the output voltage Vo1, which is maintained at a constant value by the operation of the drive circuit 50. The negative peak value −Vb of the square-wave voltage Vs is a constant value approximately proportional to the positive peak value +Vaa. Conversely, the positive peak value +Va [Va>0] of the square-wave voltage Vs, which is generated during a period Ta when the switching element 22 is on and the square-wave voltage Vs is oscillating in the positive direction, is approximately proportional to the negative peak value −Vbb, and therefore fluctuates approximately proportional to the input voltage Vi.

[0023] The voltage doubler rectifying / smoothing circuit 52 has the same configuration as the voltage doubler rectifying / smoothing circuit 32. Specifically, it includes a coupling capacitor 32a having one end connected to the amplitude terminal 26s of the voltage generating winding 26, a potential setting diode 32b having an anode connected to the second ground line 38 and a cathode connected to the other end of the coupling capacitor 32a, and a rectifier diode 32c having an anode connected to the other end of the coupling capacitor 32a. Furthermore, it includes a smoothing capacitor 32d having one end on the high-voltage side connected to the cathode of the rectifier diode 32b and one end on the low-voltage side connected to the second ground line 38, and an output voltage Vo3 is generated across the smoothing capacitor 32d.

[0024] 29(a) and 29(b), the voltage doubler rectifying and smoothing circuit 52 operates in the same manner as the voltage doubler rectifying and smoothing circuit 32, so that a DC output voltage Vo3≈Va+Vb is generated, which causes a problem that the output voltage Vo3 fluctuates when the input voltage Vi fluctuates. This is because the positive peak value +Va included in the equation of the output voltage Vo3≈Va+Vb fluctuates approximately in proportion to the input voltage Vi.

[0025] This problem will be explained using operating waveforms and specific numerical examples. Figure 30(a) shows the operating waveforms when the input voltage Vi is relatively low. The square wave voltage Vs has a positive peak value +Va = 10V, a negative peak value -Vb = -5V, and a voltage difference Vg21 = 30V, so the output voltage Vo3 = Va + Vb = 10V + 5V = 15V. Figure 30(b) shows the operating waveforms when the input voltage Vi is relatively high (approximately doubled). The positive peak value +Va changes from 10V to 20V, and the output voltage Vo3 = Va + Vb = 20V + 5V = 25V.

[0026] In this way, the main DC-DC converter 42 of the power supply device 40 causes the output voltage Vo3 supplied to the internal load 18b to fluctuate depending on the input voltage Vi, so some kind of countermeasure is necessary, especially when the range of the input voltage Vi is wide. <Switching power supply device of Patent Document 1> FIG. 1 of Patent Document 1 also discloses a switching power supply that can solve the problems of power supply device 10 described above. A distinctive feature of this device is that a square-wave generating circuit is connected to a secondary winding (corresponding to voltage generating winding 26) to generate a square wave whose amplitude is the potential difference between ground potential (corresponding to the potential of first ground line 36) and the positive voltage of the AC voltage output from the secondary winding (corresponding to the positive peak value +Va of square-wave voltage Vs), and the input terminal of a capacitor for transmitting the square wave (corresponding to coupling capacitor 32a) is connected to the output terminal of the square-wave generating circuit. In the case of the switching power supply device of Patent Document 1, the voltage corresponding to output voltage Vo3 of power supply device 10 is the voltage difference between the output terminal that outputs 16V and the output terminal that outputs 8V in FIG. 1 of Patent Document 1, and this voltage difference remains a constant value (+Va) even when input voltage Vi fluctuates. [Prior art documents] [Patent documents]

[0027] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-130211 Summary of the Invention [Problem to be solved by the invention]

[0028] As described above, the conventional power supply devices 10 and 40 have a problem in that the output voltage Vo3 supplied to the internal load 18b fluctuates depending on the input voltage Vi.

[0029] However, by applying the technology disclosed in Patent Document 1 to power supply devices 10 and 40, it is thought that a constant output voltage Vo3 = +Va can be obtained in the case of power supply device 10 regardless of the input voltage Vi, and a constant output voltage Vo3 = +Vb can be obtained in the case of power supply device 40 regardless of the input voltage Vi. However, there is a problem in that the output voltage Vo3 cannot be set to a value other than +Va or +Vb, and the output voltage Vo3 cannot be freely set.

[0030] The present invention has been made in view of the above-mentioned background art, and aims to provide a power supply device equipped with a voltage doubler rectifying and smoothing circuit that can obtain a constant output voltage regardless of the input voltage and can easily change the setting of the output voltage. [Means for solving the problem]

[0031] The invention of claim 1 includes a transformer having a switching element that interrupts an input voltage to generate an intermittent input voltage, a transformer having a plurality of windings, a first ground line, a second ground line that is controlled so that a voltage difference Vg21 [Vg21 ≧ 0] with respect to the first ground line is a constant value, and a voltage doubler rectifying and smoothing circuit, wherein the plurality of windings include an input winding to which the intermittent input voltage is applied, and a voltage generating winding having a ground terminal and an amplitude terminal, the ground terminal being connected to the first ground line, and generating a square wave voltage Vs at the amplitude terminal that oscillates in positive and negative directions with respect to the first ground line, and the square wave voltage Vs is a power supply device in which, of a positive peak value +Va [Va>0] and a negative peak value -Vb [Vb>0], the positive peak value +Va is controlled to be a constant value regardless of the value of the input voltage, and the voltage doubler rectifying and smoothing circuit includes a coupling capacitor having one end connected to the amplitude terminal of the voltage generating winding, a potential setting diode having an anode connected to the second ground line and a cathode connected to the other end of the coupling capacitor, a rectifier diode having an anode connected to the other end of the coupling capacitor, and a smoothing capacitor having one end on a high voltage side connected to the cathode of the rectifier diode and one end on a low voltage side connected to the first ground line or the second ground line, An auxiliary switch inserted in a position in series with the coupling capacitor, and a circuit for controlling on / off of the auxiliary switch, the circuit performing control to keep the auxiliary switch in an off state during a specific period within at least a period in which the rectangular-wave voltage Vs is oscillating in a negative direction, and a power supply device characterized in that, by control of the switch control circuit, an increase in the voltage Vc across both ends of the coupling capacitor beyond a certain level is blocked, and a voltage difference between one end on the high-voltage side of the smoothing capacitor with respect to the second ground line is maintained at a target value Vr [Va < Vr < Va + Vb].

[0032] The switch control circuit may be configured to detect the rectangular-wave voltage Vs, turn off the auxiliary switch when an instantaneous value of the rectangular-wave voltage Vs drops from +Va and reaches a predetermined threshold value -Vx1 [0 < Vx1 < Vb], and then turn on the auxiliary switch when the instantaneous value of the rectangular-wave voltage Vs rises from -Vb and becomes equal to or greater than the threshold value -Vx1 (the invention according to claim 2).

[0033] Alternatively, the switch control circuit may be configured to detect the voltage Vc across both ends of the coupling capacitor and the voltage Vsw across both ends of the auxiliary switch, turn off the auxiliary switch when the voltage Vc across both ends rises and reaches a predetermined threshold value Vx2 [0 < Vx2 < Vb + Vg21], and then turn on the auxiliary switch when the voltage Vsw across both ends of the turned-off auxiliary switch becomes zero or when the positive / negative of the voltage Vsw across both ends is inverted (the invention according to claim 3). In this case, the setting of the voltage difference Vg21 can be variably adjusted by the user, and when the switch control circuit detects that the voltage difference Vg21 has been changed to a voltage difference (Vg21 + ΔV), the switch control circuit actively changes the setting of the threshold value Vx2 to (Vx2 + ΔV), whereby the voltage difference between one end on the high-voltage side of the smoothing capacitor with respect to the second ground line may be maintained at the target value Vr [Va < Vr < Va + Vb] (the invention according to claim 4).

[0034] The invention according to claim 5 further includes a switching element that intermittently interrupts an input voltage to generate an input interrupted voltage, a transformer having a plurality of windings, a first ground line, a second ground line controlled such that a voltage difference Vg21 [Vg21≥0] with respect to the first ground line becomes a constant value, and a voltage doubler rectifying and smoothing circuit. Among the plurality of windings, there are an input winding to which the input interrupted voltage is applied, and a winding having a ground terminal and an amplitude terminal. The ground terminal is connected to the first ground line, and the voltage generating winding generates a rectangular wave voltage Vs that oscillates in the positive and negative directions with respect to the first ground line at the amplitude terminal. The rectangular wave voltage Vs is controlled such that, among the positive peak value +Va [Va>0] and the negative peak value -Vb [Vb>0], the negative peak value -Vb becomes a constant value regardless of the value of the input voltage. The voltage doubler rectifying and smoothing circuit includes a coupling capacitor having one end connected to the amplitude terminal of the voltage generating winding, a potential setting diode having an anode connected to the second ground line and a cathode connected to the other end of the coupling capacitor, a rectifying diode having an anode connected to the other end of the coupling capacitor, and a smoothing capacitor having one end on the high voltage side connected to the cathode of the rectifying diode and one end on the low voltage side connected to the first ground line or the second ground line. The power supply device is further provided with an auxiliary switch inserted in a position in series with the coupling capacitor, and a switch control circuit for controlling the on / off of the auxiliary switch. The switch control circuit detects the rectangular wave voltage Vs, turns off the auxiliary switch when the instantaneous value of the rectangular wave voltage Vs rises from -Vb and reaches a predetermined threshold value Vx3 [0<Vx3<Va], and then turns on the auxiliary switch when the instantaneous value of the rectangular wave voltage Vs drops from +Va and becomes less than or equal to the threshold value Vx3. By the control of the switch control circuit, an increase in the pre-rectification voltage Ve1, which is the voltage of the anode of the rectifying diode with the potential of the first ground line as the reference potential, beyond a certain level is prevented, and the voltage difference between one end on the high voltage side of the smoothing capacitor and the second ground line is maintained at a target value Vr [Va<Vr<Va+Vb]. The power supply device is

[0035] The invention of claim 6 relates to a transformer including a switching element that generates an intermittent input voltage by intermittently applying an input voltage, a transformer having a plurality of windings, a first ground line, a second ground line that is controlled so that a voltage difference Vg21 [Vg21≧0] with respect to the first ground line is a constant value, and a voltage doubler rectifying and smoothing circuit, wherein the plurality of windings include an input winding to which the intermittent input voltage is applied, and a voltage generating winding having a ground terminal and an amplitude terminal, the ground terminal being connected to the first ground line, and generating a square wave voltage Vs at the amplitude terminal that oscillates in positive and negative directions with respect to the first ground line, wherein the square wave voltage Vs has a positive peak value +Va [Va>0] and a negative peak value −Vb [Vb>0], and the positive peak value +Va is controlled to be a constant value regardless of the value of the input voltage, the voltage doubler rectifying and smoothing circuit is a power supply device including: a coupling capacitor having one end connected to the amplitude terminal of the voltage generating winding; a potential setting diode having an anode connected to the second ground line and a cathode connected to the other end of the coupling capacitor; a rectifier diode having an anode connected to the other end of the coupling capacitor; and a smoothing capacitor having one end on a high voltage side connected to the cathode of the rectifier diode and one end on a low voltage side connected to the first ground line or the second ground line, A transistor inserted between the coupling capacitor and the amplitude terminal of the voltage generating winding, wherein the emitter of the PNP transistor is connected to one end of the coupling capacitor, and the collector is connected to one end of the voltage generating winding; a bias circuit that applies a DC bias Vbi having the potential of the first ground line as a reference potential to the base of the PNP transistor; and an auxiliary diode having an anode connected to the collector of the PNP transistor and a cathode connected to the emitter of the PNP transistor. During a specific period within the period when the rectangular wave voltage Vs is oscillating in the negative direction, the PNP transistor is turned off by holding the potential of the emitter at a potential corresponding to the DC bias Vbi. As a result, the voltage Vc across the coupling capacitor is prevented from rising above a certain level, and a power supply device in which the voltage difference between one end on the high voltage side of the smoothing capacitor and the second ground line is maintained at a target value Vr [Va < Vr < Va + Vb].

[0036] The invention described in claim 7 provides a transformer including a switching element that generates an intermittent input voltage by intermittently applying an input voltage, a transformer having a plurality of windings, a first ground line, a second ground line that is controlled so that a voltage difference Vg21 [Vg21≧0] with respect to the first ground line is a constant value, and a voltage doubler rectifying and smoothing circuit, wherein the plurality of windings include an input winding to which the intermittent input voltage is applied, and a voltage generating winding having a ground terminal and an amplitude terminal, the ground terminal being connected to the first ground line, and generating a square wave voltage Vs at the amplitude terminal that oscillates in positive and negative directions with respect to the first ground line, and wherein the square wave voltage Vs is a power supply device in which, of a positive peak value +Va [Va>0] and a negative peak value -Vb [Vb>0], the negative peak value -Vb is controlled to be a constant value regardless of the value of the input voltage, and the voltage doubler rectifying and smoothing circuit includes a coupling capacitor having one end connected to the amplitude terminal of the voltage generating winding, a potential setting diode having an anode connected to the second ground line and a cathode connected to the other end of the coupling capacitor, a rectifier diode having an anode connected to the other end of the coupling capacitor, and a smoothing capacitor having one end on a high voltage side connected to the cathode of the rectifier diode and one end on a low voltage side connected to the first ground line or the second ground line, A transistor inserted between the coupling capacitor and the amplitude terminal of the voltage generating winding, the emitter of which is connected to one end of the coupling capacitor, and the collector of which is connected to one end of the voltage generating winding, a PNP transistor; a bias circuit that applies a DC bias Vbi having the potential of the amplitude terminal when the rectangular wave voltage Vs is at the positive peak value +Va as a reference potential to the base of the PNP transistor; and an auxiliary diode having an anode connected to the collector of the PNP transistor and a cathode connected to the emitter of the PNP transistor. During a specific period within the period in which the rectangular wave voltage Vs is oscillating in the negative direction, the PNP transistor becomes non-conductive by maintaining the potential of the emitter at a potential corresponding to the DC bias Vbi. As a result, the voltage Vc across the coupling capacitor is prevented from rising above a certain level, and a power supply device in which the voltage difference between one end on the high voltage side of the smoothing capacitor and the second ground line is maintained at a target value Vr [Va < Vr < Va + Vb].

[0037] The invention according to claim 7 or 8 can be configured such that the PNP transistor is replaced with a P-channel MOS type FET. In this case, the auxiliary diode may be replaced with a parasitic diode between the drain and source of the MOS type FET.

[0038] The invention of claim 10 provides a transformer including a switching element, a plurality of windings, a first ground line, a second ground line controlled so that a voltage difference Vg21 [Vg21≧0] with respect to the first ground line is a constant value, and a voltage doubler rectifying and smoothing circuit, wherein the plurality of windings include an input winding to which an intermittent voltage that intermittently outputs an input voltage is applied by turning on and off the switching element, and a voltage generating winding having a ground terminal and an amplitude terminal, the ground terminal being connected to the first ground line, and the amplitude terminal generating a square wave voltage Vs that oscillates in positive and negative directions with respect to the first ground line, the voltage Vs has a positive peak value +Va [Va>0] and a negative peak value -Vb [Vb>0], and the positive peak value +Va is controlled to be a constant value regardless of the value of the input voltage; the voltage doubler rectifying and smoothing circuit includes a coupling capacitor having one end connected to the amplitude terminal of the voltage generating winding, a potential setting diode having an anode connected to the second ground line and a cathode connected to the other end of the coupling capacitor, a rectifier diode having an anode connected to the other end of the coupling capacitor, and a smoothing capacitor having one end on a high voltage side connected to the cathode of the rectifier diode and one end on a low voltage side connected to the first ground line or the second ground line, A transistor inserted between the connection point of the potential setting diode and the rectifying diode and the coupling capacitor, wherein the emitter is connected to one end of the coupling capacitor, and the collector is connected to the connection point of the potential setting diode and the rectifying diode; an NPN transistor; a bias circuit that applies a DC bias Vbi having a reference potential based on the potential of the amplitude terminal when the rectangular wave voltage Vs becomes the negative peak value -Vb with respect to the base of the NPN transistor; and an auxiliary diode having an anode connected to the emitter of the NPN transistor and a cathode connected to the collector of the NPN transistor. During a specific period within the period when the rectangular wave voltage Vs is oscillating in the negative direction, the NPN transistor is in a non-conducting state by maintaining the potential of the emitter at a potential corresponding to the DC bias Vbi. As a result, it is prevented that the voltage Vc across the coupling capacitor becomes higher than a certain level, and a power supply device in which the voltage difference between one end on the high voltage side of the smoothing capacitor and the second ground line is maintained at a target value Vr [Va < Vr < Va + Vb].

[0039] The setting of the voltage difference Vg21 can be variably adjusted by the user. When the bias circuit detects that the voltage difference Vg21 has been changed to a voltage difference (Vg21 + ΔV), the DC bias Vbi is actively changed to a DC bias (Vbi + ΔV), whereby the voltage difference between one end on the high voltage side of the smoothing capacitor and the second ground line is maintained at a target value Vr [Va < Vr < Va + Vb] (the invention according to claim 11).

[0040] Also, the invention according to claim 10 or 11 can be configured such that the NPN transistor is replaced with an N-channel MOS type FET (the invention according to claim 12). In this case, the auxiliary diode may be replaced with a parasitic diode between the drain and source of the MOS type FET (the invention according to claim 13).

Effect of the Invention

[0041] The power supply device of the present invention has a simple configuration in which an auxiliary switch and a switch control circuit, or a transistor and a bias circuit, are added to the voltage doubler rectifying and smoothing circuit of a conventional power supply device, and the output voltage of the voltage doubler rectifying and smoothing circuit can be made constant regardless of the input voltage. Moreover, the output voltage setting can be easily changed, which is very convenient. [Brief explanation of the drawings]

[0042] [Figure 1] 1 is a circuit diagram showing a voltage doubler rectifying and smoothing circuit and its peripheral circuits, which are essential parts of a first embodiment of a power supply device of the present invention.

[0023] FIG. [Figure 2] 2A and 2B are circuit diagrams showing the operation of the voltage doubler rectifying and smoothing circuit and its peripheral circuits in FIG. 1. [Figure 3] 2A and 2B are waveforms (a) and (b) showing the operation of the voltage doubler rectifying and smoothing circuit and its peripheral circuits in FIG. 1. [Figure 4] FIG. 10 is a circuit diagram showing a voltage doubler rectifying and smoothing circuit and its peripheral circuits, which are essential parts of a second embodiment of a power supply device according to the present invention. [Figure 5] 5A and 5B are circuit diagrams showing the operation of the voltage doubler rectifying and smoothing circuit and its peripheral circuits in FIG. 4. [Figure 6] 5A and 5B show waveforms (a) and (b) of each part showing the operation of the voltage doubler rectifying and smoothing circuit and its peripheral circuits in FIG. 4. [Figure 7] FIG. 10 is a circuit diagram showing a voltage doubler rectifying and smoothing circuit and its peripheral circuits, which are essential parts of a third embodiment of a power supply device according to the present invention. [Figure 8] 8A and 8B are circuit diagrams showing the operation of the voltage doubler rectifying and smoothing circuit and its peripheral circuits in FIG. 7. [Figure 9] 8A and 8B are waveforms (a) and (b) of each part showing the operation of the voltage doubler rectifying and smoothing circuit and its peripheral circuits in FIG. 7. [Figure 10] FIG. 10 is a circuit diagram showing a voltage doubler rectifying and smoothing circuit and its peripheral circuits, which are essential parts of a fourth embodiment of a power supply device according to the present invention. [Figure 11] 11A and 11B are circuit diagrams showing the operation of the voltage doubler rectifying and smoothing circuit and its peripheral circuits in FIG. 10. [Figure 12] 11A and 11B are waveforms (a) and (b) of each part showing the operation of the voltage doubler rectifying and smoothing circuit and its peripheral circuits in FIG. 10. [Figure 13] FIG. 10 is a circuit diagram showing a voltage doubler rectifying and smoothing circuit and its peripheral circuits, which are essential parts of a fifth embodiment of a power supply device according to the present invention. [Figure 14] 14A and 14B are circuit diagrams showing the operation of the voltage doubler rectifying and smoothing circuit and its peripheral circuits in FIG. 13. [Figure 15] 14A and 14B show waveforms (a) and (b) of each part showing the operation of the voltage doubler rectifying and smoothing circuit and its peripheral circuits in FIG. 13. [Figure 16] FIG. 10 is a circuit diagram showing a voltage doubler rectifying and smoothing circuit and its peripheral circuits, which are essential parts of a sixth embodiment of a power supply device according to the present invention. [Figure 17] 17A and 17B are circuit diagrams showing the operation of the voltage doubler rectifying and smoothing circuit and its peripheral circuits in FIG. 16. [Figure 18] 17A and 17B are waveforms (a) and (b) of various parts showing the operation of the voltage doubler rectifying and smoothing circuit and its peripheral circuits in FIG. 16. [Figure 19] FIG. 10 is a circuit diagram showing a voltage doubler rectifying and smoothing circuit and its peripheral circuits, which are essential parts of a sixth embodiment of a power supply device according to the present invention. [Figure 20] 20A and 20B are circuit diagrams showing the operation of the voltage doubler rectifying and smoothing circuit and its peripheral circuits in FIG. 19. [Figure 21] 20A and 20B are waveforms (a) and (b) of each part showing the operation of the voltage doubler rectifying and smoothing circuit and its peripheral circuits in FIG. 19. [Figure 22] FIG. 10 is a circuit diagram showing a modified example of a voltage doubler rectifying and smoothing circuit and its peripheral circuits, which are essential parts of the second embodiment of the present invention. [Figure 23] (a) is a circuit diagram when the P-channel MOS FET is replaced with a PNP transistor, and (b) is a circuit diagram when the N-channel MOS FET is replaced with an NPN transistor. [Figure 24] 1A and 1B are circuit diagrams showing two modified examples in which a plurality of sets of voltage doubler rectifying and smoothing circuits and their peripheral circuits, which are essential parts of the first embodiment of the present invention, are provided. [Figure 25]FIG. 1 is a circuit diagram showing a first embodiment of a conventional power supply device. [Figure 26] 26(a) and 26(b) are circuit diagrams showing the operation of a voltage doubler rectifying and smoothing circuit and its peripheral circuits included in the power supply device of FIG. 25. [Figure 27] 26A and 26B are waveforms (a) and (b) of each part showing the operation of the voltage doubler rectifying and smoothing circuit and its peripheral circuits in FIG. 25. [Figure 28] FIG. 10 is a circuit diagram showing a second embodiment of a conventional power supply device. [Figure 29] 29(a) and 29(b) are circuit diagrams showing the operation of the voltage doubler rectifying and smoothing circuit and its peripheral circuits included in the power supply device of FIG. 28. [Figure 30] 29A and 29B are waveforms (a) and (b) of each part showing the operation of the voltage doubler rectifying and smoothing circuit and its peripheral circuits in FIG. 28. DETAILED DESCRIPTION OF THE INVENTION

[0043] <Power supply device 54 of the first embodiment> First, a first embodiment of the power supply device of the present invention will be described with reference to Figures 1 to 3. In order to solve the problems of the conventional power supply device 10 described above, a power supply device 54 of this embodiment adds an auxiliary switch 56 and a switch control circuit 58 to the power supply device 10, and the configuration other than the auxiliary switch 56 and the switch control circuit 58 is the same as that of the power supply device 10. Therefore, for the power supply device 54, the same components as those of the power supply device 10 are given the same reference numerals and their description will be omitted, and the description will focus on the voltage doubler rectifying and smoothing circuit 32 and its peripheral circuits (including the auxiliary switch 56 and the switch control circuit 58), which are the main parts of the invention.

[0044] 1, the auxiliary switch 56 is an element inserted in a position in series with the coupling capacitor 32a to short-circuit (ON) or open (OFF) this position. For example, a mechanical relay or a semiconductor switch can be used.

[0045] The switch control circuit 58 is a circuit that controls the on / off of the auxiliary switch 56, and performs control to keep the auxiliary switch 56 in the off state during at least a specific period within the period when the rectangular wave voltage Vs is oscillating in the negative direction. Specifically, it detects the rectangular wave voltage Vs, turns off the auxiliary switch 56 when the instantaneous value of the rectangular wave voltage Vs drops from +Va and reaches a predetermined threshold value -Vx1 [0 < Vx1 < Vb], and then turns on the auxiliary switch 56 when the instantaneous value of the rectangular wave voltage Vs rises from -Vb and becomes equal to or higher than the threshold value -Vx1. As will be described in detail later, the threshold value -Vx1 is determined such that the output voltage Vo3 is maintained at the target value Vr [Va < Vr < Va + Vb].

[0046] Note that the internal configuration of the switch control circuit 58 is free, and it may be composed only of discrete components, or may be composed by combining discrete components with a microcomputer, an IC, etc.

[0047] Next, the operation of the voltage-doubling rectification smoothing circuit 32 and its peripheral circuits will be described based on FIGS. 2(a) and (b). First, the operation during the period Tb(k) will be described. Assume that just before the end of the period Ta(k - 1) before the period Tb(k), the auxiliary switch 56 is on and the voltage Vc across the coupling capacitor 32a is slightly lower than the steady-state value.

[0048] When the period Ta(k - 1) ends and the period Tb(k) starts, the rectangular wave voltage Vs drops from +Va to -Vb with a predetermined slope. During this process, the potential setting diode 32b turns on and the rectifying diode 32c turns off, and the current represented by the dashed arrow in the circuit of FIG. 2(a) flows, causing the voltage Vc across the coupling capacitor 32a to rise. When the instantaneous value of the rectangular wave voltage Vs in the negative direction reaches the threshold value -Vx1 [0 < Vx1 < Vb], the switch control circuit 58 turns off the auxiliary switch 56 to cut off the current, and then the rectangular wave voltage Vs = -Vb. Therefore, the voltage Vc across the coupling capacitor 32a at the end of the period Tb(k) is Vc = Vx1 + Vg21.

[0049] When the period Tb(k) ends and the period Ta(k) starts, the rectangular wave voltage Vs rises from -Vb to +Va with a predetermined slope. During this process, when the instantaneous value of the rectangular wave voltage Vs becomes equal to or higher than the threshold value -Vx1 [0 < Vx1 < Vb], the switch control circuit 58 turns on the auxiliary switch 56, the potential setting diode 32b turns off, and the rectifying diode 32c turns on, and a current flows as indicated by the dashed arrow in the circuit of Fig. 2(b). Then, when the rectangular wave voltage Vs = +Va, the current stops flowing (or becomes very small), the voltage Ve1 before rectification becomes Vc + Va, the voltage Ve2 after rectification = Ve1, and the output voltage Vo3 = Va + Vc - Vg21 = Va + Vx1. After that, since power is supplied to the internal load 18b, just before the end of the period Ta(k), the output voltage Vo3 slightly decreases from Va + Vx1, and the voltage Vc across both ends also slightly decreases from Vx1 + Vg21. After the period Ta(k), the same operation is repeated in the order of the periods Tb(k + 1), Ta(k + 1), Tb(k + 2), ···, and thus a DC output voltage Vo3 ≈ Va + Vx1 is generated.

[0050] In the case of the power supply device 54, the formula for the output voltage Vo3 ≈ Va + Vx1 does not include the negative peak value -Vb that varies approximately proportionally to the input voltage Vi. Therefore, the problem that the output voltage Vo3 varies when the input voltage Vi varies does not occur. Regarding this point, a specific numerical example will be added to the operation waveforms for explanation. Fig. 3(a) shows the operation waveforms when the input voltage Vi is relatively low. The positive peak value +Va of the rectangular wave voltage Vs is 5V, the negative peak value -Vb is -10V, and the voltage difference Vg21 is 30V. This is the same condition as the conventional power supply device 10, but by setting the threshold value -Vx1 to -5V, the output voltage Vo3 = Va + Vx1 = 5V + 5V = 10V. Fig. 3(b) shows the operation waveforms when the input voltage Vi is relatively high (about twice as high). The negative peak value -Vb changes from -10V to -20V, but the output voltage Vo3 = Va + Vx1 = 5V + 5V = 10V, and it is maintained at the same value as when Vi is low.

[0051] Furthermore, since the relationship of output voltage Vo3 ≒ Va + Vx1 holds, when the target value of output voltage Vo3 is Vr, the desired output voltage Vo3 can be easily obtained by setting threshold Vx1 so that Vx1 = Vr - Va. Up to this point, we have assumed that the forward voltage of each diode is sufficiently small, but if it cannot be ignored, the threshold -Vx1 can be determined taking the forward voltage of each diode into consideration.

[0052] As described above, the power supply device 54 has a simple configuration in which the auxiliary switch 56 and the switch control circuit 58 are added to the voltage doubler rectifying and smoothing circuit 32 of the conventional power supply device 10. The output voltage Vo3 of the voltage doubler rectifying and smoothing circuit 32 can be made to a constant value regardless of the input voltage Vi, and the setting of the output voltage Vo3 can be easily changed, which is very convenient. <Power supply device 60 according to the second embodiment> Next, a second embodiment of the power supply device of the present invention will be described with reference to Figures 4 to 6. In order to solve the problems of the conventional power supply device 10 described above, a power supply device 60 of this embodiment adds an auxiliary switch 56 and a switch control circuit 62 to the power supply device 10, and the configuration other than the auxiliary switch 56 and the switch control circuit 62 is the same as that of the power supply device 10. Therefore, for the power supply device 60, the same components as those of the power supply device 10 are given the same reference numerals and their description will be omitted, and the description will focus on the voltage doubler rectifying and smoothing circuit 32 and its peripheral circuits (including the auxiliary switch 56 and the switch control circuit 62), which are the main parts of the invention.

[0053] As shown in FIG. 4, the auxiliary switch 56 is an element inserted in a position in series with the coupling capacitor 32a and short-circuits (ON) or opens (OFF) this position, and is similar to the auxiliary switch 56 of the power supply device 54.

[0054] The switch control circuit 62 is a circuit that controls the on / off of the auxiliary switch 56, and performs control to keep the auxiliary switch 56 in the off state during at least a specific period within the period when the rectangular wave voltage Vs is oscillating in the negative direction. Specifically, it detects the voltage Vc across the coupling capacitor 32a and the voltage Vsw across the auxiliary switch 56, turns off the auxiliary switch when the voltage Vc rises and reaches a predetermined threshold value Vx2 [0 < Vx2 < Vb + Vg21], and then turns it on when the voltage Vsw across the off auxiliary switch 56 becomes zero or when the positive / negative of the voltage Vsw is reversed. As will be described in detail later, the threshold value Vx2 is determined such that the output voltage Vo3 is maintained at the target value Vr [Va < Vr < Va + Vb].

[0055] Note that the internal configuration of the switch control circuit 62 is free, and it may be composed only of discrete components, or may be composed by combining discrete components with a microcomputer, an IC, etc.

[0056] Next, the operation of the voltage doubler rectifying and smoothing circuit 32 and its peripheral circuits will be described based on FIGS. 5(a) and (b). First, the operation during the period Tb(k) will be described. Assume that just before the period Ta(k - 1) before the period Tb(k) ends, the auxiliary switch 56 is on, and the voltage Vc across the coupling capacitor 32a is slightly lower than the steady-state value.

[0057] When the period Ta(k - 1) ends and the period Tb(k) starts, the rectangular wave voltage Vs decreases from +Va to -Vb with a predetermined slope. During this process, the potential setting diode 32b turns on and the rectifying diode 32c turns off, and the current represented by the dashed arrow in the circuit of FIG. 5(a) flows, causing the voltage Vc across the coupling capacitor 32a to rise. Then, when the voltage Vc reaches the threshold value Vx2 [0 < Vx1 < Vb + Vg21], the switch control circuit 62 turns off the auxiliary switch 56 to cut off the current, and then the rectangular wave voltage Vs = -Vb. Therefore, the voltage Vc across the coupling capacitor 32a at the end of the period Tb(k) is Vc = Vx2.

[0058] When period Tb(k) ends and period Ta(k) begins, square-wave voltage Vs rises from -Vb to +Va at a predetermined slope. When the voltage Vsw across the off auxiliary switch 56 reaches 0V (or when the polarity is reversed), switch control circuit 62 turns on auxiliary switch 56. As square-wave voltage Vs continues to rise, potential-setting diode 32b turns off and rectifier diode 32c turns on, causing current to flow in the circuit shown by the dashed arrows in Figure 5(b). When square-wave voltage Vs reaches +Va, the current stops flowing (or becomes very small), pre-rectification voltage Vel becomes Vc+Va, rectified voltage V2 = Vel, and output voltage V03 = Va+Vc-Vg21 = Va+Vx2-Vg21. Thereafter, power is supplied to internal load 18b, and so just before the end of period Ta(k), output voltage Vo3 drops slightly from Va+Vx2-Vg21, and end-to-end voltage Vc also drops slightly from Vx2. After period Ta(k), the same operation is repeated in the order of period Tb(k+1), period Ta(k+1), period Tb(k+2), and so on, thereby generating a DC output voltage Vo3≈Va+Vx2-Vg21.

[0059] In the case of the power supply device 60, the equation (output voltage Vo3≈Va+Vx2-Vg21) does not include the negative peak value -Vb, which fluctuates approximately in proportion to the input voltage Vi. Therefore, fluctuations in the input voltage Vi do not cause fluctuations in the output voltage Vo3. This point will be explained using specific numerical examples of the operating waveforms. Figure 6(a) shows the operating waveforms when the input voltage Vi is relatively low, with the square-wave voltage Vs having a positive peak value +Va of 5V, a negative peak value -Vb of -10V, and a voltage difference Vg21 of 30V. This is the same condition as the conventional power supply device 10, but by setting the threshold Vx2 to 35V, the output voltage Vo3 = Va + Vx2 - Vg21 = 5V + 35V - 30V = 10V. Furthermore, Figure 6(b) shows the operating waveform when the input voltage Vi is relatively high (approximately doubled), and although the negative peak value -Vb changes from -10V to -20V, the output voltage Vo3 = Va + Vx2 - Vg21 = 5V + 35V - 30V = 10V, which is maintained at the same value as when Vi is low.

[0060] Furthermore, since the relationship of output voltage Vo3 ≒ Va + Vx2 - Vg21 holds, when the target value of output voltage Vo3 is Vr, the desired output voltage Vo3 can be easily obtained by setting threshold Vx2 so that Vx2 = Vr - Va + Vg21. Up to this point, we have assumed that the forward voltage of each diode is sufficiently small, but if it cannot be ignored, the threshold Vx2 can be determined taking the forward voltage of each diode into consideration.

[0061] As described above, the power supply device 60 has a simple configuration in which the auxiliary switch 56 and the switch control circuit 62 are added to the voltage doubler rectifying and smoothing circuit 32 of the conventional power supply device 10. The output voltage Vo3 of the voltage doubler rectifying and smoothing circuit 32 can be made to a constant value regardless of the input voltage Vi, and the setting of the output voltage Vo3 can be easily changed, which is very convenient.

[0062] <Power supply device 64 according to the third embodiment> A third embodiment of the power supply device of the present invention will be described below with reference to Figures 7 to 9. In order to solve the problems of the conventional power supply device 40 described above, a power supply device 64 of this embodiment adds an auxiliary switch 56 and a switch control circuit 66 to the power supply device 40, and the configuration other than the auxiliary switch 56 and the switch control circuit 66 is the same as that of the power supply device 40. Therefore, for the power supply device 64, the same components as those of the power supply device 40 are assigned the same reference numerals and their description will be omitted, and the description will focus on the voltage doubler rectifying and smoothing circuit 52 and its peripheral circuits (including the auxiliary switch 56 and the switch control circuit 66), which are the main parts of the invention.

[0063] 7, the auxiliary switch 56 is an element that is inserted in a position in series with the coupling capacitor 32a and shorts (ON) or opens (OFF) this position. For example, a mechanical relay or a semiconductor switch can be used.

[0064] The switch control circuit 66 is a circuit that controls the on / off of the auxiliary switch 56. Specifically, it detects the rectangular wave voltage Vs, turns off the auxiliary switch 56 when the instantaneous value of the rectangular wave voltage Vs rises from -Vb and reaches a predetermined threshold value Vx3 [0 < Vx3 < Va], and then turns on the auxiliary switch 56 when the instantaneous value of the rectangular wave voltage Vs drops from +Va and becomes less than or equal to the threshold value Vx3. Although it will be described in detail later, the threshold value Vx3 is determined so that the output voltage Vo3 is maintained at the target value Vr [Va < Vr < Va + Vb]. Note that the internal configuration of the switch control circuit 66 is free, and it may be composed of only discrete components, or it may be composed by combining discrete components with a microcomputer, an IC, etc.

[0065] Next, the operations of the voltage doubler rectifying and smoothing circuit 52 and its peripheral circuits will be described based on FIGS. 8(a) and (b). First, the operation during the period Tb(k) will be described. It is assumed that just before the period Ta(k - 1) before the period Tb(k) ends, the auxiliary switch 56 is off, and the voltage Vc across the coupling capacitor 32a and the output voltage Vo3 are slightly lower than their steady-state values.

[0066] When the period Ta(k - 1) ends and the period Tb(k) starts, the rectangular wave voltage Vs drops from +Va towards -Vb at a predetermined slope. During this process, when the instantaneous value of the rectangular wave voltage Vs becomes less than or equal to the threshold value Vx3, the switch control circuit 66 turns on the auxiliary switch 56, the potential setting diode 32b turns on, the rectifying diode 32c turns off, and the current represented by the dashed arrow in the circuit of FIG. 8(a) flows. Then, when the rectangular wave voltage Vs = -Vb, the current stops flowing, and the voltage Vc across the coupling capacitor 32a at the end of the period Tb(k) becomes Vc = Vb + Vg21.

[0067] When the period Tb(k) ends and the period Ta(k) starts, the rectangular wave voltage Vs rises from -Vb towards +Va at a predetermined slope. When the positive instantaneous value of the rectangular wave voltage Vs reaches the threshold value Vx3 [0 < Vx3 < Va], the switch control circuit 66 turns off the auxiliary switch 56 to cut off the current, and then the rectangular wave voltage Vs reaches the positive peak value +Va.

[0068] During the period from when the square-wave voltage Vs starts rising from -Vb until just before the auxiliary switch 56 turns off, the potential setting diode 32b turns off and the rectifier diode 32c turns on, causing a current to flow through the circuit shown in FIG. 8(b) as indicated by the dashed arrows. This causes the pre-rectified voltage Ve1 to be Ve1 = Vc + Vx3 = Vb + Vg21 + Vx3, the rectified voltage Ve2 = Ve1, and the output voltage Vo3 = Vx3 + Vc - Vg21 = Vx3 + Vb. When the auxiliary switch 56 turns off, the pre-rectified voltage Ve1 drops, causing the rectifier diode 32c to turn off. If the drop in the pre-rectified voltage Ve1 is large, the potential setting diode 32b turns on, and the pre-rectified voltage Ve1 is maintained at the voltage difference Vg21. The output voltage Vo3 is generally maintained at Vx3+Vc-Vg21=Vx3+Vb, but because power is supplied to the internal load 18b, it drops slightly from Vx3+Vb just before the end of the period Ta(k). After the period Ta(k), the same operation is repeated in the order of the period Tb(k+1), the period Ta(k+1), the period Tb(k+2), and so on, thereby generating a DC output voltage Vo3≈Vx3+Vb.

[0069] In the case of the power supply 64, the equation (output voltage Vo3≈Vx3+Vb) does not include the positive peak value +Va, which fluctuates approximately in proportion to the input voltage Vi. Therefore, fluctuations in the input voltage Vi do not cause fluctuations in the output voltage Vo3. This point will be explained using specific numerical examples of the operating waveforms. Figure 9(a) shows the operating waveforms when the input voltage Vi is relatively low, with the square-wave voltage Vs having a positive peak value +Va of 10V, a negative peak value -Vb of -5V, and a voltage difference Vg21 of 30V. This is the same condition as the conventional power supply 40, but by setting the threshold value Vx3 to 5V, the output voltage Vo3 = Vx3 + Vb = 5V + 5V = 10V. Also, Figure 9(b) shows the operating waveform when the input voltage Vi is relatively high (about doubled), and although the positive peak value +Va changes from 10V to 20V, the output voltage Vo3 = Vx3 + Vb = 5V + 5V = 10V, which is maintained at the same value as when Vi is low.

[0070] Furthermore, since the relationship of output voltage Vo3 ≒ Vx3 + Vb holds, when the target value of output voltage Vo3 is Vr, the desired output voltage Vo3 can be easily obtained by setting threshold Vx3 so that Vx3 = Vr - Vb. Up to this point, we have assumed that the forward voltage of each diode is sufficiently small, but if it cannot be ignored, the threshold Vx3 can be determined taking the forward voltage of each diode into consideration.

[0071] As described above, the power supply device 64 has a simple configuration in which the auxiliary switch 56 and the switch control circuit 66 are added to the voltage doubler rectifying and smoothing circuit 52 of the conventional power supply device 40. The output voltage Vo3 of the voltage doubler rectifying and smoothing circuit 52 can be made to a constant value regardless of the input voltage Vi, and the setting of the output voltage Vo3 can be easily changed, which is very convenient.

[0072] <Power supply device 68 of the fourth embodiment> Next, a fourth embodiment of the power supply device of the present invention will be described with reference to Figures 10 to 12. In order to solve the problems of the conventional power supply device 10 described above, a power supply device 68 of this embodiment adds a P-FET 70, an auxiliary diode 72, and a bias circuit 74 to the power supply device 10, and the configuration other than the P-FET 70, auxiliary diode 72, and bias circuit 74 is the same as that of the power supply device 10. Therefore, for the power supply device 68, the same components as those of the power supply device 10 are given the same reference numerals and their description will be omitted, and the description will focus on the voltage doubler rectifying and smoothing circuit 32 and its peripheral circuitry (including the P-FET 70, auxiliary diode 72, and bias circuit 74), which are the essential parts of the invention.

[0073] As shown in FIG. 10(a), the P-FET 70 is a P-channel MOS FET (metal-oxide semiconductor field-effect transistor) inserted between the coupling capacitor 32a and the amplitude terminal 26s of the voltage generating winding 26, with its source connected to the coupling capacitor 32a and its drain connected to the amplitude terminal 26s. The auxiliary diode 72 is a diode with its anode connected to the drain of the P-FET 70 and its cathode connected to the source of the P-FET 70. The auxiliary diode 72 may be substituted by a parasitic diode between the drain and source inside the P-FET 70. Hereinafter, the gate threshold voltage of the P-FET 70 is represented as −Vth [Vth>0].

[0074] The bias circuit 74 is a circuit that applies a DC bias Vbi to the gate of the P-FET 70, with the potential of the first ground line 36 as the reference potential. FIG. 10(b) shows the internal configuration of the bias circuit 74.

[0075] The bias circuit 74 is composed of a rectifying and smoothing circuit 76 and a series regulator 78. The rectifying and smoothing circuit 76 is composed of a diode 76a and a capacitor 76b, and during a period Tb in which the switching element 22 is on and the square-wave voltage Vs oscillates in the negative direction, the rectifying and smoothing circuit 76 peak-holds the negative peak value −Vb [Vb>0] of the square-wave voltage Vs, and generates a negative output voltage Vo4≈−Vb across the capacitor 76b, with the first ground line 36 as the reference potential. This output voltage Vo4 fluctuates according to the input voltage Vi.

[0076] The series regulator 78 is a circuit that steps down the output voltage Vo4 to generate a constant DC bias Vbi. Specifically, it is composed of a resistor 78a with one end connected to the connection point of the diode 76a and the capacitor 76b, a Zener diode 78b connected between the other end of the resistor 78a and the first ground line 36, and a capacitor 78c connected in parallel with the Zener diode 78b. A DC bias Vbi = -Vzd defined by the Zener voltage Vzd of the Zener diode 78b is generated across the capacitor 78c. Although it will be described in detail later, the DC bias Vbi is determined such that the output voltage Vo3 is maintained at the target value Vr [Va < Vr < Va + Vb].

[0077] Next, the operation of the voltage-doubling rectifying and smoothing circuit 32 and its peripheral circuits will be described based on FIGS. 11(a) and (b). First, the operation during the period Tb(k) will be described. Assume that just before the end of the period Ta(k - 1) preceding the period Tb(k), the voltage Vc across the coupling capacitor 32a is slightly lower than the steady-state value.

[0078] When the period Ta(k - 1) ends and the period Tb(k) begins, the rectangular-wave voltage Vs decreases from +Va to -Vb at a predetermined slope. During this process, the potential-setting diode 32b turns on and the rectifying diode 32c turns off, and the P-FET 70 conducts, and the current represented by the dashed-arrow in the circuit of FIG. 11(a) flows, causing the voltage Vc across the coupling capacitor 32a to rise. When the voltage Vc across both ends becomes large and reaches Vg21 - Vbi + Vth, the P-FET 70 becomes non-conductive because the source potential cannot decrease (by being held at the potential corresponding to the DC bias Vbi), and remains in the non-conductive state with the rectangular-wave voltage Vs = -Vb, and the voltage Vds between the drain and source of the P-FET 70 becomes a predetermined value.

[0079] When period Tb(k) ends and period Ta(k) begins, square-wave voltage Vs rises from -Vb to +Va at a predetermined slope. During this rise, auxiliary diode 72 raises the source potential of P-FET 70, causing gate-to-source voltage Vgs to fall below -Vth. P-FET 70 is fully turned on, and voltage Vds becomes approximately 0V. Furthermore, potential-setting diode 32b turns off and rectifier diode 32c turns on, causing current, as indicated by the dashed arrows, to flow through the circuit in FIG. 11(b). When square-wave voltage Vs becomes +Va, current stops flowing (or becomes very small), pre-rectification voltage Ve1 becomes Vc + Va, rectification voltage Ve2 = Ve1, and output voltage Vo3 = Va + Vc - Vg21 = Va - Vbi + Vth. Thereafter, power is supplied to internal load 18b, and so just before the end of period Ta(k), output voltage Vo3 drops slightly from Va-Vbi+Vth, and both-end voltage Vc also drops slightly from Vg21-Vbi+Vth. After period Ta(k), the same operation is repeated in the order of period Tb(k+1), period Ta(k+1), period Tb(k+2), and so on, thereby generating a DC output voltage Vo3 ≈ Va-Vbi+Vth.

[0080] In the case of the power supply 68, the equation (output voltage Vo3≈Va-Vbi+Vth) does not include the negative peak value -Vb, which varies approximately in proportion to the input voltage Vi. Therefore, fluctuations in the input voltage Vi do not cause fluctuations in the output voltage Vo3. This point will be explained using specific numerical examples of the operating waveforms (assuming that the gate threshold voltage Vth of the P-FET 70 is 0V). Figure 12(a) shows the operating waveforms when the input voltage Vi is relatively low, with the square-wave voltage Vs having a positive peak value +Va of 5V, a negative peak value -Vb of -10V, and a voltage difference Vg21 of 30V. This is the same condition as the conventional power supply 10, but by setting the DC bias Vbi to -5V, the output voltage Vo3 = Va-Vbi + Vth = 5V + 5V + 0V = 10V. Furthermore, Figure 12(b) shows the operating waveform when the input voltage Vi is relatively high (approximately doubled), and although the negative peak value -Vb changes from -10V to -20V, the output voltage Vo3 == Va - Vbi + Vth = 5V + 5V + 0V = 10V, and is maintained at the same value as when Vi is low.

[0081] Furthermore, since the relationship of output voltage Vo3 ≒ Va - Vbi + Vth holds, when the target value of output voltage Vo3 is Vr, the desired output voltage Vo3 can be easily obtained by setting the DC bias Vbi (Zener voltage Vzd) so that Vbi = Va + Vth - Vr. Up to this point, we have assumed that the forward voltage of each diode is sufficiently small, but if it cannot be ignored, the DC bias Vbi can be determined taking the forward voltage of each diode into consideration.

[0082] As described above, the power supply device 68 has a simple configuration in which a P-FET 70, an auxiliary diode 72, and a bias circuit 74 are added to the voltage doubler rectifying and smoothing circuit 32 of the conventional power supply device 10, and the output voltage Vo3 of the voltage doubler rectifying and smoothing circuit 32 can be made to a constant value regardless of the input voltage Vi, and the setting of the output voltage Vo3 can be easily changed, making it very convenient.

[0083] <Power supply device 80 of the fifth embodiment> Next, a fifth embodiment of the power supply device of the present invention will be described with reference to Figures 13 to 15. In order to solve the problems of the conventional power supply device 40 described above, a power supply device 80 of this embodiment adds a P-FET 70, an auxiliary diode 72, and a bias circuit 82 to the power supply device 40, and the configuration other than the P-FET 70, auxiliary diode 72, and bias circuit 82 is the same as that of the power supply device 40. Therefore, for the power supply device 80, the same components as those of the power supply device 40 are given the same reference numerals and their description will be omitted, and the description will focus on the voltage doubler rectifying and smoothing circuit 52 and its peripheral circuitry (including the P-FET 70, auxiliary diode 72, and bias circuit 82), which are the essential parts of the invention.

[0084] As shown in FIG. 13(a), the P-FET 70 is a P-channel MOS FET (metal-oxide semiconductor field-effect transistor) inserted between the coupling capacitor 32a and the amplitude terminal 26s of the voltage generating winding 26, with its source connected to the coupling capacitor 32a and its drain connected to the amplitude terminal 26s. The auxiliary diode 72 is a diode with its anode connected to the drain of the P-FET 70 and its cathode connected to the source of the P-FET 70. The auxiliary diode 72 may be substituted by a parasitic diode between the drain and source inside the P-FET 70. Hereinafter, the gate threshold voltage of the P-FET 70 will be represented as −Vth [Vth>0].

[0085] The bias circuit 82 is a circuit that applies a DC bias Vbi to the gate of the P-FET 70, with the potential at the amplitude terminal 26s when the square wave voltage Vs is at the positive wave peak value +Va as the reference potential. Figure 13(b) shows the internal configuration of the bias circuit 82.

[0086] The bias circuit 74 is composed of a rectifying and smoothing circuit 30, 84 and a series regulator 86. The rectifying and smoothing circuit 30 reuses the rectifying and smoothing circuit 30 (diode 30a, capacitor 30b) of the conventional power supply device 40. During the period Tb when the switching element 22 is off and the rectangular wave voltage Vs is oscillating in the negative direction, the negative peak value -Vb [Vb>0] of the rectangular wave voltage Vs is peak-held, and a negative DC voltage Vo2≈-Vb (constant) with the first ground line 36 as the reference potential is generated across both ends of the capacitor 30b.

[0087] The rectifying and smoothing circuit 84 is composed of a diode 84a and a capacitor 84b. During the period Ta when the switching element 22 is on and the rectangular wave voltage Vs is oscillating in the positive direction, the positive peak value +Va [Va>0] of the rectangular wave voltage Vs is peak-held, and a positive output voltage Vo5≈+Va with the first ground line 36 as the reference potential is generated across both ends of the capacitor 84b. That is, the output voltage Vo5 is a voltage that varies according to the input voltage Vi. Also, the potential at the position where the output voltage Vo5 is generated, that is, the potential at the connection point of the diode 84a and the capacitor 84b, is approximately equal to the potential of the amplitude terminal 26s when the switching element 22 is on and the rectangular wave voltage Vs is oscillating in the positive direction.

[0088] The series regulator 86 is a circuit that steps down the voltage obtained by adding the output voltages Vo2 and Vo5 to generate a constant DC bias Vbi. Specifically, it is composed of a resistor 86a with one end connected to the connection point of the diode 30a and the capacitor 30b, a Zener diode 86b connected between the other end of the resistor 86a and the connection point of the diode 84a and the capacitor 84b, and a capacitor 86c connected in parallel with the Zener diode 86b. A DC bias Vbi=-Vzd defined by the Zener voltage Vzd of the Zener diode 86b is generated across both ends of the capacitor 86c. Although it will be described in detail later, the DC bias Vbi is determined such that the output voltage Vo3 is held at the target value Vr [Va<Vr<Va+Vb].

[0089] Next, the operation of the voltage doubler rectifying and smoothing circuit 52 and its peripheral circuits will be described with reference to Figures 14(a) and 14(b). First, the operation during period Tb(k) will be described. It is assumed that the voltage Vc across the coupling capacitor 32a is slightly lower than the steady-state value just before the end of period Ta(k-1) before period Tb(k).

[0090] When period Ta(k-1) ends and period Tb(k) begins, square-wave voltage Vs decreases at a predetermined slope from +Va to -Vb. During this decrease, potential-setting diode 32b turns on, rectifier diode 32c turns off, P-FET 70 conducts, and a current flows through the circuit shown by the dashed arrow in Fig. 14(a), causing voltage Vc across coupling capacitor 32a to rise. When voltage Vc increases and reaches Vg21 - Va - Vbi + Vth, the source potential of P-FET 70 can no longer decrease (because the source potential is maintained at a potential corresponding to DC bias Vbi), and the P-FET 70 enters a non-conductive state. Thus, square-wave voltage Vs = -Vb while remaining non-conductive, and drain-source voltage Vds of P-FET 70 reaches a predetermined value.

[0091] When period Tb(k) ends and period Ta(k) begins, square-wave voltage Vs rises from -Vb to +Va at a predetermined slope. During this rise, auxiliary diode 72 raises the source potential of P-FET 70, causing gate-to-source voltage Vgs to fall below -Vth, fully turning on P-FET 70 and setting voltage Vds approximately equal to 0V. Furthermore, potential-setting diode 32b turns off and rectifier diode 32c turns on, causing current to flow through the circuit shown by the dashed arrows in Figure 14(b). When square-wave voltage Vs reaches +Va, current stops flowing (or becomes very small), pre-rectification voltage Ve1 becomes Vc + Va, rectification voltage Ve2 = Ve1, and output voltage Vo3 = Va + Vc - Vg21 = -Vbi + Vth. Thereafter, power is supplied to internal load 18b, and so just before the end of period Ta(k), output voltage Vo3 drops slightly from -Vbi+Vth, and end-to-end voltage Vc also drops slightly from Vg21-Va-Vbi+Vth. After period Ta(k), the same operation is repeated in the order of period Tb(k+1), period Ta(k+1), period Tb(k+2), and so on, thereby generating a DC output voltage Vo3 ≈ -Vbi+Vth.

[0092] In the case of the power supply 80, the equation (output voltage Vo3≈-Vbi+Vth) does not include the positive peak value +Va, which fluctuates approximately in proportion to the input voltage Vi. Therefore, fluctuations in the input voltage Vi do not cause fluctuations in the output voltage Vo3. This point will be explained using specific numerical examples of the operating waveforms (assuming the gate threshold voltage Vth of the P-FET 70 is 0V). Figure 15(a) shows the operating waveforms when the input voltage Vi is relatively low, with the positive peak value +Va of the square-wave voltage Vs = 10V, the negative peak value -Vb = -5V, and the voltage difference Vg21 = 30V. This is the same condition as the conventional power supply 40, but by setting the DC bias Vbi = -10V, the output voltage Vo3 = -Vbi + Vth = 10V + 0V = 10V. Also, Figure 15(b) shows the operating waveform when the input voltage Vi is relatively high (approximately doubled), and although the positive peak value +Va changes from 10V to 20V, the output voltage Vo3 = -Vbi + Vth = 10V + 0V = 10V, which is maintained at the same value as when Vi is low.

[0093] Furthermore, since the relationship output voltage Vo3 ≈ -Vbi + Vth holds, when the target value of output voltage Vo3 is Vr, the desired output voltage Vo3 can be easily obtained by setting the DC bias Vbi (Zener voltage Vzd) so that Vbi = -Vr - Vth. Up to this point, we have assumed that the forward voltage of each diode is sufficiently small, but if it cannot be ignored, the DC bias Vbi can be determined taking the forward voltage of each diode into consideration.

[0094] As described above, the power supply device 80 has a simple configuration in which a P-FET 70, an auxiliary diode 72, and a bias circuit 82 are added to the voltage doubler rectifying and smoothing circuit 52 of the conventional power supply device 40. The output voltage Vo3 of the voltage doubler rectifying and smoothing circuit 52 can be made to a constant value regardless of the input voltage Vi, and the setting of the output voltage Vo3 can be easily changed, making it extremely convenient.

[0095] <Power supply device 88 of the sixth embodiment> Next, a sixth embodiment of the power supply device of the present invention will be described with reference to Figures 16 to 18. In order to solve the problems of the conventional power supply device 10 described above, a power supply device 88 of this embodiment adds an N-FET 90, an auxiliary diode 92, and a bias circuit 94 to the power supply device 10, and the configuration other than the N-FET 90, auxiliary diode 92, and bias circuit 94 is the same as that of the power supply device 10. Therefore, for the power supply device 88, the same components as those of the power supply device 10 are given the same reference numerals and their description will be omitted, and the description will focus on the voltage doubler rectifying and smoothing circuit 32 and its peripheral circuitry (including the N-FET 90, auxiliary diode 92, and bias circuit 94), which are the essential parts of the invention.

[0096] As shown in Fig. 16(a), the N-FET 90 is an N-channel MOS (Metal Oxide Semiconductor Field Effect Transistor) FET inserted between the connection point of the potential setting diode 32b and the rectifying diode 32c and the coupling capacitor 32a, with its source connected to the side of the coupling capacitor 32a and its drain connected to the side of the potential setting diode 32b. The auxiliary diode 92 is a diode with its anode connected to the source of the N-FET 90 and its cathode connected to the drain of the N-FET 90. The auxiliary diode 92 may be replaced by a parasitic diode between the drain and source inside the N-FET 90. Hereinafter, the gate threshold voltage of the N-FET 90 is expressed as Vth [Vth>0].

[0097] The bias circuit 94 is a circuit that applies a DC bias Vbi with the potential of the amplitude terminal 26s when the rectangular wave voltage Vs reaches the positive peak value +Va as the reference potential to the gate of the N-FET 90. Fig. 10(b) shows the internal configuration of the bias circuit 94.

[0098] The bias circuit 94 is a so-called series regulator, configured to step down the voltage generated between the connection point of the potential setting diode 32b and the rectifying diode 32c and the amplitude terminal 26s to generate a constant DC bias Vbi. Specifically, it is composed of a resistor 94a with one end connected to the connection point of the potential setting diode 32b and the rectifying diode 32c, a Zener diode 94b connected between the other end of the resistor 94a and the amplitude terminal 26s, and a capacitor 94c connected in parallel with the Zener diode 94b. A DC bias Vbi = Vzd defined by the Zener voltage Vzd of the Zener diode 94b is generated across the capacitor 94c. Although it will be described in detail later, the DC bias Vbi is determined such that the output voltage Vo3 is maintained at the target value Vr [Va < Vr < Va + Vb].

[0099] Next, the operation of the voltage doubler rectifying and smoothing circuit 32 and its peripheral circuits will be described with reference to Figures 17(a) and 17(b). First, the operation during period Tb(k) will be described. It is assumed that the voltage Vc across the coupling capacitor 32a is slightly lower than the steady-state value just before the end of period Ta(k-1) before period Tb(k).

[0100] When period Ta(k-1) ends and period Tb(k) begins, square-wave voltage Vs decreases at a predetermined slope from +Va to -Vb. During this decrease, potential-setting diode 32b turns on, rectifier diode 32c turns off, N-FET 90 conducts, and a current flows through the circuit shown by the dashed arrow in Fig. 17(a). This increases voltage Vc across coupling capacitor 32a. When voltage Vc increases to Vbi-Vth, N-FET 90 becomes nonconductive because the source potential cannot decrease (because the source potential is maintained at a potential corresponding to DC bias Vbi). While in this nonconductive state, square-wave voltage Vs = -Vb, and drain-source voltage Vds of N-FET 90 reaches a predetermined value.

[0101] When period Tb(k) ends and period Ta(k) begins, square-wave voltage Vs rises at a predetermined slope from -Vb to +Va. During this time, auxiliary diode 72 turns on (N-FET 90 may also turn on, depending on the situation), causing voltage Vds to become approximately 0V. Potential-setting diode 32b turns off and rectifier diode 32c turns on, causing current, as indicated by the dashed arrows, to flow through the circuit in Figure 17(b). When square-wave voltage Vs = +Va, current stops flowing (or becomes very small), pre-rectification voltage Ve1 becomes Vc + Va, rectified voltage Ve2 = Ve1, and output voltage Vo3 = Va + Vc - Vg21 = Va + Vbi - Vth - Vg21. Thereafter, power is supplied to internal load 18b, and so just before the end of period Ta(k), output voltage Vo3 drops slightly from Va+Vbi-Vth-Vg21, and both-end voltage Vc also drops slightly from Vbi-Vth. After period Ta(k), the same operation is repeated in the order of period Tb(k+1), period Ta(k+1), period Tb(k+2), and so on, thereby generating a DC output voltage Vo3≈Va+Vbi-Vth-Vg21.

[0102] In the case of the power supply 88, the equation (output voltage Vo3≈Va+Vbi-Vth-Vg21) does not include the negative peak value -Vb, which varies approximately in proportion to the input voltage Vi. Therefore, the problem of the output voltage Vo3 fluctuating when the input voltage Vi fluctuates does not occur. This point will be explained using specific numerical examples of the operating waveforms (assuming the gate threshold voltage Vth of the N-FET 90 is 0V). Figure 18(a) shows the operating waveforms when the input voltage Vi is relatively low, with the square-wave voltage Vs having a positive peak value +Va of 5V, a negative peak value -Vb of -10V, and a voltage difference Vg21 of 30V. This is the same condition as the conventional power supply 10, but by setting the DC bias Vbi to 35V, the output voltage Vo3 = Va + Vbi - Vth - Vg21 = 5V + 35V - 0V - 30V = 10V. Also, Figure 12(b) shows the operating waveform when the input voltage Vi is relatively high (approximately doubled), and although the negative peak value -Vb changes from -10V to -20V, the output voltage Vo3 = Va + Vbi - Vth - Vg21 = 5V + 35V - 0V - 30V = 10V, which is maintained at the same value as when Vi is low.

[0103] Furthermore, since the relationship of output voltage Vo3 ≈ Va + Vbi - Vth - Vg21 holds, when the target value of output voltage Vo3 is Vr, the desired output voltage Vo3 can be easily obtained by setting the DC bias Vbi (Zener voltage Vzd) so that Vbi = Vr - Va + Vth + Vg21. Up to this point, the explanation has been given under the assumption that the forward voltage of each diode is sufficiently small, but if it cannot be ignored, the DC bias Vbi can be determined taking the forward voltage of each diode into consideration.

[0104] As described above, the power supply device 88 has a simple configuration in which an N-FET 90, an auxiliary diode 92, and a bias circuit 94 are added to the voltage doubler rectifying and smoothing circuit 32 of the conventional power supply device 10, and the output voltage Vo3 of the voltage doubler rectifying and smoothing circuit 32 can be made to a constant value regardless of the input voltage Vi, and the setting of the output voltage Vo3 can be easily changed, making it extremely convenient.

[0105] <Power supply device 96 of the seventh embodiment> Next, a seventh embodiment of the power supply device of the present invention will be described with reference to Figures 19 to 21. A power supply device 96 of this embodiment is similar in configuration to the power supply device 88 of the sixth embodiment overall, except that the bias circuit 94 is replaced with a new bias circuit 98, as shown in Figure 19(a).

[0106] In the power supply device 88 described above, the voltage difference Vg21 is included in the equation of output voltage Vo3 ≈ Va + Vbi - Vth - Vg21, so if the voltage difference Vg21 changes to Vg21 + ΔV, in order to match the output voltage Vo3 to the target value Vr, all that is needed is to change the DC bias Vbi to Vbi + ΔV, and this can be addressed by replacing the Zener diode 94b that determines the DC bias Vbi with another one. However, there are cases where it is not possible to replace the Zener diode 94b.

[0107] The voltage difference Vg21 in the power supply device 88 is the output voltage Vo1 of the main DC-DC converter 12, which is the voltage supplied to the external load 16 (see the circuit diagram of the conventional power supply device 10 in FIG. 25). Therefore, a user may request the addition of an external variable function for the output voltage Vo1 (=Vg21). In this case, because the Zener diode 94b cannot be replaced each time, if the user changes the setting of the output voltage Vo1, the desired output voltage Vo3 cannot be obtained. Therefore, the configuration of the voltage doubler rectifying and smoothing circuit 32 of the power supply device 88 and its peripheral circuitry is not suitable for a power supply device that allows the user to freely adjust the output voltage Vo1.

[0108] In contrast, the power supply device 96 has the feature that it can obtain the desired output voltage Vo3 even when the user changes the setting of the output voltage Vo1 (=Vg21). The power supply device 96 will be described in detail below. The bias circuit 98 of the power supply device 96 has the same function as the bias circuit 94 described above, and further has the function of actively changing the DC bias Vbi to the DC bias (Vbi+ΔV) when it detects that the voltage difference Vg21 has changed to the voltage difference (Vg21+ΔV). Figure 19(b) shows the internal configuration of the bias circuit 98.

[0109] The bias circuit 98 is a so-called series regulator, configured to step down the voltage generated between the second ground line 38 and the amplitude terminal 26s to generate a constant DC bias Vbi. Specifically, it includes a reverse current blocking diode 98a with one end connected to the second ground line 38, a resistor 98b with one end connected to the cathode of the diode 98a, a capacitor 98c connected between the other end of the resistor 98b and the amplitude terminal 26s, a Zener diode 98d (Zener voltage Vzd) with its cathode connected to the other end of the resistor 98b, and a diode 98e connected between the Zener diode 98d and the second ground line 38 to block the forward current from flowing through the Zener diode 98d. A predetermined DC bias Vbi is generated across the capacitor 98c. The capacitance of the capacitor 98c is sufficiently large, and the time constant between the resistor 98b and the capacitor 98c is also sufficiently large. The DC bias Vbi is determined such that, as described above, the output voltage Vo3 is maintained at the target value Vr [Va < Vr < Va + Vb].

[0110] Next, the operation of the voltage doubler rectifier smoothing circuit 32 and its peripheral circuits will be described based on FIGS. 20(a) and (b). First, the operation during the period Tb(k) will be described. At the timing immediately before the end of the period Ta(k - 1) of the period Tb(k), it is assumed that the DC bias Vbi is maintained at Vbi = Vg21 + Vzd - Va, and the voltage Vc across the coupling capacitor 32a is slightly lower than the steady-state value.

[0111] When period Ta(k-1) ends and period Tb(k) begins, square-wave voltage Vs decreases at a predetermined rate from +Va to -Vb. During this decrease, potential-setting diode 32b turns on, rectifier diode 32c turns off, N-FET 90 conducts, and current flows through the circuit shown by the dashed arrow in FIG. 20(a). This increases voltage Vc across coupling capacitor 32a. When voltage Vc increases to Vbi-Vth, N-FET 90 becomes nonconductive because its source potential cannot decrease (because the source potential is maintained at a potential corresponding to DC bias Vbi). This nonconductive state results in square-wave voltage Vs = -Vb, and drain-source voltage Vds of N-FET 90 reaches a predetermined value. Therefore, just before period Tb(k) ends, voltage Vc = Vg21 + Vzd - Va - Vth. During this period Tb(k), the Zener diode 98d does not operate.

[0112] When period Tb(k) ends and period Ta(k) begins, square-wave voltage Vs rises from -Vb to +Va at a predetermined slope. During this rise, auxiliary diode 72 turns on (N-FET 90 may also turn on, depending on the situation), causing voltage Vds to become approximately 0V. Potential-setting diode 32b turns off and rectifier diode 32c turns on, causing current, as indicated by the dashed arrows, to flow through the circuit in Figure 20(b). When square-wave voltage Vs = +Va, current stops flowing (or becomes very small), pre-rectification voltage Ve1 becomes Vc + Va, rectified voltage Ve2 = Ve1, and output voltage Vo3 = Va + Vc - Vg21 = Vzd - Vth. Thereafter, power is supplied to the internal load 18b, and so just before the end of the period Ta(k), the output voltage Vo3 drops slightly from Va+Vc-Vg21=Vzd-Vth, and the voltage Vc across both terminals also drops slightly from Vg21+Vzd-Va-Vth.

[0113] During this period Ta(k), Zener diode 98d is conductive, Zener current Izd, represented by the solid arrow, flows, voltage (Vg21+Vzd-Va) is applied across capacitor 98c, and DC bias Vbi is determined to be Vbi=Vg21+Vzd-Va. After period Ta(k), the same operation is repeated in the order of period Tb(k+1), period Ta(k+1), period Tb(k+2), and so on, thereby generating a DC output voltage Vo3≈Vzd-Vth.

[0114] In the case of the power supply 96, the equation for output voltage Vo3 ≈ Vzd - Vth does not include the negative peak value -Vb, which fluctuates approximately in proportion to the input voltage Vi. Therefore, the problem of the output voltage Vo3 fluctuating when the input voltage Vi fluctuates does not occur. Also, because the voltage difference Vg21 is not included, the output voltage Vo3 does not change even if the user changes the setting of Vg21. This point will be explained using specific numerical examples along with operating waveforms (assuming that the gate threshold voltage Vth of the N-FET 90 is 0 V).

[0115] When the Zener voltage Vzd is set to 10V, the DC bias Vbi is Vg21 + Vzd - Va = 30V + 10V - 5V = 35V when the voltage difference Vg21 is 30V. Therefore, the operating waveforms are the same as those of the power supply 88 (Figures 18(a) and 18(b)). The output voltage Vo3 is 10V both at low and high Vi. Furthermore, if the voltage difference Vg21 is changed from 30V to 20V, the DC bias Vbi automatically changes to Vg21 + Vzd - Va = 20V + 10V - 5V = 25V. In other words, if the voltage difference Vg21 decreases by 10V, the DC bias Vbi also decreases by 10V. Therefore, as shown in the operating waveforms of Figures 21(a) and 21(b), the output voltage Vo3 is 10V both at low and high Vi. Up to this point, the explanation has been given on the assumption that the forward voltage of each diode is sufficiently small, but if it cannot be ignored, the Zener voltage Vzd can be determined taking the forward voltage of each diode into consideration.

[0116] As described above, the power supply device 96 can achieve the same effects as the power supply device 88 described above, and furthermore, can obtain the desired output voltage Vo3 even when the user changes the setting of the voltage difference Vg21.

[0117] <Other embodiments and modifications> The power supply device of the present invention is not limited to the above-described embodiment. For example, in the power supply device 60 of the second embodiment, the output voltage Vo3 is expressed as Va + Vx2 - Vg21. This equation includes the voltage difference Vg21 (= Vo1). Therefore, if this power supply device is applied to a power supply device in which the user can freely adjust the output voltage Vo1, the desired output voltage Vo3 may not be obtained. However, as in the power supply device 60h of the modified example shown in FIG. 22, by adding a function to the switch control circuit 62 that actively changes the threshold value Vx2 to (Vx2 + ΔV) upon detecting that the voltage difference Vg21 has changed to (Vg21 + ΔV), the desired output voltage Vo3 can be obtained even when the user changes the setting of the voltage difference Vg21 (= Vo1). The relationship between the power supply devices 60 and 60h is substantially the same as that between the power supply device 88 of the sixth embodiment and the power supply device 96 of the seventh embodiment.

[0118] The power supply device 54 of the first embodiment has one voltage doubler rectifying and smoothing circuit 32 that generates the output voltage Vo3, but as in the power supply device 54h-1 of a modified example shown in Figure 23(a), it is possible to configure multiple voltage doubler rectifying and smoothing circuits 32(1), 32(2), ... in parallel, each generating an output voltage Vo3(1), Vo3(2), .... However, because the power supply device 54h-1 has one set of auxiliary switch 56 and switch control circuit 58, the target values ​​Vr of the output voltages Vo3(1), Vo3(2), ... can only be the same value. When it is desired to set the target value Vr of the output voltages Vo3(1), Vo3(2), ... to different values ​​Vr1, Vr2, ..., it is preferable to provide auxiliary switches 56(1), 56(2), ... and switch control circuits 58(1), 58(2), ... separately for multiple voltage doubler rectifying and smoothing circuits 32(1), 32(2), ..., as in the power supply device 54h-2 of the modified example shown in Figure 23(b). The configuration in which multiple voltage doubler rectifying and smoothing circuits 32, 52 are provided in parallel can also be applied to the power supply devices of the other embodiments.

[0119] The power supply devices 68, 80 of the fourth and fifth embodiments use a P-FET 70 (P-channel MOS FET), but as shown in FIG. 24(a), this may be replaced with a PNP transistor 100. In this case, the drain, source, and gate of the P-FET 70 are replaced with the collector, emitter, and base, respectively, and the gate threshold voltage −Vth is replaced with the base-emitter saturation voltage −Vth. Furthermore, in order to increase the current amplification factor and stabilize operation, the PNP transistor 100 may be used in a Darlington configuration.

[0120] The power supply devices 88, 96 of the sixth and seventh embodiments use an N-FET 90 (N-channel MOS FET), but as shown in FIG. 24(b), this may be replaced with an NPN transistor 102. In this case, the drain, source, and gate of the N-FET 90 are replaced with the collector, emitter, and base, respectively, and the gate threshold voltage Vth is replaced with the base-emitter saturation voltage Vth. Furthermore, to increase the current amplification factor and stabilize operation, the NPN transistor 102 may be used in a Darlington configuration.

[0121] Additionally, the configurations of the power conversion parts in the above embodiments (the configurations of the main DC-DC converters 12, 42 and auxiliary DC-DC converter 14) are merely examples, and the technology of the present invention can be applied to various types of power supply devices as long as the power conversion part has a predetermined voltage generation winding 26. Furthermore, the voltage difference Vg21 of the second ground line 38 with respect to the first ground line 36 only needs to be Vg21≧0V, and it is also possible to share the first and second ground lines so that Vg21=0V. [Explanation of symbols]

[0122] 10,40,54,54h-1,54h-2,60,60h,64,68,80,88,96 Power supply 22 Switching element 24 Input Winding 26 Voltage generating winding 26g ground terminal 26s amplitude terminal 28,46 Trans 32,52 Voltage doubler rectifier and smoothing circuit 32a coupling capacitor 32b Potential setting diode 32c rectifier diode 32d smoothing capacitor 36 The First Grand Line 38 The Second Grand Line 56 Auxiliary switch 58, 62, 66 Switch control circuit 70 P-FET (P-channel MOS FET) 72,92 Auxiliary diode 74,82,94,98 Bias circuit 90 N-FET (N-channel MOS FET) 100 PNP transistors 102 NPN transistor Vc Voltage across the coupling capacitor Ve1 Pre-rectified voltage Ve2 Rectified voltage Vg21 Voltage difference between the first and second ground lines Vo1, Vo2 output voltage Vo3 Output voltage (voltage difference between one end of the high-voltage side of the smoothing capacitor and the second ground line) Vr Target value of output voltage Vo3 Vs Square wave voltage generated in the voltage generating winding Vsw Voltage across the auxiliary switch

Claims

1. a switching element that generates an intermittent input voltage by intermittently applying an input voltage to a second ground line; a transformer having a plurality of windings; a first ground line; a second ground line that is controlled so that a voltage difference Vg21 (Vg21≧0) with respect to the first ground line is a constant value; and a voltage doubler rectifying and smoothing circuit; The plurality of windings include an input winding to which the input intermittent voltage is applied, and a voltage generation winding having a ground terminal and an amplitude terminal, the ground terminal being connected to the first ground line, and generating a square wave voltage Vs at the amplitude terminal that oscillates in positive and negative directions with respect to the first ground line, the square wave voltage Vs having a positive peak value +Va [Va>0] and a negative peak value −Vb [Vb>0] being controlled so that the positive peak value +Va remains constant regardless of the value of the input voltage, the voltage doubler rectifying and smoothing circuit is a power supply device comprising: a coupling capacitor having one end connected to the amplitude terminal of the voltage generating winding; a potential setting diode having an anode connected to the second ground line and a cathode connected to the other end of the coupling capacitor; a rectifier diode having an anode connected to the other end of the coupling capacitor; and a smoothing capacitor having one end on a high voltage side connected to the cathode of the rectifier diode and one end on a low voltage side connected to the first ground line or the second ground line; an auxiliary switch inserted in series with the coupling capacitor; and a switch control circuit for controlling the on / off of the auxiliary switch, the switch control circuit controlling the auxiliary switch to be kept in an off state at least for a specific period during which the rectangular wave voltage Vs is oscillating in the negative direction; The power supply device is characterized in that, under the control of the switch control circuit, the voltage Vc across the coupling capacitor is prevented from rising above a certain level, and the voltage difference between the high-voltage end of the smoothing capacitor and the second ground line is maintained at a target value Vr [Va < Vr < Va + Vb].

2. 2. The power supply device according to claim 1, wherein the switch control circuit detects the square-wave voltage Vs, turns off the auxiliary switch when the instantaneous value of the square-wave voltage Vs drops from +Va and reaches a predetermined threshold value −Vx1 [0 < Vx1 < Vb], and then turns on the auxiliary switch when the instantaneous value of the square-wave voltage Vs rises from −Vb and becomes equal to or greater than the threshold value −Vx1.

3. 2. The power supply device according to claim 1, wherein the switch control circuit detects the voltage Vc across the coupling capacitor and the voltage Vsw across the auxiliary switch, turns off the auxiliary switch when the voltage Vc across the coupling capacitor rises and reaches a predetermined threshold Vx2 [0 < Vx2 < Vb + Vg21], and then turns on the auxiliary switch when the voltage Vsw across the auxiliary switch that is off becomes zero or when the positive and negative polarities of the voltage Vsw across the auxiliary switch are reversed.

4. 4. The power supply device according to claim 3, wherein a setting of the voltage difference Vg21 can be variably adjusted by a user, and when the switch control circuit detects that the voltage difference Vg21 has been changed to a voltage difference (Vg21+ΔV), the switch control circuit actively changes the setting of the threshold Vx2 to (Vx2+ΔV), thereby maintaining a voltage difference between one end on the high-voltage side of the smoothing capacitor and the second ground line at a target value Vr [Va<Vr<Va+Vb].

5. a switching element that generates an intermittent input voltage by intermittently applying an input voltage to a second ground line; a transformer having a plurality of windings; a first ground line; a second ground line that is controlled so that a voltage difference Vg21 (Vg21≧0) with respect to the first ground line is a constant value; and a voltage doubler rectifying and smoothing circuit; The plurality of windings include an input winding to which the input intermittent voltage is applied, and a voltage generation winding having a ground terminal and an amplitude terminal, the ground terminal being connected to the first ground line, and generating a square wave voltage Vs at the amplitude terminal that oscillates in positive and negative directions with respect to the first ground line, the square wave voltage Vs having a positive peak value +Va [Va>0] and a negative peak value -Vb [Vb>0] being controlled so that the negative peak value -Vb remains constant regardless of the value of the input voltage, the voltage doubler rectifying and smoothing circuit is a power supply device comprising: a coupling capacitor having one end connected to the amplitude terminal of the voltage generating winding; a potential setting diode having an anode connected to the second ground line and a cathode connected to the other end of the coupling capacitor; a rectifier diode having an anode connected to the other end of the coupling capacitor; and a smoothing capacitor having one end on a high voltage side connected to the cathode of the rectifier diode and one end on a low voltage side connected to the first ground line or the second ground line; an auxiliary switch inserted in series with the coupling capacitor; and a switch control circuit for controlling the on / off of the auxiliary switch; the switch control circuit detects the square wave voltage Vs, and turns off the auxiliary switch when an instantaneous value of the square wave voltage Vs rises from −Vb and reaches a predetermined threshold value Vx3 [0<Vx3<Va], and thereafter controls to turn on the auxiliary switch when the instantaneous value of the square wave voltage Vs falls from +Va and becomes equal to or less than the threshold value Vx3; a power supply device characterized in that, under the control of the switch control circuit, a pre-rectification voltage Ve1, which is the voltage at the anode of the rectifier diode when the potential of the first ground line is set as a reference potential, is prevented from rising above a certain level, and a voltage difference between one end of the high-voltage side of the smoothing capacitor and the second ground line is maintained at a target value Vr [Va<Vr<Va+Vb].

6. a switching element that generates an intermittent input voltage by intermittently applying an input voltage to a second ground line; a transformer having a plurality of windings; a first ground line; a second ground line that is controlled so that a voltage difference Vg21 (Vg21≧0) with respect to the first ground line is a constant value; and a voltage doubler rectifying and smoothing circuit; The plurality of windings include an input winding to which the input intermittent voltage is applied, and a voltage generation winding having a ground terminal and an amplitude terminal, the ground terminal being connected to the first ground line, and generating a square wave voltage Vs at the amplitude terminal that oscillates in positive and negative directions with respect to the first ground line, the square wave voltage Vs having a positive peak value +Va [Va>0] and a negative peak value −Vb [Vb>0] being controlled so that the positive peak value +Va remains constant regardless of the value of the input voltage, the voltage doubler rectifying and smoothing circuit is a power supply device comprising: a coupling capacitor having one end connected to the amplitude terminal of the voltage generating winding; a potential setting diode having an anode connected to the second ground line and a cathode connected to the other end of the coupling capacitor; a rectifier diode having an anode connected to the other end of the coupling capacitor; and a smoothing capacitor having one end on a high voltage side connected to the cathode of the rectifier diode and one end on a low voltage side connected to the first ground line or the second ground line; a PNP transistor inserted between the coupling capacitor and the amplitude terminal of the voltage generating winding, the PNP transistor having an emitter connected to one end of the coupling capacitor and a collector connected to one end of the voltage generating winding; a bias circuit that applies a DC bias Vbi to a base of the PNP transistor using the potential of the first ground line as a reference potential; and an auxiliary diode having an anode connected to the collector of the PNP transistor and a cathode connected to the emitter of the PNP transistor, during a specific period while the rectangular wave voltage Vs is oscillating in the negative direction, the PNP transistor is rendered non-conductive by maintaining the emitter potential at a potential corresponding to the DC bias Vbi, thereby preventing the voltage Vc across the coupling capacitor from rising above a certain level, and maintaining the voltage difference between the high-voltage end of the smoothing capacitor and the second ground line at a target value Vr [Va < Vr < Va + Vb].

7. a switching element that generates an intermittent input voltage by intermittently applying an input voltage to a second ground line; a transformer having a plurality of windings; a first ground line; a second ground line that is controlled so that a voltage difference Vg21 (Vg21≧0) with respect to the first ground line is a constant value; and a voltage doubler rectifying and smoothing circuit; The plurality of windings include an input winding to which the input intermittent voltage is applied, and a voltage generation winding having a ground terminal and an amplitude terminal, the ground terminal being connected to the first ground line, and generating a square wave voltage Vs at the amplitude terminal that oscillates in positive and negative directions with respect to the first ground line, the square wave voltage Vs having a positive peak value +Va [Va>0] and a negative peak value -Vb [Vb>0] being controlled so that the negative peak value -Vb remains constant regardless of the value of the input voltage, the voltage doubler rectifying and smoothing circuit is a power supply device comprising: a coupling capacitor having one end connected to the amplitude terminal of the voltage generating winding; a potential setting diode having an anode connected to the second ground line and a cathode connected to the other end of the coupling capacitor; a rectifier diode having an anode connected to the other end of the coupling capacitor; and a smoothing capacitor having one end on a high voltage side connected to the cathode of the rectifier diode and one end on a low voltage side connected to the first ground line or the second ground line; a PNP transistor inserted between the coupling capacitor and the amplitude terminal of the voltage generating winding, the emitter of which is connected to one end of the coupling capacitor and the collector of which is connected to one end of the voltage generating winding; a bias circuit that applies to the base of the PNP transistor a DC bias Vbi, the reference potential of which is the potential of the amplitude terminal when the rectangular wave voltage Vs is at a positive peak value +Va; and an auxiliary diode having an anode connected to the collector of the PNP transistor and a cathode connected to the emitter of the PNP transistor, during a specific period while the rectangular wave voltage Vs is oscillating in the negative direction, the PNP transistor is rendered non-conductive by maintaining the emitter potential at a potential corresponding to the DC bias Vbi, thereby preventing the voltage Vc across the coupling capacitor from rising above a certain level, and maintaining the voltage difference between the high-voltage end of the smoothing capacitor and the second ground line at a target value Vr [Va < Vr < Va + Vb].

8. 8. The power supply device according to claim 6, wherein the PNP transistor is replaced with a P-channel MOS type FET.

9. 9. The power supply device according to claim 8, wherein the auxiliary diode is substituted by a parasitic diode between the drain and source of the MOSFET.

10. a switching element, a transformer having a plurality of windings, a first ground line, a second ground line that is controlled so that a voltage difference Vg21 (Vg21≧0) with respect to the first ground line is a constant value, and a voltage doubler rectifying and smoothing circuit; The plurality of windings include an input winding to which an intermittent voltage that interrupts the input voltage is applied by turning on and off the switching element, and a voltage generation winding having a ground terminal and an amplitude terminal, the ground terminal being connected to the first ground line, and the amplitude terminal generating a square wave voltage Vs that oscillates in positive and negative directions with respect to the first ground line, the square wave voltage Vs having a positive peak value +Va [Va>0] and a negative peak value -Vb [Vb>0] being controlled so that the positive peak value +Va is a constant value regardless of the value of the input voltage, the voltage doubler rectifying and smoothing circuit is a power supply device comprising: a coupling capacitor having one end connected to the amplitude terminal of the voltage generating winding; a potential setting diode having an anode connected to the second ground line and a cathode connected to the other end of the coupling capacitor; a rectifier diode having an anode connected to the other end of the coupling capacitor; and a smoothing capacitor having one end on a high voltage side connected to the cathode of the rectifier diode and one end on a low voltage side connected to the first ground line or the second ground line; an NPN transistor inserted between the connection point of the potential setting diode and the rectifier diode and the coupling capacitor, the emitter of which is connected to one end of the coupling capacitor and the collector of which is connected to the connection point of the potential setting diode and the rectifier diode; a bias circuit that applies a DC bias Vbi to the base of the NPN transistor, the reference potential of which is the potential of the amplitude terminal when the rectangular wave voltage Vs is at a negative peak value −Vb; and an auxiliary diode having an anode connected to the emitter of the NPN transistor and a cathode connected to the collector of the NPN transistor, during a specific period while the rectangular wave voltage Vs is oscillating in the negative direction, the NPN transistor is rendered non-conductive by maintaining the emitter potential at a potential corresponding to the DC bias Vbi, thereby preventing the voltage Vc across the coupling capacitor from exceeding a certain level, and maintaining the voltage difference between the high-voltage end of the smoothing capacitor and the second ground line at a target value Vr [Va < Vr < Va + Vb].

11. 11. The power supply device of claim 10, wherein a setting of the voltage difference Vg21 can be variably adjusted by a user, and when the bias circuit detects that the voltage difference Vg21 has been changed to a voltage difference (Vg21+ΔV), it actively changes the DC bias Vbi to a DC bias (Vbi+ΔV), thereby maintaining a voltage difference between one end of the high-voltage side of the smoothing capacitor and the second ground line at a target value Vr [Va<Vr<Va+Vb].

12. 12. The power supply device according to claim 10, wherein the NPN transistor is replaced with an N-channel MOS type FET.

13. 13. The power supply device according to claim 12, wherein the auxiliary diode is substituted by a parasitic diode between the drain and source of the MOSFET.

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