Semiconductor device and writing method

Abstract

To provide a semiconductor device that suppresses an increase in writing time and a memory cell writing method.SOLUTION: A semiconductor device 1 includes an input circuit INCKT that is provided with a high voltage at time of writing and performs writing into a memory cell according to data held in an FF circuit FF and further includes a memory controller MCTR that supplies, to the input circuit, a data string IO having pieces of data as many as the FF circuits FF and makes the FF circuits FF hold them. The memory controller includes a pop counter circuit PP_CNT that counts the number of pieces of inverted data included in the data string, and, based on the number counted by the pop counter circuit, divides the FF circuits FF into a plurality of regions so that the number of FF circuits FF storing the inverted data becomes equal to or less than a predetermined number, selects the plurality of regions at mutually different timings, and controls the input circuit so as to simultaneously write the data held in the FF circuit FF arranged in the selected region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a writing method, and more particularly to a semiconductor device including a plurality of variable resistance memory cells and a method for writing data to the variable resistance memory cells. [Background technology]

[0002] A resistance change memory cell (hereinafter simply referred to as a memory cell) refers to a memory cell having a memory element whose resistance value changes depending on the information (data) stored therein. An example of an electrically rewritable nonvolatile memory device (hereinafter simply referred to as a nonvolatile memory device) configured with such memory cells is a magnetoresistive random access memory (hereinafter also referred to as an MRAM).

[0003] An MRAM includes a memory array circuit and a memory controller that reads and writes data from and to the memory array circuit in accordance with instructions from, for example, a processor. Here, the memory array circuit includes, for example, multiple memory blocks, each of which has multiple memory cells arranged in a matrix, input / output circuits corresponding to the multiple memory blocks, and a boost circuit that generates a high voltage. For example, when writing data, data is supplied from the memory controller to the input / output circuit. The input / output circuit supplies the high voltage generated by the boost circuit to the multiple memory cells in accordance with the supplied data, thereby writing data to the multiple memory cells.

[0004] MRAM is described in, for example, Non-Patent Documents 1 and 2. Non-Patent Documents 1 and 2 show that in MRAM, before writing data, a read is performed to determine whether or not rewriting is necessary. Non-Patent Document 1 also shows that if it is determined that rewriting is not necessary, the write signal is masked, and Non-Patent Document 2 shows that when rewriting is performed, the voltage applied to the memory cell is gradually increased. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] “7.2 4Mb STT-MRAM-Based Cache with Memory-Access-Aware Power Optimization and Write-Verify-Write / Read-Modify-Wite Scheme”, ISSCC 2016 / SESSION 7 / NONVOLATILE MEMORY SOLUTIONS / 7.2, 2016 IEEE International Solid-State Circuit Conference. [Non-patent document 2] “13.3 A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique”, ISSCC 2019 / SESSION 13 / NON-VOLATILE MEMORIES / 13.3, 2019 IEEE International Solid-State Circuit Conference. Summary of the Invention [Problem to be solved by the invention]

[0006] When changing the state (resistance value) of a memory cell by writing, i.e., when rewriting, it is necessary to supply a high voltage generated by a boost circuit to the memory cell. To prevent an increase in the occupied area, the boost circuit has a limited current supply capacity. This current supply capacity limit imposes a limit on the number of memory cells that can be rewritten simultaneously. Therefore, when rewriting a large number of memory cells, the write operation must be performed over multiple cycles, which poses a problem of long write times.

[0007] Non-Patent Documents 1 and 2 disclose that it is determined whether or not rewriting is necessary, but do not disclose the current supply capability of the booster circuit. [Means for solving the problem]

[0008] A brief summary of a representative embodiment of the present invention will be given below.

[0009] That is, a semiconductor device according to one embodiment includes a memory array circuit including a plurality of data lines, a plurality of memory cells connected to the plurality of data lines, a plurality of memory circuits, an input circuit to which a high voltage is supplied during writing and which writes data to the memory cells according to data stored in the memory circuits, and a memory controller that supplies a data string having a number of data corresponding to the number of memory circuits to the input circuit and causes the plurality of memory circuits to store the data. Here, the data string contains a mixture of inverted data that changes the state of the memory cells when written to the memory cells and non-inverted data that does not change the state of the memory cells. The memory controller also includes a counter circuit that counts the number of inverted data included in the data string, and based on the count by the counter circuit, divides the plurality of memory circuits storing the data string into a plurality of regions, selects the plurality of regions at different times, and controls the input circuit to simultaneously write the data stored in the memory circuits arranged in the selected regions so that the number of memory circuits storing inverted data is equal to or less than a predetermined number.

[0010] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Effects of the Invention]

[0011] According to one embodiment, it is possible to provide a semiconductor device that can prevent the write time from becoming long. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram showing a configuration of a semiconductor device according to a first embodiment. [Figure 2] 2A and 2B are diagrams for explaining the generation of a P write data string and an AP write data string by the memory controller according to the first embodiment. [Figure 3] FIG. 3 is a diagram for explaining the pop counter circuit according to the first embodiment. [Figure 4] FIG. 4 is a diagram for explaining the determination circuit according to the first embodiment. [Figure 5] FIG. 5 is a diagram for explaining the determination circuit according to the first embodiment. [Figure 6] FIG. 6 is a diagram illustrating the determination circuit according to the first embodiment. [Figure 7] FIG. 7 is a diagram for explaining data output from the bit operation circuit according to the first embodiment to the lookup table. [Figure 8] FIG. 8 is a diagram for explaining data output from the bit operation circuit according to the first embodiment to the lookup table. [Figure 9] 9A and 9B are diagrams for explaining the write operation according to the first embodiment. [Figure 10] FIG. 10 is a flowchart showing the operation of the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a circuit diagram showing a configuration example of a memory array circuit according to the first embodiment. [Figure 12] FIG. 12 is a timing chart for explaining the operation of the memory array circuit according to the first embodiment. [Figure 13] FIG. 13 is a diagram illustrating a semiconductor device according to a modification of the first embodiment. [Figure 14] FIG. 14 is a diagram illustrating a semiconductor device according to a modification of the first embodiment. [Figure 15] 15(A) and 15(B) are diagrams for explaining a semiconductor device according to the second embodiment. [Figure 16] FIG. 16 is a diagram illustrating a semiconductor device according to a modification of the second embodiment. [Figure 17] FIG. 17 is a block diagram showing a configuration of a semiconductor device according to a modification of the second embodiment. [Figure 18] FIG. 18 is a diagram illustrating a lookup table according to a modification of the second embodiment. [Figure 19] FIG. 19 is a block diagram showing a configuration of a semiconductor device according to the third embodiment. [Figure 20] FIG. 20 is a diagram for explaining a semiconductor device according to the third embodiment. [Figure 21] 21(A) and 21(B) are diagrams for explaining the write operation according to the third embodiment. [Figure 22] FIG. 22 is a timing chart for explaining the write operation according to the third embodiment. [Figure 23] 23(A) and (B) are diagrams showing an example of the configuration of an MRAM. [Figure 24] 24(A) to 24(C) are diagrams showing the configuration of an MRAM studied by the present inventors. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. Note that the disclosure is merely an example, and those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention.

[0014] Also, in this specification and each figure, elements that are the same as those described above with respect to the previously shown figures may be denoted by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0015] <Comparative Example> In order to suppress the increase in write time, the inventors studied the configuration of MRAM based on Non-Patent Documents 1 and 2, etc. To facilitate the understanding of the semiconductor device according to the embodiment, first, a configuration example of MRAM and the configuration of the studied MRAM will be described. FIG. 23 is a diagram showing a configuration example of MRAM. Here, FIG. 2(A) is a block diagram showing a configuration example of MRAM, and FIG. 2(B) is a timing diagram showing the timing at the time of writing the MRAM shown in FIG. 2(A). Further, FIG. 24 is a diagram showing the configuration of the MRAM (hereinafter also referred to as a comparative example) studied by the inventors. Here, FIG. 24(A) is a block diagram showing the configuration of the comparative example, FIG. 24(B) is a timing diagram showing the write timing of the comparative example, and FIG. 24(C) is a timing diagram for explaining the outline of the embodiment.

[0016] <<One Configuration Example of MRAM>> In FIG. 23(A), 1 indicates a semiconductor device. The semiconductor device 1 includes a processor CPU, a memory controller MCTR, and a memory array circuit MARY. The memory array circuit MARY shown in FIG. 23 includes eight memory blocks MB0 to MB7 and an input / output circuit IOCKT corresponding to the memory blocks MB0 to MB7.

[0017] Since the memory blocks MB0 to MB7 have similar configurations, the following description will be given taking memory block MB0 as an example. Memory block MB0 can simultaneously write and read data at a predetermined bit width (32 bits in FIG. 23(A)). In the case of a write operation, 32-bit data is supplied from the memory controller MCTR to the input / output circuit IOCKT via the input data bus DI_BS[31:0]. The memory controller MCTR also supplies the input / output circuit IOCKT with a block selection signal BL_SL[7:0]. The block selection signal BL_SL[7:0] corresponds one-to-one to the memory blocks MB0 to MB7. For example, the block selection signal BL_SL[0] corresponds to memory block MB0, and the block selection signal BL_SL[7] corresponds to memory block MB7.

[0018] During a write operation, when the memory controller MCTR sets, for example, the block selection signal BL_SL[0] to a selection level (high level), the memory block MB0 corresponding to this block selection signal BL_SL[0] is selected, and in the input / output circuit IOCKT, 32 bits of data on the input data bus DI_BS[31:0] are supplied to memory block MB0 via the input / output circuit section (hereinafter also referred to as the block input / output circuit) corresponding to memory block MB0, and are written to the 32 memory cells in memory block MB0 substantially simultaneously.

[0019] Since memory blocks MB1 to MB7 are similar to memory block MB0, the memory controller MCTR can supply and write 32 bits x 8 = 256 bits of data (data string) IO[255:0] to the memory array circuit MARY. This data string IO[255:0] to be written is supplied to the memory controller MCTR as write data from the processor CPU operating according to a program. The processor CPU also supplies the memory controller MCTR with an address to which the data string IO[255:0] should be written and a write command. In response to the write command, the memory controller MCTR supplies a write command to the memory array circuit MARY and also supplies a write address (not shown) to the memory array circuit MARY. As a result, the data string IO[255:0] is written to the memory cells (32 x 8) specified by the write address in the memory array circuit MARY.

[0020] In this specification, data (data string) having multiple bits m+1 is represented by [m:0]. For example, a data string IO[255:0] indicates that it is composed of 256 bits, from the least significant bit data IO[0] to the most significant bit data IO

[0255] . Furthermore, data at a predetermined position i in the data string IO is represented by IO[i], and a data string in a predetermined range (for example, bits 0 to i) is represented by IO[i:0].

[0021] As shown in Figure 23(B), the memory controller MCTR can write the data string IO[255:0] to the memory blocks MB0 to MB7 by changing the block selection signals BL_SL[0] to BL_SL[7] to the selection level in that order.

[0022] Although not shown in Figure 23(A), the memory array circuit MARY is equipped with a boost circuit, which performs a boost operation to generate a high voltage in response to a change in the selection level of the block selection signals BL_SL[0] to BL_SL[7].

[0023] As described in the "Problem to be Solved by the Invention" section, when changing the resistance value of a memory cell, i.e., when rewriting a memory cell, it is necessary to supply a high voltage to the memory cell. To prevent an increase in the occupied area, the boost circuit has a limited current supply capacity, and the number of memory cells that can be simultaneously rewritten is limited to a predetermined number. In the example shown in FIG. 23, the predetermined number is 32. Therefore, to write a 256-bit data string IO[255:0] to the memory array circuit MARY, the write operation is performed over eight cycles, as shown in FIG. 23(B), resulting in a long write time.

[0024] <<Configuration of the Comparative Example>> Based on Non-Patent Documents 1 and 2, the present inventors have devised, as a comparative example, an MRAM in which the memory array circuit MARY and the memory controller MCTR in FIG. 23 are modified to prevent the write time from becoming longer.

[0025] FIG. 24(A) shows the configuration of a comparative example that the present inventors investigated prior to the present invention. FIG. 24(A) shows only the memory array circuit MARY and the input / output circuit IOCKT shown in FIG. 23(A). In FIG. 24(A), D1_1, D1_2, D2_1, D2_2, and D2_3 indicate areas where data is to be rewritten. That is, in the data string IO[255:0] to be written, the areas where data is to be rewritten are areas D1_1, D1_2, D2_1, D2_2, and D2_3, and the remaining areas are areas where data is not to be rewritten.

[0026] Non-Patent Documents 1 and 2 disclose a technique in which data is read before being written to determine whether or not it needs to be rewritten. Based on this technique, in the comparative example of FIG. 24, data is read from memory blocks MB0 to MB7 before writing the data string IO[255:0], and the memory blocks that need to be rewritten are determined. In the example shown in FIG. 24(A), memory blocks MB1, MB3, MB4, and MB6 include areas D1_1, D1_2, and D2_1, D2_2, and D2_3 to be rewritten, and therefore are determined as memory blocks that need to be rewritten. In the comparative example, only block selection signals BL_SL[1], BL_SL[3], BL_SL[4], and BL_SL[6] that select memory blocks MB1, MB3, MB4, and MB6 determined to need to be rewritten are sequentially set to the selection level, as shown in FIG. 24(B). This allows the data string IO[255:0] to be written by executing only four cycles instead of eight cycles, thereby reducing the write time.

[0027] However, in the comparative example, the memory block is the unit of the write area, and even if the total number of memory cells to be rewritten contained in areas D1_1 and D1_2 in two memory blocks MB1 and MB3 is less than a predetermined number (32), two cycles of write operations corresponding to the two memory blocks MB1 and MB3 are required, which still poses the problem of long write time.

[0028] <<Outline of the embodiment>> In an embodiment described later, a memory block is not used as a unit of a write area, and a write area is specified as an area in which the number of memory cells to be rewritten substantially simultaneously is a predetermined number (32) or less. For example, if the total number of memory cells to be rewritten contained in areas D1_1 and D1_2 is a predetermined number or less, and the total number of memory cells to be rewritten contained in areas D2_1, D2_2, and D2_3 is also a predetermined number or less, as shown in FIG. 24(C), the block selection signals BL_SL[1] and BL_SL[3] are simultaneously set to the selection level, and the block selection signals BL_SL[4] and BL_SL[6] are simultaneously set to the selection level. As a result, as shown in FIG. 24(C), it is possible to write the data string IO[255:0] by performing only two cycles of write operation, thereby further reducing the write time.

[0029] In Fig. 24(A), the numbers 1 and 2 added immediately after the symbol D in the symbols D1_1, D1_2, D2_1, D2_2, and D2_3 indicating the areas to be rewritten represent the cycle in which writing is performed in Fig. 24(C). That is, the areas to be rewritten D1_1 and D1_2 are areas to be written in the first cycle, and the areas to be rewritten D2_1 to D2_3 are areas to be written in the second cycle.

[0030] (Embodiment 1) <Configuration of semiconductor device> Fig. 1 is a block diagram showing the configuration of a semiconductor device according to embodiment 1. In Fig. 1, 1 indicates a semiconductor device. The semiconductor device 1 includes multiple circuit blocks formed on the same semiconductor substrate, but to avoid complicating the drawing, Fig. 1 depicts only the circuit blocks necessary for explanation.

[0031] In FIG. 1, MARY indicates a memory array circuit, MCTR indicates a memory controller, and CPU indicates a processor.

[0032] The processor CPU reads a program from a storage device (not shown) and executes a predetermined process in accordance with the read program. In this predetermined process, the processor CPU issues a write command and a read command to the memory controller MCTR. When issuing a write command, the processor CPU issues to the memory controller MCTR a data string to be written to the MRAM (write data string) and an address indicating the address to write to in the MRAM (write address).

[0033] 1 shows an example in which the MRAM is configured by a memory array circuit MARY and a memory controller MCTR. However, the MRAM may be configured by, for example, only the memory array circuit MARY, and the memory controller MCTR may be a circuit block that controls the MRAM under the control of the processor CPU.

[0034] <<Memory array circuit>> <<<Memory Blocks>>> In the first embodiment, the memory array circuit MARY includes eight memory blocks MB0 to MB7 and an input / output circuit IOCKT. Since the memory blocks MB0 to MB7 have similar configurations, only the memory block MB0 will be described here as a representative.

[0035] Although not shown, the memory block MB0 includes a plurality of memory cells arranged in a matrix (array), a word line arranged in each row, and a pair of bit lines and source lines arranged in each column. As will be shown later in FIG. 11 and other examples, a plurality of memory cells arranged in the same row are connected to the word line arranged in that row, and a plurality of memory cells arranged in the same column are connected to a pair of bit lines and source lines arranged in that column. In a write operation, when a select level is applied to a word line, a plurality of memory cells connected to that word line are selected, and data is written to the selected memory cells according to the voltages on the pair of bit lines and source lines. In a read operation, when a select level is applied to a word line, a plurality of memory cells connected to that word line are selected, and the voltage on the bit line changes according to the data stored in the selected memory cells. In this specification, the bit lines and source lines are collectively referred to as data lines.

[0036] In memory block MB0, the number of memory cells arranged in one row is 32, and by supplying a selection level to the word line, all 32 memory cells can be selected simultaneously. This allows memory block MB0 to simultaneously read and write the 32-bit (32-bit width) data string UIO[31:0] during read and write operations.

[0037] The configuration of memory blocks MB1 to MB7 is similar to that of memory block MB0. However, word lines are shared among memory blocks MB0 to MB7. In FIG. 1, UIO[255:224] exemplifies a 32-bit data string that can be simultaneously read and written in memory block MB7. The other memory blocks MB1 to MB6 also have 32-bit data strings UIO[m:n] that can be simultaneously read and written. However, the position m of the start bit and the position n of the end bit of the 32-bit data string UIO that can be read and written differ for each memory block, and the overall memory blocks MB0 to MB7 have a 256-bit data string IO[255:0].

[0038] <<<Input / output circuits>>> The input / output circuit IOCKT includes an input circuit INCKT and an output circuit OPCKT. The input circuit INCKT is a circuit used in write operations, and the output circuit OPCKT is a circuit used in read and write operations.

[0039] The input circuit INCKT has eight block input circuits BINCKT in one-to-one correspondence with the memory blocks MB0 to MB7, and the output circuit OPCKT also has eight block output circuits BOPCKT in one-to-one correspondence with the memory blocks MB0 to MB7. In this specification, the block input circuits BINCKT and block output circuits BOPCKT in one-to-one correspondence with the memory blocks are collectively referred to as the block input / output circuit corresponding to the memory block.

[0040] The block output circuit BOPCKT corresponding to memory block MB0 has 32 unit output circuits, the number of which corresponds to the bit width (32 bits) of memory block MB0. During a read operation, the 32 unit output circuits output the voltages on the 32 bit lines in the corresponding memory block MB0 to the memory controller MCTR as 32-bit read data. The block output circuits BOPCKT corresponding to the other memory blocks MB1 to MB7 operate in a similar manner, outputting the voltages on the bit lines in the corresponding memory blocks to the memory controller MCTR as read data during a read operation. In FIG. 1, the 256-bit (32 bits x 8 = 256 bits) data string output from the eight block output circuits BOPCKT corresponding to memory blocks MB0 to MB7 to the memory controller MCTR during a read operation is shown as DO_Data[255:0].

[0041] The eight block input circuits BINCKT corresponding to the memory blocks MB0 to MB7 are connected to the memory controller MCTR via an input data bus DI_BS[31:0], input data selection lines DI_SL[7:0], and block selection signals (block selection lines) BL_SL[7:0]. The memory controller MCTR divides a 256-bit data string IO[255:0] to be written to the memory blocks MB0 to MB7 into 32-bit data strings and supplies them to 32 input data buses DI_BS[31:0] in a time-division manner. The memory controller MCTR also supplies an input data selection signal to the input data selection lines DI_SL[7:0], which specifies to which of the memory blocks MB0 to MB7 the divided 32-bit data should be supplied.

[0042] For example, when supplying a 32-bit data string to the block input circuit BINCKT corresponding to memory block MB0, the memory controller MCTR supplies, for example, a high-level (selection level) input data selection signal to the input data selection line DI_SL[0] that specifies memory block MB0, and supplies a low-level (non-selection level) input data selection signal to the input data selection lines DI_SL[1] to DI_SL[7] that specify the remaining memory blocks MB1 to MB7. The input data bus DI_BS[31:0] is common to the eight block input circuits BINCKT corresponding to memory blocks MB0 to MB7, but by supplying a high-level input data selection signal only to the block input circuit BINCKT corresponding to memory block MB0, the 32-bit data string on the input data bus DI_BS[31:0] is taken in only by memory block MB0.

[0043] The block input circuits corresponding to the other memory blocks MB1 to MB7 are similar to the block input circuit corresponding to memory block MB0. The memory controller MCTR supplies a 32-bit data string corresponding to memory block MB0 to the input data bus DI_BS[31:0] and supplies a high-level input data line selection signal to the input data selection line DI_SL[0]. Then, it supplies a 32-bit data string corresponding to memory block MB1 to the input data bus DI_BS[31:0] and supplies a high-level input data line selection signal to the input data selection line DI_SL[1]. At this time, it supplies a low-level input data line selection signal to the input data selection lines DI_SL[0] and DI_SL[7:2] other than the input data selection line DI_SL[1]. As a result, the 32-bit data string corresponding to memory block MB1 is taken in only by the block input circuit corresponding to memory block MB1.

[0044] Thereafter, the memory controller MCTR sequentially supplies 32-bit data strings corresponding to memory blocks MB2 to MB7 to the input data bus DI_BS[31:0], and supplies high-level input data line selection signals to the input data selection lines DI_SL[2] to DI_SL[7] in that order, resulting in the 256-bit data string IO[255:0] being taken into the eight block input circuits BINCKT corresponding to memory blocks MB0 to MB7.

[0045] <<<<Unit input circuit>>>> The block input circuit BINCKT includes a unit input circuit UIN corresponding to a pair of bit line and source line in the corresponding memory block. Since the memory block according to the first embodiment is 32 bits wide, the block input circuit BINCKT includes 32 unit input circuits. Of the 32 unit input circuits included in the block input circuit BINCKT corresponding to memory block MB0, three unit input circuits UIN[0] to UIN[2] are shown as examples in FIG. 1. Since the 32 unit input circuits have the same configuration, the following description will be given taking the unit input circuit UIN[0] as an example.

[0046] The unit input circuit UIN[0] includes a flip-flop circuit (hereinafter also referred to as an FF circuit) FF and an AND circuit (logic circuit) ALG. The FF circuit FF includes a trigger terminal TG_T, an input terminal IN_T, and an output terminal OU_T. The trigger terminal TG_T is connected to the input data selection line DI_SL[0] corresponding to the memory block MB among the input data selection lines DI_SL[7:0], and the input terminal IN_T is connected to one input data bus DI_BS[0] among the input data buses DI_BS[31:0]. The AND circuit ALG is a two-input AND circuit, with one input terminal connected to the output terminal OU_T of the FF circuit FF and the other input terminal connected to the block selection signal BL_SL[0] corresponding to the memory block MB0 among the block selection signals BL_SL[7:0].

[0047] When a selection level (high level) input data selection signal is supplied to the input data selection line DI_SL[0] connected to the trigger terminal TG_T, the FF circuit FF in the unit input circuit UIN[0] captures and holds the data (logical value 1 or 0) on the input data bus DI_BS[0] connected to the input terminal IN_T. When a selection level (high level) specifying the selection of memory block MB0 is supplied to the block selection signal BL_SL[0], the AND circuit ALG supplies the data (1 or 0) held in the FF circuit FF to the corresponding memory block MB0 as input data to be written (one bit of the data string IO[255:0]; hereinafter, also referred to as the write enable signal) IO[0]. In the case of a write operation, in memory block MB0, the voltages of the bit line and source line corresponding to the unit input circuit UIN[0] become values ​​corresponding to the data held in the FF circuit FF, and rewriting, etc., is performed.

[0048] The other unit input circuits UIN[1] to UIN

[31] arranged in the block input circuit BINCKT corresponding to the memory block MB0 are similar to the unit input circuit UIN[0], but the input data bus DI_BS[31:0] to which the input terminal IN_T of the unit input circuits is connected is different. For example, in the unit input circuit UIN[1], the input terminal IN_T of the FF circuit FF is connected to the input data bus DI_BS[1], in the unit input circuit UIN[2], the input terminal IN_T of the FF circuit FF is connected to the input data bus DI_BS[2], and in the unit input circuit UIN

[31] (not shown), the input terminal IN_T of the FF circuit FF is connected to the input data bus DI_BS

[31] .

[0049] As a result, when an input data selection signal at a selection level is supplied to the input data selection line DI_SL[0], the 32 unit input circuits UIN[0] to UIN

[31] in the block input circuit BINCKT corresponding to the memory block MB0 will hold the 32-bit data string IO[31:0] of the 256-bit data string IO[255:0] supplied from the memory controller MCTR.

[0050] The block input circuit BINCKT corresponding to memory blocks MB1 to MB7 also has 32 unit input circuits UIN[0] to UIN

[31] , similar to the block input circuit BINCKT corresponding to memory block MB0. The unit input circuit for memory block MB0 differs from the unit input circuits for the other memory blocks MB1 to MB7 in that the input data selection line connected to the trigger terminal TG_T of the FF circuit FF is different from the memory block selection line connected to the other input terminal of the AND circuit ALG. That is, the input data selection lines DI_SL[1] to DI_SL[7] are connected to the trigger terminal TG_T of the FF circuit FF corresponding to memory blocks MB1 to MB7, and the block selection signals BL_SL[1] to BL_SL[7] are connected to the other input terminal of the AND circuit ALG.

[0051] As a result, when the memory controller MCTR sets the input data selection lines, for example, to the selection level in the order of DI_SL[0] to DI_SL[7], the 256-bit data string IO[255:0] supplied to the input data bus DI_BS[31:0] in a time-division manner is held in 256 (32×8) unit input circuits in the block input circuit BINCKT corresponding to the memory blocks MB0 to MB7. Also, in a write operation, the memory controller MCTR changes the block selection signal BL_SL[7:0] to the selection level, thereby supplying the data string previously held in the unit input circuit to the corresponding memory block, thereby enabling rewriting, etc.

[0052] <<Memory Controller>> Next, the memory controller MCTR will be described. The memory controller MCTR performs read and write operations on the memory array MARY in accordance with read and write commands from the processor CPU. This specification will describe the write operation by the memory controller MCTR. Therefore, in the memory controller MCTR shown in FIG. 1, only circuit blocks mainly related to write operations are shown, and circuit blocks mainly related to read operations are omitted.

[0053] The memory controller MCTR includes a write data register W_DR, a read data register R_DR, a P / AP write register P / AP_DR, a data in sequencer D_ISQ, a write selector W_SEL, a bit calculation circuit B_CAL, a look-up table LUT, and a write sequencer W_SQR. In the case of a write operation, the processor CPU supplies a write command, a write address, and a write data string to the memory controller MCTR. In this case, the write data string is a 256-bit data string W_Data[255:0].

[0054] When a write command is supplied, the memory controller MCTR according to the first embodiment writes the write data sequence W_Data

[0256] from the processor CPU to the write data register W_DR. The memory controller MCTR also supplies the write address from the processor CPU as a read address to the memory array circuit MARY, and instructs the memory array circuit MARY to perform a read operation to read the 256-bit data sequence stored at the address specified by the read address. In response to this instruction, the memory array circuit MARY reads the data stored in the 256 memory cells specified by the read address and supplies the data as a read data sequence DO_Data[255:0] from the output circuit OPCKT to the memory controller MCTR. In the memory controller MCTR, this read data sequence DO_Data[255:0] is stored in the read data register R_DR.

[0055] The memory controller MCTR can identify the data portion to be rewritten in the data sequence by comparing the data sequence stored in the read data register R_DR and the write data register W_DR.

[0056] The MRAM according to the first embodiment has a P-write mode and an AP-write mode as write operations. Here, the P-write mode refers to a mode in which a memory cell designated by a write address is rewritten to a logical value of "0," and the AP-write mode refers to a mode in which a memory cell designated by a write address is rewritten to a logical value of "1." For example, in the P-write mode, the resistance value of the designated memory cell is changed to a low value, and in the AP-write mode, the resistance value of the designated memory cell is changed to a high value (a value higher than the resistance value achieved in the P-write mode).

[0057] Memory controller MCTR generates a P-write data sequence PW-Data and an AP-write data sequence APW-Data by computing the read data sequence DO_Data[255:0] stored in the read data register R_DR and the write data sequence W_Data[255:0] stored in the write data register W_DR. The memory controller MCTR stores the generated P-write data sequence PW-Data / AP-write data sequence APW-Data in a 256-bit P / AP write register P / AP_DR.

[0058] <<<Generation of P-write data sequence and AP-write data sequence>> Next, the method for generating the P-write data sequence PW-Data and the AP-write data sequence APW-Data will be described using the drawings. FIG. 2 is a diagram for explaining the generation of the P-write data sequence and the AP-write data sequence by the memory controller according to Embodiment 1. Here, FIG. 2(A) shows the equations used in the generation of the P-write data sequence PW-Data and the AP-write data sequence APW-Data, and FIG. 2(B) shows an example of the generated P-write data sequence PW-Data and AP-write data sequence APW-Data.

[0059] The P-write data sequence PW-Data is generated by the equation (1) shown in FIG. 2(A), and the AP-write data sequence APW-Data is generated by the equation (2) shown in FIG. 2(A). The symbols " ~ " shown in equations (1) and (2) indicate bit-by-bit logical inversion, and the symbol "&" indicates bit-by-bit logical multiplication.

[0060] Taking equation (1) as an example, "( ~W_Data[255:0]" indicates that each bit of the 256-bit write data string W_Data[255:0] is inverted, and equation (1) indicates that a 256-bit P write data string PW-Data is generated by performing a logical product operation between each bit of the write data string W_Data[255:0] inverted for each bit and each bit of the read data string DO_Data[255:0]. Equation (2) indicates that a 256-bit AP write data string APW-Data is generated by performing a logical product operation between each bit of the write data string W_Data[255:0] and each bit of the read data string DO_Data[255:0] inverted for each bit.

[0061] Equations (3) and (4) shown in Figure 2(A) show the P write data string PW-Data and the AP write data string APW-Data when the write data string W_Data[255:0] is "01100101000..." and the read data string DO_Data[255:0] is "00010101100...", as shown in the premise.

[0062] 2B shows a more specific example, specifically indicating the four lowest bits of the write data string W_Data and the read data string DO_Data. That is, the table shows a case where the four lowest bits of the write data string W_Data[255:0] are "0101" and the four lowest bits of the read data string DO_Data[255:0] are "0011." In this case, the four lowest bits of the P write data string PW-Data are calculated as "0010" according to equation (1), and the four lowest bits of the AP write data string APW-Data are calculated as "0100" according to equation (2).

[0063] The calculated data sequence PW-Data for P-write and the data sequence APW-Data for AP-write are stored in the P / AP write register P / AP_DR. Although not particularly limited, the memory controller MCTR according to Embodiment 1 first generates the data sequence PW-Data for P-write and stores it in the P / AP write register P / AP_DR. Thereafter, the memory controller MCTR generates the data sequence APW-Data for AP-write and stores it in the P / AP write register P / AP_DR.

[0064] As understood from FIG. 2(B), in the read data sequence DO_Data[255:0] and the write data sequence W_Data[255:0], when the logical values are different at the same bit position, that is, in the write operation of the write data sequence W_Data[255:0], at the bit position where the rewrite operation is performed, in the data sequence PW-Data for P-write or the data sequence APW-Data for AP-write, the logical value at that bit position becomes "1", and at the bit position where the rewrite operation is not performed, the logical value becomes "0". The data sequences PW-Data for P-write and APW-Data for AP-write are data sequences in which the logical value "1" indicating that it is a rewrite target and the logical value "0" indicating that it is not a rewrite target are mixed. Similarly, the write data sequence W_Data[255:0] supplied from the processor CPU can also be regarded as a data sequence in which bits to be rewritten (inverted data) and bits not to be rewritten (non-inverted data) are mixed.

[0065] Returning to FIG. 1, the description will be continued.

[0066] <<<<Writing of Data for P-Write>>>> The data sequence PW-Data for P-write stored in the P / AP write register P / AP_DR is supplied to the write selector W_SEL and the bit calculation circuit B_CAL.

[0067] The write selector W_SEL is controlled by the data-in sequencer D_ISQ. That is, the data-in sequencer D_ISQ controls the write selector W_SEL to divide the supplied 256-bit data string into 32-bit units from the least significant bit to the most significant bit, and to output the eight 32-bit data strings obtained by the division to the input data bus DI_BS[31:0] in a time-division manner. In addition, the data-in sequencer D_ISQ controls the write selector W_SEL to sequentially output selection levels to the input data selection lines DI_SL[0] to DI_SL[7] when outputting the 32-bit data string in a time-division manner.

[0068] As a result, the 256-bit P write data string PW-Data supplied from the P / AP write register P / AP_DR to the write selector W_SEL is divided into 32 bits and sequentially supplied from the 32 FF circuits FF in the block input circuit BINCKT corresponding to memory block MB0 to the 32 FF circuits FF in the block input circuit BINCKT corresponding to memory block MB7, and sequentially stored therein. That is, the 256-bit P write data string PW-Data is taken into the eight block input circuits BINCKT corresponding to memory blocks MB0 to MB7 as a data string IO[255:0].

[0069] As will be explained in detail later, the bit calculation circuit B_CAL counts the number of logical "1"s contained in the supplied P write data string PW-Data, which indicate that the data is to be rewritten. Based on the counting result, the bit calculation circuit B_CAL generates a block selection signal that specifies the memory blocks to be simultaneously written to, and the order in which the data is to be written. The block selection signal and the order in which the data is to be written generated by the bit calculation circuit B_CAL are supplied to and stored in the lookup table LUT.

[0070] The write sequencer W_SQR outputs a cycle signal indicating the write order to the lookup table LUT according to an instruction from the bit calculation circuit B_CAL. Also, the write sequencer W_SQR supplies the memory array MARY with a mode signal PW / APW-Mode indicating whether it is in the P write mode or the AP write mode, an address based on the write address from the processor CPU, and a write instruction P / AP-Write instructing the write operation.

[0071] The lookup table LUT selects a block selection signal corresponding to the write order specified by the cycle signal supplied from the write sequencer W_SQR from the pre-stored block selection signals and the write order, and sets the selected block selection signal to the selection level. As a result, as shown in Fig. 24(C), for example, two or more block selection signals can become the selection level at the same time, enabling simultaneous writing to two or more memory blocks across the boundaries between the memory blocks.

[0072] <<<<Writing of Data for AP Write>>>> After writing the P write data string PW-Data to the memory array MARY, the memory controller MCTR generates an AP write data string APW-Data by calculating the read data string DO_Data[255:0] stored in the read data register R_DR and the write data string W_Data[255:0] stored in the write data register W_DR, and stores the AP write data string APW-Data in the P / AP write register P / AP_DR. The 256-bit AP write data string APW-Data stored in the P / AP write register P / AP_DR is supplied to and stored in the block input circuits BINCKT corresponding to the memory blocks MB0 to MB7 in 32-bit units by the data in sequencer D_ISQ and the write selector W_SEL, similar to the P write data string P-Data. Similarly to the P write data string PW-Data, the 256-bit AP write data string APW-Data is counted by the bit calculation circuit B_CAL to count the number of logical "1"s to be rewritten. Based on the counting result, the bit calculation circuit B_CAL generates a block selection signal that specifies the memory blocks to be simultaneously written to, and the order in which to write, and supplies this to the look-up table LUT for storage.

[0073] Thereafter, the bit calculation circuit B_CAL outputs a cycle signal indicating the write order to the lookup table LUT in accordance with the instruction from the bit calculation circuit B_CAL. Also, the write sequencer W_SQR supplies a mode signal PW / APW-Mode indicating the AP write mode, a write address for P / AP based on the write address from the processor CPU, and a write command P / AP-Write to the memory array MARY.

[0074] The lookup table LUT selects a block selection signal corresponding to the write order specified by the cycle signal supplied from the write sequencer W_SQR from the pre-stored block selection signals and write order, and sets the selected block selection signal to the selection level. As a result, as shown in Figure 24(C), for example, two or more block selection signals can be set to the selection level at the same time, and the AP write data string APW-Data can also be written simultaneously to two or more memory blocks across the boundaries between the memory blocks.

[0075] <<<Bit Calculation Circuit>>> Next, a description will be given of the bit calculation circuit according to embodiment 1. The bit calculation circuit B_CAL includes a pop counter circuit PP_CNT and a determination circuit DJ_CKT that makes a determination based on the counting result by the pop counter circuit PP_CNT.

[0076] The number of memory cells to be rewritten simultaneously is limited to a predetermined number (32 in the first embodiment) depending on the current supply capacity of the booster circuit and the like.

[0077] In the P write mode, the bit calculation circuit B_CAL counts the number of logical "1"s (logical values ​​indicating that the data is to be rewritten) contained in the P write data string PW-Data and determines which block selection signals are simultaneously set to the selected level so that the number is below a predetermined number. To do this, the bit calculation circuit B_CAL must sequentially check the logical values ​​of the 256 bits constituting the P write data string PW-Data using, for example, a clock counter circuit. This means that the clock counter circuit must operate for the number of clocks (number of cycles) corresponding to 256 bits, which increases the counting time. Furthermore, the bit calculation circuit B_CAL also counts the logical "1"s in the AP write data string APW-Data, which further increases the counting time.

[0078] Therefore, in the bit calculation circuit B_CAL according to the first embodiment, the pop counter circuit PP_CNT counts the logical value "1" contained in the P write data string PW-Data and the AP write data string APW-Data. An example of the pop counter circuit PP_CNT will be described with reference to the drawings. Figure 3 is a diagram for explaining the pop counter circuit according to the first embodiment.

[0079] <<<<Pop counter circuit>>>> The pop counter circuit PP_CNT according to the first embodiment is configured by a decode circuit to which a 32-bit data string is input. This decode circuit operates by bit-shifting the input and adding adjacent bits. FIG. 3 shows logical expressions (Equations (5) to (9)) for realizing the decode circuit. In FIG. 3, the least significant 32-bit data string Data[31:0] of a 256-bit data string (e.g., a P write data string PW-Data) is shown as an example of the 32-bit data string input to the decode circuit. Equation (5) indicates that the next "1" is added to the input data string Data. Similarly, Equation (6) indicates that the next "1" is added, and Equations (7), (8), and (9) indicate that the next four "1s," the next eight "1s," and the next 16 "1s" are added. As a result, the number of logical "1"s contained in the input 32-bit data string Data[31:0] is output from the decoding circuit. Since equations (5) to (9) can be executed simultaneously, it is possible to count the number of logical "1"s contained in the 32-bit data string Data[31:0] in one clock (one cycle).

[0080] The memory controller MCTR divides the 256-bit P write data string PW-Data into eight 32-bit pieces and sequentially supplies these to the pop counter circuit PP_CNT, thereby counting the number of logical "1"s contained in the P write data string PW-Data in eight cycles. Similarly, the memory controller MCTR can count the number of logical "1"s contained in the 256-bit AP write data string APW-Data in eight cycles.

[0081] <<<<Judgment circuit>>>> The decision circuit DJ_CKT identifies memory blocks that can be written simultaneously when writing 256-bit data strings (P write data string PW-Data and AP write data string APW-Data) based on the counting result of the pop counter circuit PP_CNT. Also, the decision circuit DJ_CKT identifies the order in which the 256-bit data strings should be written when they are written over multiple cycles based on the counting result.

[0082] The decision circuit DJ_CKT according to the first embodiment will be described with reference to the drawings. Figures 4 to 6 are diagrams for explaining the decision circuit according to the first embodiment.

[0083] 4 shows a table of the counting results of the pop counter circuit PP_CNT. As described above, the memory controller MCTR divides the 256-bit data string Data[255:0] into 32-bit segments and sequentially supplies these to the pop counter circuit PP_CNT. Here, the P write data string PW-Data[255:0] will be used as an example of the data string. Since the data string is divided into 32-bit segments and supplied to the pop counter circuit PP_CNT, the pop counter circuit PP_CNT outputs the number of logical values ​​"1" contained in the 32-bit P write data string PW-Data[31:0] to PW-Data[255:224] (shown as Data[31:0] to Data[255:224] in FIG. 4) as P0 to P7. For example, the symbol P0 indicates the number of logical values ​​"1" contained in the 32-bit P write data string PW-Data[31:0] on the least significant bit side, and the symbol P7 indicates the number of logical values ​​"1" contained in the 32-bit P write data string PW-Data[255:224] on the most significant bit side.

[0084] Based on the numbers P0 to P7, which are the counting results shown in FIG. 4, the decision circuit DJ_CKT makes a decision based on the conditional expressions shown in FIG. 5. That is, the decision circuit uses the numbers P0 to P7 to perform calculations for each of the conditional expressions of the conditions Cond1 to Cond23, and decides whether each conditional expression is true (True = logical value "1") or false (Fail = logical value "0"). In the conditions Cond1 to Cond23, the sign "+" shown in the conditional expression means addition of the number, and the sign "<=" indicates that the condition is true if the value on the right side of the sign is equal to or greater than the value on the left side, and false otherwise. Also, in the conditions Cond1 to Cond23, the sign "&&" indicates the product of the logical value in parentheses on the left side and the logical value in parentheses on the right side. That is, the sign "&&" is true (logical value "1") if the conditions in parentheses on the left side and the right side are both true, and false otherwise.

[0085] An example of the conditions Cond1 to Cond23 shown in FIG. 5 will be explained as follows. For example, in condition Cond1, if the sum of the numbers P0 to P7 is 32 or less, condition 1 is satisfied, and if it exceeds 32, condition 1 is determined to be unsatisfied. In addition, in condition Cond3, if the sum of the numbers P0 and P1 is 32 or less and the sum of the numbers P2 and P3 is 32 or less, condition 1 is satisfied. In other cases, condition 1 is determined to be unsatisfied. Furthermore, in condition Cond12, if the sum of the numbers P0 to P7 is 32 or less and the sum of the numbers P2 and P3 is 32 or less, condition 1 is determined to be unsatisfied. ~ ) 11 are not satisfied, otherwise it is determined that it is not satisfied. Furthermore, in the condition Cond23, the conditions 1 and 13 to (in FIG. 5, the symbols ~ ) 22 is not established, it is determined to be established, otherwise it is determined to be not established.

[0086] The decision circuit DJ_CKT executes the calculations of the conditional expressions of the conditions Cond1 to Cond23, and determines whether each of the conditions Cond1 to Cond23 is satisfied or not.

[0087] The decision circuit DJ_CKT determines the order of memory blocks to be written into, as described below, based on the decision results of whether each of the conditions Cond1 to Cond23 is satisfied or not and the table shown in FIG.

[0088] <<<<Write order>>>> The decision circuit DJ_CKT first determines whether the condition Cond1 is satisfied or not. If the condition Cond1 is satisfied, the write operation is performed under the condition Cond1. On the other hand, if the condition Cond1 is not satisfied, the decision circuit DJ_CKT according to the first embodiment divides the data strings Data[31:0] to Data[255:224] corresponding to the eight memory blocks MB0 to MB7 into two regions (data strings Data[31:0] to Data[127:96] and Data[159:128] to Data[255:224]), and determines the order of the memory blocks to be written into for each region.

[0089] 4 and 5, conditions Cond2 to Cond12 are conditions related to the data sequence Data[31:0] to Data[127:96] of the data sequence Data[31:0] to Data[255:224], and conditions Cond13 to Cond23 are conditions related to the data sequence Data[159:128] to Data[255:224]. Therefore, the order of writing data to the data sequence Data[31:0] to Data[127:96] is specified by conditions Cond2 to Cond12, and the order of writing data to the data sequence Data[159:128] to Data[255:224] is specified by conditions Cond3 to Cond23.

[0090] In the first embodiment, if multiple conditions are satisfied among the conditions Cond2 to Cond12, the write order of the data strings Data[31:0] to Data[127:96] is determined by the condition with the smallest number among the satisfied conditions. Similarly, if multiple conditions are satisfied among the conditions Cond13 to Cond23, the write order of the data strings Data[159:128] to Data[255:224] is determined by the condition with the smallest number among the satisfied conditions.

[0091] 6 is a table showing the relationship between conditions Cond1 to 23, data strings Data[31:0] to Data[255:224], and write orders A to H. The horizontal axis of the table represents conditions Cond1 to 23, and the vertical axis represents data strings Data[31:0] to Data[255:224]. The write order is set at the intersection of the condition on the horizontal axis and the data string on the vertical axis.

[0092] As described above, the conditions Cond2 to Cond12 specify the write order of the data string Data[31:0] to Data[127:96], and therefore the write orders A to D according to the conditions Cond2 to Cond12 are set at the intersections with the data string Data[31:0] to Data[127:96], as shown in the table of Fig. 6. Similarly, the conditions Cond13 to Cond23 specify the write order of the data string Data[159:128] to Data[255:224], and therefore the write orders E to H according to the conditions Cond13 to Cond23 are set at the intersections with the data string Data[159:128] to Data[255:224], as shown in the table of Fig. 6.

[0093] On the other hand, since condition Cond1 is related to eight data strings Data[31:0] to Data[255:224], write order A is set at the intersections of condition Cond1 and each of the data strings Data[31:0] to Data[255:224].

[0094] The write operations are performed in the order of write order A, B, C, D, E, F, G, and H. When all of the write orders A to H are performed, write order A is performed earliest and write order H is performed latest. The determination circuit DJ_CKT identifies the write order by referring to the table in FIG. 6. A plurality of data strings to which the same write order (for example, write order A) is set are written simultaneously.

[0095] <<<<<Example of judgment circuit>>>> When condition Cond1 is satisfied among conditions Cond1 to Cond23 shown on the horizontal axis, the decision circuit DJ_CKT selects the column of this condition Cond1. Because the column of condition Cond1 intersects with the data sequence Data[31:0] to Data[255:224], the decision circuit DJ_CKT generates block selection signals specifying memory blocks MB0 to MB7 corresponding to the data sequence Data[31:0] to Data[255:224] and the write order, and stores these signals in the lookup table LUT.

[0096] On the other hand, if condition Cond1 is not satisfied and multiple conditions among conditions Cond2 to Cond12 (for example, conditions Cond2 to Cond5) and multiple conditions among conditions Cond13 to Cond23 (for example, conditions Cond13 to Cond18) are satisfied, the decision circuit DJ_CKT selects condition Cond2, which has the smallest number among the satisfied conditions Cond2 to Cond5, and condition Cond13, which has the smallest number among the satisfied conditions Cond13 to Cond18.

[0097] When conditions Cond2 and Cond13 are selected, the decision circuit DJ_CKT selects the column of condition Cond2 in the table of Fig. 6, generates block selection signals specifying memory blocks MB0-MB3 corresponding to the data sequence Data[31:0]-Data[127:96] that intersects with this condition Cond2, and generates a write order A, and stores these in the lookup table LUT. Also, the decision circuit DJ_CKT selects the column of condition Cond13 in the table of Fig. 6, generates block selection signals specifying memory blocks MB4-MB7 corresponding to the data sequence Data[159:128]-Data[255:224] that intersects with this condition Cond13, and generates a write order E, and stores these in the lookup table LUT.

[0098] Furthermore, if condition Cond1 is not satisfied and multiple conditions among conditions Cond2 to Cond12 (for example, conditions Cond3 to Cond5) and multiple conditions among conditions Cond13 to Cond23 (for example, conditions Cond14 to Cond18) are satisfied, the decision circuit DJ_CKT selects condition Cond3, which has the smallest number among the satisfied conditions Cond3 to Cond5, and condition Cond14, which has the smallest number among the satisfied conditions Cond14 to Cond18.

[0099] When conditions Cond3 and Cond14 are selected, the decision circuit DJ_CKT selects the column of condition Cond3 in the table of Figure 6, generates block selection signals that specify memory blocks MB0 and MB1 corresponding to the data strings Data[31:0] and Data[63:32] that intersect with this condition Cond3, and generates a write order A, and further generates block selection signals that specify memory blocks MB2 and MB3 corresponding to the data strings Data[95:64] and Data[127:96] that intersect with the condition Cond3, and generates a write order B, and stores these signals in the lookup table LUT. In addition, the decision circuit DJ_CKT selects the column of condition Cond13 in the table of Figure 6, generates a block selection signal that specifies memory blocks MB4 and MB5 corresponding to the data strings Data[159:128] and Data[191:160] that intersect with this condition Cond13, and generates a write order E, and further generates a block selection signal that specifies memory blocks MB6 and MB7 corresponding to the data strings Data[223:192] and Data[255:224] that intersect with condition Cond14, and generates a write order F, and stores these in the lookup table LUT.

[0100] The bit calculation circuit B_CAL according to the first embodiment can generate a block selection signal specifying the memory block to be written and the order in which to write, with a total of 29 cycles of calculation, consisting of 8 cycles of calculation (P0 to P7 in FIG. 4) by the pop counter circuit PP_CNT and 21 cycles of calculation (conditions Cond1 to 11, Cond13 to 22 in FIG. 5) by the decision circuit DJ_CKT. Note that conditions Cond12 and 23 shown in FIG. 5 are excluded from the number of calculation cycles because they do not require calculation.

[0101] <<<<<Data stored in the lookup table from the decision circuit>>>> 7 and 8 are diagrams for explaining data output from the bit operation circuit according to Embodiment 1 to the lookup table. Conditions Cond1 to Cond12 and the corresponding data are shown in Fig. 7, and conditions Cond13 to Cond23 and the corresponding data are shown in Fig. 8.

[0102] The data corresponding to the conditions consists of one to four 8-bit (8'b) pieces of data. In the data corresponding to conditions Cond1 to Cond12, the symbols "L(0)" to "L(3)" written on the left side of the symbol "=" indicate the cycle. That is, the symbols "L(0)" to "L(3)" indicate the cycle in which the items written on the right side of the symbol "=" are executed, and the execution order is cycles L(0) to L(3). In addition, the symbol "cyc=" written in the data corresponding to conditions Cond2 to Cond12 indicates the number of cycles. The number of symbols L(0) to L(3) is the number of cycles. For example, if the corresponding expression is only L(0), the number of cycles is cyc = 1, and if the corresponding expressions are L(0) to (2), the number of cycles is cyc = 3. Note that condition Cond1 does not occur in combination with conditions 13 to 23, which will be described later, so the number of cycles is not written, and the number of cycles is cyc = 1.

[0103] Furthermore, the code "xxxxxxxx" following the code "8'b" written on the right side of the sign "=" is the block number (block selection signal BL_SL[7:0]) that specifies memory blocks MB to MB7. That is, each of the 8-bit code "xxxxxxxx" corresponds to each of memory blocks MB0 to MB7. For example, memory block MB0 is represented by a least significant bit with a logical value of "1" and is "10000000", and memory block MB7 is represented by a most significant bit with a logical value of "1" and is "00000001". When multiple memory blocks are indicated at the same time, the logical value corresponding to the memory blocks is "1".

[0104] The equations corresponding to conditions Cond13 to 23 are similar to the equations corresponding to conditions Cond1 to 12. The difference is that the symbol indicating the cycle written on the left side of the symbol "=" is "L(0+cyc)" to "L(3+cyc)". Here, the number of cycles of the symbol "cyc" shown in FIG. 7 is substituted for cyc. For example, in the data corresponding to condition Cond13, the cycle written on the left side of the symbol "=" is the value obtained by adding the cycle L(0) indicating 1 cycle to the number of cycles cyc= shown in FIG. 7.

[0105] Next, examples of data output from the bit operation circuit to the look-up table will be described based on the three examples described above in <<<<Determination Examples of the Determination Circuit>>>>.

[0106] First, when the condition Cond1 is satisfied, the bit calculation circuit B_CAL supplies 8'b11111111, which is the data corresponding to the condition Cond1 shown in Fig. 7, to the lookup table LUT, and the lookup table LUT stores this data. Since all 8 bits of this data specifying the block number (block selection signal) have a logical value of "1", all memory blocks MB0 to MB7 are specified in the same cycle.

[0107] Next, when the condition Cond1 is not satisfied and the conditions Cond2 and Cond13 are selected, the bit calculation circuit B_CAL combines the data corresponding to the conditions shown in FIG. 7 and the data corresponding to the conditions shown in FIG. 8 and stores them in the lookup table LUT. That is, the bit calculation circuit B_CAL supplies 8'b11110000, which is the data corresponding to the condition Cond2 shown in FIG. 7, to the lookup table LUT as the data for the first cycle L(0), and the lookup table LUT stores this data. Thereafter, the bit calculation circuit B_CAL supplies 8'b00001111, which is the data corresponding to the condition Cond13 shown in FIG. 8, to the lookup table LUT as the data for the second cycle L(0+cyc (cyc=1: the number of cycles of the condition Cond2)), and the lookup table LUT stores this data. As a result, the data corresponding to the condition Cond2 and the data corresponding to the condition Cond13 are stored in the lookup table LUT in this order.

[0108] Furthermore, if the condition Cond1 is not satisfied and the conditions Cond3 and Cond14 are selected, the bit calculation circuit B_CAL supplies 8'b11000000, which is data corresponding to the condition Cond3 shown in Figure 7, to the lookup table LUT as the data for the 1st cycle L(0)th data, and further supplies data 8'b00110000 to the lookup table LUT as the data for the 2nd cycle L(1)th data. After that, the bit calculation circuit B_CAL supplies 8'b00001100, which is data corresponding to the condition Cond14 shown in Figure 8, to the lookup table LUT as the data for the 3rd cycle L(0 + (cyc = 2: number of cycles of the condition Cond3)), and further supplies data 8'b00000011 to the lookup table LUT as the data for the 4th cycle L(1 + (cyc = 2)). As a result, the data 8'b11000000 and 8'b00110000 corresponding to the condition Cond3, and the data 8'b00001100 and 8'b00000011 corresponding to the condition Cond14 are stored in the lookup table LUT in this order.

[0109] In this way, the bit calculation circuit B_CAL generates the number of cycles for the write operation by adding the number of cycles cyc in the data shown in FIG. 7 to the cycles L(0+cyc) to L(3+cyc) shown in FIG. 8. The generated number of cycles is notified to the write sequencer W_SQR as the number of write operations when writing a 256-bit data string. The write sequencer W_SQR generates a cycle signal that specifies the data stored in the lookup table LUT based on the notified number of cycles, and supplies it to the lookup table LUT.

[0110] <<<Write operation of 256-bit data string>>> Next, we will explain the operation when writing a 256-bit data string output from the P / AP write register P / AP_DR shown in Figure 1 to the memory array circuit MARY. The 256-bit data string is, for example, a P write data string PW-Data[255:0], but it can also be an AP write data string APW-Data[255:0]. Also, in the bit calculation circuit B_CAL, it is assumed that condition Cond1 is not satisfied and conditions Cond2 and Cond13 are selected.

[0111] 9A and 9B are diagrams for explaining a write operation according to the first embodiment, where Fig. 9A shows data stored in a lookup table, and Fig. 9B shows the timing of the write operation.

[0112] Because the condition Cond1 is not satisfied and the conditions Cond2 and Cond13 are selected, the bit calculation circuit B_CAL supplies the data 8'b11110000 to the lookup table LUT as the data for the first cycle L(0), as described in FIGS. 7 and 8, and then supplies the data 8'b00001111 to the lookup table LUT as the data for the second cycle L(1). This 8-bit data for the first cycle and the 8-bit data for the second cycle are stored in the lookup table LUT. This 8-bit data is the block selection signal BL_SL[7:0] that specifies the eight memory blocks that make up the 256-bit data string.

[0113] 9A, the block selection signal BL_SL[7:0], which is data for cycle number 0 (the first cycle) stored in the lookup table LUT, selects memory blocks MB0 to MB3 and deselects memory blocks MB4 to MB7. In contrast, the block selection signal BL_SL[7:0], which is data for cycle number 1 (the second cycle), deselects memory blocks MB0 to MB3 and selects memory blocks MB4 to MB7.

[0114] The write sequencer W_SQR is notified of the cycle number by the bit calculation circuit B_CAL, so in the first cycle, which is cycle number 0, the write sequencer W_SQR supplies a cycle signal specifying cycle number 0 to the lookup table LUT. This causes the lookup table LUT to output a block selection signal BL_SL[7:0] for cycle number 0. In addition, in the second cycle, which is cycle number 1, the write sequencer W_SQR supplies a cycle signal specifying cycle number 1 to the lookup table LUT. This causes the lookup table LUT to output a block selection signal BL_SL[7:0] for cycle number 1.

[0115] 9A and 9B, when the cycle number is 0 (cycle signal is 0), the block selection signals BL_SL[0] to BL_SL[3] have a logical value of 1, and the block selection signals BL_SL[4] to BL_SL[7] have a logical value of 0. Therefore, a logical value of 1 is supplied to the AND circuits ALG of the unit input circuits UIN[0] to UIN

[31] in the block input circuits BINCKT corresponding to the memory blocks MB0 to MB3. Therefore, when the logical value 1 indicating a rewrite is stored in the FF circuits FF in these unit input circuits, rewrites of multiple memory cells are executed simultaneously in the memory blocks MB0 to MB3.

[0116] 9A and 9B, when the cycle number is 1 (cycle signal is 1), the block selection signals BL_SL[0] to BL_SL[3] have a logical value of 0, and the block selection signals BL_SL[4] to BL_SL[7] have a logical value of 1. Therefore, a logical value of 1 is supplied to the AND circuits ALG of the unit input circuits UIN[0] to UIN

[31] in the block input circuit BINCKT corresponding to the memory blocks MB4 to MB7. Therefore, when the logical value 1 indicating a rewrite is stored in the FF circuits FF in these unit input circuits, rewrites of multiple memory cells are executed simultaneously in the memory blocks MB0 to MB3.

[0117] That is, according to FIG. 9, it is possible to carry out rewrite operations on four memory blocks simultaneously across memory block boundaries, and it is possible to prevent the write time from becoming longer.

[0118] Although it is possible to prevent the write time from becoming longer in this way, the memory controller MCTR must perform complex arithmetic processing, and there is a concern that the time required for the arithmetic processing may delay the start of the write operation to the memory array circuit MARY.

[0119] The memory controller MCTR performs the following complex calculations: First, to generate the P write data string PW-Data and the AP write data string APW-Data, it is necessary to perform calculations between the read data string DO_Data[255:0] and the write data string W_Data[255:0]. Furthermore, the bit calculation circuit B_CAL requires calculations by the pop counter circuit PP_CNT and calculations related to conditions by the decision circuit DJ_CKT.

[0120] To reduce the delay in the start of the write operation due to the calculation time, the semiconductor device according to the first embodiment performs the above-described calculation during a transition period between the P write mode and the AP write mode, as will be explained below with reference to the drawings. The transition period is a period during which, for example, a boosting operation is performed by a boost circuit to generate a stable high voltage. This period is unrelated to the complex calculation described above and is required for the write operation. By overlapping the calculation time with the transition period, it is possible to reduce the delay in the start of the write operation.

[0121] <<<Operation flow>>> Fig. 10 is a flow diagram showing the operation of the semiconductor device according to the first embodiment. Fig. 10 shows the flow of the write operation. Hereinafter, with reference to Figs. 1 and 10, it will be described that in the write operation according to the first embodiment, the arithmetic processing and the mode transition processing are executed in parallel.

[0122] In step S0, the memory controller MCTR starts a write operation (Start). In step S1, the memory controller MCTR stores 256-bit write data W-Data from the processor CPU in the write data register W_DR. In the next step S2, the memory controller MCTR reads (Pre-Read) the 256-bit data stored at the address of the memory array circuit MARY specified by the write address.

[0123] The memory controller MCTR then executes steps S3, S4_P to S7_P in that order, and also starts step S8_P when executing step S3. As a result, the processing of steps S3 to S7_P and the processing of step S8_P are executed in parallel. Steps S3 to S7_P are specifically described as follows.

[0124] First, in step S3, the memory controller MCTR stores the read data R-Data read in step S2 in the read data register R_DR. In step S4_P, the memory controller MCTR executes an operation to obtain a 256-bit P write data string PW-Data using the write data W-Data stored in the write data register W_DR and the read data R-Data stored in the read data register R_DR, and stores the P / AP write data string PW-Data in the P / AP write register P / AP_DR.

[0125] Next, in step S5_P, the memory controller MCTR divides the 256-bit P write data string PW-Data stored in the P / AP write register P / AP_DR into eight (x8) 32-bit data strings PW-Data (32 bits) each using the data in sequencer D_ISQ and the write selector W_SEL, and supplies them to the FF circuits FF (32x8=256) in the eight block input circuits BINCKT corresponding to the memory blocks MB0 to MB7. As a result, all of the 256-bit P write data string PW-Data are stored in the 256 FF circuits FF corresponding to the memory blocks MB0 to MB7.

[0126] In step S6_P, the memory controller MCTR executes the calculation process described with reference to Figures 4 and 5, etc., using the pop counter circuit PP_CNT and the decision circuit DJ_CKT. Also, in step S7_P, the memory controller MCTR stores one to eight (x1 to x8) 8-bit data (block selection signals BL_SL[7:0]) obtained in step S6_P in the lookup table LUT. Also, although not particularly limited, in step S7_P, the memory controller MCTR supplies the number of cycles obtained in step S6_P to the write sequencer W_SQR.

[0127] On the other hand, in step S8_P, a transition to the P write mode is performed. In this step S8_P, the memory controller MCTR instructs a boost circuit (not shown) to perform a boost operation to generate a high voltage. It takes a relatively long time for the boost circuit to generate a stable high voltage.

[0128] Next, in step S9_P, 1 to 8 (x1 to x2) stored in the lookup table LUT are ~ From the 8-bit data (block selection signals BL_SL[7:0]) of 8×8), the one identified by the cycle signal from the write sequencer W_SQR is selected, and the selected block selection signals BL_SL[7:0] are supplied to eight block input circuits BINCKT corresponding to memory blocks MB0 to MB7, and P write data is written simultaneously to multiple memory cells across the memory block boundaries using the high voltage generated in step S8_P.

[0129] Steps S4_A to S7_A and S9_A are similar to steps S4_P to S7_P and S9_P. The difference is that in steps S4_A to S7_A and S9_A, the target data is the AP write data string APW-Data. The operations performed in steps S4_A to S7_A and S9_A are the same as those in steps S4_P to S7_P and S9_P, so their explanation will be omitted.

[0130] In step S8_A, which is executed in parallel with steps S4_A to S7_A, a transition to the AP write mode is performed. In this step S8_A, the memory controller MCTR instructs a boost circuit (not shown) to perform a boost operation to generate a high voltage. As a result, a stable high voltage is generated by the boost circuit.

[0131] After the 256-bit data string W-Data is written to the memory array circuit MARY through steps S0 to S9_A, step S10 is executed. In step S10, the memory controller MCTR transitions from the write operation to the standby mode.

[0132] <<<Memory array circuit configuration example>>> Next, a specific configuration example of the memory array circuit MARY according to the first embodiment will be described with reference to the drawings. Here, a case will be described in which the memory array circuit MARY includes a boost circuit that generates a high voltage used for a write operation, but the present invention is not limited to this. For example, the boost circuit may be provided in the memory controller MCTR.

[0133] Fig. 11 is a circuit diagram showing a configuration example of a memory array circuit according to embodiment 1. Fig. 12 is a timing chart for explaining the operation of the memory array circuit according to embodiment 1. Note that while Fig. 11 also shows a memory controller MCTR, Fig. 11 shows only a write sequencer W_SQR, and other circuit blocks are omitted.

[0134] The memory array circuit MARY includes multiple circuit blocks, but only those necessary for explanation are shown in Figure 11. The memory array circuit MARY includes a boost circuit PWC, a distribution circuit (distributor) DIST, a decoder DEC, a word driver WLD, memory blocks MB0 to MB7, and unit input circuits UIN[0] to UIN

[31] .

[0135] Since the memory blocks MB0 to MB7 have similar configurations, the memory block MB0 will be described as an example. The memory block MB0 includes a plurality of memory cells MCL arranged in a matrix, word lines WL arranged in each row (only WL1 is shown as a representative in FIG. 11), and a pair of bit lines BL and source lines SL arranged in each column. The memory block MB0 shown in FIG. 11 includes 32 columns, although this is not a limitation.

[0136] The bit lines BL and source lines SL of each column are connected to the power supply lines VLB and VLS via the source-drain paths of N-channel field-effect transistors (hereinafter also referred to as transistors) N1 and N2 that constitute the column switch. The gates of transistors N1 and N2 are connected to the unit input circuits (e.g., UIN[0]) that correspond to the bit lines BL and source lines SL arranged in the column. The unit input circuits UIN[0] to UIN

[31] have the configuration shown in Figure 1, and write enable signals (input data) IO[0] to IO

[31] output from the unit input circuits are supplied to the gates of transistors N1 and N2 that constitute the column switch.

[0137] Each memory cell MCL includes a select transistor NC and a storage element MTJ. The gate of the select transistor NC is connected to a word line WL1 arranged in a row, the drain is connected to a bit line BL via the storage element MTJ, and the source is connected to a source line SL. The storage element MTJ is, although not limited to, a three-layer magnetic tunneling junction element. This three-layer element is an element with a stacked structure of a pinned layer, a tunneling layer, and a free layer, and its resistance value changes according to the written data.

[0138] The word line WL1 arranged in each row is connected to a decoder DEC via a corresponding word driver WLD. The power supply terminal of the word driver WLD is connected to a power supply line WVD, and the word driver WLD supplies the operating voltage or ground voltage on the power supply line WVD to the word line WL1 in accordance with a selection signal from the decoder DEC.

[0139] The boost circuit PWC is common to the memory blocks MB0 to MB7, and there is only one boost circuit in FIG. 11. This boost circuit PWC includes a charge pump circuit CPC controlled by a mode signal PW / APW-Mode from the write sequencer W_SQR, and a regulator LDO that stabilizes the high voltage generated by the boost operation of the charge pump circuit CPC. When the mode signal PW / APW-Mode indicates the P write mode or AP write mode, the charge pump circuit CPC starts its boost operation, and the high voltage generated by the boost operation is stabilized by the regulator LDO and supplied from the boost circuit PWC to the distribution circuit DIST as a high voltage VCP for writing.

[0140] The distribution circuit DIST supplies a high voltage for writing based on the high voltage VCP supplied from the boost circuit PWC or a ground voltage VS (for example, 0 V) ​​to the power supply lines VLS, VLB, and WVD in accordance with the mode signal PW / APW-Mode.

[0141] When a write command P / AP-Write is supplied, the decoder DEC decodes the write address from the write sequencer W_SQR, generates a selection signal for selecting a word line specified by the write address, and supplies the selection signal to the word driver WLD.

[0142] <<<<<Write High Voltage and Write Operation>>>> The distribution circuit DIST determines the voltages to be supplied to the power supply lines VLS, VLB, and WVD according to the mode specified by the mode signal PW / APW-Mode, ie, whether it is the P write mode or the AP write mode.

[0143] In other words, in the P write mode, the distribution circuit DIST supplies a first high voltage VBL0 based on the high voltage VCP from the boost circuit PWC to the power supply line VLB, a first word line voltage VWL0 based on the high voltage VCP to the power supply line WVD, and a ground voltage VS to the power supply line VLS. At this time, if the write enable signal (e.g., IO[0]) is at a high level corresponding to a logic value of 1, the transistors N1 and N2 become conductive, supplying the first high voltage VBL0 to the bit line BL and the ground voltage VS to the source line SL. Furthermore, if the decoder DEC supplies a high-level select signal specifying the word line WL1 to the word driver WLD, the word driver WLD supplies the first word line voltage VWL0 to the word line WL. This causes the select transistor NC constituting the memory cell MCL to become conductive, causing a current to flow from the power supply line VLB to the power supply line VLS via the memory element MTJ and the select transistor NC, changing the resistance of the memory element MTJ. This means that the memory cell MCL is rewritten.

[0144] In contrast, in the AP write mode, the distribution circuit DIST supplies a second high voltage VSL1 based on the high voltage VCP to the power supply line VLS, a second word line voltage VWL1 based on the high voltage VCP to the power supply line WVD, and a ground voltage VS to the power supply line VLB. At this time, if the write enable signal (e.g., IO[0]) is at a high level corresponding to a logic value of 1, the transistors N1 and N2 become conductive, the second high voltage VSL1 is supplied to the source line SL, and the ground voltage VS is supplied to the bit line BL. Furthermore, if the decoder DEC supplies a high-level select signal specifying the word line WL1 to the word driver WLD, the word driver WLD supplies the second word line voltage VWL1 to the word line WL. This causes the select transistor NC constituting the memory cell MCL to become conductive, causing a current to flow from the power supply line VLS to the power supply line VLB via the select transistor NC and the memory element MTJ, changing the resistance of the memory element MTJ. This means that the memory cell MCL is rewritten.

[0145] If the write enable signal (e.g., IO[0]) is at a low level corresponding to a logical value of 0, the transistors N1 and N2 are turned off, the first high voltage VBL0, the second high voltage VSL1, and the ground voltage VS are not supplied to the bit line BL and the source line SL, and no writing (rewriting) of the memory cell MCL is performed. Similarly, if the selection signal supplied from the decoder DEC to the word driver WLD is at a low level, the selection transistor NC constituting the memory cell MCL is turned off, and no writing (rewriting) of the memory cell MCL is performed.

[0146] 12, at time t1, when the mode signal PW / APW-Mode specifies the P write mode or AP write mode to the memory array circuit MARY, a mode transition to the P write mode or AP write mode begins. During this mode transition period (the period from time t1 to t2), the charge pump circuit CPC starts a boost operation, generating a stable high voltage VCP for writing. After the mode transition, the distribution circuit DIST supplies the high voltages (VBL0, VSL1, VWL0, VWL1) and the ground voltage VS according to the mode to the power supply wiring.

[0147] Although not particularly limited, a write address ADDR is also supplied to the memory array circuit MARY at time t1, and when a write command P / AP-Write is supplied at time t2, the decoder DEC outputs a selection signal to select the word line WL1 specified by the address ADDR, thereby changing the voltage of the word line WL1 to a voltage value that turns on the selection transistor NC of the memory cell MCL.

[0148] When the lookup table LUT shown in FIG. 1 outputs the block selection signal BL_SL[7:0] as shown in FIG. 9(A), memory blocks MB0 to MB3 are simultaneously selected during the period from time t2 to t3 shown in FIG. 12, and memory blocks MB4 to MB7 are simultaneously selected during the period from time t3 to t4.

[0149] As a result, memory cells arranged in memory blocks MB0 to MB3 and corresponding to unit input circuits outputting high-level write enable signals (e.g., IO[0]) are simultaneously rewritten during the period from time t3 to t4. Similarly, memory cells arranged in memory blocks MB4 to MB7 and corresponding to unit input circuits outputting high-level write enable signals (e.g., IO

[0255] ) are simultaneously rewritten during the period from time t3 to t4.

[0150] According to the first embodiment, the number of write enable signals that are simultaneously at a high level during the period from time t2 to t3 is a predetermined number (32) or less. Similarly, the number of write enable signals that are simultaneously at a high level during the period from time t2 to t3 is a predetermined number (32) or less. As a result, it is possible to simultaneously rewrite multiple memory cells while limiting the value of the combined current supplied from the distribution circuit DIST to the memory cells, and it is possible to prevent the write time from becoming long.

[0151] <Modification> 13 and 14 are diagrams for explaining a semiconductor device according to a modification of embodiment 1. Fig. 13 is a block diagram showing the configuration of a semiconductor device according to a modification of embodiment 1. Fig. 14 is a diagram for explaining the write operation of the semiconductor device shown in Fig. 13. Fig. 14 is similar to Fig. 6 and shows the order of memory blocks to be written.

[0152] In the modified example, the semiconductor device 1 includes two memory array circuits MARY1 and MARY2 and a common memory controller MCTR that controls writing to the two memory array circuits MARY1 and MARY2.

[0153] Each of the memory array circuits MARY1 and MARY2 includes eight memory blocks MB0 to MB7, and data is written to each memory block in 32-bit units.

[0154] The memory controller MCTR distributes and writes, for example, a 512-bit data string Data to two memory arrays MARY1 and MARY2. In Fig. 13, D1_1 to D2_2 indicate areas to which the data is distributed and written.

[0155] The memory controller MCTR divides the 512-bit data string into a 256-bit data string for the memory array circuit MARY1 and a 256-bit data string for the memory array circuit MARY2, and writes each as a 32-bit data string Data[31:0] to Data[255:224]. During this writing, the memory controller MCTR performs the counting described in FIG. 4 so that the number of memory cells to be simultaneously rewritten is equal to or less than a predetermined number, and further performs the calculation of the conditions described in FIG. 5. Based on the conditions obtained by this calculation, the memory controller MCTR refers to the table shown in FIG. 14 to determine the memory blocks to be written to and the order in which to write, and then writes to the two memory array circuits MARY1 and MARY2. In FIG. 14, as in FIG. 6, the order of writing is alphabetical.

[0156] Although two memory array circuits are used as an example in the description of FIGS. 13 and 14, the number of memory array circuits is not limited to two and may be any number as long as it is plural.

[0157] In the first embodiment, the unit input circuit (for example, UIN[1]) is configured by an AND circuit ALG and an FF circuit FF as shown in Fig. 1, so that it is possible to suppress an increase in the area occupied by the memory array circuit MARY. Also, since the number of memory cells to be rewritten is counted in units of memory blocks such as 32 bits, and the memory blocks to be simultaneously written and the order of writing are specified, even if the period for transitioning to the P write mode and the AP write mode is short, it is possible to perform the counting of the number of memory cells to be rewritten in parallel during the transition period.

[0158] In the first embodiment, the 256 FF circuits FF corresponding to the memory blocks MB0 to MB7 are divided into a plurality of areas (e.g., symbols A to H in FIG. 6) by the block selection signal BL_SL[7:0] output from the lookup table LUT, and each of the divided areas is selected at a different timing (e.g., symbols L(0) to L(3+cyc) in FIGS. 7 and 8), and writing is performed substantially simultaneously according to the data held in the FF circuits FF included in the selected area. Here, the memory controller MCTR according to the first embodiment generates the block selection signal BL_SL[7:0] for dividing the 256 FF circuits FF into a plurality of areas so that the number of FF circuits FF storing the logical value “1”, which is inverted data, among the 256 FF circuits FF (storage circuits), is equal to or less than a predetermined number (32), and stores the signal in the lookup table LUT. This makes it possible to limit the number of memory cells that are rewritten substantially simultaneously to a predetermined number or less, and even in a boost circuit with low current supply capacity, it is possible to increase the number of memory cells to be written to, thereby reducing the number of write cycles and preventing the write time from becoming longer.

[0159] (Embodiment 2) In the first embodiment, the memory blocks to which the write operation is to be performed simultaneously and the write order are specified for each memory block. In the second embodiment, the areas to which the write operation is to be performed simultaneously and the write order are specified across memory blocks. For example, in the second embodiment, one memory block is divided into multiple (e.g., two) areas, and write operations are performed at different times.

[0160] 15 is a diagram for explaining a semiconductor device according to a second embodiment. As in the first embodiment, the memory controller MCTR according to the second embodiment generates a 256-bit P write data string PW-Data and an AP write data string APW-Data and stores them in the P / AP write register P / AP_DR. FIG. 15(A) shows an example of a 256-bit data string stored in the P / AP write register P / AP_DR. Here, the P write data string PW-Data will be described as an example, but the same applies to the AP write data string APW-Data.

[0161] The memory controller MCTR according to the second embodiment counts the number of logical values ​​"1" in the 256-bit P write data string PW-Data stored in the P / AP write register P / AP_DR, clock by clock, from the least significant bit PW-Data[0] to the most significant bit PW-Data

[0255] , and divides the P write data string PW-Data every time the number of logical values ​​"1" reaches a predetermined number (32). As a result, the P write data string PW-Data is divided into 1 to a maximum of 8 regions, depending on the number of logical values ​​"1".

[0162] 15(B) shows an example in which the P write data string PW-Data is divided into four regions (regions 1 to 4). In the P write data string PW-Data, bit positions where the number of logical values ​​"1" reaches a predetermined number are shown as separation points 1 to 3, with region 1 being the region from the least significant bit to separation point 1, region 2 (3) being the region from separation point 1 (separation point 2) to separation point 2 (separation point 3), and region 4 being the region from separation point 3 to the most significant bit.

[0163] By determining regions 1 to 4 in this manner, the memory controller MCTR can simultaneously perform write operations on multiple memory cells included in region 1 without being limited by memory blocks, while limiting the number of memory cells to be simultaneously rewritten to a predetermined number or less. Similarly, for regions 2, 3, and 4, simultaneous write operations can be performed on memory cells within each region. Furthermore, the write order is, for example, from region 1 to region 4. This makes it possible to write 256 bits of P write data string PW-Data in four cycles, thereby preventing the write time from becoming too long.

[0164] Furthermore, since the circuit for counting the logical value "1" can be realized by a clock counter circuit that occupies a small area, it is possible to reduce the size of the memory controller MCTR.

[0165] <Modification> In Fig. 15, the number of logical values ​​"1" is counted by counting one bit per clock for the 256-bit P write data string PW-Data. Therefore, counting the logical values ​​"1" requires clock cycles equal to the number of bits that make up the P write data string PW-Data. Therefore, there is a concern that the counting time will be long with the method shown in Fig. 15.

[0166] In this modification, the pop counter circuit PP_CNT counts the number of logical values ​​"1" in 32-bit units. When the number of logical values ​​"1" exceeds 32 when counted in 32-bit units by the pop counter circuit PP_CNT, the clock counter circuit identifies the bit position at which the number of logical values ​​"1" exceeds 32, thereby identifying the separation point.

[0167] 16 is a diagram illustrating a semiconductor device according to a modification of the second embodiment. First, the pop counter circuit PP_CNT counts the number of logical "1"s PP1 for the least significant 32-bit data string PW-Data[31:0] of the P write data string PW-Data. Next, the pop counter circuit PP_CNT counts the number of logical "1"s PP2 for the next 32-bit data string PW-Data[63:32]. If the sum of the counted numbers PP1 and PP2 exceeds a predetermined number (32), the clock counter circuit CLK_CNT counts the number of logical "1"s from bit position PW-Data

[31] +1 in the previous data string PW-Data[31:0]. The point at which the sum of the number PP1 counted by the pop counter circuit PP_CNT and the number counted by the clock counter circuit CLK_CNT reaches the predetermined number is identified as separation point 1.

[0168] Next, the pop counter circuit PP_CNT counts each 32-bit data string starting from separation point 1, and when the number counted by the pop counter circuit PP_CNT exceeds a predetermined number, the clock counter circuit CLK_CNT counts to identify separation point 2. Thereafter, separation point 3 is identified in the same manner.

[0169] Fig. 17 is a block diagram showing the configuration of a semiconductor device according to a modification of the second embodiment. Fig. 17 is similar to Fig. 1. The main difference between Fig. 17 and Fig. 1 is that the bit calculation circuit B_CAL, the block input circuits BINCKT corresponding to each of the memory blocks MB0 to MB7, and the look-up table LUT in Fig. 17 are changed from those in Fig. 1.

[0170] 17, the bit calculation circuit B_CAL includes a pop counter circuit PP_CNT, a clock counter circuit CLK_CNT, and an adder circuit ADD_CKT. As described in FIG. 15, the memory controller MCTR counts the number of logical values ​​"1" in units of a 32-bit data string using the pop counter circuit PP_CNT.

[0171] When the number of logical values ​​"1" counted by the pop counter circuit PP_CNT (PP1+PP2) exceeds a predetermined number (32), the memory controller MCTR counts the number of logical values ​​"1" using the clock counter circuit CLK_CNT from the bit position +1 of the previous 32-bit data string, and adds the number of logical values ​​"1" counted by the pop counter circuit PP_CNT to the number of logical values ​​"1" counted by the clock counter circuit CLK_CNT using the adder circuit ADD_CKT, and identifies the bit position in the P write data string PW-Data when the predetermined number (32) is reached as the separation point.

[0172] The memory controller MCTR uses the bit calculation circuit B_CAL to identify separation points for all bits of the P write data string PW-Data, stores the identified separation points (in the example of Figure 16, separation points 1 to 3) in the lookup table LUT, and notifies the write sequencer W_SQR of the identified separation point + 1 as the number of cycles.

[0173] Each block input circuit BINCKT has 32 unit input circuits UIN, as in Fig. 1. Fig. 17 shows three unit input circuits UIN[0] to UIN[2] in the block input circuit BINCKT corresponding to memory block MB0. Since the 32 unit input circuits according to the modified example have the same configuration, the unit input circuit UIN[0] will be described here as an example.

[0174] The unit input circuit UIN[0] includes a three-input AND circuit ALG1, an FF circuit FF, and two comparators (an upper comparator and a lower comparator) CMP_U and CMP_L. The AND circuit ALG1 is supplied with the output of the FF circuit FF, the output of the upper comparator CMP_U, and the output of the lower comparator CMP_L. The output of the AND circuit ALG1 becomes a write enable signal (input data) IO[0], similar to the output of the AND circuit ALG shown in FIG. 1. Furthermore, similar to the FF circuit FF shown in FIG. 1, the FF circuit FF stores data to be written in advance.

[0175] The lower comparator CMP_L compares the bit position A0 corresponding to the least significant bit position PW-Data[0] in the P write data string PW-Data with the lower mask signal MSK_L and outputs the comparison result to the AND circuit ALG1. The upper comparator CMP_U compares the bit position A1 corresponding to the next most significant bit position PW-Data[1] with the upper mask signal MSK_U and outputs the comparison result to the AND circuit ALG1. Here, the bit positions A0 and A1 can be considered as specific information that identifies the area in which the FF circuit FF is located within the unit input circuit UIN[0].

[0176] The other unit input circuits (for example, unit input circuits UIN[1], UIN[2]) are similar to unit input circuit UIN[0], but the bit positions compared in the lower-side comparator CMP_L and the upper-side comparator CMP_U are different. For example, the lower-side comparator CMP_L in unit input circuit UIN[1] compares the bit position A1 corresponding to this unit input circuit UIN[1] with the lower-side mask signal MSK_L, and the upper-side comparator CMP_U compares the upper-side bit position A2 with the upper-side mask signal MSK_U.

[0177] The upper mask signal MSK_U and the lower mask signal MSK_L are output from the lookup table LUT. That is, the separation points stored in the lookup table LUT are output as the upper mask signal MSK_U and the lower mask signal MSK_L.

[0178] Fig. 18 is a diagram for explaining a lookup table LUT according to a modification of the second embodiment. As described above, the lookup table LUT stores separation points identified by the bit calculation circuit B_CAL. Fig. 18 shows an example in which separation points 1 to 3 shown in Fig. 16 and the number of cycles notified to the write sequencer W_SQR are stored in the lookup table LUT.

[0179] The upper mask signal MSK_U and the lower mask signal MSK_L identify regions 1 to 4 shown in FIG. 16. The lookup table LUT outputs separation points as the upper mask signal MSK_U and the lower mask signal MSK_L in the order of cycle numbers 1 to 4 according to the cycle signal from the write sequencer W_SQR. For example, in cycle number 1, the lookup table LUT outputs separation point 1 as the upper mask signal MSK_U and the numerical value 0 as the lower mask signal MSK. As a result, multiple unit input circuits included in the range from numerical value 0 to separation point 1 (range of region 1) are simultaneously selected, allowing multiple memory cells to be simultaneously written. At this time, for those whose FF circuits FF store a logical value "1," the write enable signal becomes a logical value "1," and the memory cells are rewritten. The number of memory cells to be rewritten in region 1 is a predetermined number, 32. At this time, since the area outside the area 1 is masked, even if the logical value "1" is stored in the FF circuit FF, the write valid signal becomes the logical value "0" and no rewrite operation is performed.

[0180] Thereafter, the ranges of regions 2 to 4 are selected in order of cycle numbers 2 to 4, and writing is performed to multiple memory cells simultaneously. As a result, a 256-bit data string (for example, a P write data string PW-Data) is written in four cycles.

[0181] Here, the P write data string has been used as an example, but the same applies to the AP write data string.

[0182] A modified example has been described using Figure 17, but in Figure 17, if the pop counter circuit PP_CNT and the addition circuit ADD_CKT are removed from the bit calculation circuit B_CAL, and the clock counter circuit CLK_CNT counts the number of logical values ​​"1" in the data string for P write and the data string for AP write, and divides them into 32-bit units, the embodiment 2 described in Figure 15(B) can be realized.

[0183] In the second embodiment, the 256 FF circuits FF are divided into a plurality of regions (e.g., regions 1 to 4 in FIGS. 15B and 16) by the mask signals MSK_U and MSK_L output from the lookup table LUT, and each of the divided regions is selected at a different timing (e.g., cycle numbers 1 to 4 in FIG. 18). Data is written substantially simultaneously in accordance with the data held in the FF circuits FF included in the selected region. Here, the memory controller MCTR according to the second embodiment identifies separation points for dividing the 256 FF circuits FF into a plurality of regions so that the number of FF circuits FF storing inverted data in the 256 FF circuits FF (storage circuits) is a predetermined number (32) or less. This makes it possible to limit the number of memory cells to be rewritten substantially simultaneously to a predetermined number or less. This makes it possible to increase the number of memory cells to be written to even in a booster circuit with low current supply capability, thereby reducing the number of write cycles and preventing the write time from becoming longer.

[0184] (Embodiment 3) According to the second embodiment, it is possible to prevent the write time from becoming longer by specifying the area to be written by the separation point. However, for example, in Fig. 17, each unit input circuit requires two comparators CMP_U and CMP_L, which may increase the occupied area.

[0185] Fig. 19 is a block diagram showing the configuration of a semiconductor device according to embodiment 3. Fig. 19 is similar to Fig. 1 and Fig. 17. The main difference from Fig. 1 is that the data-in sequencer D_ISQ, write selector W_SEL, lookup table LUT, write sequencer W_SQR, bit calculation circuit B_CAL, and unit input circuit are changed in Fig. 19.

[0186] First, the unit input circuit will be explained. The memory array circuit MARY has 256 unit input circuits UIN[0] to UIN

[0255] to correspond to the 256-bit input data (write enable signal) IO[255:0]. Since these unit input circuits are similar to each other, the unit input circuit UIN[n] will be explained as a representative example. The unit input circuit UIN[n] is composed of AND circuits ALG2, AND1, AND2, OR circuits OR, FF circuits FF, and a data selector D_SEL.

[0187] In FIG. 19, the symbol U_MSK indicates an upper mask circuit that implements a function equivalent to the function implemented by the upper mask signal and the upper comparator CMP_U described in the modified example of the second embodiment, i.e., the function of allowing the write enable signal to have a logical value of "1" on the lower side from the separation point. The upper mask circuit U_MSK includes an AND circuit AND1 and an OR circuit OR. The inputs of the OR circuit OR are connected to the input data Data[n] in the input data bus DI_BS[31:0] and the block selection signal BL_SL[n+1], and the inputs of the AND circuit AND1 are connected to the output of the OR circuit OR and the block selection signal BL_SL[n]. The output of the AND circuit AND1 is the write area signal W_ARA, which is the output of the upper mask circuit U_MSK.

[0188] 19, the symbol L_MSK indicates a lower mask circuit that implements a function equivalent to the function implemented by the lower mask signal and the lower comparator CMP_L described in the modified example of the second embodiment, i.e., the function of prohibiting the write enable signal from becoming logical "1" on the lower side from the separation point. The lower mask circuit L_MSK includes an AND circuit AND2, and the inputs of the AND circuit AND2 are connected to the write area signal W_ARA and the reset enable signal RST_EN.

[0189] The data selector D_SEL has two selection terminals S0 and S1 (in FIG. 19, the symbol S is omitted and symbols 0 and 1 are used), three input terminals 00, 01, and 1X, and an output terminal OT. According to the logical values ​​supplied to the selection terminals S0 and S1, the data selector D_SEL selects one of the three input terminals and electrically connects the selected input terminal to the output terminal OT.

[0190] That is, when the data-in enable signal Data-In_EN supplied to the selection terminal S0 is a logical "1" and the output of the AND circuit AND2 supplied to the selection terminal S1 is a logical "0", the data selector D_SEL outputs data Data[n] in the input data bus DI_BS[31:0] connected to the input terminal 1X from the output terminal OT. Also, when the data-in enable signal Data-In_EN at the selection terminal S0 is a logical "0" and the output of the AND circuit AND2 at the selection terminal S1 is a logical "0", the data selector D_SEL outputs 1-bit data output from the FF circuit FF connected to the input terminal O0 to the output terminal OT. Furthermore, when the data-in enable signal Data-In_EN at the selection terminal S0 is a logical "0" and the output of the AND circuit AND2 at the selection terminal S1 is a logical "1", the data selector D_SEL outputs 1-bit data supplied to the input terminal O1 with a logical "0" to the output terminal OT.

[0191] The FF circuit FF stores and outputs the 1-bit logical value data output from the data selector D_SEL.

[0192] The output of the FF circuit FF and the write area signal W_ARA are supplied to the input of the AND circuit ALG2, and the output of the AND circuit ALG2 becomes the write valid signal (input data) IO[n].

[0193] The data-in enable signal Data-In_EN is output from the data-in sequencer D_ISQ, and becomes a logical value "1" when P write data or AP write data is stored in the FF circuit FF.

[0194] The input data bus DI_BS[31:0] and the block selection signal BL_SL[7:0] are connected to the write selector W_SEL and the look-up table LUT. The reset enable signal RST_EN is output from the write sequencer W_SQR.

[0195] In the first embodiment, as shown in Fig. 1, the input data bus DI_BS[31:0] and the input data selection line DI_SL[7:0] are used to store P write data or AP write data in the FF circuit FF, and the block selection signal BL_SL[7:0] is used to select the write area. In contrast, in Fig. 19, the input data bus DI_BS[31:0] and the block selection signal BL_SL[7:0] are used to select both the storage of P write data or AP write data in the FF circuit FF and the write area. This makes it possible to reduce the number of buses to be arranged, and to prevent an increase in the occupied area.

[0196] In the unit input circuit UIN[n] shown in Figure 19, the upper mask circuit U_MSK realizes the function of identifying the separation point on the upper side of the write area, and after the P write data or AP write data held in the FF circuit FF is written, the lower mask circuit L_MSK resets the FF circuit FF to a logical value of "0" to identify the separation point on the lower side of the write area. By setting the logical value stored in the FF circuit FF to "0" in this way, the write enable signal is prohibited from becoming a logical value of "1," and rewriting is prevented. As a result, the lower mask circuit L_MSK essentially identifies the separation point on the lower side of the write area.

[0197] Although the unit input circuit UIN[n] has been used as an example, the other unit input circuits have the same configuration, except that the bit position of Data connected to the data selector D_SEL and the OR circuit OR and the block selection signal to which the OR circuit OR and the AND circuit AND1 are connected are different according to the corresponding memory block and the corresponding write enable signal.

[0198] As shown in FIG. 19, the bit calculation circuit B_CAL includes a pop counter circuit (first counter circuit) PP_CNT and a clock counter circuit (second counter circuit) CLK_CNT. The memory controller MCTR counts the number of logical values ​​"1" in 32-bit units using the pop counter circuit PP_CNT, and continues counting until the number of logical values ​​"1" reaches a predetermined number. Furthermore, when the count by the pop counter circuit PP_CNT exceeds the predetermined number, the memory controller MCTR counts the number of logical values ​​"1" for the excess 32-bit unit area using the clock counter circuit CLK_CNT. Furthermore, the memory controller MCTR identifies the bit position where the logical value "1" exists when the number of logical values ​​"1" reaches the predetermined number using the clock counter circuit CLK_CNT.

[0199] In FIG. 19, the memory controller MCTR represents the result of the 32-bit counting by the pop counter circuit PP_CNT as a logical value of "1" for the corresponding block select signal. For example, if the counting result of the least significant P write data string PW-Data[31:0] is equal to or less than a predetermined number, the least significant block select signal BL_SL[0] is set to a logical value of "1." The memory controller MCTR also generates a 32-bit input data string Data that reflects the bit positions of the logical value "1" identified by the clock counter circuit CLK_CNT. The block select signal and input data string Data generated by the bit calculation circuit B_CAL are supplied to and stored in the lookup table LUT.

[0200] Next, an example of operation will be described with reference to the drawings. Figure 20 is a diagram for explaining the semiconductor device according to the third embodiment.

[0201] 20, the data at the bit position where the number of logical "1"s in the P write data string PW-Data reaches a predetermined number is shown as Data[n]. In the example of FIG. 20, the bit position of Data[n] is within the 32-bit data string stored in memory block MB3.

[0202] The memory controller MCTR determines that the number of logical "1"s counted by the pop counter circuit PP_CNT in the bit calculation circuit B_CAL for memory blocks MB0 to MB3 exceeds a predetermined number, and sets the block selection signals BL_SL[7:0] corresponding to memory blocks MB0 to MB3 to [1, 1, 1, 1, 0, 0, 0, 0]. It sets all selection signals corresponding to the memory block where the separation point is located (MB3 in this example) and the memory blocks to the left of it (toward MB0) to "1." The memory controller MCTR also determines that the number of logical "1"s counted by the pop counter circuit PP_CNT for memory block MB3 exceeds a predetermined number, and counts the number of logical "1"s in memory block MB3 using the clock counter circuit CLK_CNT. When the number of logical "1"s reaches the predetermined number, the memory controller MCTR identifies the bit position reached in the 32 bits corresponding to memory block MB3. 20, the bit position of the fourth bit is identified. The memory controller MCTR sets all bits from the identified bit position (fourth bit) to the left (lowest order side) to a logical value of "1" and all bits from the fifth bit to the right (highest order side) to a logical value of "0" to generate the input data string Data[31:0]=32'b11110000...0.

[0203] The block select signal generated by the memory controller MCTR is supplied to the upper mask circuit U_MSK in the unit input circuit UIN[n] shown in FIG. 19. For memory blocks on the left side (MB0 side) of the memory block where the separation point is located, selection is performed based on the result of a bitwise AND operation between the block select signal BL_SL[n] and the block select signal BL_SL[n+1]. This operation generates a block select signal BL_SL[n+1]&BL_SL[n]=[1, 1, 1, 0, 0, 0, 0, 0] that selects memory blocks MB0 to MB2. As a result, the first region 0_0 that constitutes region 0 is selected as shown in FIG. 20.

[0204] Also, the input data string Data[31:0] generated by the memory controller MCTR is supplied to the input data bus DI_BS[31:0]. In the memory block where the separation point is located, a bitwise AND operation is performed between the block selection signal BL_SL[n] and the input data string Data[31:0]. This AND operation selects the second region 0_1 that constitutes region 0, as shown in FIG. 20.

[0205] In area 0, the write area signal W_ARA has a logical value of 1. As a result, if the logical value of 1 is stored in the FF circuit FF, the write enable signal IO[n] becomes high level, and rewriting is executed.

[0206] After writing, the write sequencer W_SQR sets the reset enable signal RST_EN to a logical value of "1." When the write area signal W_ARA and the reset enable signal RST_EN both become logical values ​​of "1," the data selector D_SEL supplies the logical value of "0" supplied to the input terminal 01 to the FF circuit FF, resetting the data in the FF circuit FF to a logical value of "0." As a result, even if the write area signal W_ARA becomes logical value "1" in the next cycle, the write enable signal IO[n] becomes logical value "0," and no rewrite operation is performed.

[0207] 21 is a diagram for explaining a write operation according to the third embodiment. FIG. 21 shows a case where a 256-bit P write data string PW-Data is written. Of course, the same applies to the AP write data string APW-Data. In FIG. 21, as shown in FIG. 20, the separation point is identified by the fourth bit of memory block MB3, and FIG. 21(A) shows a case where data in area 0 on the lower side from the separation point is simultaneously written, and data in area 1 on the upper side from the separation point is simultaneously written.

[0208] In this case, the lookup table LUT stores the block selection signal BL_SL[7:0] and the input data string Data[31:0] as shown in Fig. 21(B) from the bit calculation circuit B_CAL. During a write operation, the cycle signal from the write sequencer W_SQR selects the block selection signal BL_SL[7:0] and the input data string Data[31:0] in the order of write cycle numbers 1 and 2, and supplies them to the 256 unit input circuits UIN[0] to UIN

[0255] , thereby performing the write operation.

[0209] Fig. 22 is a timing diagram for explaining a write operation according to embodiment 3. In Fig. 22, clk represents a clock signal, and for example, the charge pump circuit CPC (Fig. 11) and the like operate in synchronization with this clock signal.

[0210] A write operation starts by issuing a write command P / AP-Write (changing to a logical value of "1" in FIG. 22). The memory controller MCTR supplies the memory array circuit MARY with a block selection signal BL_SL[7:0] that sequentially specifies multiple memory blocks B0, B1, and an input data string Data[31:0] that sequentially indicates input data D0, D1.

[0211] In the 256 unit input circuits UIN, the write area signal W_ARA specifying area 0 becomes logical "1" based on the block selection signal BL_SL[7:0] specifying memory block B0 and the input data string Data[31:0] indicating input data D0, and the write enable signal corresponding to the FF circuit FF corresponding to area 0, in which logical "1" is stored, becomes logical "1", thereby executing rewriting. Thereafter, the reset enable signal RST_EN becomes logical "1", thereby resetting the FF circuit FF corresponding to area 0.

[0212] Thereafter, in the same manner as in the case of the area 0, the area 1 is rewritten and the corresponding FF circuit FF is reset.

[0213] The operation flow of the semiconductor device according to the third embodiment is similar to that of the first embodiment shown in FIG. 10. The difference is that in the third embodiment, a clock counter circuit CLK_CNT is used instead of the decision circuit in steps S6_P and S6_A, and the input data string Data[31:0] and the block selection signal BL_SL[7:0] are stored in the look-up table LUT in steps S7_P and S7_A. Also in the third embodiment, the data-in sequencer D_ISQ enables (logical value "1") the data-in enable signal Data-In_EN (FIG. 19) in steps S5_P and S5_A. This causes the data selector D_SEL shown in FIG. 19 to select the input terminal 1X, and the corresponding input data on the input data bus DI_BS[31:0] is stored in the FF circuit FF.

[0214] In the second and third embodiments, the number of memory cells to be rewritten is counted until it reaches a predetermined number, so that it is possible to flexibly select the areas to be written to simultaneously and to optimize the areas to be written to.

[0215] In the third embodiment, the 256 FF circuits FF are divided into a plurality of regions (e.g., regions 0 to 1 in FIGS. 20 and 21) by the block selection signal BL_SL[7:0] output from the lookup table LUT and the input data string Data[31:0]. Each of the divided regions is selected at a different timing (e.g., cycle numbers 1 to 2 in FIG. 21B). Data is written substantially simultaneously in accordance with the data held in the FF circuits FF included in the selected region. In the memory controller MCTR according to the third embodiment, the 256 FF circuits FF (storage circuits) are also divided into a plurality of regions so that the number of FF circuits FF storing inverted data is a predetermined number (32) or less. This makes it possible to limit the number of memory cells to be rewritten substantially simultaneously to a predetermined number or less. This makes it possible to increase the number of memory cells to be written to even in a booster circuit with low current supply capability, thereby reducing the number of write cycles and preventing the write time from becoming longer.

[0216] In the embodiment, an example in which the memory circuits (FF circuits FF) correspond to the data lines has been described, but this is not limiting. That is, the memory circuits only need to correspond to the data to be written. For example, if the number of data to be written simultaneously is smaller than the number of data lines, the number of memory circuits will be smaller than the number of data lines.

[0217] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0218] 1. Semiconductor device B_CAL Bit Calculation Circuit DJ_CKT judgment circuit D_ISQ Data In Sequencer LUT Lookup Table MB0~MB7 memory blocks MARY memory array circuit MCTR Memory Controller PP_CNT Pop counter circuit P / AP_DR P / AP Write Register R_DR Read Data Register W_DR Write Data Register W_SEL Light Selector W_SQR Light Sequencer

Claims

1. a memory array circuit including a plurality of data lines, a plurality of memory cells connected to the plurality of data lines, and an input circuit including a plurality of storage circuits, to which a high voltage is supplied at the time of writing and which writes data into the memory cells in accordance with data held in the storage circuits; a memory controller that supplies a data string having a number of data corresponding to the number of the storage circuits to the input circuit and causes the data string to be stored in the plurality of storage circuits; Equipped with The data string contains a mixture of inverted data that changes the state of the memory cell when written to the memory cell, and non-inverted data that does not change the state of the memory cell; The memory controller a counter circuit for counting the number of inverted data pieces included in the data string; dividing the plurality of memory circuits storing the data string into a plurality of regions based on the count by the counter circuit so that the number of memory circuits storing the inverted data is equal to or less than a predetermined number, selecting the plurality of regions at different timings, and controlling the input circuit to simultaneously write the data held in the memory circuits arranged in the selected regions; Semiconductor device.

2. 2. The semiconductor device according to claim 1, the memory array circuit includes a booster circuit that generates the high voltage during writing; The memory cell is a resistance change memory cell in which a resistance value in the state is determined according to written data. Semiconductor device.

3. 3. The semiconductor device according to claim 2, the memory array circuit comprises a plurality of memory blocks each including n data lines and a plurality of memory cells connected to the n data lines, a plurality of block input circuits corresponding to the plurality of memory blocks, and a plurality of block select lines corresponding to the plurality of memory blocks; the block input circuit comprises n memory circuits and a logic circuit connected to the memory circuits, the block selection lines, and the data lines; The memory controller a determination circuit that determines, based on the count of the counter circuit, a number of regions in which the number of memory circuits storing the inverted data is equal to or less than the predetermined number; a table storing block selection information specifying an area selected from the plurality of areas determined by the determination circuit and order information indicating the order of the block selection information; Equipped with the block selection information is output from the table to the block selection line in the order indicated by the order information stored in the table, and data is written to the memory cell in the memory block designated by the block selection information; Semiconductor device.

4. 4. The semiconductor device according to claim 3, The determination circuit performs a determination during a period in which the boosting operation is performed by the boosting circuit. Semiconductor device.

5. 5. The semiconductor device according to claim 4, the data sequence stored in the plurality of memory circuits is a data sequence obtained by performing an operation between the data sequence read from the memory array circuit and the data sequence to be written; Semiconductor device.

6. 6. The semiconductor device according to claim 5, the counter circuit includes a pop counter circuit to which a plurality of data to be stored in the n memory circuits in the block input circuit are supplied in the data string, and the pop counter circuit counts the number of the inverted data. Semiconductor device.

7. 3. The semiconductor device according to claim 2, the memory array circuit comprises a plurality of memory blocks each including n data lines and a plurality of memory cells connected to the n data lines, and a plurality of block input circuits corresponding to the plurality of memory blocks; the block input circuit comprises n memory circuits and n logic circuits connected to the n data lines and the n memory circuits; The counter circuit a pop counter circuit to which n pieces of data to be stored in the n memory circuits in the block input circuit are supplied and which counts the number of inverted data pieces in the n pieces of data; a clock counter circuit that, when it is determined by the pop counter circuit that the number of inverted data pieces exceeds the predetermined number, counts the number of inverted data pieces in the n pieces of data and determines the point at which the number exceeds the predetermined number; an arithmetic circuit that adds the count value of the pop counter circuit and the count value of the clock counter circuit to calculate separation points that indicate boundaries of the plurality of regions in the plurality of memory circuits that store the data strings; Equipped with the memory controller sequentially outputs separation point information indicating the separation points calculated by the counter circuit; the logic circuit includes a comparator that compares the separation point information with specific information that identifies an area in which the connected memory circuit is located, and when the comparator indicates that an area indicated by the specific information exists in the area identified by the separation point information, the logic circuit supplies data stored in the connected memory circuit to the data line. Semiconductor device.

8. 3. The semiconductor device according to claim 2, the memory controller selects a first region at a first timing, and selects a second region including the first region at a second timing subsequent to the first timing; the memory controller instructs, at the first timing, to write inverted data stored in the plurality of memory circuits included in the first region to a plurality of memory cells, and then instructs, in the first region, to write non-inverted data to the memory circuits storing the inverted data; Semiconductor device.

9. 9. The semiconductor device according to claim 8, the memory array circuit comprises a plurality of memory blocks each including n data lines and a plurality of memory cells connected to the n data lines, and a plurality of block input circuits corresponding to the plurality of memory blocks; the block input circuit comprises n memory circuits corresponding to the n data lines, and n logic circuits connected to the n data lines and the n memory circuits; The counter circuit a first counter circuit that generates a first block selection signal indicating an area where the number of the inverted data is less than the predetermined number at the first timing; a second counter circuit that generates, at the first timing, a first data signal indicating a region from when the region indicated by the first block selection signal is exceeded until the number of the inverted data reaches the predetermined number; Equipped with Semiconductor device.

10. 10. The semiconductor device according to claim 9, the first counter circuit includes a pop counter circuit that is supplied with n pieces of data to be stored in the n memory circuits in the block input circuit and that counts the number of inverted data pieces in the n pieces of data; the second counter circuit includes a clock counter circuit that counts the number of the inverted data in an area exceeding the first area; Semiconductor device.

11. a memory array circuit including a plurality of data lines, a plurality of memory cells connected to the plurality of data lines, and an input circuit including a plurality of storage circuits, to which a high voltage is supplied at the time of writing and which writes data into the memory cells in accordance with data held in the storage circuits; a memory controller that supplies a data string having a number of data corresponding to the number of the storage circuits to the input circuit and causes the data string to be stored in the plurality of storage circuits; Equipped with The data string contains a mixture of inverted data that changes the state of the memory cell when written to the memory cell, and non-inverted data that does not change the state of the memory cell, The memory controller counting the number of inverted data included in the data string during the period in which the high voltage is being generated; dividing the plurality of memory circuits into a plurality of regions so that the number of memory circuits storing the inverted data is equal to or less than a predetermined number based on the counting, selecting the plurality of regions at different timings, and writing the data held in the memory circuits arranged in the selected regions into the memory cells; How to write.

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