Interface circuit using mirrored current feedback to reduce input impedance

Abstract

To provide an interface circuit that uses mirrored current feedback to reduce input impedance.SOLUTION: An interface circuit 111 includes a current mirror and an input circuit path. Shunt feedback via a return circuit path provides a mirrored current to an interface input, thereby reducing an input impedance of the interface circuit 111. By virtue of shunt feedback, the input impedance of the interface circuit 111 is reduced relative to the impedance of the input circuit path. In this manner, the input impedance of the interface circuit 111 may be reduced without changing the impedance of the input circuit path.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 633,320, filed April 12, 2024, which is incorporated by reference in its entirety herein.

[0002] The present invention relates to interface circuits, and more particularly to interface circuits using mirrored current feedback. [Background technology]

[0003]

[0003] Control devices and systems that include switched-mode power supply topologies (e.g., flyback converter topologies) often may include interface circuitry (i.e., circuitry) between different types of circuit blocks, circuits, circuits, and / or circuit components. For example, interface circuitry between a sensor (e.g., a sensor circuit) and a gain stage (e.g., an amplifier or amplifier circuit) may condition the signal from the sensor before it reaches the amplifier input.

[0004]

[0004] Switching power converters are often used to power modern electronic devices from conventional wall sockets because of their high efficiency, small size, and light weight. A controller for a switching power converter can be part of a closed-loop system for regulating output power as a function of one or more system signals (e.g., output voltage).

[0005]

[0005] In operation, the switch is gated according to a switching cycle based on a system or controller configuration (e.g., a flyback configuration). The duty cycle (typically the ratio of the on-time of the switch to the total switching period), switching frequency, or number of pulses per unit time of the switch can be varied to regulate the output (e.g., output power) based on a detected feedback signal. Summary of the Invention

[0006]

[0006] This disclosure presents a circuit approach for improving input impedance in electronic circuits, such as the interface circuits described above. The input impedance may include resistance from the input circuit path. The input circuit path may include components and circuit elements necessary for circuit operation. Unfortunately, the components and circuit elements may present impedance that can limit or degrade circuit performance. For example, resistance may degrade switching performance.

[0007]

[0007] Therefore, a problem occurs when the resistance cannot be reduced to improve circuit performance due to the system specifications. The following disclosure presents a technique to solve this problem by using a feedback approach. A feedback path is introduced at the input to effectively reduce the input impedance without changing the original components of the input circuit path. This technique allows the components to function as originally intended, while the feedback path enhances performance.

[0008]

[0008] Non-limiting and non-exhaustive embodiments of an interface circuit using mirrored current feedback to reduce input impedance are described with reference to the following figures, in which like reference numerals refer to like parts throughout the various drawings unless otherwise specified. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 illustrates a flyback converter in accordance with the teachings herein. [Figure 2A]

[0010] FIG. 2A illustrates an interface circuit in accordance with the teachings herein. [Figure 2B]

[0011] FIG. 2B shows an interface circuit according to the embodiment of FIG. 2A. [Figure 2C]

[0012] FIG. 2C illustrates an interface circuit according to an embodiment. [Figure 3A]

[0013] FIG. 3A illustrates an interface circuit in accordance with the teachings herein. [Figure 3B]

[0014] FIG. 3B shows an interface circuit according to the embodiment of FIG. 3A. [Figure 3C]

[0015] FIG. 3C illustrates an interface circuit according to an embodiment. [Figure 4]

[0016] FIG. 4 shows an interface circuit according to an embodiment. [Figure 5A]

[0017] FIG. 5A shows an interface circuit according to another embodiment. [Figure 5B]

[0018] FIG. 5B shows a thermal shutdown circuit according to the embodiment of FIG. 5A. [Figure 5C]

[0019] FIG. 5C shows a bias circuit according to the embodiment of FIG. 5A. DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0020] Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Those skilled in the art will understand that the elements in the figures are drawn for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to facilitate a better understanding of various embodiments of the teachings herein. Furthermore, common but well-understood elements useful or necessary in commercially suitable embodiments are often not shown in the drawings so as not to obscure the illustrations of these various embodiments of interface circuits using mirrored current feedback to reduce input impedance.

[0011]

[0021] In the following description, numerous specific details are set forth to provide a thorough understanding of an interface circuit using mirrored current feedback to reduce input impedance. However, it will be apparent to those skilled in the art that the specific details may not be used to practice the teachings herein. In other instances, well-known materials or methods have not been described in detail so as not to obscure the present disclosure.

[0012]

[0022] References herein to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of an interface circuit using mirrored current feedback to reduce input impedance. Thus, the use of the phrases "in one embodiment," "in an embodiment," "an example," or "an example" in various places throughout this specification do not necessarily all refer to the same embodiment or example. Furthermore, particular features, structures, or characteristics may be combined in any suitable combination and / or subcombination in one or more embodiments or examples. Particular features, structures, or characteristics may be included in integrated circuits, electronic circuits, logic circuits, or other suitable components that provide the described functionality. Additionally, it is understood that the figures provided herewith are for explanation purposes to persons skilled in the art and that the drawings, including waveforms and graphs, are not necessarily drawn to scale.

[0013]

[0023] In the context of this application, when a transistor is in an "off state" or "off," the transistor blocks current and / or does not substantially conduct current. Conversely, when a transistor is in an "on state" or "on," the transistor can substantially conduct current. By way of example, in one embodiment, the high-voltage transistor comprises an N-channel metal-oxide-semiconductor (NMOS) field-effect transistor (FET) in which a high voltage is supported between a first terminal, the drain, and a second terminal, the source. Furthermore, for purposes of this disclosure, "ground" or "ground potential" refers to a reference voltage or potential relative to which all other voltages or potentials in an electronic circuit or integrated circuit (IC) are defined or measured.

[0014]

[0024] As mentioned above, a flyback converter is a type of switched-mode power supply topology. A flyback converter is an SMPS topology that includes isolation between the primary and secondary windings of an energy transfer element (e.g., a magnetic component or coupled inductor). Components and circuits connected to and referenced to the primary winding are often referred to as primary-side components / circuits. Similarly, components and circuits connected to and referenced to the secondary winding are often referred to as secondary-side components / circuits. With this approach, a flyback converter is configured with a primary side and a secondary side.

[0015]

[0025] Additionally, as discussed above, the switches may be gated or controlled according to a switching cycle based on the system or controller configuration. During operation, switching power supplies often use one or more controllers to regulate and deliver power based on signal information, such as output voltage and / or current.

[0016]

[0026] In a flyback configuration, the controller may include a primary-side controller and / or a secondary-side controller and may need to communicate signal information from the secondary side to the primary side. For example, to regulate the output power on the secondary side, the primary-side controller may need the value of the output voltage on the secondary side.

[0017]

[0027] One way to communicate signal information is through an optocoupler, for example, an optocoupler can generate a current (e.g., a phototransistor current) proportional to the output voltage.

[0018]

[0028] A current (e.g., phototransistor current) may be provided to the primary side controller, and in response, the primary side controller may vary the switching of the primary side switch to regulate / adjust the power (e.g., output power).

[0019]

[0029] The primary-side controller may include an interface circuit or circuitry for receiving the current (e.g., phototransistor current) and converting the current into a usable internal signal. For example, the interface circuit may convert the current (e.g., phototransistor current) into a voltage. Alternatively, or additionally, the interface circuit may amplify, attenuate, or level-shift the current (e.g., phototransistor current).

[0020]

[0030] According to the teachings herein, an SMPS can be treated as a system in which the transient response and switching can be related to the system bandwidth. The system bandwidth can be related to the impedance of the system loop. The system behavior (e.g., switching behavior and bandwidth) of a flyback converter can be determined at least in part by the dominant pole associated with the electrical coupling of the optocoupler and interface circuitry.

[0021]

[0031] For example, the output of an optocoupler may be connected to the input of an interface circuit / circuits, and an extra pole may be generated by the interface. The extra pole may be related at least in part to the capacitance at the output of the optocoupler and the resistance at the input of the interface circuit / circuits.

[0022]

[0032] To meet the basic requirement of improving switching performance, the extra poles can be reduced by reducing capacitance, by reducing resistance, and / or by a combination of both. Unfortunately, reducing the capacitance of an optocoupler may not be an option. Therefore, reducing the resistance at the input of the interface circuit / circuitry may be a preferred approach to improve bandwidth.

[0023]

[0033] One way to reduce the resistance at the input of the interface circuit / circuitry is to reduce the impedance of the input circuit path. For example, non-linear devices (such as field effect transistors) can be made using a larger area to reduce their on-resistance, and any series resistors can be designed to have a lower resistance.

[0024]

[0034] Unfortunately, there may be underlying or conflicting specifications that make it more difficult to reduce the impedance of the input circuit path. For example, when the input circuit path includes an electrostatic discharge (ESD) resistor / resistance, the ESD voltage specification may prevent the resistor / resistance from being further reduced. Furthermore, increasing the area of ​​a nonlinear device (e.g., a field-effect transistor) to reduce its on-resistance may be impractical and costly.

[0025]

[0035] Therefore, there is a need to find alternative approaches to reducing the input impedance of interface circuits and / or interface circuitry.

[0026]

[0036] Disclosed herein is an interface circuit using mirrored current feedback to reduce input impedance. According to the teachings herein, the interface circuit includes a current mirror and an input circuit path. Shunt feedback via a return circuit path provides a mirrored current to the interface input, thereby reducing the input impedance of the interface circuit. Due to the shunt feedback, the input impedance of the interface circuit is reduced compared to the impedance of the input circuit path. This approach can reduce the input impedance of the interface circuit without changing the impedance of the input circuit path.

[0027]

[0037] 1 illustrates a flyback converter 100 according to the teachings herein. The flyback converter 100 includes an energy transfer element 114. As described above, the energy transfer element 114 (e.g., a transformer and / or a coupled inductor / inductance) may provide isolation (i.e., galvanic isolation) between a primary side 115 and a secondary side 117. The primary side 115 is referenced to a primary ground GND, and the secondary side 117 is referenced to a secondary ground RTN.

[0028]

[0038] The flyback converter 100 further includes an optocoupler 102 and a switcher circuit 105. The switcher circuit 105 may be an integrated switcher circuit including a primary switch (not shown). The optocoupler 102 may communicate information related to the output voltage V from the secondary side 117 to the switcher circuit 105 on the primary side 115 by generating a current I (i.e., a phototransistor current I).

[0029]

[0039] The switcher circuit 105 may include an interface circuit 111 for converting a current Ic at an interface input C to an internal usable current I2. In accordance with the teachings herein, the interface circuit 111 has an input impedance Z IN Mirrored current feedback may be used to improve (i.e., reduce) the input impedance Z IN Reducing .times. ...

[0030]

[0040] 2A illustrates an interface circuit 111 according to the teachings herein. The interface circuit 111 includes a current mirror 210, a circuit path 220, and a circuit path 230. The circuit path 220 and the circuit path 230 are electrically coupled (electrically connected) to a node N1. A current Ic is a current at an interface input C and may be referred to as an input current Ic. A voltage Vc is a voltage at the interface input C relative to ground GND, and an input impedance Z of the interface circuit 111 IN may be the impedance at the interface input C.

[0031]

[0041] As shown, circuit path 230 is electrically connected between node N1 and the input IREF of current mirror 210, and circuit path 220 is electrically connected between node N1 and the output IOUT1 of current mirror 210.

[0032]

[0042] The interface input C is electrically connected (coupled) to the node N1. Although not shown, there may be additional components connected between the interface input C and the node N1, and the terms "electrically connected (coupled)" and / or "connected (coupled)" do not limit or exclude the additional components herein. Furthermore, the input IREF and the output IOUT1 may also be referred to as the current mirror input IREF and the current mirror output IOUT1, respectively.

[0033]

[0043] Thus, circuit path 220 is electrically coupled (connected) between interface input C and current mirror output IOUT1, and circuit path 230 is electrically coupled between interface input C and current mirror input IREF.

[0034]

[0044] current I R is the current in the circuit path 230. The current I Ris the current provided to (received by) the current mirror 210 at the current mirror input IREF, and the reference current I R It can be called.

[0035]

[0045] Current I1 is the current in circuit path 220 to current mirror output IOUT1. As described herein, current mirror 210 is configured to provide a current I R , where current I1 may be referred to as an output current I1 and / or a mirrored current I1. For example, current mirror 210 may generate a current I1 proportional to current I R In terms of the ratio K, which is the ratio of the current I1 to the current I R may generate a current I1 related to I1=KI R formula 1

[0036]

[0046] Circuit path 230 may be the input circuit path of interface circuit 111 and may have an impedance Z1. Furthermore, in the absence of circuit path 220, the input impedance Z1 at interface input C IN may be determined by the impedance Z1. As explained herein, the input impedance Z of the interface circuit 111 compared to the impedance Z1 IN There is a need to reduce

[0037]

[0047] According to the teachings herein, the current I R is the current I C and the input impedance Z at the interface input C INCircuit path 220 may be connected to circuit path 230 at node N1 such that impedance Z is reduced compared to impedance Z1. Connecting circuit path 220 to circuit path 230 at node N1 provides shunt feedback, and thus circuit path 220 may also be referred to as return circuit path 220, and current I1 may further be referred to as return current I1. Because current I1 is the mirrored current I1 from current mirror 210, the "shunt" feedback may also be referred to as "mirrored current" feedback.

[0038]

[0048] According to feedback (control) theory, the interface circuit 111 can be treated as a closed-loop system with the interface input C being the system input. Shunt feedback can beneficially reduce the input impedance at the interface input C compared to impedance Z1. For example, if the input impedance Z IN can be determined by the relationship in Equation 2, where the ratio K (current I R The ratio of current I1 to the return voltage is called the return ratio K. Z IN =Z1 / (1+K) Equation 2

[0039]

[0049] The output X of the interface circuit 111 is electrically connected to the output IOUT2 ​​of the current mirror 210 and may be referred to as the current mirror output IOUT2. The current I2 at the current mirror output IOUT2 ​​may also be generated by the current mirror 210 and may be referred to as the output current I2 and / or the mirrored current I2.

[0040]

[0050] 2B illustrates the interface circuit 111 according to the embodiment of FIG. 2A. A current mirror 210 includes a current source 202 and a current source 203. As shown, the current source 202 outputs a current I R According to the teachings herein, as the return ratio K increases, the input impedance Z at the interface input C decreases. INPractical values ​​of the return ratio K may be greater than or equal to 1, with an upper limit based on alternating current (AC) stability considerations.

[0041]

[0051] As further shown, current source 203 generates current I R A current I2 proportional to I2=NI R formula 3

[0042]

[0052] According to feedback and circuit theory, the input current I C is the current I1 and the current I R Therefore, the input current I C is the current I R may be related to. I C =(1+K)I R formula 4

[0043]

[0053] Therefore, the interface circuit 111 receives the input current I as determined by Equation 5. C may provide a usable current I2 in response to I2=NI C / (1+K) Equation 5

[0044]

[0054] 2C illustrates interface circuit 111 according to an embodiment. Circuit path 220 includes component 221 and component 222 electrically connected in series. In some embodiments, there may be more or fewer than two components 221, 222. In accordance with the teachings herein, input impedance Z IN may be independent of the impedance due to the components of the circuit path 220 (eg, components 221, 222).

[0045]

[0055] Circuit path 230 includes component 231 and component 232 electrically connected in series. Thus, impedance Z1 includes the impedance of component 231 and the impedance of component 232. In some embodiments, there may be more or fewer than two components 231, 232.

[0046]

[0056] Current mirror 210 includes N-channel field effect transistors (NFETs) 211, NFET 212, and NFET 213. NFET 211 has a size (e.g., area) scale factor M1. NFET 212 has a size scale factor M2, and NFET 213 has a size scale factor M3. The drain of NFET 211 is electrically coupled to circuit path 230, and therefore the drain of NFET 211 may be the current mirror input IREF. The drain of NFET 212 is electrically coupled to circuit path 220, and therefore the drain of NFET 212 may be the current mirror output IOUT1. The gate of NFET 212 is electrically connected to the gate of NFET 211, and the source of NFET 212 is electrically connected to ground GND. The drain of NFET 213 is electrically coupled to output X, and therefore the drain of NFET 213 may be the current mirror output IOUT2. The gate of NFET 213 is electrically connected to the gate of NFET 211, and the source of NFET 213 is electrically connected to ground GND.

[0047]

[0057] As shown, NFET 211 is diode-connected (i.e., the gate of NFET 211 is electrically connected to the drain of NFET 211). NFET 211 conducts a current I R receives the current I R NFET 211 therefore provides a voltage VGS (i.e., gate-to-source voltage VGS) that varies as the current I R can be converted to a voltage VGS.

[0048]

[0058] NFET 212 receives voltage V from NFET 211 and provides current I as a function of voltage V. Referring to FIG. 2B, NFET 212 may operate as current source 202, and the ratio K may be determined at least in part by the ratio of scale factor M to scale factor M (i.e., Equation 6). K=M2 / M1 Equation 6

[0049]

[0059] Alternatively, and additionally, the ratio K may be determined at least in part by the transconductance gm1 of NFET 211 and the transconductance gm2 of NFET 212 (ie, Equation 7). K=gm2 / gm1 Equation 7

[0050]

[0060] NFET 213 receives voltage V from NFET 211 and provides current I as a function of voltage V. Referring to FIG. 2B, NFET 213 may operate as current source 203, where ratio N may be determined at least in part by the ratio of scale factor M to scale factor M (i.e., Equation 8). N=M3 / M1 Equation 8

[0051]

[0061] Alternatively, and additionally, the ratio N may be determined at least in part by the transconductance gm1 of NFET 211 and the transconductance gm3 of NFET 213 (ie, Equation 9). N=gm3 / gm1 Equation 9

[0052]

[0062] According to the teachings herein, connecting return circuit path 220 to circuit path 230 at node N1 reduces the input impedance Z of interface circuit 111. IN is related to the impedance Z1 of circuit path 230 and by the ratio K (i.e., Equation 2). Thus, if impedance Z1 represents the impedance of interface circuit 111 in the absence of return circuit path 220, the introduction of return circuit path 220 reduces the input impedance ZIN Furthermore, the input impedance Z IN may be (substantially) independent of the impedance in the return circuit path 220.

[0053]

[0063] 3A illustrates an interface circuit 309 according to the teachings herein. The interface circuit 309 includes a current mirror 310, a circuit path 320, and a circuit path 330. The circuit path 320 and the circuit path 330 are electrically coupled to a node N3. The input impedance Z of the interface circuit 309 is IN may be the impedance at the interface input C.

[0054]

[0064] As shown, circuit path 330 is electrically connected between node N3 and the input IREF of current mirror 310, and circuit path 320 is electrically connected between node N3 and the output IOUT1 of current mirror 310.

[0055]

[0065] Interface input C is electrically connected to node N3. Thus, circuit path 320 is electrically coupled between interface input C and current mirror output IOUT1, and circuit path 330 is electrically coupled between interface input C and current mirror input IREF.

[0056]

[0066] current I R is the current in the circuit path 330. The current I R is the current provided by (received from) the current mirror 310 at the current mirror input IREF, and the reference current I R The current I1 is the current in the circuit path 320 from the current mirror output IOUT1 and may also be referred to as the output current I1. The current mirror 310 outputs the current I R(i.e., Equation 1). Therefore, as described above, current I1 may also be referred to as mirrored current I1.

[0057]

[0067] Circuit path 330 may be the input circuit path of interface circuit 309 and may have an impedance Z1. Furthermore, in the absence of circuit path 320, the input impedance Z1 at interface input C IN can be determined by the impedance Z1. The input impedance Z of the interface circuit 309, similar to that of the interface 111, IN can be reduced compared to the impedance Z1.

[0058]

[0068] According to the teachings herein, the current I R is the current I C and the input impedance Z at the interface input C IN Circuit path 320 may be connected to circuit path 330 at node N3 such that the impedance Z is reduced compared to the impedance Z. Connecting circuit path 320 to circuit path 330 at node N3 provides shunt feedback, and thus circuit path 320 may also be referred to as return circuit path 320, and current I may also be referred to as return current I. As discussed above, shunt (mirrored current) feedback reduces the input impedance Z at interface input C according to the relationship in Equation 2. IN can be reduced.

[0059]

[0069] The output X of the interface circuit 309 is electrically connected to the output IOUT2 ​​of the current mirror 310 and may be referred to as the current mirror output IOUT2. The current I2 at the current mirror output IOUT2 ​​may be further generated by the current mirror 310 and may be referred to as the output current I2 and / or the mirrored current I2.

[0060]

[0070] 3B illustrates an interface circuit 309 according to the embodiment of FIG. 3A. A current mirror 310 includes a current source 302 and a current source 303. As shown, the current source 302 outputs a current I R According to the teachings herein, as the return ratio K increases, the input impedance Z at the interface input C decreases. IN A practical value for the return ratio K may be greater than or equal to 1, with an upper limit based on alternating current (AC) stability considerations.

[0061]

[0071] As further shown, current source 303 supplies current I at a ratio N according to the relationship in Equation 3. R A current I2 proportional to

[0062]

[0072] According to feedback and circuit theory, the input current I C is the current I1 and the current I R Therefore, the input current I C is the current I R Therefore, the interface circuit 309 can be related to the input current I as determined by Equation 5. C may provide a usable current I2 in response to

[0063]

[0073] 3C illustrates an interface circuit 309 according to an embodiment. Circuit path 320 includes component 321 and component 322 electrically connected in series. In some embodiments, there may be more or fewer than two components 321, 322. In accordance with the teachings herein, input impedance Z IN may be independent of the impedance due to the components of the circuit path 320 (eg, components 321, 322).

[0064]

[0074] Circuit path 330 includes component 331 and component 332 electrically connected in series. Impedance Z1 therefore includes the impedance of component 331 and the impedance of component 332. In some embodiments, there may be more or fewer than two components 331, 332.

[0065]

[0075] Current mirror 310 includes P-channel field effect transistors (PFETs) 311, 312, and 313. PFET 311 has a size (e.g., area) scale factor M1. PFET 312 has a size scale factor M2, and PFET 313 has a size scale factor M3. The drain of PFET 311 is electrically coupled to circuit path 330, and thus, the drain of PFET 311 may be the current mirror input IREF.

[0066]

[0076] The drain of PFET 312 is electrically coupled to circuit path 320, and therefore may be the current mirror output IOUT1. The gate of PFET 312 is electrically connected to the gate of PFET 311, and the source of PFET 312 is electrically connected to a power supply node NVP. The power supply node NVP receives a power supply voltage VP. The power supply voltage VP may be greater than 0 volts.

[0067]

[0077] The drain of PFET 313 is electrically coupled to output X, and therefore may be the current mirror output IOUT2. The gate of PFET 313 is electrically connected to the gate of PFET 311, and the source of PFET 313 is electrically connected to the power supply node NVP.

[0068]

[0078] As shown, PFET 311 is diode-connected (i.e., the gate of PFET 311 is electrically connected to the drain of PFET 311).R The PFET 311 generates a voltage VGS (i.e., gate-to-source voltage VGS) that changes when V changes. Therefore, the PFET 311 generates a voltage VGS that changes when the current I R can be converted to a voltage VGS.

[0069]

[0079] PFET 312 receives voltage V from PFET 311 and provides current I as a function of voltage V. Referring to Figure 3B, PFET 312 may operate as current source 302, and the ratio K may be determined at least in part by the ratio of scale factor M to scale factor M (i.e., Equation 6).

[0070]

[0080] Alternatively, and additionally, the ratio K may be determined at least in part by the transconductance gm1 of PFET 311 and the transconductance gm2 of PFET 312 (ie, Equation 7).

[0071]

[0081] PFET 313 receives voltage V from PFET 311 and provides current I as a function of voltage V. Referring to Figure 3B, NFET 313 may operate as current source 303, where ratio N may be determined at least in part by the ratio of scale factor M to scale factor M (i.e., Equation 8).

[0072]

[0082] Alternatively, and additionally, the ratio N may be determined at least in part by the transconductance gm1 of PFET 311 and the transconductance gm3 of PFET 313 (ie, Equation 9).

[0073]

[0083] In accordance with the teachings herein, connecting return circuit path 320 to circuit path 330 at node N3 reduces the input impedance Z of interface circuit 309. INis related to the impedance Z1 of circuit path 330 and by the ratio K (i.e., Equation 2). Thus, if impedance Z1 represents the impedance of interface circuit 309 in the absence of return circuit path 320, then the introduction of return circuit path 320 reduces the input impedance Z IN Furthermore, the input impedance Z IN may be (substantially) independent of the impedance in the return circuit path 320.

[0074]

[0084] 4 illustrates interface circuit 111 according to an embodiment. Component 232 may include PFET 432. The gate of PFET 432 receives bias voltage VB (e.g., a voltage between 1 volt and 2 volts). The impedance of component 232 may therefore be determined at least in part by the area, bias voltage, and on-resistivity of PFET 432. The drain of PFET 432 is electrically coupled to the drain of diode-connected NFET 211.

[0075]

[0085] Component 231 may include resistor R2 electrically coupled to the source of PFET 432. Resistor R2 may have a resistance value (e.g., 300 ohms) selected to protect the component (e.g., PFET 432) from electrostatic discharge (ESD). Accordingly, resistor R2 may also be referred to as ESD resistor R2.

[0076]

[0086] As described herein, it may be impractical to reduce the resistance of ESD resistor R2 and the impedance (on-resistance) of PFET 432, and therefore the impedance Z1 of circuit path 230 may be limited to a minimum practical value.

[0077]

[0087] Component 221 may include a resistor R1 connected between node N1 and the drain of NFET 212. Resistor R1 may also be an ESD resistor R1 with a resistance selected to protect the component (e.g., NFET 212) from electrostatic discharge (ESD).

[0078]

[0088] In accordance with the teachings herein, the connection of the return circuit path 220 at node N1 has an input impedance Z compared to impedance Z1. IN For example, if the scale factor M1 is 5 and the scale factor M2 is 45, then the input impedance Z IN can be one tenth of the impedance Z1. Furthermore, as mentioned above, the input impedance Z IN may be independent or substantially independent of the impedance associated with the return path 220 (eg, resistor R1).

[0079]

[0089] 5A shows interface circuit 111 according to another embodiment. Interface circuit 111 of FIG. 5A is similar to that of FIG. 4, except that circuit path 230 includes component 233. Component 233 comprises NFET 533. The drain of PFET 432 is electrically coupled to the drain of NFET 533, and the source of NFET 533 is electrically coupled to the drain of diode-connected NFET 211. NFET 533 flows a current I R The gate of NFET 533 receives a bias voltage VBN so as to limit the excessive input current I at interface node C. C This may beneficially reduce the risk of overcurrent and / or thermal anomalies due to

[0080]

[0090] Furthermore, the gate of PFET 432 receives voltage VBP instead of bias voltage VB. Unlike bias voltage VB, voltage VBP can be varied and / or switched to have more than one value. For example, voltage VBP can be switched between a first value (e.g., 1 volt to 2 volts) and a second value (e.g., power supply voltage VP). When circuit path 230 is in a normal operating state, current I R A first value of voltage VBP may be applied to conduct current I during an abnormal condition (e.g., during an overtemperature condition). R A second value of the voltage VBP may be applied to block the

[0081]

[0091] 5B shows a thermal shutdown circuit 502 according to the embodiment of FIG. 5A. The thermal shutdown circuit 502 may provide a voltage VBP to the gate of PFET 432. As described above, the thermal shutdown circuit 502 may vary and / or switch the value of the voltage VBP. For example, the thermal shutdown circuit may cause the voltage VBP to have a value of 1 to 2 volts during normal operation and a value of the power supply voltage VBP during a fault (overcurrent or thermal overload).

[0082]

[0092] 5C illustrates a bias circuit 503 according to the embodiment of FIG. 5A. The bias circuit 503 controls the current I R The bias voltage VBN may be generated to limit the current I R , which in turn limits the input current I to prevent overcurrent and / or abnormal conditions at the interface input C. C Bias circuit 503 includes NFET 511, NFET 512, and current source 513. As shown, NFET 511 and NFET 512 are diode-connected and connected in series between current source 513 and ground GND. Current source 513 supplies a current I B , which in response generates a bias voltage VBN at the gate / drain node of diode-connected NFET 511.

[0083] summary

[0093] The foregoing description of illustrated examples of the present disclosure, including those described in the Abstract, is not intended to be exhaustive or to be limited to the precise form disclosed. Specific embodiments and examples of interface circuits using mirrored current feedback to reduce input impedance are described herein for illustrative purposes, and various equivalent modifications are possible without departing from the broader spirit and scope of the present disclosure. Indeed, it will be understood that specific and example voltages, currents, frequencies, output range values, times, and the like are presented for purposes of illustration, and that other values ​​may be used in other embodiments and examples in accordance with the teachings herein.

[0084]

[0094] The above description may refer to elements or features being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" or "electrically connected" means that one element / feature is directly or indirectly connected to another element / feature, and does not necessarily mean that they are mechanically connected. Similarly, unless expressly stated otherwise, "coupled" or "electrically coupled" means that one element / feature is directly or indirectly coupled to another element / feature, and does not necessarily mean that they are mechanically connected. Thus, while the various schematic diagrams depicted in the figures show example configurations of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (provided that the functionality of the depicted circuitry is not adversely affected).

[0085]

[0095] Additionally, conditional expressions used herein, such as "may," "could," "may," "may," "for example," "for example," "etc.," among others, are generally intended to convey that certain embodiments include certain features, elements, and / or conditions, while other embodiments do not include certain features, elements, and / or conditions, unless expressly stated otherwise or understood otherwise in the context in which they are used. Thus, such conditional expressions are generally not intended to imply that features, elements, and / or conditions are required in any way by one or more embodiments, or that one or more embodiments necessarily include logic for determining whether or not these features, elements, and / or conditions are included in or implemented in any particular embodiment.

[0086]

[0096] While specific embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the present disclosure. For example, while the disclosed embodiments are shown in a given configuration, alternative embodiments may perform similar functions using different components and / or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and / or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of elements and operations of the various embodiments described above may be combined to provide further embodiments. The scope of the present invention, therefore, is defined solely by reference to the appended claims.

[0087]

[0097] Although the claims presented in this application are in singly dependent form for purposes of filing in the USPTO, it is understood that any claim may depend on any one of the preceding claims of the same type unless it is clearly not technically feasible.

Claims

1. Interface input; a current mirror having a current mirror input and a first current mirror output; an input circuit path electrically coupled between the interface input and the current mirror input; a return circuit path electrically coupled between the interface input and the first current mirror output; An interface circuit comprising:

2. the input circuit path includes an electrostatic discharge (ESD) resistor; 2. The interface circuit of claim 1.

3. the return circuit path comprises an electrostatic discharge (ESD) resistor; 2. The interface circuit of claim 1.

4. the current mirror is configured to receive a reference current at the current mirror input via the input circuit path and to provide a return current from the first current mirror output to the interface input via the return circuit path; 2. The interface circuit of claim 1.

5. an input impedance of the interface input is determined at least in part by the impedance of the input circuit path and by a return ratio of the return current to the reference current; 5. The interface circuit of claim 4.

6. As the return ratio increases, the input impedance decreases.

6. The interface circuit of claim 5.

7. the input circuit path comprising a P-channel field effect transistor (PFET); 5. The interface circuit of claim 4.

8. the PFET configured to receive a fixed reference voltage; 8. The interface circuit of claim 7.

9. the PFET configured to open the input circuit path during a thermal shutdown (TSD) condition; 8. The interface circuit of claim 7.

10. the input circuit path comprising an N-channel field effect transistor (NFET); 5. The interface circuit of claim 4.

11. the NFET configured to receive a bias voltage and to limit the reference current; 11. An interface circuit according to claim 10.

12. an interface output electrically coupled to the second current mirror output and configured to provide an output current proportional to the reference current; 5. The interface circuit of claim 4.

13. The current mirror is a diode-connected N-channel field effect transistor (NFET) configured to receive the reference current and to generate a gate voltage; a first NFET configured to receive the gate voltage and to provide the return current; Further comprising:

13. An interface circuit according to claim 12.

14. 1. A closed loop system, comprising: System input and a current mirror configured to receive a reference current and to provide a return current; an input circuit path electrically coupled to the system input and configured to conduct the reference current; a return circuit path electrically coupled to the system input and configured to conduct the return current such that an impedance of the closed loop system is less than an impedance of the input circuit path and is determined at least in part by a return ratio; A closed loop system comprising:

15. an input current of the closed loop system is determined at least in part by the sum of the return current and the reference current, and the return ratio is determined at least in part by the ratio of the return current to the reference current; 15. The closed loop system of claim 14.

16. The current mirror is a diode-connected transistor configured to receive the reference current and to provide a reference voltage in response thereto; a first transistor configured to receive the reference voltage and to provide the return current; Equipped with 15. The closed loop system of claim 14.

17. the diode-connected transistor is a diode-connected N-channel field effect transistor (NFET); the first transistor is a first NFET; 17. The closed loop system of claim 16.

18. the diode-connected transistor is a diode-connected P-channel field effect transistor (PFET); the first transistor is a first PFET; 17. The closed loop system of claim 16.

19. the reference voltage is determined at least in part by the transconductance of the diode-connected transistor; the return current is at least partially determined by the transconductance of the first transistor; 17. The closed loop system of claim 16.

20. the return ratio is determined at least in part by a ratio of the transconductance of the first transistor to the transconductance of the diode-connected transistor.

20. The closed loop system of claim 19.

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