Fan-out type wafer level packaging unit

Abstract

To provide a fan-out type wafer level packaging unit.SOLUTION: A fan-out type wafer level packaging unit includes a carrier substrate, at least two dies, a first insulating layer, a second insulating layer, a plurality of wires, and a protective layer. The wires are formed of metal paste filled in a plurality of first grooves in the first insulating layer and a plurality of second grooves in the second insulating layer. One ends of the wires are electrically connected through a plurality of pads on the die, and the other ends of the wires are exposed to the outside through solder pads in a plurality of openings in the protective layer. At least one solder pad is arranged around the chip area on the second surface of the die, and the die is electrically connected to the outside through the pads, the wirings, and the solder pads, which can effectively solve the problems of high manufacturing costs and environmental loads that arise when manufacturing wires in the conventional fan-out type packaging technology.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a chip packaging unit, and more particularly to a fan-out type wafer level packaging unit. [Background technology]

[0002] Packaging technology that is thin, lightweight, compact, yet highly efficient and reliable is a trend in the semiconductor industry. Among these, fan-out wafer level packaging (FOWLP) is one of the packaging technologies that has already been put to practical use.

[0003] In the advanced packaging FOWLP technology, the redistribution layer (RDL) is the most important element. This is because the wiring in the RDL electrically extends and interconnects multiple pads on the die in the XY plane, allowing multiple solder pads to be more distributed around the periphery of the die. This makes it possible to improve the degree of freedom and reliability of wiring design. However, the wiring within the RDL must have electrical extension and interconnection functions in the X and Y directions while maintaining or achieving a certain level of thinness, lightness, and miniaturization, and for this purpose, the RDL wiring formation technology is extremely important. However, the RDL forming technology used in the current FOWLP technology employs forming techniques using chemical plating or electrolytic plating, which not only increases material and manufacturing costs, but also makes the manufacturing process less environmentally friendly.

[0004] Furthermore, when realizing a product with higher performance or more functions using FOWLP, it is common to place at least two or more dies within the FOWLP and integrate them via a chip to form a FOWLP unit with a multi-chip structure. In this case, the need for design space in the RDL wiring within the FOWLP unit will become even greater, and the manufacturing technology for the wiring within the RDL will become even more important. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-140972 Summary of the Invention [Problem to be solved by the invention]

[0006] The primary objective of the present invention is to provide a Fan-Out Wafer Level Packaging (FOWLP) unit, the unit comprising: a carrier substrate, a die, a first insulating layer, a second insulating layer, a plurality of conductive traces, and a protective layer, the conductive traces being formed by metal paste filling a plurality of first grooves in the first insulating layer and a plurality of second grooves in the second insulating layer, one end of the conductive traces being electrically connected to a plurality of pads on the die, and the other end being exposed to the outside through a plurality of openings in the protective layer, with solder pads formed in the openings, and at least one solder pad being disposed around a chip area on a second surface of the die to form a FOWLP unit, the die being electrically connected to the outside through the pads, conductive traces, and solder pads, thereby effectively solving the problems of high cost and environmental load that tend to occur when forming conductive traces in conventional fan-out packaging technology. [Means for solving the problem]

[0007] In order to achieve the above object, the present invention provides a fan-out type wafer level packaging unit, the FOWLP unit comprising: a carrier substrate, at least two dies, a first insulating layer, a second insulating layer, a plurality of wirings, and a protective layer; the dies are separated and molded from the same wafer or different wafers, the dies are arranged parallel and spaced apart on a carrier substrate, the dies have a first surface and an opposing second surface, the first surface of the dies is fixed on the carrier substrate, the second surface of the dies has a plurality of pads, and the vertical extent of the second surface is a chip area; the first insulating layer is disposed on the carrier substrate and the second surface of the die, and has a plurality of first grooves extending horizontally, the pads of the die being exposed to the outside through the first grooves; the second insulating layer is disposed on the first insulating layer, and the second insulating layer has a plurality of second grooves extending horizontally, the second grooves communicating with the first grooves; the wiring is formed by a metal paste filled in the first groove and the second groove, and the wiring is electrically connected to the pad of the die; the protective layer is disposed on the second insulating layer, the protective layer has a plurality of openings, at least two of which are formed around a chip area on the second surface of the die, the wiring is exposed to the outside through the openings, and solder pads are formed within the openings; the die is then electrically connected to the outside via the pads, the wiring, and the solder pads arranged around a chip area on the second side of the die, thereby forming a FOWLP unit; A method for manufacturing the FOWLP unit includes the following steps: Step S1: Prepare a carrier substrate; Step S2: Arranging a plurality of dies separated from the same wafer or different wafers parallel and spaced apart on the carrier substrate, each of the dies having a first surface and an opposing second surface, the first surface of the die being disposed on the carrier substrate, the second surface of the die having a plurality of pads, the vertical extent of the second surface being a chip area; Step S3: forming a first insulating layer on the carrier substrate and the second surface of the die; Step S4: forming a plurality of first grooves extending horizontally on the first insulating layer, so that the pads of the die are exposed through the first grooves; Step S5: forming a second insulating layer on the first insulating layer; Step S6: forming a plurality of second grooves in the horizontal direction on the second insulating layer, and connecting the second grooves to the first grooves; Step S7: Filling the first groove and the second groove with a metal paste, and making the thickness of the metal paste higher than the surface of the second insulating layer; Step S8: Polishing the metal paste that is higher than the surface of the second insulating layer to make the surface of the metal paste flat with the surface of the second insulating layer, and forming wiring. Step S9: forming a protective layer on the second insulating layer; Step S10: forming a plurality of openings in the protective layer, and at least one opening is disposed around a chip area on the second surface of the die, so that the wiring is exposed to the outside through the opening and a solder pad is formed within the opening; Step S11: A division operation is performed, and one package is divided into units each having at least two dies to form a plurality of FOWLP units.

[0008] In one embodiment according to the invention, the dies are formed separately from the same wafer.

[0009] In one embodiment according to the invention, the dies are formed separately from different wafers.

[0010] In one embodiment according to the present invention, the horizontal heights of the second faces of the dies on the carrier substrate are the same.

[0011] In one embodiment according to the present invention, the carrier substrate comprises a silicon (Si) carrier substrate, a glass carrier substrate, or a ceramic carrier substrate.

[0012] In one embodiment according to the present invention, the metal paste comprises a silver paste, a nanosilver paste, a copper paste, or a nanocopper paste.

[0013] In one embodiment according to the present invention, the first surface of the die is fixed onto the carrier substrate via a die attach film (DAF).

[0014] In one embodiment according to the present invention, the openings further include solder balls disposed therein, which are electrically connected to the solder pads.

[0015] In one embodiment according to the invention, the FOWLP unit is mounted on a printed circuit board (PCB) in electrical connection via the solder balls. [Effects of the Invention]

[0016] The present invention includes a carrier substrate, a die, a first insulating layer, a second insulating layer, a plurality of conductive traces, and a protective layer, the conductive traces being formed by a metal paste filling a plurality of first grooves in the first insulating layer and a plurality of second grooves in the second insulating layer, one end of the conductive traces being electrically connected to a plurality of pads on the die, and the other end being exposed to the outside through a plurality of openings in the protective layer, with solder pads formed in the openings, and at least one solder pad being disposed around the chip area on the second side of the die to form a FOWLP unit, and the die being electrically connected to the outside through the pads, conductive traces, and solder pads, thereby effectively solving the problems of high cost and environmental load that are often encountered when molding conductive traces in conventional fan-out packaging technology. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 1 is a side cross-sectional view of a FOWLP unit of the present invention installed on a printed circuit board. [Figure 2] FIG. 2 is a cross-sectional side view of a die of the present invention mounted on a carrier substrate. [Figure 3] 1 is a cross-sectional side view of a first insulating layer of the present invention disposed on a carrier substrate and a second surface of a die. [Figure 4] FIG. 2 is a cross-sectional side view of a state in which a second insulating layer of the present invention is placed on a first insulating layer. [Figure 5] FIG. 2 is a side cross-sectional view of the first and second grooves of the present invention in a state where metal paste is filled in the grooves. [Figure 6] FIG. 6 is a side cross-sectional view showing a step of polishing the metal paste that has risen above the surface of the second insulating layer shown in FIG. 5. [Figure 7] FIG. 2 is a cross-sectional side view of the protective layer of the present invention having a plurality of openings formed therein. [Figure 8] FIG. 2 is a schematic side cross-sectional view of the FOWLP unit of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0018] As shown in FIG. 1, in a fan-out wafer level packaging (FOWLP) unit 1 according to the present invention, the FOWLP unit 1 includes a carrier substrate 10, at least two dies 20, a first insulating layer 30, a second insulating layer 40, a plurality of wirings 50, and a protective layer 60.

[0019] The carrier substrate 10 may be, but is not limited to, a silicon (Si) carrier substrate, a glass carrier substrate, or a ceramic carrier substrate, and may be used for various product development applications (see FIG. 2).

[0020] The dies 20 may be cut from the same or different wafers, and the dies 20 are arranged parallel and spaced apart on a carrier substrate 10 . The die 20 has a first surface 21 and an opposing second surface 22, the first surface 21 of the die 20 is fixed on the carrier substrate 10, and the second surface 22 of the die 20 has a plurality of pads 23 on it. Moreover, the range of the second surface 22 in the vertical direction is defined as a chip area 1a (see FIG. 2). In FIG. 2, the die 20 has two pads 23 as an example, but this is not intended to limit the present invention.

[0021] In addition, in the embodiment of the present invention shown in Figures 1 to 8, the die 20 mounted on the carrier substrate 10 further includes a first die 20a and a second die 20b, and two dies are described as an example, but this also does not limit the present invention.

[0022] The first insulating layer 30 is disposed on the second surface 22 of the carrier substrate 10 and the die 20 (20a, 20b), and the first insulating layer 30 has a plurality of first grooves 31 extending horizontally (see FIG. 3). The pads 23 of the die 20 (20a, 20b) are exposed to the outside through the first grooves 31.

[0023] The second insulating layer 40 is disposed on the first insulating layer 30, and the second insulating layer 40 has a plurality of second grooves 41 formed to extend in the horizontal direction. The second groove 41 communicates with the first groove 31 (see FIG. 4).

[0024] The wiring 50 is formed by a metal paste 50a filled in the first groove 31 and the second groove 41, and the wiring 50 is electrically connected to the pads 23 of the die 20 (20a, 20b) (see FIG. 6). The metal paste 50a includes, but is not limited to, silver paste, nano-silver paste, copper paste, or nano-copper paste. The nano silver paste material has properties such as low cost, high conductivity, and low-temperature sintering, but since it is a known material, detailed description will be omitted. The protective layer 60 is disposed on the second insulating layer 40, and the protective layer 60 has a plurality of openings 61, at least two of which are formed around the chip area 1a on the second surface 22 of the die 20 (20a, 20b) (see Figure 7). The wiring 50 is exposed to the outside through the opening 61, and a solder pad 51 is formed inside the opening 61. The protective layer 60 in FIG. 7 has two openings 61 as an example, but this does not limit the present invention. The die 20 (the first die 20a and the second die 20b) are electrically connected to the outside via the pads 23, the wiring 50, and solder pads 51 formed around the chip area 1a located on the second surface 22 of the die 20 (20a, 20b), thereby forming a FOWLP unit 1 (see Figure 7).

[0025] The manufacturing method of the FOWLP unit 1 includes the following steps. Step S1: Prepare a carrier substrate 10 (see FIG. 2). Step S2: A plurality of dies 20 cut from the same or different wafers are arranged parallel and spaced apart on a carrier substrate 10 (see FIG. 2). The die 20 has a first surface 21 and a second surface 22, the first surface 21 being mounted on the carrier substrate 10, the second surface 22 having a plurality of pads 23, and the vertical extent of the second surface 22 being the chip area 1a. Step S3: Form a first insulating layer 30 on the carrier substrate 10 and the second surface 22 of the die 20 (see FIG. 3). Step S4: A plurality of first grooves 31 extending horizontally are formed on the first insulating layer 30 so that the pads 23 of the die 20 are exposed from these first grooves 31 (see FIG. 3). Step S5: The second insulating layer 40 is formed on the first insulating layer 30 (see FIG. 4). Step S6: A plurality of second grooves 41 are formed horizontally on the second insulating layer 40, and the second grooves 41 are connected to the first grooves 31 (see FIG. 4). Step S7: Fill the first groove 31 and the second groove 41 with metal paste 50a, and make the thickness of the metal paste 50a higher than the surface of the second insulating layer 40 (see FIG. 5). Step S8: The metal paste 50a that is higher than the surface of the second insulating layer 40 is polished to make the surface of the metal paste 50a flat with the surface of the second insulating layer 40, and the wiring 50 is formed (see FIG. 6). Step S9: A protective layer 60 is formed on the second insulating layer 40 (see FIG. 7). Step S10: A plurality of openings 61 are formed in the protective layer 60, and at least one opening 61 is placed around the chip area 1a on the second surface 22 of the die 20, so that the wiring 50 is exposed to the outside through the opening 61, and a solder pad 51 is formed within the opening 61 (see Figure 7). Step S11: A dividing step is performed to divide the mold into units each having at least two dies 20 (a first die 20a and a second die 20b) to form a plurality of FOWLP units 1 (see FIG. 7). Although FIG. 7 shows an example of one FOWLP unit 1, it is not intended to limit the present invention.

[0026] The above steps S3 to S8 are important steps in forming the redistribution layer (RDL) in the FOWLP unit 1. Steps S4 to S8 can be performed precisely and easily, which not only simplifies the manufacturing process and enables the wiring 50 to form electrical extensions and interconnections in the XY plane, but also achieves a certain thin and compact design for the completed FOWLP unit 1. Furthermore, even when at least two dies 20 are included, the thin and compact design effect can be maintained.

[0027] As shown in FIG. 2, when the dies 20 are cut from the same wafer, the dies 20 have the same specifications, performance, or functions.

[0028] As shown in Fig. 2, when the die 20 is cut from a different wafer, it can have different specifications, performance, or functions, which can promote product diversification. For example, the first die 20a in Fig. 2 has a smaller specification than the second die 20b.

[0029] As shown in FIG. 2, the second surfaces 22 of the dies 20 arranged on the carrier substrate 10 have the same horizontal height, and the first grooves 31 and second grooves 41 of the redistribution layer formed subsequently are formed flat, which maintains good flatness in the subsequent stacked structure and improves product reliability.

[0030] As shown in FIG. 2, the first surface 21 of the die 20 is fixed onto the carrier substrate 10 via a die attach film (DAF) 70.

[0031] As shown in FIG. 8, a solder ball 80 is further provided in the opening 61 , and is thereby electrically connected to the solder pad 51 .

[0032] As shown in FIG. 1, the FOWLP unit 1 is mounted on a printed circuit board (PCB) 2 in electrical connection via these solder balls 80.

[0033] The FOWLP unit 1 of the present invention has the following advantages over the prior art: (1) The process of steps S3 to S8 of the present invention is simplified, enabling precise manufacturing, which in particular contributes to thinner packages, thereby simplifying the process and reducing costs, while also improving the usage efficiency and reliability of the FOWLP unit 1. (2) In the present invention, the method for forming the wiring 50 disclosed in steps S3 to S8 effectively solves the problems of high manufacturing costs and environmental loads in the conventional FOWLP technology. (3) The present invention can achieve a certain degree of thinness and miniaturization even in FOWLP units with multiple die configurations, making it possible to provide products with the same specifications and performance (when derived from the same wafer) or multi-functional products that combine different specifications and performance (when derived from different wafers), thereby increasing product competitiveness.

[0034] The above description is of the preferred embodiment showing the technical features of the present invention, and those skilled in the art can make changes and modifications without departing from the spirit of the present invention, and these changes and modifications are included in the scope of the claims of the present invention. [Explanation of symbols]

[0035] 1 Fan-out type wafer level package unit 1a Chip area 10 Carrier Board 20 Die 20a First die 20b Second die 21 Page 1 22 Side 2 23 Pad 30 First insulating layer 31 First groove 40 Second insulating layer 41 Second groove 50 Wiring 50a Metal Paste 60 protective layer 61 Aperture 70 Die Attach Film 80 solder balls 2 Printed circuit board

Claims

1. The fan-out wafer level package (FOWLP) unit includes a carrier substrate, at least two dies, a first insulating layer, a second insulating layer, a plurality of wirings, and a protective layer; the at least two dies are separated from the same wafer or different wafers, the dies are arranged parallel and spaced apart on a carrier substrate, the dies have a first surface and an opposing second surface, the first surface of the die is fixed on the carrier substrate, the second surface of the die has a plurality of pads, and the vertical extent of the second surface is a chip area; the first insulating layer is disposed on the carrier substrate and the second surface of the die, the first insulating layer is provided with a plurality of first grooves extending horizontally, and the pads of the die are exposed to the outside through the first grooves; the second insulating layer is disposed on the first insulating layer, and a plurality of second grooves are formed in the second insulating layer and extend in a horizontal direction, and each of the second grooves is connected to one of the first grooves; the wiring is formed by a metal paste filled in the first groove and the second groove, and the wiring is electrically connected to the pad of the die; the protective layer is disposed on the second insulating layer, the protective layer has a plurality of openings, at least two of which are formed around a chip region on the second surface of the die, the wiring is exposed to the outside through the openings, and solder pads are formed within the openings; the die is electrically connected to the outside via the pads, the wiring, and solder pads disposed around the chip area on the second surface of the die, thereby forming a fan-out type wafer level package unit; The manufacturing method of the fan-out type wafer level packaging unit includes the following steps: Step S1: Prepare a carrier substrate; Step S2: Arranging a plurality of dies cut from the same or different wafers on a carrier substrate in parallel and spaced relation, each die having a first surface and an opposing second surface, the first surface of each die being disposed on the carrier substrate, the second surface of each die having a plurality of pads, the vertical extent of the second surface being a chip area; Step S3: forming a first insulating layer on the carrier substrate and the second surface of the die; Step S4: forming a plurality of first grooves extending horizontally on the first insulating layer, so that the pads of the die are exposed through the first grooves; Step S5: forming a second insulating layer on the first insulating layer; Step S6: forming a plurality of second grooves in the horizontal direction on the second insulating layer, and connecting the second grooves to the first grooves; Step S7: Filling the first groove and the second groove with a metal paste, and making the thickness of the metal paste higher than the surface of the second insulating layer; Step S8: Polishing the metal paste that is higher than the surface of the second insulating layer to make the surface of the metal paste flat with the surface of the second insulating layer, and forming wiring. Step S9: forming a protective layer on the second insulating layer; Step S10: forming a plurality of openings in the protective layer, and at least one opening is disposed around a chip area on the second surface of the die, so that the wiring is exposed to the outside through the opening and a solder pad is formed within the opening; Step S11: A division operation is performed, and one package is divided into a unit having at least two dies to form a plurality of FOWLP units.

2. The FOWLP unit of claim 1 , wherein the dies are formed separately from the same wafer.

3. The FOWLP unit of claim 1 , wherein the dies are formed separately from different wafers.

4. The FOWLP unit of claim 1 , wherein the second surfaces of the dies on the carrier substrate are at the same horizontal height.

5. The FOWLP unit of claim 1 , wherein the carrier substrate comprises a silicon (Si) carrier substrate, a glass carrier substrate, or a ceramic carrier substrate.

6. The FOWLP unit of claim 1 , wherein the metal paste comprises silver paste, nano-silver paste, copper paste, or nano-copper paste.

7. The FOWLP unit of claim 1 , wherein the first surface of the die is further attached to the carrier substrate using a die attach film.

8. The FOWLP unit of claim 1 , further comprising a solder ball disposed in the opening, which is electrically connected to the solder pad.

9. The FOWLP unit according to claim 8 , wherein the fan-out type wafer level package unit is electrically connected via the solder balls and is mounted on a printed circuit board.

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