Display panel and manufacturing method for display panel

Abstract

To improve the process performance of an OLED display product.SOLUTION: A display panel includes an array substrate 110, a first electrode 120 existing on one side of the array substrate, and an insulating layer 130 existing on a side of the first electrode 120 that is farther from the array substrate 110. The insulating layer 130 includes a first opening 810. The first opening 810 exposes a central region of the first electrode 120. An edge region of the first electrode 120 is covered with the insulating layer 130. The thickness of the insulating layer 130 is larger than or equal to the thickness of the first electrode 120. By increasing the thickness of the insulating layer 130 to be larger than that of the first electrode 120, the risk that a breaking port exists in the insulating layer 130 is reduced, the damage of the first electrode 120 due to an etchant in a subsequent process of pattern-etching of the other film layers is avoided, and the yield of the display panel can be secured.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This application claims priority to a Chinese patent application bearing application number 202410477141.6 and entitled "Display panel, display panel manufacturing method and electronic device," filed with the China Patent Office on April 19, 2024, the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the technical field of displays, and in particular to display panels and methods for manufacturing display panels. [Background technology]

[0003] Flat panel displays based on technologies such as organic light emitting diodes (OLEDs) and light emitting diodes (LEDs) have advantages such as high image quality, low power consumption, a thin body, and a wide range of applications. As a result, they are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers, and have become the mainstream display device. Summary of the Invention [Problem to be solved by the invention]

[0004] However, the process performance of current OLED display products needs to be improved. [Means for solving the problem]

[0005] In order to overcome the above deficiencies in the prior art, the present application provides: an array substrate; an insulating layer positioned on one side of the array substrate and having a plurality of first openings; a plurality of first electrodes located on one side of the array substrate and spaced apart from one another, the first electrodes having portions exposed through the first openings and having side surfaces covered with the insulating layer; a light-emitting unit located on a side of the first electrode farther from the array substrate, the thickness of the insulating layer is greater than or equal to the thickness of the first electrode; The object is to provide a display panel.

[0006] In some possible implementations, the insulating layer comprises a first insulating portion covering the first electrode and a second insulating portion not covering the first electrode, and the ratio of the thickness of the first insulating portion to the thickness of the first electrode is greater than or equal to 1.

[0007] The display panel of some embodiments of the present application comprises: an array substrate; an insulating layer positioned on one side of the array substrate and having a first opening; a plurality of first electrodes located on one side of the array substrate and spaced apart from one another, the first electrodes having portions exposed through the first openings; a light-emitting unit located on a side of the first electrode farther from the array substrate; and a second electrode located on the side of the light-emitting unit farther from the array substrate, and the insulating layer has a first insulating portion covering the first electrode and a second insulating portion offset from the first electrode, and the thickness at the boundary between the first insulating portion and the second insulating portion is greater than the thickness of the first insulating portion corresponding to the first electrode.

[0008] The method for manufacturing a display panel of the present application includes: providing an array substrate; providing a first electrode on one side of the array substrate; an insulating layer having a first opening is provided on a side of the first electrode farther from the array substrate, the first electrode has a portion exposed from the first opening, and a side surface is covered with the insulating layer, and the thickness of the insulating layer is greater than or equal to the thickness of the first electrode; forming a light-emitting unit located on a side of the first electrode farther from the array substrate.

[0009] In some possible implementations, the step of providing an insulating layer on the side of the first electrode farther from the array substrate comprises: providing an insulating layer on the side of the first electrode remote from the array substrate, the insulating layer having a thickness greater than or equal to 1000 Angstroms; [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a structural schematic diagram of a display panel according to the present embodiment. [Figure 2] 2 is a structural schematic diagram 2 of the display panel according to the present embodiment. [Figure 3] 3 is a structural schematic diagram of the display panel according to the present embodiment. [Figure 4] 4 is a structural schematic diagram of the display panel according to the present embodiment. [Figure 5] 5 is a structural schematic diagram of the display panel according to the present embodiment. [Figure 6] 6 is a structural schematic diagram of the display panel according to the present embodiment. [Figure 7] 7 is a structural schematic diagram of the display panel according to the present embodiment. [Figure 8] FIG. 2 is a schematic diagram of an isolation structure according to the present embodiment. [Figure 9] 8 is a structural schematic diagram of the display panel according to this embodiment. [Figure 10] 9 is a structural schematic diagram of the display panel according to this embodiment. [Figure 11] 5A to 5C are schematic diagrams illustrating a method for manufacturing a display panel according to the present embodiment. [Figure 12] 1 is a schematic diagram illustrating a manufacturing process of a display panel according to the present embodiment. [Figure 13] 2 is a schematic diagram 2 of the manufacturing process of the display panel according to the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] The following detailed description of the embodiments of the present application, taken in conjunction with the drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the present application.

[0012] According to the inventor's research, it has been found that a conventional OLED display panel typically includes an array substrate, a first electrode (e.g., an anode) located on one side of the array substrate, and an insulating layer (e.g., a pixel definition layer) located on the side of the first electrode farther from the array substrate, where the insulating layer typically needs to cover at least a portion of the first electrode (e.g., an edge of the first electrode). In this case, if the thicknesses of the first electrode and the insulating layer are inappropriately set, the first electrode may be damaged during subsequent etching of other film layers, which may affect the yield of the display panel.

[0013] In view of this, the present embodiment provides an aspect that can reduce the risk of damaging the first electrode, and the aspect according to this embodiment will be described in detail below.

[0014] 1 and 2, which show a display panel according to this embodiment, which may include an array substrate 110, a first electrode 120, an insulating layer 130 and a light emitting unit 150. As shown in FIG.

[0015] In this embodiment, the array substrate 110 may have a multi-layer structure, such as a substrate, a buffer layer, an active layer, a multi-metal layer, a multi-insulating layer, a planarization layer, etc. The multi-layer structure of the array substrate 110 can form a multi-thin film transistor (TFT) at different positions on the array substrate 110, and the TFTs can cooperate with each other to form a multi-pixel driving unit or driving circuit.

[0016] The insulating layer 130 is located on the side of the first electrode 120 that is farther from the array substrate 110 and has a first opening 810 .

[0017] A plurality of first electrodes 120 are located on one side of the array substrate 110 and are spaced apart from one another. Each first electrode 120 has a portion exposed through the first opening 810, and its side surface is covered with the insulating layer 130. For example, the first opening 810 exposes the central region of each first electrode 120, and the edge region of each first electrode 120 is covered with the insulating layer 130. That is, the insulating layer 130 extends along the side surface of each first electrode 120 toward the side of the first electrode 120 that is far from the array substrate 110, and covers at least a portion of the surface of each first electrode 120 that is far from the array substrate 110.

[0018] In this embodiment, the thickness H1 of the insulating layer 130 is greater than or equal to the thickness H2 of the first electrode 120. The thickness of the insulating layer 130 is the minimum distance from the side of the insulating layer 130 farther from the array substrate 110 to the side of the insulating layer 130 closer to the array substrate 110 in the direction perpendicular to the array substrate 110. Due to errors in the manufacturing process, process design, the effects of subsequent processes, etc., the thickness of the insulating layer at its edge may be thinner or non-uniform. Therefore, in this application, the thickness of the insulating layer refers to the thickness of the uniform portion of the insulating layer.

[0019] The light-emitting unit 150 is at least partially located within the first opening 810 and is located on the side of the first electrode 120 farther from the array substrate 110. The light-emitting unit 150 may include a hole injection layer, a hole transport layer, an electron blocking layer, and the like.

[0020] Preferably, the display panel according to this embodiment may further include a second electrode 160 located on the side of the light emitting unit 150 farther from the array substrate 110 .

[0021] Based on the above design, in this embodiment, the thickness of the insulating layer 130 is made greater than the thickness of the first electrode 120, thereby reducing the risk of breakages in the insulating layer 130 covering the edge of the first electrode 120, and preventing the etching solution from penetrating into the first electrode 120 through the breakages in the insulating layer 130 during the subsequent patterned etching of other film layers, thereby protecting the first electrode 120 and ensuring the yield of the display panel.

[0022] 3 , in some possible implementations, the insulating layer 130 includes a first insulating portion 1301 that covers the first electrode 120 and a second insulating portion 1302 that does not cover the first electrode 120. That is, the orthogonal projection of the first insulating portion 1301 on the array substrate 110 overlaps with the orthogonal projection of the first electrode 120 on the array substrate, and the orthogonal projection of the second insulating portion 1302 on the array substrate does not overlap with the orthogonal projection of the first electrode 120 on the array substrate 110. The ratio of the thickness of the first insulating portion 1301 to the thickness of the first electrode 120 is greater than or equal to 1.

[0023] In some possible implementations, the thickness of the first electrode 120 is about 1000 angstroms, so that the thickness of the insulating layer 130 is greater than or equal to 1000 angstroms.

[0024] Preferably, the thickness range of the insulating layer 130 is 2000 to 4000 angstroms, which can ensure that the insulating layer 130 can cover the edge of the first electrode 120 well and reduce the risk of breakage in the insulating layer 130.

[0025] In some possible implementations, referring to FIG. 4, the first electrode 120 has a first surface 1201 that is farther from the array substrate 110 and a second surface 1202 that is closer to the array substrate 110 .

[0026] Preferably, the orthogonal projection of the first surface 1201 on the array substrate 110 is located within the orthogonal projection of the second surface 1202 on the array substrate 110 .

[0027] For example, in this embodiment, the cross-sectional shape of the first electrode 120 may be rectangular in a cross section perpendicular to the array substrate 110. In this case, the first insulating portion 1301 is a portion of the insulating layer 130 that covers the surface of the first electrode 120 farther from the array substrate 110.

[0028] Also, for example, in this embodiment, the cross-sectional shape of the first electrode 120 may be trapezoidal in a cross section perpendicular to the array substrate 110, and the relatively long base of the trapezoid is located on the side closer to the array substrate 110. In this case, the first insulating portion 1301 is a portion of the insulating layer 130 that covers the surface of the first electrode 120 farther from the array substrate 110 and the side surface of the first electrode 120.

[0029] Alternatively, referring to FIG. 5, preferably, the orthogonal projection of the second surface 1202 on the array substrate 110 is located within the orthogonal projection of the first surface 1201 on the array substrate 110 .

[0030] For example, in this embodiment, the cross-sectional shape of the first electrode 120 may be trapezoidal in a cross section perpendicular to the array substrate 110, with a relatively long base of the trapezoid located on the side farther from the array substrate 110. In this case, the first insulating portion 1301 is a portion of the insulating layer 130 that covers the surface of the first electrode 120 farther from the array substrate 110.

[0031] In addition, when the first electrode 120 has multiple film layers, the cross-sectional shape may be trapezoidal as a whole, but the side may form a stepped or sawtooth structure due to the etching process or differences in the etching resistance of different film layers. Due to errors in the manufacturing process, process design, the effects of subsequent processes, etc., the thickness of the first electrode 120 at the edge position may be thin or uneven. Therefore, in this application, the thickness of the first electrode 120 refers to the thickness of the uniform part of the electrode layer.

[0032] In some possible implementations, the insulating layer 130 may be a pixel definition layer, the first opening 810 may be a pixel opening, and the material of the insulating layer 130 is an inorganic material.

[0033] In some possible implementations, referring to FIG. 6, the insulating layer 130 comprises a first sublayer 131 and a second sublayer 132 stacked in a direction away from the array substrate 110, and the silicon content in the first sublayer 131 and the second sublayer 132 is different.

[0034] Preferably, the content ratio of nitrogen to silicon in the first sub-layer 131 is a first ratio value, the content ratio of nitrogen to silicon in the second sub-layer 132 is a second ratio value, and the first ratio value is different from the second ratio value.

[0035] In some possible implementation manners, the materials of the first sub-layer 131 and the second sub-layer 132 may both be silicon nitride, but the first ratio value is different from the second ratio value.

[0036] For example, in the formation process of the first sub-layer 131 and the second sub-layer 132, the silicon target material can be impacted by adopting different powers in an environment containing nitrogen gas to form.

[0037] In some other possible implementation manners, the material of the first sub-layer 131 may be silicon nitride, and the material of the second sub-layer 132 may be silicon oxide.

[0038] In some possible implementation manners, the first ratio value is X, the second ratio value is Y, where 0 < X < 3 / 4, 0 ≤ Y < 3 / 4, and X > Y.

[0039] Based on this, preferably, when Y = 0, the thickness H2 of the second sub-layer 132 is smaller than the thickness H3 of the first sub-layer 131, and when Y ≠ 0, the thickness H2 of the second sub-layer 132 is larger than the thickness H3 of the first sub-layer 131.

[0040] Preferably, the range of the thickness H3 of the first sub-layer 131 is from 0 to 3000 angstroms, and the range of the thickness H2 of the second sub-layer 132 is from 0 to 4000 Å.

[0041] In some possible implementation manners, referring to FIGS. 1 and 2, the first electrode 120 includes a first conductive layer 121, a second conductive layer 122, and a third conductive layer 123 that are stacked in a direction away from the array substrate 110, and the etching rate of the second conductive layer 122 is different from the etching rates of the first conductive layer 121 and the third conductive layer 123.

[0042] 7, preferably, the orthogonal projection of the second conductive layer 122 on the array substrate 110 is located within the orthogonal projection of the first conductive layer 121 and the third conductive layer 123 on the array substrate 110. That is, on the side of the first electrode 120, the second conductive layer 122 is shorter than the first conductive layer 121 and the third conductive layer 123, so that the cross-sectional shape of the first electrode 120 as a whole exhibits a U-shape. In this case, the first insulating portion 1301 is a portion of the insulating layer 130 covering the surface of the first electrode 120 farther from the array substrate 110.

[0043] For example, the first conductive layer 121 and the third conductive layer 123 may be made of at least one of indium tin oxide, indium zinc oxide, and indium gallium oxide, and the second conductive layer 122 may be made of silver, which can ensure that the first electrode 120 has low resistance and good conductivity, and the first conductive layer 121 and the third conductive layer 123 may be made of at least one of indium tin oxide, indium zinc oxide, and indium gallium oxide, which can protect the second conductive layer 122 located between the first conductive layer 121 and the third conductive layer 123 and reduce the risk of oxidation of the second conductive layer 122.

[0044] In some possible implementations, referring again to FIGS. 1 and 2, the display panel according to this embodiment may further include an isolation structure 140.

[0045] The isolation structure 140 is located on the side of the insulating layer 130 away from the array substrate 110 and includes an isolation opening, and the orthogonal projection of the first opening 810 on the array substrate 110 is located within the orthogonal projection of the isolation opening on the array substrate 110. The isolation opening communicates with the first opening 810, and together they expose at least a portion of the first electrode 120.

[0046] The isolation structure 140 can be used to separate the light emitting units 150 and second electrodes 160 between adjacent pixels when the light emitting units 150 and second electrodes 160 are subsequently formed by deposition, thereby allowing light emitting units 150 of different colors to be provided in different first openings 810 by full layer deposition and etching.

[0047] Among them, patent applications PCT / CN2023 / 134518, 202310759370.2, 202310740412.8, 202310707209.0, and 202311346196.5 describe relevant technical aspects of the isolation structure 140, the contents of which are incorporated herein by reference.

[0048] Furthermore, in some possible implementations, the material of the insulating layer 130 is an inorganic material, which can ensure the stability of the insulating layer 130 during the subsequent wet manufacturing process of the light emitting unit 150 and the second electrode 160.

[0049] 8, in some possible implementations, the isolation structure 140 includes a supporting portion 141 and a blocking portion 142 stacked toward the side away from the array substrate 110, and the orthogonal projection of the supporting portion 141 on the array substrate 110 is located within the orthogonal projection of the blocking portion 142 on the array substrate 110. That is, the side of the isolation structure 140 forms an undercut structure. In this way, when other organic material layers are subsequently deposited and formed, these organic material layers can be separated.

[0050] In some possible implementations, the support portion 141 may include a first metal layer 1411 and a second metal layer 1412 stacked toward the side away from the array substrate 110, and the blocking portion 142 includes a third metal layer 1421.

[0051] Preferably, the material of the first metal layer 1411 includes molybdenum, the material of the second metal layer 1412 includes aluminum, and the material of the third metal layer 1421 includes titanium.

[0052] In some possible implementations, at least a portion of the isolation structure 140 is conductive. Referring to FIG. 2, at least a portion of the second electrode 160 is located on the side of the light-emitting unit 150 far from the array substrate 110 and is in electrical contact with the light-emitting unit 150, and at least a portion of the second electrode 160 is located on the side of the insulating layer 130 far from the array substrate 110 and is in electrical contact with the isolation structure 140. For example, the second electrode 160 extends from within the first opening 810 to the side of the insulating layer 130 far from the array substrate 110 and is in electrical contact with the isolation structure 140.

[0053] The first electrode 120 can be connected to a pixel driving circuit in the array substrate 110, and the second electrode 160 can be connected to a common voltage providing circuit through the isolation structure 140. When there is a potential difference between the first electrode 120 and the second electrode 160, the light-emitting unit 150 located between the first electrode 120 and the second electrode 160 is driven to emit light.

[0054] In some possible implementations, referring again to FIG. 1, the orthogonal projection of the first electrode 120 on the array substrate 110 at least partially overlaps with the orthogonal projection of the isolation structure 140 on the array substrate 110, for example, the orthogonal projection of the side of the first electrode 120 on the array substrate 110 is located within the orthogonal projection of the isolation structure 140 on the array substrate 110.

[0055] That is, at least a portion of the first electrode 120 extends below the isolation structure 140. Because parasitic capacitance may be formed between the conductive first electrode 120 and the conductive isolation structure 140, parasitic capacitance exists between the first electrode 120 and the second electrode 160 electrically connected to the isolation structure 140, which affects the reset effectiveness of the light-emitting device.

[0056] In this case, in the display panel of this embodiment, by increasing the thickness of the insulating layer 130, the distance H0 between the isolation structure 140 and the first electrode 120 can be increased, the parasitic capacitance between the first electrode 120 and the second electrode 160 can be reduced, and the reset effectiveness when resetting the light-emitting element can be ensured.

[0057] In some possible implementations, referring to FIG. 9, the display panel according to this embodiment may further include a first sealing layer 170.

[0058] Preferably, the first encapsulating layer 170 may extend from within the first opening 810 to the side of the isolation structure 140 that is farther from the array substrate 110. The first encapsulating layers 170 corresponding to adjacent first openings 810 may be separated on the side of the isolation structure 140 that is farther from the array substrate 110.

[0059] Furthermore, in some possible implementations, the display panel of this embodiment further includes a second sealing layer 180 and a third sealing layer 190 stacked on the side of the first sealing layer 170 that is farther from the array substrate 110.

[0060] Preferably, the material of the first sealing layer 170 and the third sealing layer 190 includes an inorganic material, and the material of the second sealing layer 180 includes an organic material. For example, the first sealing layer 170 and the third sealing layer 190 can be formed by chemical vapor deposition (CVD), and the second sealing layer 180 can be formed by ink-jet printing (IJP).

[0061] Preferably, there may be a gap between the isolation structure 140 and the portion of the first encapsulating layer 170 located farther from the array substrate 110 than the isolation structure 140. The second encapsulating layer 180 can fill the gap.

[0062] In some possible implementations, referring to FIG. 10 , the isolated opening comprises a first isolated opening 161 and a second isolated opening 162, the light-emitting unit 150 comprises a first light-emitting unit 151 and a second light-emitting unit 152 having different light-emitting colors, and the first light-emitting unit 151 is at least partially located within the first isolated opening 161, and the second light-emitting unit 152 is at least partially located within the second isolated opening 162.

[0063] The insulating layer 130 has a first limiting portion 1305 that protrudes from the isolation structure 140 corresponding to the first isolation opening 161 and a second limiting portion 1306 that protrudes from the isolation structure 140 corresponding to the second isolation opening 162, and the orthogonal projection of the first limiting portion 1305 on the array substrate 110 is located within the orthogonal projection of the first isolation opening 161 on the array substrate 110, i.e., the first isolation opening 161 exposes the first limiting portion 1305 of the insulating layer 130. The orthogonal projection of the second limiting portion 1306 on the array substrate 110 is located within the orthogonal projection of the second isolation opening 162 on the array substrate 110, i.e., the second isolation opening 162 exposes the second limiting portion 1306 of the insulating layer 130.

[0064] For example, in the vicinity of the first isolation opening 161, the portion of the insulating layer 130 that protrudes from the isolation structure 140 more than the side of the isolation structure 140 closer to the array substrate 110 (i.e., not covered by the isolation structure 140) is the first limiting portion 1305, and the first limiting portion 1305 is exposed from at least a portion of the first isolation opening 161.

[0065] In the vicinity of the second isolation opening 162, the portion of the insulating layer 130 that protrudes from the isolation structure 140 more than the side of the isolation structure 140 closer to the array substrate 110 (i.e., not covered by the isolation structure 140) is the second limiting portion 1306, and the second limiting portion 1306 is exposed from at least a portion of the second isolation opening 162.

[0066] The thickness D21 of the first limiting portion 1305 and the thickness D22 of the second limiting portion 1306 are both greater than the thickness of the first electrode 120.

[0067] Preferably, in some possible implementations, the thickness D21 of the first limiting portion 1305 and the thickness D22 of the second limiting portion 1306 are approximately equal.

[0068] Preferably, in some other possible implementations, the thickness D21 of the first limiting portion 1305 is greater than the thickness D22 of the second limiting portion 1306.

[0069] For example, the first light-emitting unit 151 may be manufactured before the second light-emitting unit 152, and during the patterning etching process of the first light-emitting unit 151, the second limiting portion 1306 of the insulating layer 130 located in the second isolation opening 162 and not covered by the isolation structure 140 may be etched and thinned accordingly, so that the thickness D21 of the first limiting portion 1305 located in the first isolation opening 161 of the insulating layer 130 is greater than the thickness D22 of the second limiting portion 1306 located in the second isolation opening 162.

[0070] Preferably, the isolation openings further include a third isolation opening 163, and the light-emitting unit 150 further includes a third light-emitting unit 153 having an emission color different from that of the first light-emitting unit 151 and the second light-emitting unit 152, with the third light-emitting unit 153 at least partially located within the third isolation opening 163. For example, the emission colors of the first light-emitting unit 151, the second light-emitting unit 152, and the third light-emitting unit 153 may be one of red, green, and blue, respectively.

[0071] The insulating layer 130 further includes a third limiting portion 1307 extending from the isolation structure 140 corresponding to the third isolation opening 163, and the orthogonal projection of the third limiting portion 1307 on the array substrate 110 is located within the orthogonal projection of the third isolation opening 163 on the array substrate 110, i.e., the third isolation opening 163 exposes the third limiting portion 1307 of the insulating layer 130.

[0072] For example, in the vicinity of the third isolation opening 163, the portion of the insulating layer 130 that protrudes from the isolation structure 140 more than the side of the isolation structure 140 closer to the array substrate 110 (i.e., not covered by the isolation structure 140) is the third limiting portion 1307, and the third limiting portion 1307 is exposed from at least a portion of the third isolation opening 163.

[0073] Among them, the thickness D21 of the first limiting portion 1305, the thickness D22 of the second limiting portion 1306, and the thickness D23 of the third limiting portion 1307 are all greater than the thickness of the first electrode 120.

[0074] Preferably, in some possible implementations, the thickness D22 of the second limiting portion 1306 and the thickness D23 of the third limiting portion 1307 are approximately equal, i.e., the thickness D21 of the first limiting portion 1305, the thickness D22 of the second limiting portion 1306, and the thickness D23 of the third limiting portion 1307 are approximately equal.

[0075] Preferably, in some other possible implementations, the thickness D22 of the second limiting portion 1306 is greater than the thickness D23 of the third limiting portion 1307. That is, the thickness D21 of the first limiting portion 1305, the thickness D22 of the second limiting portion 1306, and the thickness D23 of the third limiting portion 1307 decrease in this order.

[0076] For example, the first light-emitting unit 151 may be fabricated before the second light-emitting unit 152, and the second light-emitting unit 152 may be fabricated before the third light-emitting unit 153. During the patterning etching process of the first light-emitting unit 151, the third limiting portion 1307 of the insulating layer 130 located in the third isolation opening 163 and not covered by the isolation structure 140 may be etched accordingly and thinned, so that the thickness D21 of the first limiting portion 1305 located in the first isolation opening 161 of the insulating layer 130 is greater than the thickness D23 of the third limiting portion 1307 located in the third isolation opening 163. Then, during the patterned etching process of the second light-emitting unit 152, the third limiting portion 1307 of the insulating layer 130 located in the third isolation opening 163 and not covered by the isolation structure 140 is again etched and thinned accordingly, so that the thickness D22 of the second limiting portion 1306 located in the second isolation opening 162 of the insulating layer 130 is greater than the thickness D23 of the third limiting portion 1307 located in the third isolation opening 163.

[0077] In some possible implementations, in the region where the insulating layer 130 covers the first electrode 120, the ratio of the thickness of the insulating layer 130 to the thickness of the first electrode 120 is greater than or equal to 1. For example, referring to FIG. 2 , the insulating layer 130 includes a first insulating portion 1301 and a second insulating portion 1302, and the orthogonal projection of the first insulating portion 1301 on the array substrate 110 overlaps with the orthogonal projection of the first electrode 120 on the array substrate 110, and the orthogonal projection of the second insulating portion 1302 on the array substrate 110 is offset from the orthogonal projection of the first electrode 120 on the array substrate 110. That is, the portion of the insulating layer 130 that covers the first electrode 120 is the first insulating portion 1301, and the portion that does not cover the first electrode 120 is the second insulating portion 1302.

[0078] A distance H5 from the side of the first insulating portion 1301 farther from the array substrate 110 to the array substrate 110 is greater than a distance H6 from the side of the first electrode 120 farther from the array substrate 110 to the array substrate 110. In other words, the insulating layer 130 at least partially covers the side of the first electrode 120 farther from the array substrate 110.

[0079] In some possible implementations, the display panel according to this embodiment may further include a touch function layer, which may be located on the side of the third encapsulation layer 190 farther from the array substrate 110. The touch function layer may include a touch electrode for performing touch detection. Preferably, the touch electrode may be arranged in a self-capacitance detection manner and / or a mutual capacitance detection manner, which is not specifically limited in this embodiment.

[0080] In some possible implementations, the display panel according to this embodiment may further include a polarizing layer, which may be located on the side of the third sealing layer 190 that is farther from the array substrate 110. The polarizer can reduce the reflection of external light on the display panel and ensure the display effect of the display panel.

[0081] In some possible implementations, the display panel of this embodiment may further include a cover plate for protecting the display panel, and the cover plate may be located on the side of the film layer farthest from the array substrate 110 away from the array substrate 110.

[0082] 2 , the insulating layer 130 is located on the side of the first electrode 120 that is farther from the array substrate 110, and has a first opening 810. The first electrode 120 has a portion that is exposed through the first opening 810, for example, the first opening 810 exposes a central region of the first electrode 120, and the edge regions of the first electrode 120 are covered by the insulating layer 130.

[0083] The insulating layer 130 includes a first insulating portion 1301 that covers the first electrode 120 and a second insulating portion 1302 that is offset from the first electrode 120. Referring to Figures 2, 3, 4, 5, and 7, the insulating layer 130 is located near an end of the first electrode 120 at a boundary P between the first insulating portion 1301 and the second insulating portion 1302. Referring again to Figure 3, a thickness H7 of the insulating layer 130 at the boundary P between the first insulating portion 1301 and the second insulating portion 1302 is greater than a thickness H8 of the first insulating portion 1301 that corresponds to the first electrode 120.

[0084] Among these, the thickness H7 of the insulating layer 130 at the boundary point P between the first insulating portion 1301 and the second insulating portion 1302 is the thickness of the insulating layer 130 at that position in the direction perpendicular to the array substrate 110.

[0085] The light-emitting unit 150 is at least partially located within the first opening 810 and is located on the side of the first electrode 120 that is farther from the array substrate 110. The material of the light-emitting unit 150 includes an electroluminescent material.

[0086] In some possible implementation manners, the side surface of the first electrode 120 is covered by an insulating layer 130. That is, the insulating layer 130 extends along the side surface of the first electrode 120 to the side far from the array substrate 110 of the first electrode 120, and covers at least a part of the surface of the first electrode 120 far from the array substrate 110. In some possible implementation manners, the insulating layer 130 may be a pixel definition layer, the first opening 810 may be a pixel opening, and the material of the insulating layer 130 is an inorganic material.

[0087] In some possible implementation manners, referring to FIG. 6, the insulating layer 130 includes a first sub-layer 131 and a second sub-layer 132 which are stacked and provided in a direction away from the array substrate 110, and a first ratio value of the nitrogen and silicon content in the first sub-layer 131 is different from a second ratio value of the nitrogen and silicon content in the second sub-layer 132.

[0088] In some possible implementation manners, the materials of both the first sub-layer 131 and the second sub-layer 132 may be silicon nitride, but a first ratio value of the nitrogen and silicon content in the first sub-layer 131 is different from a second ratio value of the nitrogen and silicon content in the second sub-layer 132.

[0089] In some other possible implementation manners, the material of the first sub-layer 131 may be silicon nitride, and the material of the second sub-layer 132 may be silicon oxide.

[0090] In some possible implementation manners, a first ratio value of the nitrogen and silicon content in the first sub-layer 131 is X, and a second ratio value of the nitrogen and silicon content in the second sub-layer 132 is Y, where 0 < X < 3 / 4, and 0 ≤ Y < 3 / 4, and X > Y.

[0091] Based on this, preferably, when Y = 0, the thickness H2 of the second sub-layer 132 is smaller than the thickness H3 of the first sub-layer 131, and when Y ≠ 0, the thickness H2 of the second sub-layer 132 is larger than the thickness H3 of the first sub-layer 131.

[0092] Preferably, the thickness H3 of the first sub-layer 131 ranges from 0 to 3000 Angstroms, and the thickness H2 of the second sub-layer 132 ranges from 0 to 4000 Angstroms.

[0093] In some possible implementations, referring again to FIG. 1, the orthogonal projection of the first electrode 120 on the array substrate 110 at least partially overlaps with the orthogonal projection of the isolation structure 140 on the array substrate 110, for example, the orthogonal projection of the side of the first electrode 120 on the array substrate 110 is located within the orthogonal projection of the isolation structure 140 on the array substrate 110.

[0094] In some possible implementations, referring again to FIGS. 1 and 2, the display panel according to this embodiment may further include an isolation structure 140.

[0095] The isolation structure 140 is located on the side of the insulating layer 130 away from the array substrate 110 and includes an isolation opening, and the orthogonal projection of the first opening 810 on the array substrate 110 is located within the orthogonal projection of the isolation opening on the array substrate 110. The isolation opening communicates with the first opening 810, and together they expose at least a portion of the first electrode 120.

[0096] 8, in some possible implementations, the isolation structure 140 includes a support portion 141 and a blocking portion 142 stacked toward the side farther from the array substrate 110, and the orthogonal projection of the support portion 141 on the array substrate 110 is located within the orthogonal projection of the blocking portion 142 on the array substrate 110. That is, the side surface of the isolation structure 140 forms an undercut structure.

[0097] In some possible implementations, the display panel comprises a display area and a non-display area (eg, a frame area) that at least partially surrounds the display area.

[0098] The first electrodes 120 are located in the display area, and the display panel further includes signal lines located in the non-display area and provided in the same layer as the first electrodes 120. The insulating layer 130 continuously covers the sides of the signal lines and the sides of the signal lines farther from the array substrate 110.

[0099] For example, in the display area, the insulating layer 130 covers the edge regions of the first electrodes 120 and exposes the central regions of the first electrodes, and in the non-display area, the insulating layer 130 completely covers the signal wiring provided in the same layer as the first electrodes 120.

[0100] In this case, the thickness of the insulating layer 130 may be greater than or equal to the thickness of the signal wiring, thereby ensuring that the signal wiring in the non-display area is not damaged by the etching solution during the patterning etching operation of the isolation structure 140.

[0101] Referring to FIG. 11, this embodiment further provides a method for manufacturing a display panel, which may include the following steps.

[0102] In step S110, an array substrate 110 is provided.

[0103] In step S120, a first electrode 120 is provided on one side of the array substrate 110.

[0104] In step S130, an insulating layer 130 is provided on the side of the first electrode 120 farther from the array substrate 110, the insulating layer 130 having a first opening 810, the first electrode 120 having a portion exposed through the first opening 810, and the side surface of the first electrode 120 being covered by the insulating layer 130. The thickness H1 of the insulating layer 130 is greater than or equal to the thickness H2 of the first electrode 120.

[0105] In step S140, a light emitting unit 150 is formed, at least a portion of which is located within the first opening 810 and on the side of the first electrode 120 farther from the array substrate 110.

[0106] In some possible implementations, in step S130, an insulating layer 130 having a thickness greater than or equal to 1000 angstroms can be provided on the side of the first electrode 120 away from the array substrate 110.

[0107] In some possible implementation manners, after step S130, the method further includes the following steps:

[0108] In step S210, an isolation layer 1401 is provided on the insulating layer 130 on the side farther from the array substrate 110.

[0109] For example, referring to FIG. 12, in this embodiment, an isolation layer 1401 that covers the entire surface may be formed first.

[0110] In step S220, the isolation layer 1401 is etched to form an isolation structure 140 having an isolation opening.

[0111] For example, referring to FIG. 13, in this embodiment, the isolation layer 1401 can be patterned by etching to form the isolation structure 140 having the isolation opening.

[0112] Among these, since the risk of the existence of fractures in the insulating layer 130 is reduced in the above-mentioned steps, the risk of the etching solution penetrating into the first electrode 120 through the fractures in the insulating layer 130 during the patterned etching of the isolation layer 1401 in step S150 is reduced, and damage to the first electrode 120 can be avoided.

[0113] In step S230, the insulating layer 130 is etched through the isolation opening to form a first opening 810, which exposes at least a portion of the first electrode 120.

[0114] After etching to form the isolation openings, insulating layer 130 can be further etched to form the structure shown in FIG.

[0115] In some possible implementations, in step S130, a material having a nitrogen and silicon content of a first ratio value may be first used to form a first sub-layer 131 of the insulating layer 130 on the side of the first electrode 120 farther from the array substrate 110, and then a material having a nitrogen and silicon content of a second ratio value may be used to form a second sub-layer 132 of the insulating layer 130 on the side of the first sub-layer 131 farther from the array substrate 110.

[0116] Among them, the first ratio value and the second ratio value are different.

[0117] In some possible implementations, in step S140, a method of depositing all layers and then etching may be adopted to form the light-emitting unit 150, the second electrode 160 and the sealing unit 170, at least a portion of which is located in the isolation opening and is stacked in a direction away from the array substrate 110.

[0118] The present application further provides an electronic device, which includes a display panel according to the present application or a display panel manufactured by the display panel manufacturing method according to the present application, and the electronic device may include devices with display functions such as mobile phones, tablets, smart wearable devices, televisions, laptops, and displays.

[0119] In summary, the present application provides a display panel, a manufacturing method for a display panel, and an electronic device, and by making the thickness of the insulating layer greater than the thickness of the first electrode, the risk of a fracture occurring at the position of the insulating layer covering the first electrode is reduced, and the etching solution is prevented from damaging the first electrode during the subsequent patterned etching of other film layers, thereby ensuring the yield of the display panel.

[0120] The technical features of the above-described embodiments can be combined in any manner. For the sake of simplicity, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered within the scope of the present specification. [Explanation of symbols]

[0121] 110 array substrate, 120 first electrode, 121 first conductive layer, 122 second conductive layer, 123 third conductive layer, 1201 first surface, 1202 second surface, 130 insulating layer, 131 first sub-layer, 132 second sub-layer, 1301 first insulating portion, 1302 second insulating portion, P boundary portion, 1305 first limiting portion, 1306 second limiting portion, 1307 third limiting portion, 140 isolation structure, 141 support portion, 142 blocking portion, 161 First isolation opening, 162, second isolation opening, 163, third isolation opening, 150, light-emitting unit, 151, first light-emitting unit, 152, second light-emitting unit, 153, third light-emitting unit, 160, second electrode, 170, first encapsulation layer, 180, second encapsulation layer, 301, undercut structure, 302, break opening, 1190, third encapsulation layer, 1401, isolation layer, 1411, first metal layer, 1412, second metal layer, 1421, third metal layer, 810, first opening.

Claims

1. an array substrate; an insulating layer positioned on one side of the array substrate and having a plurality of first openings; a plurality of first electrodes located on one side of the array substrate and spaced apart from one another, the first electrodes having portions exposed through the first openings and having side surfaces covered with the insulating layer; a light-emitting unit located on a side of the first electrode farther from the array substrate, the thickness of the insulating layer is greater than or equal to the thickness of the first electrode; A display panel characterized by:

2. the insulating layer includes a first insulating portion covering the first electrode and a second insulating portion not covering the first electrode, and a ratio of a thickness of the first insulating portion to a thickness of the first electrode is greater than or equal to 1; the insulating layer has a thickness ranging from 2000 to 4000 angstroms; a distance from a side of the first insulating portion farther from the array substrate to the array substrate is greater than a distance from a side of the first electrode farther from the array substrate to the array substrate; 2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

3. the first electrode has a first surface farther from the array substrate and a second surface closer to the array substrate; an orthogonal projection on the array substrate of the second surface is located within an orthogonal projection on the array substrate of the first surface, or an orthogonal projection on the array substrate of the first surface is located within an orthogonal projection on the array substrate of the second surface; 2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

4. the insulating layer is made of an inorganic material; the insulating layer includes a first sub-layer and a second sub-layer stacked in a direction away from the array substrate, the first sub-layer having a different silicon content from the second sub-layer, The nitrogen and silicon contents in the first sublayer are a first ratio value, and the nitrogen and silicon contents in the second sublayer are a second ratio value, and the first ratio value and the second ratio value are different; the material of the first sub-layer includes silicon nitride, and the material of the second sub-layer includes silicon nitride or silicon oxide; 2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

5. the first ratio value is X, the second ratio value is Y, 0<X<3 / 4, 0≦Y<3 / 4, and X>Y; When Y=0, the thickness of the second sublayer is smaller than the thickness of the first sublayer, and when Y≠0, the thickness of the second sublayer is greater than the thickness of the first sublayer.

5. The display panel according to claim 4.

6. the first electrode includes a first conductive layer, a second conductive layer, and a third conductive layer that are stacked in a direction away from the array substrate, and an etching rate of the second conductive layer is different from etching rates of the first conductive layer and the third conductive layer; an orthogonal projection of the second conductive layer on the array substrate is located within an orthogonal projection of the first conductive layer and the third conductive layer on the array substrate; a material of the first conductive layer and the third conductive layer includes at least one of indium tin oxide, indium zinc oxide, and indium gallium oxide, and a material of the second conductive layer includes silver; 2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

7. an isolation structure having an isolation opening located on a side of the insulating layer away from the array substrate, wherein an orthogonal projection of the first opening on the array substrate is located within an orthogonal projection of the isolation opening on the array substrate; the isolation structure includes a support portion and a blocking portion stacked toward a side farther from the array substrate, and an orthogonal projection of the support portion on the array substrate is located within an orthogonal projection of the blocking portion on the array substrate.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

8. an orthogonal projection of at least a portion of the first electrode on the array substrate at least partially overlaps an orthogonal projection of the isolation structure on the array substrate; an orthogonal projection of a side surface of the first electrode on the array substrate is located within an orthogonal projection of the isolation structure on the array substrate; 8. The display panel according to claim 7,

9. the support portion includes a first metal layer and a second metal layer stacked toward a side farther from the array substrate, and the blocking portion includes a third metal layer; the material of the first metal layer includes molybdenum, the material of the second metal layer includes aluminum, and the material of the third metal layer includes titanium; 9. The display panel according to claim 8.

10. a second electrode, at least a portion of which is located within the isolation opening, wherein at least a portion of the second electrode is located on a side of the light emitting unit farther from the array substrate and electrically contacts the light emitting unit, and at least a portion of the second electrode is located on a side of the insulating layer farther from the array substrate and electrically contacts the isolation structure; 9. The display panel according to claim 8.

11. a first sealing layer located on a side of the second electrode farther from the array substrate and at least a portion of which is located within the first opening; At least a portion of the first sealing layer is located on a side of the isolation structure that is farther from the array substrate; the display panel further includes a second sealing layer and a third sealing layer located on a side of the first sealing layer farther from the array substrate and stacked in a direction away from the array substrate, a material of the first sealing layer and the third sealing layer includes an inorganic material, and a material of the second sealing layer includes an organic material; 11. The display panel according to claim 10.

12. the isolated opening comprises a first isolated opening and a second isolated opening, the light emitting unit comprises a first light emitting unit and a second light emitting unit having different light emitting colors, at least a portion of the first light emitting unit is located within the first isolated opening, and at least a portion of the second light emitting unit is located within the second isolated opening; the insulating layer includes a first limiting portion protruding from the isolation structure corresponding to the first isolation opening and a second limiting portion protruding from the isolation structure corresponding to the second isolation opening, wherein an orthogonal projection of the first limiting portion on the array substrate is located within an orthogonal projection of the first isolation opening on the array substrate, and an orthogonal projection of the second limiting portion on the array substrate is located within an orthogonal projection of the second isolation opening on the array substrate; the thickness of the first limiting portion and the thickness of the second limiting portion are both greater than the thickness of the first electrode; The thickness of the first limiting portion is greater than the thickness of the second limiting portion, Alternatively, the thickness of the first limiting portion and the thickness of the second limiting portion are substantially equal, the isolating opening further comprises a third isolating opening, the light emitting unit further comprises a third light emitting unit having a light emission color different from that of the first light emitting unit and the second light emitting unit, and at least a portion of the third light emitting unit is located within the third isolating opening; the insulating layer further includes a third limiting portion extending from the isolation structure corresponding to the third isolation opening, and an orthogonal projection of the third limiting portion on the array substrate is located within an orthogonal projection of the third isolation opening on the array substrate; the thicknesses of the first limiting portion, the second limiting portion, and the third limiting portion are all greater than the thickness of the first electrode; The thickness of the second limiting portion is greater than the thickness of the third limiting portion, Alternatively, the thickness of the second limiting portion and the thickness of the third limiting portion are approximately equal.

8. The display panel according to claim 7,

13. the display device includes a display area in which the first electrodes are located and a non-display area at least partially surrounding the display area, and further includes signal wiring provided in the same layer as the first electrodes and located in the non-display area, the insulating layer continuously covering a side surface of the signal wiring and a side of the signal wiring farther from the array substrate, The thickness of the insulating layer is greater than or equal to the thickness of the signal wiring.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

14. an array substrate; an insulating layer positioned on one side of the array substrate and having a first opening; a plurality of first electrodes located on one side of the array substrate and spaced apart from one another, the first electrodes having portions exposed through the first openings; a light-emitting unit located on a side of the first electrode farther from the array substrate; a second electrode located on a side of the light-emitting unit farther from the array substrate, the insulating layer includes a first insulating portion covering the first electrode and a second insulating portion provided offset from the first electrode, and a thickness at a boundary between the first insulating portion and the second insulating portion is greater than a thickness of the first insulating portion corresponding to the first electrode; A display panel characterized by:

15. the insulating layer covers a sidewall of the first electrode, or is made of an inorganic material; the insulating layer includes a first sub-layer and a second sub-layer stacked in a direction away from the array substrate, the first sub-layer having a first ratio of nitrogen and silicon content, and the second sub-layer having a second ratio of nitrogen and silicon content, the first ratio being different from the second ratio; the material of the first sub-layer includes silicon nitride, and the material of the second sub-layer includes silicon nitride or silicon oxide; 15. The display panel according to claim 14.

16. the first ratio value is X, the second ratio value is Y, 0<X<3 / 4, 0≦Y<3 / 4, and X>Y; When Y=0, the thickness of the second sublayer is smaller than the thickness of the first sublayer, and when Y≠0, the thickness of the second sublayer is greater than the thickness of the first sublayer.

16. The display panel according to claim 15.

17. an orthogonal projection of at least a portion of the first electrode on the array substrate at least partially overlaps an orthogonal projection of the isolation structure on the array substrate; an orthogonal projection of a side surface of the first electrode on the array substrate is located within an orthogonal projection of the isolation structure on the array substrate; Alternatively, the display panel further includes an isolation structure having an isolation opening located on a side of the insulating layer farther from the array substrate, wherein an orthogonal projection of the first opening on the array substrate is located within an orthogonal projection of the isolation opening on the array substrate; the isolation structure includes a support portion and a blocking portion stacked toward a side farther from the array substrate, and an orthogonal projection of the support portion on the array substrate is located within an orthogonal projection of the blocking portion on the array substrate.

16. The display panel according to claim 15.

18. providing an array substrate; providing a first electrode on one side of the array substrate; an insulating layer having a first opening is provided on a side of the first electrode farther from the array substrate, the first electrode has a portion exposed from the first opening, and a side surface of the first electrode is covered with the insulating layer, and the thickness of the insulating layer is greater than or equal to the thickness of the first electrode; forming a light-emitting unit located on a side of the first electrode farther from the array substrate; 10. A display panel manufacturing method comprising:

19. The above-described provision of an insulating layer on the side of the first electrode farther from the array substrate is providing an insulating layer on the side of the first electrode away from the array substrate, the insulating layer having a thickness greater than or equal to 1000 angstroms; Alternatively, providing an insulating layer on the side of the first electrode farther from the array substrate may a first sub-layer of the insulating layer is formed on a side of the first electrode farther from the array substrate by using a material having a first ratio of nitrogen and silicon content; and forming a second sub-layer of the insulating layer on a side of the first sub-layer farther from the array substrate by using a material having a second ratio of nitrogen and silicon content; the first ratio value and the second ratio value are different; 19. The method for manufacturing a display panel according to claim 18.

20. providing an isolation layer on a side of the insulating layer remote from the array substrate; Etching the isolation layer to form an isolation structure having an isolation opening; etching the insulating layer through the isolation opening to form a first opening exposing at least a portion of the first electrode; 19. The method for manufacturing a display panel according to claim 18.

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