Vibration device

Abstract

To provide a vibration device that suppresses deterioration in strength.SOLUTION: A vibration device includes: a semiconductor substrate 5 having an upper surface 5a and a lower surface 5b which are in a front-rear relationship and having a through hole th1 penetrating from the upper surface 5a to the lower surface 5b; a vibration element 3 disposed on the semiconductor substrate 5; a lid 4 which is bonded to an outer peripheral part 5p of the upper surface 5a of the semiconductor substrate 5 and houses the vibration element 3 between itself and the upper surface 5a of the semiconductor substrate 5; an oscillation circuit 70 which is provided on the upper surface 5a of the semiconductor substrate 5 and oscillates the vibration element 3; a terminal 510 disposed on to the lower surface 5b of the semiconductor substrate 5; and a through electrode 51 provided in the through hole th1 of the semiconductor substrate 5, and electrically connecting the terminal 510 with the oscillation circuit 70. The through electrode 51 is disposed closer to the outer peripheral portion 5p than a center c1 of the upper surface 5a in a plan view of the semiconductor substrate 5.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a vibration device. [Background technology]

[0002] Patent document 1 discloses a vibrating device having a semiconductor substrate having a first surface and a second surface which are opposite sides of the semiconductor substrate, a vibrating element arranged on the semiconductor substrate, an oscillation circuit provided on the first surface of the semiconductor substrate and causing the vibrating element to oscillate, a terminal arranged on the second surface of the semiconductor substrate, a through electrode that penetrates from the second surface to the first surface of the semiconductor substrate and electrically connects the terminal and the oscillation circuit, and a lid joined to the outer periphery of the semiconductor substrate to house the vibrating element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-72464 Summary of the Invention [Problem to be solved by the invention]

[0004] Such a resonator device has a through electrode, and therefore there is a concern that the strength of the semiconductor substrate on which the through electrode is provided may be reduced. [Means for solving the problem]

[0005] A vibrating device according to one embodiment of the present application comprises a semiconductor substrate having a first surface and a second surface, which are opposite surfaces, and having a through hole penetrating from the first surface to the second surface; a vibrating element disposed on the semiconductor substrate; a lid body joined to the outer periphery of the first surface of the semiconductor substrate and storing the vibrating element between the lid body and the first surface of the semiconductor substrate; an oscillation circuit disposed on the first surface of the semiconductor substrate and causing the vibrating element to oscillate; a terminal disposed on the second surface of the semiconductor substrate; and a through electrode disposed in the through hole of the semiconductor substrate and electrically connecting the terminal and the oscillation circuit, wherein the through electrode is disposed closer to the outer periphery than the center of the first surface when viewed in a plane of the semiconductor substrate.

[0006] A vibrating device according to one aspect of the present application includes a semiconductor substrate having a first surface and a second surface that are opposite surfaces, the semiconductor substrate having a first through hole, a second through hole, a third through hole, and a fourth through hole that penetrate from the first surface to the second surface, a vibrating element disposed on the semiconductor substrate, a lid body that is bonded to an outer periphery of the first surface of the semiconductor substrate and that houses the vibrating element between the lid body and the first surface of the semiconductor substrate, an oscillation circuit that is disposed on the first surface of the semiconductor substrate and causes the vibrating element to oscillate, a first terminal, a second terminal, a third terminal, and a fourth terminal that are disposed on the second surface of the semiconductor substrate, and a terminal that is disposed in the first through hole of the semiconductor substrate and that oscillates the vibrating element. The semiconductor device includes a first through electrode that electrically connects one terminal and the oscillation circuit, a second through electrode provided in the second through hole of the semiconductor substrate and electrically connecting the second terminal and the oscillation circuit, a third through electrode provided in the third through hole of the semiconductor substrate and electrically connecting the third terminal and the oscillation circuit, and a fourth through electrode provided in the fourth through hole of the semiconductor substrate and electrically connecting the fourth terminal and the oscillation circuit, and the first through electrode, the second through electrode, the third through electrode, and the fourth through electrode are arranged closer to the outer periphery than to the center of the first surface when viewed in a plane of the semiconductor substrate. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a perspective view of a vibration device according to a first embodiment. [Figure 2] FIG. 2 is a perspective view of the resonation device of FIG. 1 as seen from the back side. [Figure 3A] 5 is a cross-sectional view of the vibration device taken along line AA in FIGS. 1 and 4. FIG. [Figure 3B] Enlarged view of area C in Figure 3A. [Figure 4] FIG. [Figure 5] FIG. 2 is a plan view of a semiconductor substrate and a vibration element. [Figure 6] FIG. 2 is a cross-sectional view of the vibration device taken along line BB in FIG. 1. [Figure 7] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor circuit. [Figure 8] 1 is a flowchart showing a manufacturing process of a vibration device. [Figure 9] 9 is a flowchart showing details of a through electrode forming step S4 in FIG. 8. [Figure 10] 1A to 1C are cross-sectional views showing one embodiment of a manufacturing process. [Figure 11] 1A to 1C are cross-sectional views showing one embodiment of a manufacturing process. [Figure 12] 1A to 1C are cross-sectional views showing one embodiment of a manufacturing process. [Figure 13] 1A to 1C are cross-sectional views showing one embodiment of a manufacturing process. [Figure 14] 1A to 1C are cross-sectional views showing one embodiment of a manufacturing process. [Figure 15] 1A to 1C are cross-sectional views showing one embodiment of a manufacturing process. [Figure 16] 1A to 1C are cross-sectional views showing one embodiment of a manufacturing process. [Figure 17] 1A to 1C are cross-sectional views showing one embodiment of a manufacturing process. [Figure 18] 1A to 1C are cross-sectional views showing one embodiment of a manufacturing process. [Figure 19] 1A to 1C are cross-sectional views showing one embodiment of a manufacturing process. [Figure 20] 1A to 1C are cross-sectional views showing one embodiment of a manufacturing process. [Figure 21] 1A to 1C are cross-sectional views showing one embodiment of a manufacturing process. DETAILED DESCRIPTION OF THE INVENTION

[0008] In the embodiments of the present invention, components shown in the drawings may be shown with different scales for clarity. Drawings may show three mutually perpendicular axes: the X-axis, the Y-axis, and the Z-axis. In the following explanation, the tip of the arrows on the three axes may be referred to as the "plus side," and the base of the arrows may be referred to as the "minus side." The direction parallel to the X-axis may be referred to as the "X-axis direction," the direction parallel to the Y-axis may be referred to as the "Y-axis direction," and the direction parallel to the Z-axis may be referred to as the "Z-axis direction." Viewing in the Z-axis direction may be referred to as "planar view."

[0009] In the following description, for example, the expression "on the substrate" in relation to a substrate means that the substrate is placed in contact with the substrate, that the substrate is placed via another structure, or that a portion of the substrate is placed in contact with the substrate and a portion of the substrate is placed via another structure. The term "top surface" of a certain structure refers to the surface on the positive side of the Z axis direction of the structure, for example, "top surface of a substrate" refers to the surface on the positive side of the Z axis direction of a movable body. The term "bottom surface" of a certain structure refers to the surface on the negative side of the Z axis direction of the structure, for example, "bottom surface of the substrate" refers to the surface on the negative side of the Z axis direction of the movable body. The terms "front surface" and "back surface" of a certain structure refer to the surface that appears on the outside of the structure, with the "front surface" referring to the surface on the positive side of the Z-axis direction of the structure and the "back surface" referring to the surface on the negative side of the Z-axis direction of the structure.

[0010] 1. Embodiment 1 1.1. Overview of the vibration device 1 to 7 show a schematic configuration of a vibration device 1 according to this embodiment.

[0011] FIG. 1 is a perspective view of a resonation device 1 according to a first embodiment. FIG. 2 is a perspective view of the resonation device 1 as viewed from the back side. FIG. 3A is a cross-sectional view of the resonation device 1 taken along line AA in FIGS. 1 and 4. FIG. 3B is an enlarged view of region C in FIG. 3A. FIG. 4 is a plan view of a semiconductor substrate 5. FIG. 5 is a plan view of the semiconductor substrate 5 and a resonator element 3. FIG. 6 is a cross-sectional view of the resonation device 1 taken along line BB in FIGS. 1 and 5. FIG. 7 is a block diagram showing an example of the configuration of a semiconductor circuit 7.

[0012] 1 is an oscillator, and more specifically, a crystal oscillator in which a resonator element 3 made of quartz crystal and an oscillation circuit 70 are packaged together. The resonator device 1 is mounted on, for example, a mounting substrate 100, and outputs a reference signal to the mounting substrate 100. In this embodiment, the resonator element 3 is an example of a resonator element.

[0013] The resonator device 1 includes a semiconductor device 2, a resonator element 3, and a lid 4. 3A, the semiconductor device 2 includes a semiconductor substrate 5 and a semiconductor circuit 7. The semiconductor circuit 7 is provided on an upper surface 5a of the semiconductor substrate 5. The vibration element 3 is disposed on the upper surface of the semiconductor circuit 7 provided on the semiconductor substrate 5. In this manner, in this embodiment, a face-up method is adopted in which the vibration element 3 is mounted on the surface of the semiconductor substrate 5 on which the semiconductor circuit 7 is formed.

[0014] The lid 4 has a recess 41 and is joined to the outer periphery 5p of the top surface of the semiconductor device 2 to form a package P. The resonator element 3 is housed in a storage space S within the package P. The storage space S is airtight and in a reduced pressure state, preferably closer to a vacuum. This reduces viscous resistance and improves the oscillation characteristics of the resonator element 3. However, the atmosphere in the storage space S is not particularly limited.

[0015] 2, terminals 510, 520, 530, and 540 are provided on the back surface of the resonation device 1. The terminals 510, 520, 530, and 540 are electrically connected via through electrodes 51, 52, 53, and 54 to the semiconductor circuit 7 including the oscillation circuit 70 shown in FIG. In this embodiment, the terminal 510 is an example of a first terminal, the terminal 520 is an example of a second terminal, the terminal 530 is an example of a third terminal, and the terminal 540 is an example of a fourth terminal. The through electrode 51 is an example of a first through electrode, the through electrode 52 is an example of a second through electrode, the through electrode 53 is an example of a third through electrode, and the through electrode 54 is an example of a fourth through electrode.

[0016] 7 is a block diagram showing an example of the configuration of the semiconductor circuit 7. The semiconductor circuit 7 includes an oscillation circuit 70, a control circuit 130, a storage unit 140, a temperature compensation circuit 150, a temperature sensor 160, a reference voltage generation circuit 170, and a clock signal output circuit 180.

[0017] The oscillator circuit 70 is a circuit that generates an oscillation signal using the vibrating element 3. Specifically, the oscillator circuit 70 is connected to the vibrating element 3 via terminals 323 and 324. The oscillator circuit 70 generates an oscillation signal by oscillating the vibrating element 3. For example, in a TCXO (Temperature Compensated Crystal Oscillator) or an OCXO (Oven Controlled Crystal Oscillator), a control voltage VCOMP corresponding to a detected temperature is input to the oscillator circuit 70, and the oscillator circuit 70 oscillates the vibrating element 3 at an oscillation frequency corresponding to the control voltage VCOMP. The control voltage VCOMP is a temperature compensation voltage that compensates for the temperature characteristics of the oscillation frequency.

[0018] The clock signal output circuit 180 outputs a clock signal to a terminal CLKO based on the output signal OSQ of the oscillation circuit 70. In Fig. 2, the terminal CLKO corresponds to, for example, the terminal 510. The clock signal output circuit 180 buffers the output signal OSQ or a signal obtained by dividing the output signal OSQ, and outputs the buffered signal as a clock signal.

[0019] The control circuit 130 controls each part of the semiconductor circuit 7. The control circuit 130 also performs interface processing with a CPU or the like external to the semiconductor circuit 7. The control circuit 130 is realized by a logic circuit such as a gate array, for example.

[0020] The storage unit 140 stores various types of information necessary for the operation of the semiconductor circuit 7. For example, it stores coefficients of a temperature compensation polynomial necessary for the temperature compensation circuit 150 to perform temperature compensation processing. The storage unit 140 is, for example, a nonvolatile memory.

[0021] The temperature compensation circuit 150 outputs a control voltage VCOMP based on a temperature detection signal VT from the temperature sensor 160 and a control voltage for the oscillation frequency input from the outside via a terminal VCNT. The terminal VCNT corresponds to the terminal 520 in FIG. 2, for example.

[0022] The temperature sensor 160 is a sensor that detects the temperature of the semiconductor circuit 7. For example, the temperature sensor 160 can be configured with a diode or the like. The temperature sensor 160 configured with a diode detects temperature using the temperature dependency of the diode's forward voltage, and outputs a temperature detection signal VT.

[0023] The reference voltage generation circuit 170 is a circuit that generates power supplies, reference voltages, bias voltages, bias currents, etc. to be supplied to each component of the semiconductor circuit 7. A high-potential power supply is input to the reference voltage generation circuit 170 via a terminal VDD connected to the high-potential power supply, and a low-potential power supply (ground) is input to the reference voltage generation circuit 170 via a terminal VSS connected to the low-potential power supply. In FIG. 2, the terminal VDD corresponds to, for example, a terminal 530, and the terminal VSS corresponds to, for example, a terminal 540. The reference voltage generation circuit 170 supplies a reference voltage to the temperature compensation circuit 150 or supplies a power supply voltage to the oscillation circuit 70.

[0024] 1.2. Configuration of Semiconductor Device 2 As described above, the semiconductor device 2 includes the semiconductor substrate 5 and the semiconductor circuit 7.

[0025] 1.2.1. Structure of Semiconductor Substrate 5 The semiconductor substrate 5 is a silicon substrate. The semiconductor substrate 5 may be made of a semiconductor material other than silicon, such as Ge, GaP, GaAs, or InP. The semiconductor substrate 5 has an upper surface 5a as a first surface and a lower surface 5b as a second surface, which are opposite surfaces.

[0026] As shown in FIGS. 3A, 4, 5, and 6, the semiconductor substrate 5 has through-holes th1, th2, th3, and th4 that penetrate from the upper surface 5a to the lower surface 5b. The through electrodes 51, 52, 53, and 54 are provided in the through holes th1, th2, th3, and th4, respectively. The through electrodes 51, 52, 53, and 54 are each a TSV (Through Silicon Via). Although cross sections of the through electrode 54 and the through hole th4 are not shown, they are configured similarly to the through electrodes 51, 52, and 53 and the through holes th1, th2, and th3.

[0027] As shown in FIG. 1, the through electrodes 51, 52, 53, and 54 are respectively arranged near the four corners of the outer periphery 5p of the semiconductor substrate 5. More specifically, as shown in FIGS. 4 and 5, the through electrode 51 is arranged closer to a corner 5p1 of the outer periphery 5p than to a center c1 of the upper surface 5a of the semiconductor substrate 5 in a planar view. The through electrode 52 is arranged closer to a corner 5p2 of the outer periphery 5p than to the center c1 of the upper surface 5a of the semiconductor substrate 5 in a planar view. The through electrode 53 is arranged closer to a corner 5p3 of the outer periphery 5p than to the center c1 of the upper surface 5a of the semiconductor substrate 5 in a planar view. The through electrode 54 is arranged closer to a corner 5p4 of the outer periphery 5p than to the center c1 of the upper surface 5a of the semiconductor substrate 5 in a planar view. In this embodiment, corner 5p1 is an example of a first corner, corner 5p2 is an example of a second corner, corner 5p3 is an example of a third corner, and corner 5p4 is an example of a fourth corner.

[0028] As described above, in this embodiment, the semiconductor circuit 7 including the oscillation circuit 70 is provided on the surface of the semiconductor substrate 5 facing the vibration element 3. Therefore, the vibration device 1 needs to be provided with at least four through electrodes 51, 52, 53, and 54 to enable the semiconductor circuit 7 to function. In other words, in this embodiment, the semiconductor substrate 5 needs to be provided with at least four through holes th1, th2, th3, and th4.

[0029] However, providing the through electrodes 51, 52, 53, and 54 in the semiconductor substrate 5 may reduce the strength of the semiconductor substrate 5. In this embodiment, in order to prevent a reduction in the strength of the semiconductor substrate 5, the through electrodes 51, 52, 53, and 54 are provided at positions close to the outer periphery 5p. In other words, in this embodiment, the through holes th1, th2, th3, and th4 are provided at positions close to the outer periphery 5p. Since the lid 4 is joined to the outer periphery 5p, the semiconductor substrate 5 can be reinforced by the lid 4.

[0030] Furthermore, in terms of strength, it is more preferable to provide the through electrodes 51, 52, 53, 54 one each near the four corners 5p1, 5p2, 5p3, 5p4 of the outer periphery 5p. Because the lid 4 and the outer periphery 5p are each rectangular, the corners 5p1, 5p2, 5p3, 5p4 where two sides of the outer periphery 5p intersect provide a stronger reinforcing effect from the lid 4 than the sides between the corners.

[0031] 3A and 6, an insulating film 61 is provided on the upper surface 5a of the semiconductor substrate 5. An insulating film 62 is provided on the lower surface 5b of the semiconductor substrate 5. The insulating film 62 is also provided on the inner surfaces of the through holes th1, th2, th3, and th4. The insulating films 61 and 62 are, for example, silicon oxide (SiO2).

[0032] The through electrode 51 and the terminal 510 are copper (Cu) plated electrodes formed by electrolytic plating. The through electrode 51 and the terminal 510 are integrally formed because they are formed in the same process. In this embodiment, the portions that overlap with the through holes th1, th2, th3, and th4 in plan view are defined as through electrodes 51, 52, 53, and 54, respectively.

[0033] A seed layer 57 is provided between the through electrode 51 and the terminal 510 and the insulating film 62. The through electrode 51 and the terminal 510 may be formed by copper paste printing. The through electrode 52 and the terminal 520, the through electrode 53 and the terminal 530, and the through electrode 54 and the terminal 540 are also configured in the same manner as the through electrode 51 and the terminal 510.

[0034] A conductive protective film 59 is provided to cover the through electrode 51 and the terminal 510. The conductive protective film 59 is provided to suppress outgassing from the through electrode 51 and the terminal 510. The through electrode 51 and the terminal 510, which are made of copper-plated electrodes, contain moisture and hydrogen, and there is a risk that the moisture and hydrogen will be released as outgassing. This outgassing can cause problems such as poor contact at the electrical connection surface with the mounting substrate 100. The through electrode 52 and the terminal 520, the through electrode 53 and the terminal 530, and the through electrode 54 and the terminal 540 are also covered with the conductive protective film 59, similar to the through electrode 51 and the terminal 510.

[0035] FIG. 3B is an enlarged cross-sectional view of region C in FIG. 3A, showing the configuration of seed layer 57 and conductive protective film 59. Seed layer 57 has a two-layered structure made up of titanium / tungsten alloy (TiW) sputtered film 571 and copper sputtered film 572. Instead of the titanium / tungsten alloy of seed layer 57, chromium (Cr) or titanium (Ti) may be used. Conductive protective film 59 has a three-layer laminate structure consisting of electroless plating film 591 of nickel (Ni), electroless plating film 592 of palladium (Pd), and electroless plating film 593 of gold (Au).

[0036] 1.2.2. Configuration of Semiconductor Circuit 7 As shown in FIG. 3A, the semiconductor circuit 7 has a plurality of elements 700 formed on the upper surface 5a of the semiconductor substrate 5, and a stacked body 71 stacked on the upper surface 5a of the semiconductor substrate 5. The laminate 71 has a wiring layer 72 formed on the upper surface 5a of the semiconductor substrate 5, an insulating layer 73 formed on the upper surface of the wiring layer 72, a passivation film 74 formed on the upper surface of the insulating layer 73, and a terminal layer 75 formed on the upper surface of the passivation film 74. The number of wiring layers 72 is not limited to one. A plurality of wiring layers 72 may be provided with a plurality of insulating layers 73 interposed therebetween.

[0037] The multiple elements 700, the wiring layer 72, and the terminal layer 75 are electrically connected via contact holes 76, connecting members (not shown), etc. to form the oscillator circuit 70. The elements 700 are, for example, transistors, resistors, capacitors, etc.

[0038] In this way, by forming the semiconductor circuit 7 on the semiconductor substrate 5, it is possible to effectively utilize the space of the semiconductor substrate 5. Furthermore, since the semiconductor circuit 7 can be integrally formed with the resonator device 1, it is also possible to reduce the size of the entire device.

[0039] 3A and 6, the wiring layer 72 has electrode pads 721, 722, and 723. The electrode pad 721 overlaps the through hole th1 and the through electrode 51 and is electrically connected to the through electrode 51. The electrode pad 722 overlaps the through hole th2 and the through electrode 52 and is electrically connected to the through electrode 52. The electrode pad 723 overlaps the through hole th3 and the through electrode 53 and is electrically connected to the through electrode 53. Although not shown, the wiring layer 72 has an electrode pad 724 that overlaps the through hole th4 and the through electrode 54 and is electrically connected to the through electrode 54.

[0040] The terminal layer 75 has internal terminals 751 and 752 that also serve as wiring. The internal terminals 751 electrically connect the wiring layer 72 and the bonding member B1. The internal terminals 752 electrically connect the wiring layer 72 and the bonding member B2.

[0041] 1.3.Configuration of the lid 4 The lid 4 is a silicon substrate, similar to the semiconductor substrate 5. This makes the linear expansion coefficients of the semiconductor substrate 5 and the lid 4 equal, suppressing the generation of thermal stress due to thermal expansion, resulting in a resonator device 1 with excellent vibration characteristics. Furthermore, since the resonator device 1 can be formed by a semiconductor process, the resonator device 1 can be manufactured with high precision and can be made smaller. However, the lid 4 is not particularly limited, and a substrate made of a semiconductor material other than silicon, such as Ge, GaP, GaAs, or InP, may also be used.

[0042] 1.4.Configuration of vibration element 3 As shown in FIGS. 3A, 5, and 6, the vibration element 3 has a vibration substrate 31 and excitation electrodes 321 and 322. The vibration substrate 31 has a thickness-shear vibration mode and is made of an AT-cut quartz crystal substrate in this embodiment. The AT-cut quartz crystal substrate has a third-order frequency-temperature characteristic, which results in the vibration element 3 having excellent temperature characteristics.

[0043] The excitation electrode 321 is disposed on the upper surface of the vibration substrate 31 and is electrically connected to the terminal 323 via a wiring 325 . The excitation electrode 322 is disposed on the lower surface of the vibration substrate 31 and is electrically connected to a terminal 324 via a wiring 326 .

[0044] The configuration of the vibration element 3 is not limited to the above. For example, the vibration element 3 may have a mesa shape in which the vibration region sandwiched between the excitation electrodes 321 and 322 protrudes from its surroundings, or conversely, an inverted mesa shape in which the vibration region is recessed from its surroundings. The vibration substrate 31 may also be beveled to grind the periphery, or may be convexly curved on its upper and lower surfaces. The vibration element 3 is not limited to a vibration element that vibrates in a thickness-shear vibration mode, and may be, for example, a vibration element in which multiple vibrating arms vibrate in an in-plane flexural direction. In other words, the vibration substrate 31 is not limited to a vibration element formed from an AT-cut quartz substrate, and may be formed from a quartz substrate other than an AT-cut quartz substrate, such as an X-cut quartz substrate, a Y-cut quartz substrate, a Z-cut quartz substrate, a BT-cut quartz substrate, an SC-cut quartz substrate, or an ST-cut quartz substrate. In addition, in this embodiment, the vibration substrate 31 is made of quartz, but is not limited to this, and may be made of, for example, a piezoelectric single crystal such as lithium niobate, lithium tantalate, lithium tetraborate, langasite, potassium niobate, gallium phosphate, or other piezoelectric single crystals. Furthermore, the vibration element 3 is not limited to a piezoelectrically driven vibration element, but may also be an electrostatically driven vibration element using electrostatic force.

[0045] 3A and 6, the vibration element 3 is bonded to the internal terminals 751 and 752 by conductive bonding members B1 and B2. This electrically connects the vibration element 3 and the semiconductor circuit 7 via the bonding members B1 and B2. In this embodiment, the bonding members B1 and B2 are bumps formed by electroless plating.

[0046] 1.5.Method of manufacturing vibration device 8 to 21 are diagrams illustrating a method for manufacturing the vibration device 1 of this embodiment. Fig. 8 is a flowchart illustrating the manufacturing process of the resonator device 1. Fig. 9 is a flowchart showing details of the through electrode forming step S4 in Fig. 8. Figs. 10 to 21 are cross-sectional views showing one embodiment of the manufacturing process, and each cross-sectional view shows a cross section at a position corresponding to line AA in Figs. 1 and 4.

[0047] As shown in FIG. 8, the method for manufacturing the resonator device 1 includes a semiconductor substrate preparation step S1, a resonator element mounting step S2, a sealing step S3, a through electrode formation step S4, and a conductive protection film formation step S5.

[0048] 10, in the semiconductor substrate preparation step S1, a semiconductor substrate 5 is prepared, and a semiconductor circuit 7 is formed on the upper surface 5a side, thereby obtaining a base material for the semiconductor device 2. In the vibrator element mounting step S2, as shown in FIG. 11, the vibrator element 3 is bonded to the internal terminals 751 and 752 via bonding members B1 and B2. In the sealing step S3, as shown in FIG. 12, the lid 4 is bonded to the outer periphery 5p of the upper surface 5a of the semiconductor substrate 5 via the bonding member 40 in a reduced pressure state, and the vibration element 3 is vacuum-sealed in the accommodation space S.

[0049] As shown in FIG. 9, the through electrode formation process S4 includes a thinning process S41, a resist mask formation process S42, a through hole formation process S43, a pad exposure process S44, an insulating film formation process S45, a pad exposure process S46, a seed layer formation process S47, a through electrode formation process S48, a removal process S49, and a conductive protective film formation process S50.

[0050] In the thinning step S41, as shown in FIG. 13, the semiconductor substrate 5 is ground and polished from the lower surface 5b side to thin the semiconductor substrate 5 to a predetermined thickness.

[0051] In the resist mask forming step S42, as shown in FIG. 14, a resist is applied to the lower surface 5b of the semiconductor substrate 5, and the resist is patterned to form a resist mask 81 having openings at positions corresponding to the through holes th1, th2, th3, and th4.

[0052] 15, in the through-hole forming step S43, the semiconductor substrate 5 is dry-etched to form through-holes th1, th2, th3, and th4 in the semiconductor substrate 5, the through-holes reaching the insulating film 61 at positions corresponding to the electrode pads 721, 722, 723, and 724. Thereafter, in this step, the resist mask 81 is removed.

[0053] In the pad exposing step S44, as shown in FIG. 16, the insulating film 61 at the bottom of the through holes th1, th2, th3, and th4 is removed to expose the electrode pads 721, 722, 723, and 724 at the bottom of the through holes th1, th2, th3, and th4.

[0054] In the insulating film forming step S45, as shown in FIG. 17, an insulating film 62 is formed on the lower surface 5b of the semiconductor substrate 5 and the inner surfaces of the through holes th1, th2, th3, and th4.

[0055] 18, in the pad exposing step S46, the insulating film 62 at the bottom of the through holes th1, th2, th3, and th4 is removed to expose the electrode pads 721, 722, 723, and 724 at the bottom of the through holes th1, th2, th3, and th4. When the insulating film 62 at the bottom of the through holes th1, th2, th3, and th4 is removed together with the insulating film 62 at the inner circumferential surfaces of the through holes th1, th2, th3, and th4, an organic insulating film may be provided on the inner circumferential surfaces of the through holes th1, th2, th3, and th4.

[0056] 19, in the seed layer forming step S47, a seed layer 57 is formed by sputtering so as to cover the lower surface 5b of the semiconductor substrate 5 and the insulating film 62 on the inner surfaces of the through holes th1, th2, th3, and th4. As shown in FIG. 3B, the seed layer 57 is a laminated film made up of a titanium / tungsten alloy sputtered film 571 as a deep layer and a copper sputtered film 572 as a surface layer. Chromium or titanium may be used instead of the titanium / tungsten alloy of the seed layer 57.

[0057] 20, in the through electrode formation process S48, a resist mask 82 is formed having openings at positions corresponding to the through holes th1, th2, th3, and th4 and the terminals 510, 520, 530, and 540. Then, in this process, copper plating is formed in the openings by electrolytic plating to form the through electrodes 51, 52, 53, and 54 and the terminals 510, 520, 530, and 540.

[0058] In the removal step S49, as shown in FIG. 21, the resist mask 82 is removed, and then the seed layer 57 exposed from the through electrodes 51, 52, 53, and 54 and the terminals 510, 520, 530, and 540 is removed by etching using the copper plating as a mask.

[0059] 3A and 6, in the conductive protective film forming step S5, conductive protective film 59 is formed by electroless plating to cover through electrodes 51, 52, 53, and 54 and terminals 510, 520, 530, and 540. Conductive protective film 59 is a laminated film made up of a deep layer of electroless plated nickel film 591, an intermediate layer of electroless plated palladium film 592, and a surface layer of electroless plated gold film 593.

[0060] As described above, the vibration device 1 of this embodiment has a semiconductor substrate 5 having an upper surface 5a as a first surface and a lower surface 5b as a second surface, which are opposite surfaces, and having a through hole th1 that penetrates from the upper surface 5a to the lower surface 5b, a vibration element 3 as a vibrating piece arranged on the semiconductor substrate 5, a lid body 4 that is joined to the outer periphery 5p of the upper surface 5a of the semiconductor substrate 5 and stores the vibration element 3 between it and the upper surface 5a of the semiconductor substrate 5, an oscillation circuit 70 that is arranged on the upper surface 5a of the semiconductor substrate 5 and causes the vibration element 3 to oscillate, a terminal 510 that is arranged on the lower surface 5b of the semiconductor substrate 5, and a through electrode 51 that is arranged in the through hole th1 of the semiconductor substrate 5 and electrically connects the terminal 510 and the oscillation circuit 70, and the through electrode 51 is arranged closer to the outer periphery 5p than the center c1 of the upper surface 5a when viewed in a plane of the semiconductor substrate 5.

[0061] As described above, in this embodiment, the through electrodes 51 provided in the semiconductor substrate 5 are disposed closer to the outer periphery 5p than to the center c1 of the upper surface 5a. Since the lid 4 is joined to the outer periphery 5p, the strength of the outer periphery 5p is higher than that of the center c1 in the resonation device 1. Therefore, even if the through electrodes 51 are provided in the semiconductor substrate 5, the resonation device 1 of this embodiment can prevent a decrease in the strength of the semiconductor substrate 5.

[0062] In the resonation device 1 of this embodiment, the outer periphery 5p of the top surface 5a serving as the first surface has a corner 5p1, and the through electrode 51 is disposed near the corner 5p1. As described above, in this embodiment, the through electrodes 51 are disposed near the corners 5p1. Because the cover 4 and the outer peripheral portion 5p are each rectangular, the position of the corners 5p1 where two sides of the outer peripheral portion 5p intersect is stronger than the sides of the outer peripheral portion 5p. Therefore, even if the resonation device 1 of this embodiment has the through electrodes 51 provided in the semiconductor substrate 5, it is possible to prevent a decrease in the strength of the semiconductor substrate 5.

[0063] In the resonator device 1 of this embodiment, the terminals 510 and the through electrodes 51 are covered with a conductive protective film 59. In this manner, in this embodiment, the terminals 510 and the through electrodes 51 are covered with the conductive protective film 59. Therefore, when the resonator device 1 is mounted on the mounting substrate 100, problems such as poor contact can be prevented from occurring on the electrical connection surface with the mounting substrate 100.

[0064] In the resonator device 1 of this embodiment, the conductive protective film 59 is made of a laminated film of nickel, palladium, and gold. In this manner, in this embodiment, the terminals 510 and the through electrodes 51 are covered with the conductive protective film 59 made of a laminated film of nickel, palladium, and gold. Therefore, when the resonation device 1 is mounted on the mounting substrate 100, problems such as poor contact can be suppressed from occurring on the electrical connection surface with the mounting substrate 100.

[0065] The vibration device 1 of this embodiment has an insulating film 62 provided between the through hole th1 and the through electrode 51, and a seed layer 57 provided between the insulating film 62 and the through electrode 51, and the through electrode 51 is made of copper. As described above, in this embodiment, the inner surface of the through hole th1 has the insulating film 62, the seed layer 57, and the through electrode 51, and the through electrode 51 is made of copper. Therefore, the through electrode 51 can be formed with excellent electrical connectivity and conductivity.

[0066] The resonator device 1 of this embodiment has an upper surface 5a as a first surface and a lower surface 5b as a second surface, which are opposite surfaces, and includes a semiconductor substrate 5 having a through hole th1 as a first through hole, a through hole th2 as a second through hole, a through hole th3 as a third through hole, and a through hole th4 as a fourth through hole, which penetrate from the upper surface 5a to the lower surface 5b; a resonator element 3 as a resonator piece arranged on the semiconductor substrate 5; a lid body 4 bonded to an outer periphery 5p of the upper surface 5a of the semiconductor substrate 5 and accommodating the resonator element 3 between the upper surface 5a and the lid body 4; an oscillation circuit 70 provided on the upper surface 5a of the semiconductor substrate 5 and causing the resonator element 3 to oscillate; a terminal 510 as a first terminal, a terminal 520 as a second terminal, a terminal 530 as a third terminal, and a fourth terminal, which are arranged on the lower surface 5b of the semiconductor substrate 5; The semiconductor substrate 5 includes a terminal 540 as a terminal, a through electrode 51 as a first through electrode provided in the through hole th1 of the semiconductor substrate 5 and electrically connecting the terminal 510 and the oscillator circuit 70, a through electrode 52 as a second through electrode provided in the through hole th2 of the semiconductor substrate 5 and electrically connecting the terminal 520 and the oscillator circuit 70, a through electrode 53 as a third through electrode provided in the through hole th3 of the semiconductor substrate 5 and electrically connecting the terminal 530 and the oscillator circuit 70, and a through electrode 54 as a fourth through electrode provided in the through hole th4 of the semiconductor substrate 5 and electrically connecting the terminal 540 and the oscillator circuit 70, and the through electrode 51, the through electrode 52, the through electrode 53, and the through electrode 54 are arranged closer to the outer periphery 5p than the center c1 of the top surface 5a when viewed in a plane of the semiconductor substrate 5.

[0067] As described above, in this embodiment, the through electrodes 51, 52, 53, and 54 provided in the semiconductor substrate 5 are each disposed closer to the outer periphery 5p than to the center c1 of the upper surface 5a. Since the lid 4 is joined to the outer periphery 5p, the strength of the outer periphery 5p is higher than that of the center c1 in the resonation device 1. Therefore, even if the through electrodes 51, 52, 53, and 54 are provided in the semiconductor substrate 5, the resonation device 1 of this embodiment can prevent a decrease in the strength of the semiconductor substrate 5.

[0068] In the vibration device 1 of this embodiment, the outer peripheral portion 5p of the upper surface 5a has a corner 5p1 as the first corner, a corner 5p2 as the second corner, a corner 5p3 as the third corner, and a corner 5p4 as the fourth corner, and the through electrode 51 is arranged near the corner 5p1, the through electrode 52 is arranged near the corner 5p2, the through electrode 53 is arranged near the corner 5p3, and the through electrode 54 is arranged near the corner 5p4.

[0069] As described above, in this embodiment, the through electrodes 51, 52, 53, and 54 are disposed near the corners 5p1, 5p2, 5p3, and 5p4, respectively. Because the cover 4 and the outer peripheral portion 5p are each rectangular, the positions of the corners 5p1, 5p2, 5p3, and 5p4 where two sides of the outer peripheral portion 5p intersect are stronger than the portions of the sides between the corners of the outer peripheral portion 5p. Therefore, in the resonation device 1 of this embodiment, even if the semiconductor substrate 5 is provided with the through electrodes 51, 52, 53, and 54, a decrease in the strength of the semiconductor substrate 5 can be suppressed.

[0070] Although the preferred embodiment has been described above, the present invention is not limited to the above embodiment. The configuration of each part of the present invention can be replaced with any configuration that exhibits the same function as the above embodiment. [Explanation of symbols]

[0071] 1... vibrating device, 2... semiconductor device, 3... vibrating element, 31... vibrating substrate, 321, 322... excitation electrodes, 323, 324... terminals, 325, 326... wiring, 4... lid body, 40... bonding member, 41... recess, 5... semiconductor substrate, 5p... outer periphery, 5p1, 5p2, 5p3, 5p4... corners, 5a... upper surface, 5b... lower surface, 51, 52, 53, 54... through electrodes, 57... seed layer, 59... conductive protective film, 61, 62... insulating film, 7... semiconductor circuit, 70... oscillation circuit, 71... laminate, 7 2...wiring layer, 73...insulating layer, 74...passivation film, 75...terminal layer, 76...contact hole, 81, 82...resist mask, 100...mounting substrate, 510, 520, 530, 540...terminal, 571, 572...sputtered film, 591, 592, 593...electroless plated film, 700...element, 721, 722, 723, 724...electrode pad, 751, 752...internal terminal, B1, B2...bonding member, c1...center, th1, th2, th3, th4...through hole.

Claims

1. a semiconductor substrate having a first surface and a second surface opposite each other, the semiconductor substrate having a through hole penetrating from the first surface to the second surface; a vibrator element disposed on the semiconductor substrate; a lid body joined to an outer periphery of the first surface of the semiconductor substrate, the lid body housing the vibrator element between the first surface of the semiconductor substrate and the lid body; an oscillation circuit provided on the first surface of the semiconductor substrate and causing the vibrating element to oscillate; a terminal disposed on the second surface of the semiconductor substrate; a through electrode provided in the through hole of the semiconductor substrate and electrically connecting the terminal and the oscillation circuit, the through electrode is disposed closer to the outer periphery than to the center of the first surface in a plan view of the semiconductor substrate; Vibration device.

2. the outer periphery of the first surface has a corner, the through electrode is disposed near the corner; The vibration device according to claim 1 .

3. The terminal and the through electrode are covered with a conductive protective film. The vibration device according to claim 1 .

4. the conductive protective film is a laminated film of nickel, palladium, and gold; The vibration device according to claim 3 .

5. an insulating film provided between the through hole and the through electrode; a seed layer provided between the insulating film and the through electrode, The through electrode is made of copper. The vibration device according to claim 3 .

6. a semiconductor substrate having a first surface and a second surface opposite each other, and a first through hole, a second through hole, a third through hole, and a fourth through hole penetrating from the first surface to the second surface; a vibrator element disposed on the semiconductor substrate; a lid body joined to an outer periphery of the first surface of the semiconductor substrate, the lid body housing the vibrator element between the first surface of the semiconductor substrate and the lid body; an oscillation circuit provided on the first surface of the semiconductor substrate and causing the vibrating element to oscillate; a first terminal, a second terminal, a third terminal, and a fourth terminal disposed on the second surface of the semiconductor substrate; a first through electrode provided in the first through hole of the semiconductor substrate, the first through electrode electrically connecting the first terminal and the oscillation circuit; a second through electrode provided in the second through hole of the semiconductor substrate, the second through electrode electrically connecting the second terminal and the oscillation circuit; a third through electrode provided in the third through hole of the semiconductor substrate, electrically connecting the third terminal and the oscillation circuit; a fourth through electrode provided in the fourth through hole of the semiconductor substrate and electrically connecting the fourth terminal and the oscillation circuit; the first through electrode, the second through electrode, the third through electrode, and the fourth through electrode are arranged closer to the outer periphery than to the center of the first surface in a plan view of the semiconductor substrate; Vibration device.

7. the outer periphery of the first surface has a first corner, a second corner, a third corner, and a fourth corner; the first through electrode is disposed near the first corner, the second through electrode is disposed near the second corner, the third through electrode is disposed near the third corner, and the fourth through electrode is disposed near the fourth corner. The vibration device according to claim 6 .

Images