Semiconductor memory device

Abstract

To provide a semiconductor memory device capable of reducing a circuit area.SOLUTION: A semiconductor memory device (10) includes: a memory cell (MC); a high-voltage generation circuit (4) configured to apply a high voltage (Vh) to the memory cell during at least one of write and read operations; and an element (6) connected to the output terminal of the high-voltage generation circuit and configured to suppress an increase in the absolute value of the high voltage by flowing a current when a high voltage that exceeds a target voltage (Vtg) is applied.SELECTED DRAWING: Figure 10A

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor memory devices. [Background technology]

[0002] Conventionally, semiconductor memory devices having memory cells are known. The memory cells include memory elements. For example, some memory elements have a control gate and a floating gate, and apply a high voltage to an oxide film adjacent to the floating gate to inject or extract electrons into or from the floating gate, thereby performing erasure or programming (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-174485

[0004] [overview] In semiconductor memory devices, there is a demand for a reduction in circuit area.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor memory device that can reduce the circuit area.

[0006] A semiconductor memory device according to one aspect of the present disclosure includes: A memory cell; a high voltage generating circuit configured to apply a high voltage to the memory cell during at least one of a write and a read; an element connected to an output terminal of the high voltage generation circuit, configured to suppress an increase in the absolute value of the high voltage by flowing a current when the high voltage exceeding a target voltage is applied; The configuration is provided with the following. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing the configuration of a memory cell. [Figure 2] FIG. 2 is a diagram showing the vertical structure of a memory element. [Figure 3] FIG. 3 is a diagram showing a program / erase circuit associated with a memory device. [Figure 4A] FIG. 4A is a diagram showing a memory cell including a memory element in a programmed state (written state). [Figure 4B] FIG. 4B is a diagram showing a memory cell including a memory element in an erased state. [Figure 5] FIG. 5 is a diagram showing an example of the relationship between the gate voltage and the drain current in the programmed state and the erased state. [Figure 6] FIG. 6 is a diagram showing a complementary cell. [Figure 7] FIG. 7 is a diagram showing data states (memory states) of a complementary cell and the characteristics of gate voltage Vcg-drain current Id corresponding to each data state. [Figure 8] FIG. 8 is a diagram showing a configuration according to a comparative example for applying a high voltage to a memory cell. [Figure 9] FIG. 9 is a waveform diagram schematically showing the behavior of a high voltage in the comparative example. [Figure 10A] FIG. 10A is a diagram illustrating a configuration according to an embodiment of the present disclosure for applying a high voltage (positive voltage) to a memory cell. [Figure 10B] FIG. 10B is a diagram illustrating a configuration according to an embodiment of the present disclosure for applying a high voltage (negative voltage) to a memory cell. [Figure 11] FIG. 11 is a waveform diagram that schematically illustrates the behavior of a high voltage in an embodiment of the present disclosure. [Figure 12] FIG. 12 is a vertical structural view showing an example of a MOS transistor. [Figure 13] FIG. 13 is a diagram showing a configuration according to a modification of the present disclosure for applying a high voltage to a memory cell.

[0008] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0009] <1. Complementary cell> 1 is a diagram showing the configuration of a memory cell MC. The memory cell MC has a memory element MT and a selection transistor ST. The memory element MT is configured with an NMOS transistor (N-channel MOSFET (metal-oxide-semiconductor field-effect transistor)) and is an element for storing data. The memory element MT has a control gate Cg and a floating gate Fg.

[0010] The select transistor ST is an NMOS transistor and is used to select the memory element MT. The source of the memory element MT is connected to a terminal to which a ground potential is applied. The drain of the memory element MT is connected to the source of the select transistor ST. The drain of the select transistor ST is connected to a bit line BL. The select transistor ST has a read gate Rg. The select transistor ST is switched on and off depending on the voltage applied to the read gate Rg.

[0011] 2 is a diagram showing the vertical structure of the memory element MT. As shown in FIG. 2, a P-well region PW is formed in a semiconductor substrate. Two N-type wells are formed on the surface of the P-well region PW. + The region is formed. Two N + An oxide film Ox is formed directly above the channel region sandwiched between the regions. A floating gate Fg is formed directly above the oxide film Ox. A control gate Cg (not shown) is disposed directly above the floating gate Fg.

[0012] FIG. 3 shows a circuit EC for injecting charges into the floating gate Fg of a memory element MT. The circuit EC is provided in a memory cell MC. The circuit EC includes a PMOS transistor PM1 configured as a P-channel MOSFET and NMOS transistors NM1 and NM2. The PMOS transistor PM1 is an element for injecting holes into the floating gate Fg. The NMOS transistor NM1 is an element for injecting electrons into the floating gate Fg. The NMOS transistor NM2 is an element with a coupling rate of 80% or more with the floating gate Fg for controlling the potential of the floating gate Fg.

[0013] To program the memory element MT (write state), a positive voltage Vpp is applied to the program gate Pg of the PMOS transistor PM1, attracting electrons to the connected back gate and driving holes toward the floating gate Fg. At this time, the potential of the control gate Cg is set to a negative voltage Vmm, which captures the holes attracted to the floating gate Fg. As a result, the floating gate Fg becomes hole-rich, as shown in Figure 4A, and this state is the program state.

[0014] On the other hand, when the memory element MT is put into the erase state, a negative voltage Vmm is applied to the erase gate Eg of the NMOS transistor NM1, attracting holes to the connected back gate and driving electrons to the floating gate Fg. At this time, the potential of the control gate Cg is set to a positive voltage Vpp, and the electrons attracted to the floating gate Fg are absorbed into the floating gate Fg. As a result, as shown in Figure 4B, the floating gate Fg becomes electron-rich, which is the erase state.

[0015] The positive voltage Vpp is, for example, 12V, and the negative voltage Vmm is, for example, -7V.

[0016] 5 shows the relationship between the gate voltage Vcg applied to the control gate Cg of the memory element MT in the programmed state PG and the erased state ER, and the drain current Id flowing through the memory element MT, with the select transistor ST turned on by the gate voltage Vrg applied to the read gate Rg. As shown in FIG. 4, in the programmed state PG, the threshold voltage Vt is negative, and in the erased state ER, the threshold voltage Vt is positive.

[0017] Due to these characteristics of the programmed and erased states, when a read gate voltage Vcg is applied to the control gate Cg, the magnitude of the drain current Id varies between the programmed and erased states. Therefore, by turning on the select transistor ST and applying a read gate voltage Vcg to the control gate Cg, the drain Id flows through the bit line BL, and data can be read based on the magnitude of the drain current Id.

[0018] In an embodiment of the present disclosure, as shown in FIG. 6, two memory cells are arranged side by side to form a so-called complementary memory cell (complementary cell). The complementary cell CL includes a first memory cell MC1 and a second memory cell MC2. The first memory cell MC1 includes a first select transistor ST1 and a first memory element MT1. The second memory cell MC2 includes a second select transistor ST2 and a second memory element MT2. A first bit line BL1 is connected to the first select transistor ST1. A second bit line BL2 is connected to the second select transistor ST2. The bit lines BL1 and BL2 are connected to a sense amplifier SA. The sense amplifier SA reads one bit of data DT by detecting the magnitude relationship between a first drain current Id1 flowing through the first memory cell MC1 and a second drain current Id2 flowing through the second memory cell MC2 while the select transistors ST1 and ST2 are turned on by a gate voltage Vrg applied to the read gate and a read gate voltage Vcg is applied to the control gates of the memory elements MT1 and MT2. By setting the gate voltage Vcg applied to the control gate within the range indicated by the solid arrow in FIG. 5, a current difference is generated between the erased and programmed states as indicated by the dashed arrow in FIG. 5, enabling data determination.

[0019] 7 shows the data states (memory states) of the complementary cell CL and the gate voltage Vcg-drain current Id characteristics corresponding to each data state. In FIG. 7, the solid line shows the characteristics of the first memory element MT1, and the dashed line shows the characteristics of the second memory element MT2.

[0020] As shown in FIG. 7, when both the memory elements MT1 and MT2 are in the erased state ER, the data DT read by the sense amplifier SA becomes indefinite, and the complementary cell CL is in the erased state.

[0021] When the first memory element MT1 is in the programmed state and the second memory element MT2 is in the erased state ER, the first drain current Id1 is greater than the second drain current Id2, and therefore the sense amplifier SA reads out data DT="1". In other words, data "1" is stored in the complementary cell CL.

[0022] When the second memory element MT2 is in the programmed state and the first memory element MT1 is in the erased state ER, the first drain current Id1 is smaller than the second drain current Id2, and therefore the sense amplifier SA reads out data DT="0". In other words, data "0" is stored in the complementary cell CL.

[0023] 7, data "1" or "0" is stored in the complementary cell CL depending on which of the memory elements MT1 and MT2 is changed from the erased state of the complementary cell CL to the programmed state. In the stored state of data "1" or "0", the complementary cell CL is changed to the erased state by changing the programmed memory element to the erased state.

[0024] <2. High voltage application configuration> As described above, when changing the characteristics of the memory element MT to a programmed state or an erased state, it is necessary to apply a high voltage, a positive voltage Vpp, to the memory cell MC (specifically, the program gate Pg or the control gate Cg). Depending on the circuit configuration, it may be necessary to apply a high voltage to the memory cell not only during write (program or erase) as described above, but also during read (read). Here, a configuration for applying such a high voltage will be described.

[0025] 8 is a diagram showing a comparative example of a configuration for applying a high voltage Vh (positive voltage) to a memory cell MC. In the configuration shown in Fig. 8, a high voltage generating circuit 1 and a memory cell MC are provided in a semiconductor memory device 100. The high voltage generating circuit 1 has a boosting circuit 2 and a comparing circuit 3.

[0026] The boost circuit 2 is configured as, for example, a charge pump. The boost circuit 2 includes a control circuit 2A. A high voltage Vh is output from the boost circuit 2 and applied to the memory cells MC. If the high voltage Vh is not controlled to a target voltage, a voltage higher than expected may be applied to the memory cells MC or peripheral circuits, potentially resulting in malfunction due to a breakdown voltage violation. Therefore, a comparison circuit 3 and a control circuit 2A are provided to control the high voltage Vh.

[0027] FIG. 9 is a waveform diagram schematically illustrating the behavior of the high voltage Vh in the configuration of the comparative example shown in FIG. 8. When the high voltage Vh exceeds the target voltage Vtg while the boost circuit is on, the comparison circuit 3 detects this and the control circuit 2A turns the boost circuit off. As a result, the high voltage Vh exceeds the target voltage Vh and then drops (off period Toff). When the high voltage Vth falls below the target voltage Vtg, the comparison circuit 3 detects this and the control circuit 2A turns the boost circuit on. As a result, the high voltage Vth falls below the target voltage Vtg and then rises (on period Ton). This operation is repeated to control the high voltage Vh.

[0028] However, in the comparative example described above, it is necessary to provide the comparison circuit 3 and the control circuit 2A, which increases the circuit area. To solve this problem, the following embodiments of the present disclosure are implemented.

[0029] 10A is a diagram showing a configuration according to an embodiment of the present disclosure for applying a high voltage Vh to a memory cell MC. In the configuration shown in FIG. 10A, a high voltage generation circuit 4, a diode element 6, and a memory cell MC are provided in a semiconductor memory device 10. The high voltage generation circuit 4 includes a boost circuit 5.

[0030] The anode of the diode element 6 is connected to a terminal to which the ground potential is applied. The cathode of the diode element 6 is connected to a terminal to which the high voltage Vh output from the boost circuit 5 and applied to the memory cell MC is applied. The breakdown voltage of the diode element 6 is adjusted to a target voltage.

[0031] FIG. 11 is a waveform diagram that schematically illustrates the behavior of the high voltage Vh in the configuration shown in FIG. 10A. When the high voltage Vh rises and exceeds the target voltage Vtg, the diode element 6 breaks down, causing current to flow through the diode element 6 and suppressing the rise in the high voltage Vh. When the high voltage Vh drops below the target voltage Vtg, current stops flowing through the diode element 6. In the configuration shown in FIG. 10A, the boost circuit 5 is always on, so the high voltage Vh rises again. This operation is repeated to control the high voltage Vh.

[0032] According to the embodiment of the present disclosure, the comparison circuit 3 and the control circuit 2A in the comparative example are replaced with the diode element 6, thereby making it possible to significantly reduce the circuit area.

[0033] 10B shows an embodiment in which a negative high voltage Vhm is applied to a memory cell. The difference between the configuration shown in FIG. 10B and that shown in FIG. 10A is that the cathode of diode element 6 is connected to the application terminal of ground potential, and the anode of diode element 6 is connected to the application terminal of high voltage Vhm. Even with this configuration, the high voltage Vhm can be controlled while significantly reducing the circuit area.

[0034] <3. Diode element> The diode element 6 can be configured as a parasitic diode of a MOS transistor (MOSFET), for example. Fig. 12 is a vertical structural diagram showing an example of the configuration of a MOS transistor.

[0035] The MOS transistor 7 shown in FIG. 12 includes a semiconductor substrate 71, a deep N-type well region 72, a P-type well region 73, and an N + Type region 74 and P + N-type region 75, N-type well region 76, and N + a P-type region 77, a P-type well region 78, and a P + and a gate region 79. The MOS transistor 7 is configured as an NMOS transistor.

[0036] The deep N-type well region 72 is formed above a P-type semiconductor substrate 71. Above the deep N-type well region 72, a P-type well region 73 and an N-type well region 76 are formed side by side in the horizontal direction. + Type region 74 and P + The N-type well region 76 has a surface layer formed with N-type regions 75 arranged in a horizontal direction. + Mold region 77 is formed. + The gate is located to the left of the mold region 74, and the N + The P type region 74 corresponds to the source or drain. + The P-type region 75 corresponds to the back gate. The P-type well region 78 is formed above the semiconductor substrate 71. + The P-type region 79 is formed on the surface of the P-type well region 78. + The mold region 79 is a region for fixing the potential of the semiconductor substrate 71 .

[0037] A space SP is provided in the lateral direction between the P-type well region 73 and the N-type well region 77, and a Deep N-type well region 72 is provided in the space SP. The Deep N-type well region 72 has a lower N-type impurity concentration than the N-type well region 76. + Type region 75 and N + Between the P-type region 77 and the diode element 6, a parasitic diode is formed as shown in FIG. + The terminal to which the ground potential is applied is connected to the N + An application terminal for high voltage Vh is connected to the mold region 77. The withstand voltage of the diode element 6 can be adjusted by adjusting the lateral distance L of the space SP. The longer the distance L, the higher the withstand voltage of the element.

[0038] <4. Modifications> 13 is a diagram showing a configuration according to a modification of the present disclosure for applying a high voltage Vh to a memory cell MC. In the configuration shown in FIG. 13, a high voltage generating circuit 4, a memory cell MC, a diode element 6, and a selection unit 8 are provided in a semiconductor memory device 10X. In FIG. 13, the diode element 6 includes diodes 6A and 6B. The selection unit 8 includes switches 8A and 8B.

[0039] The diode 6A and the switch 8A form a pair, and the diode 6B and the switch 8B form a pair. The number of pairs is not limited to two and may be three or more. The switches 8A and 8B are connected between the anode and cathode of the diodes 6A and 6B, respectively. The diodes 6A and 6B are connected in series between an application terminal of the high voltage Vh and an application terminal of the ground potential. Specifically, the anode of the diode 6B is connected to the application terminal of the ground potential, and the cathode of the diode 6B is connected to the anode of the diode 6A. The cathode of the diode 6A is connected to the application terminal of the high voltage Vh.

[0040] By turning on the switches 8A and 8B, the diodes 6A and 6B are turned on. By turning off the switches 8A and 8B, the diodes 6A and 6B are enabled. By selecting the on / off state of the switches 8A and 8B, the breakdown voltage of the diode element 6 can be variably set. In other words, the on / off state of the switches 8A and 8B can be selected according to the desired target voltage Vtg.

[0041] <5.Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0042] <6. Notes> As described above, the semiconductor memory device (10) according to one aspect of the present disclosure includes: a memory cell (MC); a high voltage generating circuit (4) configured to apply a high voltage (Vh) to the memory cell during at least one of a write and a read; The first configuration further comprises an element (6) connected to the output terminal of the high voltage generating circuit and configured to suppress an increase in the absolute value of the high voltage by passing a current when the high voltage exceeds a target voltage (Vtg).

[0043] In addition, in the first configuration, the element may be configured as a diode element having one of a cathode and an anode connected to the output terminal and the other of the cathode and the anode connected to a low potential terminal (second configuration).

[0044] In the second configuration, the diode element may be a parasitic diode included in the MOS transistor (7) (third configuration).

[0045] In the third configuration, the MOS transistor is A Deep N-type well region (72); A P-type well region (73) and an N-type well region (76) formed side by side above the Deep N-type well region; A first N formed on the surface layer of the P-type well region + Type region (74) and P + a mold region (75); A second N formed on the surface of the N-type well region + a type region (77); and the Deep N-type well region has a lower N-type impurity concentration than the N-type well region; a space (SP) is provided between the P-type well region and the N-type well region in the lateral direction; The Deep N-type well region may be provided in the space (fourth configuration).

[0046] Furthermore, the second configuration may be configured to include a selection section (8) configured to be able to variably select the breakdown voltage of the diode element (fifth configuration).

[0047] In any one of the first to fifth configurations, the high voltage generating circuit may include a booster circuit (sixth configuration). [Industrial Applicability]

[0048] The present disclosure can be used in semiconductor memory devices for various applications. [Explanation of symbols]

[0049] 1 High voltage generation circuit 2. Boost circuit 2A control circuit 3 Comparison circuit 4 High voltage generation circuit 5. Boost circuit 6 Diode elements 6A, 6B diodes 7. MOS transistors 10,10X semiconductor memory device 71 Semiconductor substrate 72 Deep N-type well region 73 P-type well region 74 N + type area 75 P + type area 76 N-type well region 77 N-type well region 78 P-type well region 79 P + type area 100 Semiconductor memory device BL Bit Line BL1 1st bit line BL2 Second bit line CL complementary cell Cg Control gate EC circuit Eg Erase Gate Fg Floating Gate MC memory cell MC1 First memory cell MC2 Second memory cell MT memory element MT1 First memory element MT2 Second memory element NM1, NM2 NMOS transistors Ox oxide film PM1 PMOS transistor Pg Program Gate Rg Read Gate SA Sense Amplifier SP Space ST Select Transistor ST1 First selection transistor ST2 Second selection transistor

Claims

1. A memory cell; a high voltage generating circuit configured to apply a high voltage to the memory cell during at least one of a write and a read; an element connected to an output terminal of the high voltage generation circuit, configured to suppress an increase in the absolute value of the high voltage by flowing a current when the high voltage exceeding a target voltage is applied; A semiconductor memory device comprising:

2. 2. The semiconductor memory device according to claim 1, wherein said element is a diode element having one of a cathode and an anode connected to said output terminal and the other of said cathode and said anode connected to a low potential terminal.

3. 3. The semiconductor memory device according to claim 2, wherein said diode element is a parasitic diode included in a MOS transistor.

4. The MOS transistor is a deep N-type well region; a P-type well region and an N-type well region formed side by side in the lateral direction above the Deep N-type well region; A first N formed on the surface of the P-type well region ＋ Type region and P ＋ a type region; A second N formed on the surface of the N-type well region ＋ a type region; and the deep N-type well region has a lower N-type impurity concentration than the N-type well region; a space is provided between the P-type well region and the N-type well region in a lateral direction; 4. The semiconductor memory device according to claim 3, wherein the deep N-type well region is provided in the space.

5. 3. The semiconductor memory device according to claim 2, further comprising a selection section configured to variably select an element breakdown voltage of said diode element.

6. 2. The semiconductor memory device according to claim 1, wherein said high voltage generating circuit comprises a booster circuit.

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