Display device

Abstract

To suppress variations in electrical characteristics and improving the reliability of a semiconductor device comprising a transistor including an oxide semiconductor.SOLUTION: A semiconductor device has a transistor. The transistor includes a gate electrode, a gate insulation film in the gate electrode, an oxide semiconductor film on the gate insulation film, a source electrode electrically connected to the oxide semiconductor film, and a drain electrode electrically connected to the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film on the gate electrode side, and a second oxide semiconductor film on the first oxide semiconductor film. The first oxide semiconductor film includes a first region in which an atomic ratio of In is greater than an atomic ratio of M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf) while the second oxide semiconductor film includes a second region in which the atomic ratio of In is less than that of the first oxide semiconductor film. The second region includes a portion thinner than the first region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device including an oxide semiconductor film. Regarding the law.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to a product, a method, or a manufacturing method. Process, Machine, Manufacture, or Composition of Matter In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, The present invention relates to a device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] A transistor (field-effect transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology that makes up the field-effect transistor (FET) or thin-film transistor (TFT) is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in electronic devices. Silicon is a semiconductor thin film that can be used in transistors. Semiconductor materials, such as silicon, are widely known, but oxide semiconductors are also attracting attention. It is being watched.

[0005] To provide a highly reliable oxide semiconductor transistor with stable electrical characteristics. To obtain the device, oxide semiconductor films with different compositions are stacked, and the channel side is doped with more In. An oxide semiconductor film containing a large amount of stabilizers such as Ga is used on the back channel side. A semiconductor device using a compound semiconductor film has been disclosed (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-175715 Summary of the Invention [Problem to be solved by the invention]

[0007] When an oxide semiconductor film containing a large amount of In is used, the energy band gap (Eg) is small. In this case, the oxide semiconductor with a large Eg may be used. Oxide semiconductors with smaller Eg than conductive films (for example, Eg between 3.0 eV and 3.5 eV) The conductive film is more susceptible to light. Stress test (photo-negative GBT (Gate Bias Temperature) stress test) In this case, the reliability of a transistor including an oxide semiconductor film with a small Eg is reduced. This may occur.

[0008] The light-induced GBT stress test is a type of accelerated test, and is performed under light irradiation for a long period of time. It is possible to evaluate in a short time the changes in transistor characteristics that occur due to the use of , the change in the threshold voltage of the transistor before and after the negative GBT light stress test (ΔVth ) is an important index for investigating reliability. Before and after the light negative GBT stress test, The smaller the change in threshold voltage (ΔVth), the higher the reliability.

[0009] In view of the above problems, in one embodiment of the present invention, a semiconductor device having an oxide semiconductor film containing a large amount of In is The challenge for transistors is to suppress fluctuations in electrical characteristics and improve reliability. Another embodiment of the present invention is a semiconductor device with reduced power consumption. Another object of the present invention is to provide a novel semiconductor. Another object of the present invention is to provide a novel semiconductor device. Another object of the present invention is to provide a method for manufacturing a semiconductor device. One of the objectives of the present invention is to provide a novel display device.

[0010] The above description of the problem does not preclude the existence of other problems. The embodiment does not necessarily have to solve all of these problems. Problems other than those mentioned above can be solved by the specification. It is clear from the description of the specification, etc. that the problems other than those mentioned above cannot be extracted from the description of the specification, etc. It is possible to issue it. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device including a transistor, a gate electrode, a gate insulating film on the gate electrode, an oxide semiconductor film on the gate insulating film, and an oxide A source electrode electrically connected to the semiconductor film and a drain electrode electrically connected to the oxide semiconductor film are and a gate electrode, and the oxide semiconductor film includes a first oxide semiconductor film on the gate electrode side and a first a second oxide semiconductor film on the first oxide semiconductor film, The atomic ratio of M (M is Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) the second oxide semiconductor film has a first region in which the atomic ratio of the first oxide semiconductor layer is greater than the atomic ratio of the second oxide semiconductor layer The semiconductor film has a second region having a lower atomic ratio of In than the first region. The semiconductor device is characterized in that it has a portion thinner than the

[0012] Another embodiment of the present invention is a semiconductor device including a transistor, The gate electrode includes a first gate electrode, a first gate insulating film on the first gate electrode, and a first gate insulating film on the first gate electrode. an oxide semiconductor film on an insulating film; a source electrode electrically connected to the oxide semiconductor film; a drain electrode electrically connected to the oxide semiconductor film; and a second gate insulator on the oxide semiconductor film. a second gate electrode on the second gate insulating film, and the oxide semiconductor film is a first oxide semiconductor film on the gate electrode side and a second oxide semiconductor film on the first oxide semiconductor film; and a first oxide semiconductor film having an In atomic ratio of M (M is a ratio of Ti, Ga, Sn , Y, Zr, La, Ce, Nd, or Hf) than the atomic ratio of the first region the second oxide semiconductor film has a lower atomic ratio of In than the first oxide semiconductor film; The second region has a portion thinner than the first region. It is a semiconductor device.

[0013] In each of the above structures, the oxide semiconductor film contains In, M, and Zn. In each of the above structures, the oxide semiconductor film preferably has a crystalline part. The crystal part has a part in which the c-axis of the crystal part is parallel to the normal vector of the surface on which the oxide semiconductor film is formed. This is preferable.

[0014] In each of the above structures, the first region has a higher proportion of crystal portions than the second region. In each of the above structures, the first region preferably has a thicker portion than the second region. It is preferable that the hydrogen concentration of the silicon dioxide particles is low.

[0015] Another embodiment of the present invention is a semiconductor device and a display element according to any one of the above structures. Another embodiment of the present invention is a display device including the display device and a touch sensor. Another embodiment of the present invention is a display module having any one of the above structures. a semiconductor device, the display device, or the display module according to one of the above; and an operation key or and a battery.

[0016] Another embodiment of the present invention is a method for manufacturing a semiconductor device including a transistor, forming a gate electrode on a substrate; and forming a gate insulating film on the gate electrode. forming a first oxide semiconductor film over a gate insulating film; forming a second oxide semiconductor film, and forming a source electrode and a drain electrode on the second oxide semiconductor film; forming an oxide insulating film on the second oxide semiconductor film; forming an oxide conductive film on the oxide insulating film; and removing the oxide conductive film. In the step of forming the doped electrode, a part of the second oxide semiconductor film is The oxide insulating film is thinner than the semiconductor film and is formed in a PECVD device at 180°C. The oxide insulating film is formed at a temperature of 350° C. or higher during the manufacturing process of a transistor. The manufacturing method of a semiconductor device is characterized in that the temperature in the step of forming the first insulating film is the highest.

[0017] Another embodiment of the present invention is a method for manufacturing a semiconductor device including a transistor, forming a first gate electrode on a substrate; and forming a first gate insulating film on the first gate electrode. forming a first oxide semiconductor film on the first gate insulating film; forming a second oxide semiconductor film on the first oxide semiconductor film; forming a source electrode and a drain electrode on the second oxide semiconductor film; forming an oxide insulating film which functions as a gate insulating film; a step of forming an oxide conductive film; and a step of adding oxygen to the oxide insulating film through the oxide conductive film. a step of removing the oxide conductive film; and a step of forming a second gate electrode on the oxide insulating film. In the step of forming the source electrode and the drain electrode, The oxide insulating film is formed by forming a first oxide semiconductor film on the first oxide semiconductor film. This is carried out in a PECVD apparatus at a temperature of 180°C to 350°C, and transistor fabrication is performed. A semiconductor device characterized in that the temperature in the step of forming an oxide insulating film is the highest among the steps. A method for fabricating the device.

[0018] In each of the above structures, the first oxide semiconductor film and the second oxide semiconductor film each have the following characteristics: Oxygen, In, Zn, and M (M is Ti, Ga, Sn, Y, Zr, La, Ce, Nd, In each of the above structures, the first oxide preferably has a structure represented by the formula (I) or (II). The semiconductor film and the second oxide semiconductor film each have a crystalline portion, and the crystalline portion has a c The axis is parallel to the normal vector of the surface on which the first oxide semiconductor film is formed, or It is preferable that the insulating layer has a portion parallel to the normal vector of the surface on which the nitride semiconductor film is formed. [Effects of the Invention]

[0019] According to one embodiment of the present invention, a semiconductor device including a transistor including an oxide semiconductor This makes it possible to suppress fluctuations in electrical characteristics and improve reliability. According to one embodiment, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. In the present invention, a method for manufacturing a novel semiconductor device can be provided. According to one embodiment, a novel display device can be provided.

[0020] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other effects from the descriptions in the aspects and claims. [Brief explanation of the drawings]

[0021] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 2] 1A and 1B are cross-sectional views illustrating one embodiment of a semiconductor device. [Figure 3] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 5] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 6] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 7] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 8] FIG. 1 is a top view illustrating one embodiment of a display device. [Figure 9] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 10] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 11] 1A and 1B are a block diagram and a circuit diagram illustrating a display device. [Figure 12] FIG. 2 is a diagram illustrating a display module. [Figure 13] 1A to 1C illustrate electronic devices. [Figure 14] FIG. 1 is a diagram illustrating the results of SIMS analysis. [Figure 15] FIG. 1 is a diagram illustrating the results of TDS analysis. [Figure 16] FIG. 1 is a diagram illustrating the results of TDS analysis. [Figure 17] FIG. 1 is a diagram illustrating the ESR measurement results. [Figure 18] FIG. 1 is a diagram illustrating the ESR measurement results. [Figure 19] FIG. 10 is a graph showing ID-VG characteristics of a transistor according to an embodiment. [Figure 20] FIG. 10 is a graph showing ID-VG characteristics of a transistor according to an embodiment. [Figure 21] FIG. 10 is a graph showing ID-VG characteristics of a transistor according to an embodiment. [Figure 22] 10 shows the results of a gate BT stress test on a transistor according to an example. [Figure 23] 10 shows the results of a gate BT stress test on a transistor according to an example. [Figure 24] FIG. 10 is a graph showing ID-VG characteristics of a transistor according to an embodiment. [Figure 25] FIG. 10 is a graph showing ID-VG characteristics of a transistor according to an embodiment. [Figure 26] FIG. 10 is a graph showing ID-VG characteristics of a transistor according to an embodiment. [Figure 27] 10A and 10B are diagrams illustrating probability distributions of Vth and Ion of a transistor according to an embodiment. [Figure 28] 10A to 10C are diagrams illustrating the results of a gate BT stress test on a transistor according to an embodiment. [Figure 29] 10A to 10C are diagrams illustrating the results of a gate BT stress test on a transistor according to an embodiment. [Figure 30] FIG. 2 is a top view of a pixel portion of a display device according to an embodiment. [Figure 31] FIG. 2 is a top view illustrating a frame region of a display device according to an embodiment. [Figure 32] FIG. 2 is a cross-sectional view of a pixel section and a protection circuit section according to an embodiment. [Figure 33] FIG. 2 is a circuit diagram illustrating a protection circuit according to an embodiment. [Figure 34] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 35] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 36] 10A and 10B illustrate structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 37] Electron diffraction pattern of CAAC-OS. [Figure 38] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 39] Schematic diagram illustrating the film formation model of CAAC-OS and nc-OS. [Figure 40] A diagram explaining InGaZnO4 crystals and pellets. [Figure 41] Schematic diagram illustrating a film formation model of CAAC-OS. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments will be described with reference to the drawings. It is possible to implement the present invention in various ways without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0023] Also, in the drawings, the size, thickness of layers, or areas are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown. The drawings are merely schematic illustrations and are not limited to the shapes or values ​​shown in the drawings.

[0024] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the number of components. It should be noted that this is added to avoid confusion and is not intended to limit the number.

[0025] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used to indicate the position of components. The positional relationship is used for convenience in describing the structure with reference to the drawings. The relationship between the two components changes depending on the direction in which each component is depicted. The terms are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0026] In this specification, a transistor includes a gate, a drain, and a source. It is an element having at least three terminals including a drain (drain terminal, drain Between the drain electrode and the source terminal The semiconductor device has a channel region therein, and a current flows through the drain, the channel region, and the source. In this specification and the like, the channel region is a region where a current mainly flows. The flow area.

[0027] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. do.

[0028] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "of" is not subject to any particular restrictions as long as it allows the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. It has various functions such as switching elements, resistors, inductors, capacitors, etc. This includes elements such as:

[0029] In this specification and the like, a silicon oxynitride film is a film containing more oxygen than nitrogen as a component. A silicon nitride film is a film that contains more nitrogen than oxygen. This refers to a film with a high content of

[0030] In addition, in this specification and the like, when explaining the configuration of the invention using drawings, the same The reference numerals are used commonly even among different drawings.

[0031] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes cases where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0032] In addition, in this specification and the like, the terms "film" and "layer" may be used interchangeably. For example, the "conductive layer" It may be possible to change the term to "conductive film". For example, it may be possible to change the term "insulating film" to the term "insulating layer." .

[0033] (Embodiment 1) In this embodiment, a semiconductor device and a manufacturing method of the semiconductor device according to one embodiment of the present invention will be described. The description will be made with reference to FIGS.

[0034] <Configuration Example 1 of Semiconductor Device> FIG. 1A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention. 1(B) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. 1(A). 1(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 1(A). In FIG. 1A, in order to avoid complication, the transistor 100 Some of the components (such as the insulating film that functions as the gate insulating film) are omitted in the illustration. The dashed line X1-X2 direction is the channel length direction, and the dashed line Y1-Y2 direction is the channel width direction. In the top view of the transistor, 1(A), some of the components may be omitted.

[0035] The transistor 100 includes a conductive film 104 over a substrate 102, which functions as a gate electrode, and a An insulating film 106 on the plate 102 and the conductive film 104, an insulating film 107 on the insulating film 106, and an insulating film The oxide semiconductor film 108 on the film 107 and the source electrode 106 electrically connected to the oxide semiconductor film 108 are The conductive film 112a serving as a gate electrode and the gate electrode electrically connected to the oxide semiconductor film 108 are and a conductive film 112b serving as a drain electrode. More specifically, the insulating film 114 is formed over the conductive films 112a and 112b and the oxide semiconductor film 108. , 116, and an insulating film 118 are provided. It functions as a protective insulating film for the sta 100.

[0036] In addition, the oxide semiconductor film 108 is formed by the first oxide film on the conductive film 104 side, which functions as a gate electrode. a second oxide semiconductor film 108a on the first oxide semiconductor film 108a; The insulating film 106 and the insulating film 107 are formed on the gate electrode 8b of the transistor 100. It functions as an insulating film.

[0037] The oxide semiconductor film 108 is an In-M (wherein M is Ti, Ga, Sn, Y, Zr, or La) , Ce, Nd, or Hf) oxide, In-M-Zn oxide can be used. In particular, it is preferable to use In-M-Zn oxide for the oxide semiconductor film 108.

[0038] The first oxide semiconductor film 108a has a first oxide semiconductor layer in which the atomic ratio of In is larger than the atomic ratio of M. The second oxide semiconductor film 108b has a region similar to that of the first oxide semiconductor film 108. The second region has a lower atomic ratio of In than the first region a. It has a thinner portion than

[0039] A first region in which the atomic ratio of In is larger than the atomic ratio of M is formed in the first oxide semiconductor film 108a. By having this, the field effect mobility (simply called mobility, or μFE) of the transistor 100 can be improved. In particular, the field effect transport of the transistor 100 can be increased. degree is 10cm 2 / Vs, and more preferably the field effect mobility of the transistor 100 is 30cm 2 / Vs can be exceeded.

[0040] For example, the above-mentioned high field effect mobility transistor is used as a gate driver for generating a gate signal. driver (especially, the demux connected to the output terminal of the shift register of the gate driver) By using it in a semiconductor device or display device with a narrow frame width (also called a narrow frame), Locations can be provided.

[0041] On the other hand, a first oxide semiconductor having a first region in which the atomic ratio of In is greater than the atomic ratio of M is By using the solid film 108a, the electrical characteristics of the transistor 100 are less likely to change when irradiated with light. However, in the semiconductor device of one embodiment of the present invention, the first oxide semiconductor film 10 A second oxide semiconductor film 108b is formed on the second oxide semiconductor film 8a. The thickness of the first oxide semiconductor film 108b in the vicinity of the channel region is smaller than the thickness of the first oxide semiconductor film 108a. .

[0042] The second oxide semiconductor film 108b contains more In than the first oxide semiconductor film 108a. Since the second region having a smaller atomic ratio is included, Eg is smaller than that of the first oxide semiconductor film 108a. Therefore, the first oxide semiconductor film 108a and the second oxide semiconductor film 10 The oxide semiconductor film 108, which has a stacked structure with the oxide semiconductor film 8b, has a resistance to a negative bias stress test using light. becomes higher.

[0043] By using the oxide semiconductor film having the above structure, the oxide semiconductor film 108 can be effectively prevented from being damaged by light irradiation. Therefore, the amount of absorption of the transistor 100 when irradiated with light can be reduced. Fluctuations in electrical characteristics can be suppressed. Since the insulating film 114 or the insulating film 116 contains excess oxygen, the insulating film 114 or the insulating film 116 is not easily irradiated with light. This can further suppress fluctuations in the electrical characteristics of the transistor 100.

[0044] Here, the oxide semiconductor film 108 will be described in detail with reference to FIG.

[0045] FIG. 2 is an enlarged view of the oxide semiconductor film 108 and its vicinity in the transistor 100 shown in FIG. FIG.

[0046] In FIG. 2, the thickness of the first oxide semiconductor film 108a is t1, and the thickness of the second oxide semiconductor film 108b is t2. The thicknesses of the oxide film 108b are indicated as t2-1 and t2-2, respectively. Since the second oxide semiconductor film 108b is provided on the oxide semiconductor film 108a, When the films 112a and 112b are formed, the first oxide semiconductor film 108a is etched by the etching gas. Therefore, the first oxide semiconductor film 1 is not exposed to gas or etching solution. In the case of 08a, there is no or very little film loss. In the case of 108b, when the conductive films 112a and 112b are formed, the second oxide semiconductor The portions of the film 108b that do not overlap the conductive films 112a and 112b are etched to form recesses. That is, the second oxide semiconductor film 108b overlaps with the conductive films 112a and 112b. The thickness of the region is t2-1, and the conductive films 112a and 112b of the second oxide semiconductor film 108b are The thickness of the region that does not overlap with b is t2-2.

[0047] The relationship between the thicknesses of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b is as follows: It is preferable that -1>t1>t2-2. By making such a film thickness relationship, high A transistor having high field-effect mobility and small change in threshold voltage when irradiated with light. It is possible to make it a digital camera.

[0048] Furthermore, when oxygen vacancies are formed in the oxide semiconductor film 108 of the transistor 100, This generates electrons as carriers, making it easy for the oxide semiconductor to have normally-on characteristics. By reducing oxygen vacancies in the oxide semiconductor film 108, particularly in the first oxide semiconductor film 108a, This is also important for obtaining stable transistor characteristics. In the transistor configuration, an insulating film on the oxide semiconductor film 108, By introducing excess oxygen into the insulating film 114 and / or the insulating film 116 on the insulating film 108, Oxygen is transferred from the insulating film 114 and / or the insulating film 116 into the oxide semiconductor film 108, and the oxide To compensate for oxygen vacancies in the oxide semiconductor film 108, particularly in the first oxide semiconductor film 108a. It is characterized by:

[0049] The insulating films 114 and 116 are formed from a material containing oxygen in excess of the stoichiometric composition. In other words, the insulating films 114 and 116 have The insulating films 114 and 116 are insulating films that can release oxygen. To provide a region, for example, oxygen is introduced into the insulating films 114 and 116 after film formation to form an oxygen-excess region. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

[0050] In addition, in order to compensate for oxygen deficiencies in the first oxide semiconductor film 108a, it is preferable to reduce the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b. Therefore, the relationship of t2 - 2 < t1 may be satisfied. For example, the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b is preferably 1 nm or more and 20 nm or less, and more preferably 3 nm or more and 10 nm or less.

[0051] Hereinafter, other components included in the semiconductor device of the present embodiment will be described in detail. <O

[0052] <Substrate> There is no major limitation on the material of the substrate 102, etc., but it is necessary to have at least heat resistance enough to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. Also, a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc., made of silicon or silicon carbide can be applied, and those with semiconductor elements provided on these substrates may be used as the substrate 102. When using a glass substrate as the substrate 102, the sixth generation (1500 mm × 1850 mm), the seventh generation (1870 mm × 2200 mm), the eighth generation (2200 mm × 2400 mm), the ninth generation (2400 mm × 2800 mm), etc. By using large area substrates such as 10th generation (2950mm x 3400mm), Larger display devices can be fabricated.

[0053] In addition, a flexible substrate is used as the substrate 102, and the transistor 10 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100. The release layer is preferably removed from the substrate 102 after a semiconductor device is partially or completely completed thereon. The transistor 100 can be separated and transferred to another substrate. It can also be transferred to substrates with poor thermal properties or flexible substrates.

[0054] <Conductive film functioning as gate electrode, source electrode, and drain electrode> A conductive film 104 that functions as a gate electrode and a conductive film 112 that functions as a source electrode The conductive film 112b functioning as a drain electrode is made of chromium (Cr), copper (C u), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (M o), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), a metal element selected from nickel (Ni), iron (Fe), cobalt (Co), or the above The alloys are made of metal elements or alloys that combine the above metal elements. It can be formed.

[0055] The conductive films 104, 112a, and 112b may have a single-layer structure or a stacked structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a titanium film on an aluminum film, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film, titanium nitride film Two-layer structure with tungsten film laminated on top, tantalum nitride film or tungsten nitride film Two-layer structure with tungsten film stacked, titanium film, and aluminum film stacked on the titanium film. There are also three-layer structures, such as a titanium film on top of an aluminum film. Select from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film or a nitride film made by combining one or more of these may be used.

[0056] The conductive films 104, 112a, and 112b are made of indium tin oxide or tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide A conductive material having light-transmitting properties, such as indium tin oxide doped with silicon oxide, is used. It is also possible.

[0057] The conductive films 104, 112a, and 112b are made of a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied. This allows for processing using a wet etching process, which reduces manufacturing costs. It becomes possible.

[0058] <Insulating film that functions as a gate insulating film> The insulating films 106 and 107 functioning as gate insulating films of the transistor 100 are Plasma Enhanced Chemical Vapor Deposition (PECVD) Silicon oxide is deposited by vapor deposition, sputtering, etc. silicon oxide film, silicon nitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide film , hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, oxide Tantalum film, magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film The insulating films 106 and 107 may each be an insulating layer containing one or more films. Instead of the laminated structure, a single layer insulating film selected from the above materials or an insulating film with three or more layers may also be used.

[0059] The insulating film 106 also functions as a blocking film that suppresses oxygen permeation. For example, the insulating films 107, 114, and 116 and / or the oxide semiconductor film 108 may contain excess acid. When oxygen is supplied, the insulating film 106 can suppress oxygen permeation.

[0060] Note that the oxide semiconductor film 108, which functions as a channel region of the transistor 100, is in contact with the oxide semiconductor film 108. The insulating film 107 is preferably an oxide insulating film, and the oxide content is in excess of the stoichiometric composition. It is more preferable that the insulating film 1 has a region containing oxygen (an oxygen-excess region). The insulating film 107 is an insulating film capable of releasing oxygen. To provide the insulating film 107, for example, the insulating film 107 may be formed in an oxygen atmosphere. Oxygen may be introduced into the insulating film 107 later to form an oxygen-excess region. These include ion implantation, ion doping, plasma immersion ion implantation, and plasma Zuma processing or the like can be used.

[0061] Furthermore, when hafnium oxide is used as the insulating film 107, the following effects are achieved. Hafnium has a higher dielectric constant than silicon oxide and silicon oxynitride. Compared to the case where silicon oxide is used, the thickness of the insulating film 107 can be made larger, so that the tunnel This reduces the leakage current due to the current flowing through the transistor. Furthermore, hafnium oxide, which has a crystalline structure, can be used to form amorphous structures. Therefore, the off-state current is small. To form a transistor, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal structure include monoclinic and cubic crystals. The types are not limited to these.

[0062] In this embodiment, a silicon nitride film is formed as the insulating film 106, and the insulating film 107 The silicon nitride film has a lower dielectric constant than the silicon oxide film. The film thickness required to obtain the same capacitance as a silicon oxide film is large, so The gate insulating film of the transistor 100 can be made thick by including a silicon nitride film. Therefore, the decrease in the dielectric strength voltage of the transistor 100 can be suppressed, and further, the dielectric strength voltage can be increased. This can improve the resistance of the transistor 100 and suppress electrostatic breakdown of the transistor 100.

[0063] <Oxide semiconductor film> The oxide semiconductor film 108 can be formed using the above-described materials. When 108 is an In-M-Zn oxide, the catalyst used to form the In-M-Zn oxide film is The atomic ratio of the metal elements in the sputtering target preferably satisfies In≧M, Zn≧M. The atomic ratio of the metal elements in such a sputtering target is preferably In:M: Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, I Preferably, n:M:Zn=3:1:2, In:M:Zn=4:2:4.1. When the semiconductor film 108 is an In-M-Zn oxide, many sputtering targets are used. It is preferable to use a target containing crystalline In-M-Zn oxide. By using a target containing Zn oxide, a crystalline oxide semiconductor film 108 is formed. The atomic ratio of the oxide semiconductor film 108 to be formed is subject to an error. The atomic ratio of the metal elements contained in the sputtering target is plus or minus 4. For example, as a sputtering target, the atomic ratio is In:Ga: When Zn=4:2:4.1 is used, the atomic ratio of the oxide semiconductor film 108 to be formed is I In some cases, the n:Ga:Zn ratio is approximately 4:2:3.

[0064] For example, the first oxide semiconductor film 108a may be formed of the above-mentioned In:M:Zn=2:1:3 , In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, etc. The second oxide semiconductor film 108b may be formed using the above-described oxide semiconductor film. If the material is formed using In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, etc. Note that the metal element of the sputtering target used for the second oxide semiconductor film 108b is The atomic ratio of elements does not necessarily satisfy In≧M, Zn≧M, but In≧M, Zn <Mを A specific example is a composition where In:M:Zn=1:3:2.

[0065] The oxide semiconductor film 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. eV or more, more preferably 3 eV or more. By using a nitride semiconductor, the off-state current of the transistor 100 can be reduced. In particular, the first oxide semiconductor film 108a preferably has an energy gap of 2 eV or more. The second oxide semiconductor film 108b is an oxide semiconductor film having a conductivity of 2 eV to 3.0 eV. When an oxide semiconductor film having an energy gap of 2.5 eV or more and 3.5 eV or less is used, In addition, the second oxide semiconductor film 108b is more preferable than the first oxide semiconductor film 108a. The larger the energy gap, the more preferable.

[0066] The thicknesses of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b are Each of these is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably Preferably, the thickness is 3 nm or more and 50 nm or less. .

[0067] The second oxide semiconductor film 108b is an oxide semiconductor film with low carrier density. For example, the second oxide semiconductor film 108b has a carrier density of 1×10 17 pcs / c m 3 Less than 1 × 10 15 pieces / cm 3 or less, more preferably 1 × 10 13 pieces / cm 3 Less than or equal to 1×10 11 pieces / cm 3 The following applies.

[0068] However, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (e.g., the mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of the transistor, the first oxide semiconductor film 108a and the second oxide semiconductor film 108b are The carrier density, impurity concentration, defect density, metal element and oxygen atoms of the oxide semiconductor film 108b It is preferable to make the numerical ratio, interatomic distance, density, etc. appropriate.

[0069] Note that the first oxide semiconductor film 108a and the second oxide semiconductor film 108b are formed of By using an oxide semiconductor film with a low impurity concentration and a low density of defect states, This is preferable because it allows the fabrication of a transistor with excellent electrical characteristics. The term "high purity intrinsic or substantially intrinsic" refers to a low concentration and a low defect level density (low oxygen vacancy). A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film is called a highly purified intrinsic oxide semiconductor film. Since there are fewer carrier sources, the carrier density can be reduced. The transistor in which the channel region is formed in the semiconductor film has an electrical characteristic in which the threshold voltage is negative. It is rare for the material to become normally on. A highly pure intrinsic oxide semiconductor film has a low density of defect states and therefore a low density of trap states. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film may be formed by The off-state current is extremely small, and the channel width is 1×10 6 μm and channel length L is 10 μm Even if the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V, In this range, the off-state current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1×1 0 -13 It can achieve a characteristic of A or below.

[0070] Therefore, the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is provided with a channel. The transistors in which the regions are formed have small fluctuations in electrical characteristics and are highly reliable. Note that charges trapped in the trap states of the oxide semiconductor film are lost. It takes a long time for the charge to dissipate, and it can behave as if it were a fixed charge. A transistor in which a channel region is formed in an oxide semiconductor film with a high density of trap states has Impurities include hydrogen, nitrogen, alkali metals, or Alkaline earth metals, etc.

[0071] The hydrogen contained in the oxide semiconductor film reacts with oxygen that is bonded to metal atoms to form water. The oxygen vacancies are formed in the lattice from which oxygen is desorbed (or in the portions from which oxygen is desorbed). When hydrogen enters the electron carrier, it can generate electrons. It can bond with oxygen, which bonds with metal atoms, to generate electrons, which are carriers. A transistor using an oxide semiconductor film containing hydrogen has normally-on characteristics. Therefore, it is preferable that the amount of hydrogen in the oxide semiconductor film 108 be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor film 108 obtained by SIMS analysis is degrees, 2 x 10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Less than or equal to 5x1, more preferably 0 17 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 below Let's say.

[0072] The first oxide semiconductor film 108a has a higher hydrogen concentration than the second oxide semiconductor film 108b. It is preferable that the first oxide semiconductor film 108a has a portion where the degree of oxidation is low. By having a portion with a lower hydrogen concentration than the compound semiconductor film 108b, a highly reliable semiconductor is obtained. The device may be a device.

[0073] In addition, the first oxide semiconductor film 108a contains silicon and carbon, which are group 14 elements. When the first oxide semiconductor film 108a contains oxygen, oxygen vacancies increase in the first oxide semiconductor film 108a, and the first oxide semiconductor film 108a becomes n-type. Therefore, the concentrations of silicon and carbon in the first oxide semiconductor film 108a and The concentrations of silicon and carbon near the interface with the oxide semiconductor film 108a of The resulting concentration is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 at oms / cm 3 The following applies.

[0074] In addition, the alkali metal oxide film 108a obtained by SIMS analysis The concentration of metal or alkaline earth metal is 1×10 18 atoms / cm 3 The following is preferably is 2 x 10 16 atoms / cm 3 The alkali metals and alkaline earth metals are as follows: When bonded to an oxide semiconductor, carriers may be generated, increasing the off-state current of the transistor. Therefore, the alkali metal or It is preferable to reduce the concentration of alkaline earth metals.

[0075] When the first oxide semiconductor film 108a contains nitrogen, electrons serving as carriers This increases the carrier density and makes it easier to become n-type. A transistor using a conductor film tends to have normally-on characteristics. It is preferable that nitrogen is reduced as much as possible in the solid film. For example, SIMS analysis The nitrogen concentration obtained is 5×10 18 atoms / cm 3 It is preferable to do the following: .

[0076] The first oxide semiconductor film 108a and the second oxide semiconductor film 108b are The non-single crystal structure may be, for example, CAAC-OS (CAx is Aligned Crystalline Oxide Semiconductor or), polycrystalline structure, microcrystalline structure, or amorphous structure. The amorphous structure has the highest density of defect states, while the CAAC-OS has the lowest density of defect states.

[0077] <Insulating film that functions as a protective insulating film for transistors> The insulating films 114 and 116 have a function of supplying oxygen to the oxide semiconductor film 108. The insulating film 118 functions as a protective insulating film for the transistor 100. The films 114 and 116 contain oxygen. The insulating film 114 is also permeable to oxygen. The insulating film 114 is an insulating film formed by etching when the insulating film 116 is formed later. It also functions as a film for reducing damage to the compound semiconductor film 108 .

[0078] The insulating film 114 has a thickness of 5 nm to 150 nm, preferably 5 nm to 50 Silicon oxide, silicon oxynitride, etc., having a thickness of 1 nm or less can be used.

[0079] Furthermore, it is preferable that the insulating film 114 has a small number of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 3 x 10 17 spins / cm 3 This is because the insulating film 114 is preferably If the density of defects contained is high, oxygen will be bonded to the defects, and the oxygen in the insulating film 114 will The amount of transmission of light decreases.

[0080] In the insulating film 114, all the oxygen that has entered the insulating film 114 from the outside is Some oxygen does not move to the outside of the insulating film 114 and remains in the insulating film 114. At the same time, oxygen contained in the insulating film 114 moves to the outside of the insulating film 114, Oxygen may move in the film 114. When the oxide insulating film capable of forming the insulating film 114 is formed, the insulating film 116 and the insulating film 116 are formed on the insulating film 114. The desorbed oxygen can be transferred to the oxide semiconductor film 108 through the insulating film 114. .

[0081] The insulating film 114 is formed using an oxide insulating film with a low density of states due to nitrogen oxides. Note that the density of states due to the nitrogen oxide can be determined by the valence Energy of the top of the electronic band (Ev_os) and energy of the bottom of the conduction band of the oxide semiconductor film (Ec_os) may be formed between E v_os and E c_os Nitrogen oxide during As the oxide insulating film having a low density of states of atoms, silicon oxynitride which emits a small amount of nitrogen oxide is used. It is possible to use aluminum oxide nitride film or aluminum oxynitride film which emits less nitrogen oxide. Cut.

[0082] In addition, a silicon oxynitride film that emits a small amount of nitrogen oxides can be analyzed by thermal desorption spectroscopy. This membrane releases more ammonia than nitrogen oxides, and typically releases ammonia. The amount of release is 1×10 18 pieces / cm 3 5x10 or more 19 pieces / cm 3 The following is the case. The amount of monia released is determined when the surface temperature of the membrane is 50°C or higher and 650°C or lower, preferably 50°C or higher and 55°C or lower. The amount released by heating at 0°C or below.

[0083] Nitrogen oxides (NO x , x is 0 or more and 2 or less, preferably 1 or more and 2 or less), typically NO 2 or NO forms a level in the insulating film 114 or the like. Therefore, the nitrogen oxide is located within the energy gap of the insulating film 114 and the oxide film. When the electrons diffuse to the interface of the compound semiconductor film 108, the level traps electrons on the insulating film 114 side. As a result, the trapped electrons may be trapped in the insulating film 114 and the oxide semiconductor film 116. 108 Because it remains near the interface, the threshold voltage of the transistor is shifted in the positive direction. Put away.

[0084] Nitrogen oxide reacts with ammonia and oxygen during heat treatment. The nitrogen oxide contained in the insulating film 116 reacts with the ammonia contained in the insulating film 116 during the heat treatment. Therefore, the nitrogen oxide contained in the insulating film 114 is reduced. Electrons are less likely to be trapped at the interface between the oxide semiconductor film 106 and the oxide semiconductor film 108.

[0085] By using the oxide insulating film as the insulating film 114, the threshold voltage of the transistor can be reduced. It is possible to reduce the shift in the electrical characteristics of the transistor. can.

[0086] Note that the heat treatment in the manufacturing process of a transistor is typically performed at a temperature of 300° C. or higher and lower than 350° C. By the heat treatment, the insulating film 114 shows the following characteristics in the spectrum obtained by ESR measurement at 100K or less. The first signal has a g value of 2.037 or more and 2.039 or less, and the second signal has a g value of 2.001 or more. A second signal less than .003 and a third signal with a g value between 1.964 and 1.966. The split width of the first signal and the second signal, and the The split width of the second signal and the third signal is about 5 in the X-band ESR measurement. mT. The first signal has a g value of 2.037 or more and 2.039 or less, and the g value is 2. A second signal between 0.001 and 2.003, and a g value between 1.964 and 1.966 The total spin density of the third signal is 1×10 18 spins / cm 3 is less than A typical example is 1×10 17 spins / cm 3 More than 1×10 18 spins / cm 3 Less than be.

[0087] In addition, the g value is between 2.037 and 2.039 in the ESR spectrum below 100K. The first signal has a g value of 2.001 or more and 2.003 or less, and the second signal has a g value of 1 The third signal, between 0.964 and 1.966, is nitrogen oxide (NO x , x is between 0 and 2 Representative examples of nitrogen oxides include: , nitrogen monoxide, nitrogen dioxide, etc. That is, the first a signal with a g value between 2.001 and 2.003, and a second signal with a g value between 1.9 The smaller the sum of the spin densities of the third signals between 64 and 1.966, the better the oxide insulation. It can be said that the nitrogen oxide content in the coating is low.

[0088] The oxide insulating film has a nitrogen concentration of 6×10 as measured by SIMS. 20 atoms / cm 3 The following is the result.

[0089] The substrate temperature is between 220℃ and 350℃, and PEC using silane and nitrous oxide is used. By forming the oxide insulating film using a VD method, a dense and hard film can be obtained. It can be formed.

[0090] The insulating film 116 is an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. The oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition is formed using When heated, some of the oxygen is released. The oxygen content is greater than the stoichiometric value. The oxide insulating film had a desorption of 1.0 x 10 oxygen atoms in TDS analysis. 1 9 atoms / cm 3 or more, preferably 3.0 × 10 20 atoms / cm 3 That's all The surface temperature of the film during the TDS analysis was 100°C or higher. The temperature range is preferably from 100°C to 500°C or from 100°C to 700°C.

[0091] The insulating film 116 has a thickness of 30 nm to 500 nm, preferably 50 nm or more. Silicon oxide, silicon oxynitride, etc., of 400 nm or less can be used.

[0092] Furthermore, it is preferable that the insulating film 116 has a small number of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 1.5 x 10 18 spins / cm 3 Less than, or even 1×10 18 spins / cm 3 It is preferable that the insulating film 116 has a higher oxide semiconductor content than the insulating film 114. Since it is separated from the insulating film 108, it may have a higher defect density than the insulating film 114.

[0093] In addition, the insulating films 114 and 116 can be made of the same material, so that the insulating film In some cases, the interface between the film 114 and the insulating film 116 cannot be clearly seen. In this embodiment, the interface between the insulating film 114 and the insulating film 116 is shown by a broken line. In the embodiment, the two-layer structure of the insulating film 114 and the insulating film 116 has been described. For example, the insulating film 114 may have a single-layer structure.

[0094] The insulating film 118 contains nitrogen and silicon. The insulating film 118 also contains blockers such as oxygen, hydrogen, water, alkali metals, and alkaline earth metals. By providing the insulating film 118, the oxide semiconductor film 108 can be prevented from being oxidized. The diffusion of oxygen from the insulating films 114 and 116 to the outside. This can prevent hydrogen, water, and the like from entering the oxide semiconductor film 108. For example, a nitride insulating film can be used. Silicon nitride, silicon oxide nitride, aluminum nitride, aluminum oxide nitride, etc. Nitride insulating material with blocking effect against hydrogen, water, alkali metals, alkaline earth metals, etc. Instead of the insulating film, an oxide insulating film having a blocking effect on oxygen, hydrogen, water, etc. may be provided. As an oxide insulating film having a blocking effect against oxygen, hydrogen, water, etc., aluminum oxide is preferable. aluminum oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide, Examples include yttrium oxide nitride, hafnium oxide, and hafnium oxide nitride.

[0095] Note that the various films described above, such as the conductive film, insulating film, and oxide semiconductor film, are formed by sputtering. It can be formed by a coating method or a PECVD method, but other methods, such as thermal CVD (Ch emical Vapor Deposition (ALD) method or Atomic It may be formed by a thermal CVD method. OCVD(Metal Organic Chemical Vapor Deposit) tion) method.

[0096] The thermal CVD method is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that no further processing is required.

[0097] In the thermal CVD method, the source gas and oxidant are simultaneously fed into a chamber, and the chamber is heated to atmospheric pressure. Alternatively, a film is formed by reacting the material near or on the substrate under reduced pressure and depositing the material on the substrate. You may go.

[0098] In addition, in the ALD method, the pressure inside the chamber is atmospheric or reduced, and the source gas for the reaction is The gases may be introduced into the chamber in sequence, and the film may be formed by repeating this gas introduction sequence. For example, by switching between two or more types of switching valves (also called high-speed valves), The source gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the source gases. Inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the fuel gas. In case of simultaneously introducing an inert gas, the inert gas is The second source gas may be introduced as a carrier gas, and an inert gas may be introduced at the same time as the second source gas is introduced. Also, instead of introducing an inert gas, the first raw material gas is discharged by vacuum evacuation. The first source gas may be adsorbed on the surface of the substrate to form a first layer. The second layer is deposited on the first layer by reacting with the second source gas introduced later. This process is repeated several times while controlling the gas introduction order until a desired thickness is achieved. By doing so, a thin film with excellent step coverage can be formed. The thickness of the thin film is determined by the order of gas introduction. The thickness can be precisely adjusted by changing the number of times the process is repeated. This is suitable for producing thin FETs.

[0099] Thermal CVD methods such as MOCVD can be used to form the conductive film, insulating film, oxide semiconductor film, It is possible to form various films such as metal oxide films, for example, In-Ga-ZnO films. In this case, trimethylindium, trimethylgallium, and dimethylzinc are used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of gallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn( CH3)2. In addition, the combination is not limited to these, and instead of trimethylgallium, Triethylgallium (chemical formula Ga(C2H5)3) can also be used, and dimethylzinc Alternatively, diethylzinc (chemical formula Zn(C2H5)2) can be used.

[0100] For example, when forming a hafnium oxide film using a film forming apparatus that uses ALD, the solvent and liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethyl The raw material gas is vaporized hafnium amide (such as TDMAH) and acid Two types of gases are used: tetrakisdimethylamide (TDMA) and ozone (O3) as a chlorine gas. The chemical formula for Hf is Hf[N(CH3)2]4. Other materials include tetrahydrofuran, Examples include rakis(ethylmethylamido) hafnium.

[0101] For example, when forming an aluminum oxide film using an ALD film forming device, A liquid containing a catalyst and an aluminum precursor compound (e.g., trimethylaluminum (TMA)) is added. Two types of gases are used: vaporized source gas and H2O as an oxidizing agent. The chemical formula for aluminum is Al(CH3)3. Other liquid materials include Tris( dimethylamido)aluminum, triisobutylaluminum, aluminum tris(2 ,2,6,6-tetramethyl-3,5-heptanedionate).

[0102] For example, when forming a silicon oxide film using a film forming device that uses ALD, Chlorodisilane is adsorbed onto the surface to be coated, removing the chlorine contained in the adsorbed material, and the oxidizing gas (O 2. Nitrous oxide (NO) radicals are supplied to react with the adsorbed material.

[0103] For example, when forming a tungsten film using an ALD deposition system, WF6 The initial tungsten film was formed by sequentially introducing BH gas and BH gas. The tungsten film is formed by simultaneously introducing B2H6 gas and H2 gas. Alternatively, SiH4 gas may be used.

[0104] For example, an oxide semiconductor film, such as In-Ga-ZnO, can be formed using a film formation device that uses ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly to form an In- After that, Ga(CH3)3 gas and O3 gas are introduced repeatedly to form a GaO Then, Zn(CH3)2 and O3 gases are introduced repeatedly to form a ZnO layer. The order of these layers is not limited to this example. Even if mixed compound layers such as n-Ga-O, In-Zn-O, and Ga-Zn-O layers are formed, It is also good to use H2O gas obtained by bubbling an inert gas such as Ar instead of O3 gas. However, it is preferable to use O3 gas that does not contain H. In(CH3) Instead of In(C2H5)3 gas, Ga(CH3)3 gas may be used. Instead of gas, Ga(C2H5)3 gas may be used. You can use it.

[0105] <Configuration Example 2 of Semiconductor Device> Next, examples of structures different from those of the transistor 100 shown in FIGS. 3(A)(B)(C) will be used for the explanation. Note that the functions described above are the same as those described above. In some cases, the hatch pattern may be the same and no particular reference numeral may be assigned.

[0106] FIG. 3A is a top view of a transistor 170 which is a semiconductor device of one embodiment of the present invention. 3(B) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. 3(A). 3(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 3(A). Correct.

[0107] The transistor 170 includes a conductive film 104 over a substrate 102, which functions as a first gate electrode. an insulating film 106 on the substrate 102 and the conductive film 104; and an insulating film 107 on the insulating film 106. , the oxide semiconductor film 108 on the insulating film 107, and the insulating film 114 on the oxide semiconductor film 108. , an insulating film 116 on the insulating film 114, and a source electrode electrically connected to the oxide semiconductor film 108. The conductive film 112a serving as an electrode and the drain electrically connected to the oxide semiconductor film 108 are 112b functioning as an in-electrode, an insulating film 114 on the oxide semiconductor film 108, and an insulating film an insulating film 116 on the insulating film 114, an insulating film 118 on the insulating film 116, and a conductive film on the insulating film 118; 120a and a conductive film 120b on the insulating film 118. The conductive film 18 functions as a second gate insulating film of the transistor 170. The insulating film 114, 116, and 118 are provided with openings 142c through which the conductive film 120a is formed. In the transistor 170, the conductive film 120a is electrically connected to the conductive film 112b. The transistor 17 functions as, for example, a pixel electrode used in a display device. In FIG. 1, the conductive film 120b is used as a second gate electrode (also referred to as a back gate electrode). It works.

[0108] As shown in FIG. 3C, the conductive film 120b is formed by insulating films 106, 107, 114, and 1 In the openings 142a and 142b formed in the gate electrodes 16 and 118, Therefore, the conductive film 120b and the conductive film 104 are connected to the conductive film 104. A potential is applied.

[0109] In this embodiment, openings 142a and 142b are provided, and the conductive film 120b and Although the configuration in which the conductive film 104 is connected has been exemplified, the present invention is not limited to this. Only one of the openings 142a and 142b is formed. The conductive film 104 is connected, or the openings 142a and 142b are not provided, and the conductive film 104 is not connected. The conductive film 120b and the conductive film 104 may not be connected to each other. In the case where the conductive film 104 is not connected, the conductive film 120b and the conductive film 104 are respectively connected to different A potential can be applied.

[0110] As shown in FIG. 3B, the oxide semiconductor film 108 functions as a gate electrode. The conductive film 104 and the conductive film 120b functioning as the second gate electrode are opposed to each other. The second gate electrode is sandwiched between two conductive films that function as gate electrodes. The length in the channel length direction and the length in the channel width direction of the conductive film 120b functioning as an electrode are as follows: The length of the oxide semiconductor film 108 in the channel length direction and the length of the oxide semiconductor film 108 in the channel width direction are The entire oxide semiconductor film 108 is covered with the conductive film 1 via the insulating films 114, 116, and 118. The gate electrode is covered with a conductive film 120b that functions as a second gate electrode. The conductive film 104 functioning as an electrode is made up of insulating films 106, 107, 114, 116, and 118. 108. The oxide semiconductor film 108 is connected through the openings 142a and 142b. The side surfaces of the gate electrode 111 in the channel width direction are connected to the second gate electrode 112 via insulating films 114, 116, and 118. The conductive film 120b faces the conductive film 120b.

[0111] In other words, in the channel width direction of the transistor 170, The conductive film 104 functioning as the second gate electrode and the conductive film 120b functioning as the second gate electrode are used as gate insulating films. the insulating films 106 and 107 functioning as the second gate insulating film and the insulating film 114 functioning as the second gate insulating film. , 116, 118 are connected in the openings and function as gate insulating films. and insulating films 114 and 116 functioning as second gate insulating films. , 118 surround the oxide semiconductor film 108 .

[0112] With such a structure, the oxide semiconductor film 108 included in the transistor 170 The conductive film 104 functions as a gate electrode and the conductive film 105 functions as a second gate electrode. 120b. an oxide semiconductor film in which a channel region is formed by the electric field of the first electrode and the second gate electrode; The device structure of a transistor that electrically surrounds the This can be called an s-channel structure.

[0113] The transistor 170 has an s-channel structure, and therefore functions as a gate electrode. The conductive film 104 effectively applies an electric field for inducing a channel to the oxide semiconductor film 1. 08, the current driving capability of the transistor 170 is improved, and a high It is also possible to increase the on-current, It is possible to miniaturize the transistor 170. In addition, the transistor 170 has a gate The conductive film 104 functions as a first electrode and the conductive film 120b functions as a second gate electrode. Since the transistor 170 has a structure surrounded by the Cut.

[0114] The other configurations of the transistor 170 are the same as those of the transistor 100 shown above. and has the same effect.

[0115] In addition, the transistor according to this embodiment can be freely combined with each of the above structures. For example, the transistor 100 shown in FIG. 1 can be used as a transistor for a pixel of a display device. 3 is used as a transistor for the gate driver of the display device. It can be used for

[0116] <Method 1 for manufacturing semiconductor device> Next, a method for manufacturing the transistor 100, which is a semiconductor device of one embodiment of the present invention, will be described with reference to FIGS. 4 to 6. Note that FIGS. 4 to 6 show a method for manufacturing a semiconductor device. FIG.

[0117] Note that the films (insulating film, oxide semiconductor film, conductive film, etc.) constituting the transistor 100 are Sputtering, Chemical Vapor Deposition (CVD), Vacuum Evaporation, Pulsed Laser Deposition (PLD) Alternatively, the layer can be formed by a coating method or a printing method. Typical film formation methods are sputtering and plasma enhanced chemical vapor deposition (PECVD). However, thermal CVD or ALD (atomic layer deposition) may also be used. Examples of thermal CVD include: One example is the MOCVD (metal organic chemical vapor deposition) method.

[0118] In the thermal CVD method, the pressure in the chamber is atmospheric or reduced, and the source gas and oxidant are simultaneously mixed. The reaction is carried out in the chamber near or on the substrate, where it is deposited on the substrate to form a film. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that defects are not generated due to damage.

[0119] In addition, in the ALD method, the pressure inside the chamber is atmospheric or reduced, and the source gas for the reaction is The gases are introduced into the chamber in sequence, and the film is formed by repeating this gas introduction sequence. By switching each switching valve (also called high-speed valve), two or more types of raw materials can be The source gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the source gases. Simultaneously with or after the second gas, an inert gas (argon, nitrogen, etc.) is introduced. Introduce the source gas. If an inert gas is introduced at the same time, the inert gas is used as a carrier gas. In addition, an inert gas may be introduced at the same time as the second source gas is introduced. Alternatively, instead of introducing an inert gas, the first source gas is discharged by vacuum evacuation, and then the second source gas is introduced. The first source gas may be adsorbed on the surface of the substrate to form a first monoatomic layer. The second monoatomic layer is formed by reacting with the second source gas introduced later. Layer upon layer is laminated to form a thin film.

[0120] This gas introduction sequence is repeated multiple times while controlling it until the desired thickness is achieved. The thickness of the thin film increases depending on the number of times the gas introduction sequence is repeated. Therefore, precise film thickness control is possible, and fine transistors can be fabricated. It is suitable for manufacturing.

[0121] First, a conductive film is formed on the substrate 102, and the conductive film is then subjected to a lithography process and an etching process. Then, the conductive film 104 is formed to function as a gate electrode. Insulating films 106 and 107 that function as gate insulating films are formed on the insulating film 04 (see FIG. 4(A)). ).

[0122] The conductive film 104 functioning as the gate electrode is formed by a sputtering method, a chemical vapor deposition (CVD) method, or the like. It can be formed by using a method such as a vacuum evaporation method or a pulsed laser deposition (PLD) method. Alternatively, the film can be formed by a coating method or a printing method. The plasma enhanced chemical vapor deposition (PECVD) method is a typical example, but the metal organic chemical vapor deposition method described above is also used. Thermal CVD methods such as metal-organic chemical vapor deposition (MOCVD) or atomic layer deposition (ALD) may also be used.

[0123] In this embodiment, a glass substrate is used as the substrate 102, and a conductive film is formed on the substrate 102 to function as a gate electrode. As the conductive film 104, a tungsten film having a thickness of 100 nm is formed by sputtering.

[0124] The insulating films 106 and 107 that function as gate insulating films are formed by sputtering, PECVD, or the like. The film can be formed by a method such as a thermal CVD method, a vacuum deposition method, or a PLD method. Then, a silicon nitride film having a thickness of 400 nm is formed as the insulating film 106 by the PECVD method. Then, a silicon oxynitride film having a thickness of 50 nm is formed as the insulating film 107 .

[0125] The insulating film 106 may have a stacked structure of silicon nitride films. The insulating film 106 is made of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. A three-layer laminated structure with a silicon film can be formed. An example of the three-layer laminated structure is as follows: It can be formed as follows.

[0126] The first silicon nitride film is formed by, for example, silane at a flow rate of 200 sccm, PE-CV was performed using nitrogen at a flow rate of 100 sccm and ammonia gas at a flow rate of 100 sccm as source gases. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high frequency was generated. If a power of 2000 W is supplied using a frequency power supply and the thickness is formed to be 50 nm, good.

[0127] For the second silicon nitride film, silane at a flow rate of 200 sccm and 2000 sccm The PECVD equipment was operated using nitrogen at a flow rate of 2000 sccm and ammonia gas at a flow rate of 2000 sccm as raw material gases. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high frequency power supply A power of 2000 W may be supplied using a heater to form the film to a thickness of 300 nm.

[0128] The third silicon nitride film was formed using silane at a flow rate of 200 sccm and silane at a flow rate of 5000 sccm. The pressure in the reaction chamber was adjusted to 100 The thickness was measured by controlling the temperature to 50 Pa and supplying 2000 W of power using a 27.12 MHz high frequency power supply. It is sufficient to form it so that the thickness is 50 nm.

[0129] The first silicon nitride film, the second silicon nitride film, and the third silicon nitride film The substrate temperature during the formation can be 350° C. or less.

[0130] By forming the insulating film 106 as a three-layered structure of silicon nitride films, for example, the conductive film 10 When a conductive film containing copper (Cu) is used for 4, the following effects are achieved.

[0131] The first silicon nitride film can suppress the diffusion of copper (Cu) elements from the conductive film 104. The second silicon nitride film has the function of releasing hydrogen and functions as a gate insulating film. The third silicon nitride film can improve the breakdown voltage of the insulating film. The hydrogen released from the silicon nitride film is small, and the hydrogen released from the second silicon nitride film is diffused. can be suppressed.

[0132] The insulating film 107 is formed by the oxide semiconductor film 108 (more specifically, the first In order to improve the interface characteristics with the oxide semiconductor film 108a), It would be preferable if this could be done.

[0133] Next, a first oxide semiconductor film 108a is formed over the insulating film 107. A second oxide semiconductor film 108b is formed over the oxide semiconductor film 108a (see FIG. 4B). see).

[0134] In this embodiment, an In-Ga-Zn metal oxide target (In:Ga:Zn=3: A first oxide semiconductor film was formed by sputtering using a SiO 2 -SiO 3 (atomic ratio: 1:2). Then, in vacuum, an In-Ga-Zn metal oxide target (In:Ga:Zn =1:1:1.2 (atomic ratio)) by sputtering. Next, the oxide semiconductor film of the first layer is formed. A mask is formed on the oxide semiconductor film by a lithography process, and the oxide semiconductor film is applied to a desired region. By this process, the island-shaped oxide semiconductor film 108 is formed.

[0135] When the oxide semiconductor film 108 is formed by a sputtering method, a sputtering gas In this case, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is appropriately used. In the case of a mixed gas, it is preferable to increase the ratio of oxygen to rare gas. It is also necessary to increase the purity of the sputtering gas. For example, the oxygen used as the sputtering gas The dew point of the gas or argon gas is -40°C or less, preferably -80°C or less, more preferably By using gas that has been highly purified to temperatures below -100°C, and more preferably below -120°C, This can prevent moisture and the like from being taken into the oxide semiconductor film 108 as much as possible.

[0136] In addition, when the oxide semiconductor film 108 is formed by a sputtering method, a sputtering apparatus The chamber is designed to remove water and other impurities that may be present in the oxide semiconductor film 108 as much as possible. To remove the gas, a high vacuum (1×10) was created using an adsorption type vacuum pump such as a cryopump. -4 Pa to 5 x 10 -7 It is preferable to evacuate the gas to a temperature of about 100 Pa. A combination of a pump and a cold trap is used to extract gases, especially carbon or water, from the exhaust system into the chamber. It is preferable to prevent backflow of oxygen-containing gas.

[0137] Next, a source electrode and a drain electrode are formed over the insulating film 107 and the oxide semiconductor film 108a. Then, a conductive film 112 that functions as a conductive film is formed (see FIG. 4C).

[0138] In this embodiment, the conductive film 112 is a tungsten film having a thickness of 50 nm and a SiO 2 film having a thickness of 40 A laminated film in which a 0 nm thick aluminum film and a 10 nm thick aluminum film are laminated in this order is formed by sputtering. In this embodiment, the conductive film 112 has a two-layer stacked structure, but the present invention is not limited to this. For example, the conductive film 112 may be a tungsten film having a thickness of 50 nm and a 400 nm thick tungsten film having a thickness of 400 nm. A three-layer laminate structure consisting of a 100 nm thick aluminum film and a 100 nm thick titanium film stacked in sequence. You may do so.

[0139] Next, masks 140a and 140b are formed in desired regions on the conductive film 112 (FIG. 4(D) )reference).

[0140] In this embodiment, the masks 140a and 140b are formed by applying a photosensitive resin film. The photosensitive resin film is then patterned by a lithography process to form the film.

[0141] Next, etching gas 138 is used to remove the conductive film 112 and the masks 140a and 140b. Then, the conductive film 112 and the second oxide semiconductor film 108b are processed (see FIG. 5A).

[0142] In this embodiment, the conductive film 112 and the second acid are removed by using a dry etching apparatus. However, the method for forming the conductive film 112 is not limited to this. For example, by using a chemical solution as the etching gas 138, a wet etching apparatus can be used. The conductive film 112 and the second oxide semiconductor film 108b may be processed by using a device. Then, the conductive film 112 and the second oxide semiconductor film 108 were removed using a wet etching apparatus. Rather than processing the conductive film 112 and the second oxide semiconductor layer 113 using a dry etching apparatus, Processing the conductive film 108b is preferable because it allows for the formation of finer patterns. is.

[0143] Next, the masks 140a and 140b are removed, so that the second oxide semiconductor film 108b is left unremoved. The conductive film 112a serving as a source electrode of the second oxide semiconductor film 108b and the drain electrode of the second oxide semiconductor film 108b are A conductive film 112b serving as an in-electrode is formed. The oxide semiconductor film 108 has a stacked structure of a first oxide semiconductor film 108a and a second oxide semiconductor film 108b. (See FIG. 5(B)).

[0144] In addition, a chemical solution was sprayed onto the second oxide semiconductor film 108b and the conductive films 112a and 112b. The surface (on the back channel side) of the second oxide semiconductor film 108b may be cleaned by applying the solution. The cleaning method may be, for example, cleaning using a chemical solution such as phosphoric acid. By performing cleaning using a chemical solution, impurities attached to the surface of the second oxide semiconductor film 108b are removed. (For example, elements contained in the conductive films 112a and 112b) can be removed. However, the washing is not necessarily required, and in some cases washing may not be performed.

[0145] In addition, when forming the conductive films 112a and 112b and / or in the cleaning process, The oxide semiconductor film 108b has a second region thinner than the first oxide semiconductor film 108a. A region is formed.

[0146] Next, insulating films 114 and 112 are formed over the oxide semiconductor film 108 and the conductive films 112a and 112b. 6 is formed (see FIG. 5(C)).

[0147] After the insulating film 114 is formed, the insulating film 116 is successively formed without exposure to the air. After the insulating film 114 is formed, it is preferable to control the flow rate, pressure, and temperature of the source gas without exposing the insulating film 114 to the atmosphere. By adjusting one or more of the frequency power and the substrate temperature, the insulating film 116 is continuously formed. The concentration of impurities derived from atmospheric components can be reduced at the interface between the insulating film 114 and the insulating film 116. At the same time, oxygen contained in the insulating films 114 and 116 is transferred to the oxide semiconductor film 108. As a result, the amount of oxygen vacancies in the oxide semiconductor film 108 can be reduced.

[0148] For example, a silicon oxynitride film is formed as the insulating film 114 by using a PECVD method. In this case, the source gas may be a deposition gas containing silicon and an oxidizing gas. It is preferable to use the following gases. Typical examples of deposition gases containing silicon include silane, disilane, and the like. Examples of oxidizing gases include nitrous oxide, nitrous dioxide, etc. In addition, the oxidizing gas is more than 20 times but less than 100 times the deposition gas. The pressure in the treatment chamber is set to less than 100 Pa, preferably 40 times or more and 80 times or less. By using the PECVD method at a pressure of 50 Pa or less, the insulating film 114 contains nitrogen and The insulating film has a small number of defects.

[0149] In this embodiment, the insulating film 114 is formed by heating the substrate 102 at a temperature of 220°C. Silane at a flow rate of 50 sccm and dinitrogen monoxide at a flow rate of 2000 sccm were used as source gases. The pressure in the processing chamber was set to 20 Pa, and the high frequency power supplied to the parallel plate electrodes was set to 13.56 M. Hz, 100W (power density is 1.6 x 10 -2 W / cm 2 ) PECVD method A silicon oxynitride film is formed using the silicon oxynitride film.

[0150] The insulating film 116 is formed by depositing a substrate placed in a vacuum-evacuated processing chamber of a PECVD device. The temperature is kept at 180°C or higher and 350°C or lower, and the raw material gas is introduced into the processing chamber to increase the pressure in the processing chamber. is set to 100 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 200 Pa or less. , 0.17 W / cm to the electrode installed in the processing chamber 2 More than 0.5W / cm 2 Below are some more good ones: Preferably 0.25W / cm 2 More than 0.35W / cm 2 The following high frequency power supply conditions are met: In this way, a silicon oxide film or a silicon oxynitride film is formed.

[0151] The conditions for forming the insulating film 116 are as follows: a high frequency voltage of the above power density in a reaction chamber of the above pressure; By supplying power, the decomposition efficiency of the source gas in the plasma increases, and oxygen radicals increase. As the oxidation of the source gas progresses, the oxygen content in the insulating film 116 becomes higher than the stoichiometric composition. On the other hand, in the film formed at the above substrate temperature, the bonding strength between silicon and oxygen is As a result, the stoichiometric amount of oxygen in the film is reduced by the heat treatment in the subsequent process. Oxides that contain more oxygen than the stoichiometric composition and lose some of the oxygen when heated An insulating film can be formed.

[0152] The process of forming the insulating film 116 is carried out in a PECVD apparatus at a temperature of 180° C. to 350° C. The insulating film 116 is formed during the manufacturing process of the transistor 100. For example, the temperature for forming the insulating film 116 is set to 350° C. By implementing the method, it is possible to form the transistor 100 directly on a flexible substrate or the like. .

[0153] In the step of forming the insulating film 116, the insulating film 114 serves as a protection film for the oxide semiconductor film 108. Therefore, the power density can be reduced while reducing damage to the oxide semiconductor film 108. The insulating film 116 can be formed using high radio frequency power.

[0154] In the film formation conditions for the insulating film 116, a deposition gas containing silicon is mixed with an oxidizing gas. By increasing the flow rate of the gas, it is possible to reduce the number of defects in the insulating film 116. In the ESR measurement, the g value of 2.001, which is due to the dangling bond of silicon, The spin density of the signal is 6×10 17 spins / cm 3 Less than 3 x 10 17 spins / cm 3 Less than or equal to 1.5 × 10 17 spins / cm 3 The following is a missing An oxide insulating layer with fewer defects can be formed, resulting in improved reliability of the transistor. It can be done.

[0155] After the insulating films 114 and 116 are formed, heat treatment may be performed. This can reduce the amount of nitrogen oxide contained in the insulating films 114 and 116. By the heat treatment, part of oxygen contained in the insulating films 114 and 116 is transferred to the oxide semiconductor film 108. By this, the amount of oxygen vacancies in the oxide semiconductor film 108 can be reduced.

[0156] The temperature for the heat treatment of the insulating films 114 and 116 is typically 150° C. or higher and 350° C. or lower. Heat treatment is carried out in nitrogen, oxygen, or ultra-dry air (water content of 20 ppm or less, preferably air, preferably 1 ppm or less, more preferably 10 ppb or less), or a rare gas (argon, The above-mentioned nitrogen, oxygen, ultra-dry air, or rare gas atmosphere may be used. It is preferable that the gas does not contain hydrogen, water, etc. For the heat treatment, an electric furnace, an RTA device, etc. It can be used.

[0157] In this embodiment mode, heat treatment is performed in a nitrogen atmosphere at 350° C. for 1 hour. In the step of forming the transistor 100, the temperature at which the insulating film 116 is formed should be the highest. Alternatively, heat treatment at a temperature equivalent to the temperature at which the insulating film 116 is formed may be performed in a different step.

[0158] Next, an oxide conductive film 131 is formed over the insulating film 116 (see FIG. 5D).

[0159] The oxide conductive film 131 is made of oxygen and a metal (indium, zinc, titanium, aluminum, tantalum, etc.). at least one selected from the group consisting of tungsten, tantalum, and molybdenum; do.

[0160] Examples of the oxide conductive film 131 include a tantalum oxynitride film, a titanium oxide film, and an indium oxide film. Tin oxide (hereinafter also referred to as ITO) film, aluminum oxide film, oxide semiconductor film (e.g., I A GZO film (In:Ga:Zn=1:4:5 (atomic ratio)) can be used. The oxide conductive film 131 can be formed by a sputtering method. The thickness of the oxide conductive film 131 is 1 nm or more and 20 nm or less, or 2 nm or more and 10 nm or less. In this embodiment, the oxide conductive film 131 has a thickness of 50 nm or less. Indium tin oxide doped with silicon oxide (hereinafter referred to as ITSO) is used.

[0161] Next, the insulating films 114 and 116 and the oxide semiconductor film 108 are Oxygen 139 is added (see FIG. 6(A)).

[0162] The insulating films 114 and 116 and the oxide semiconductor film 108 are filled with oxygen through the oxide conductive film 131. The methods for adding 39 include ion doping, ion implantation, and plasma treatment. In addition, when adding oxygen 139, applying a bias to the substrate side can effectively increase the amount of oxygen. The element 139 can be added to the insulating films 114 and 116 and the oxide semiconductor film 108. The bias may be, for example, a power density of 1 W / cm 2 More than 5W / cm 2 If we do the following, By providing the oxide conductive film 131 over the insulating film 116 and adding oxygen, the oxide conductive film The insulating film 131 functions as a protective film that prevents oxygen from being released from the insulating film 116. Therefore, more oxygen can be added to the insulating films 114 and 116 and the oxide semiconductor film 108. can.

[0163] Next, the oxide conductive film 131 is removed by an etchant 142 (see FIG. 6B). .

[0164] The oxide conductive film 131 can be removed by dry etching or wet etching. or a method in which dry etching and wet etching are combined. In the case of dry etching, the etchant 142 is an etching gas. In the case of wet etching, the etchant 142 is a chemical liquid. In the second step, the oxide conductive film 131 is removed by wet etching.

[0165] Next, the insulating film 118 is formed on the insulating film 116 (see FIG. 6C).

[0166] Note that heat treatment is performed before or after the insulating film 118 is formed to form an insulating film. Excess oxygen contained in the films 114 and 116 is diffused into the oxide semiconductor film 108, and the oxide semiconductor Alternatively, the insulating film 118 can be formed by heating and filling the oxygen vacancies in the insulating film 108. By this, excess oxygen contained in the insulating films 114 and 116 is diffused into the oxide semiconductor film 108. As a result, oxygen vacancies in the oxide semiconductor film 108 can be filled.

[0167] When the insulating film 118 is formed by the PECVD method, the substrate temperature is set to 180° C. or more and 350° C. or less. This is preferable because it allows the formation of a dense film.

[0168] For example, when a silicon nitride film is formed as the insulating film 118 by the PECVD method, the silicon It is preferable to use a deposition gas containing carbon, nitrogen, and ammonia as the source gas. By using a small amount of ammonia compared to nitrogen, ammonia dissociates in the plasma and becomes active. The activated species react with silicon and hydrogen contained in the silicon-containing deposition gas. This breaks the silicon-nitrogen triple bond, promoting the bonding of silicon and nitrogen. To form a dense silicon nitride film with few bonds between silicon and hydrogen and few defects. On the other hand, if the amount of ammonia relative to nitrogen is large, the deposition gas containing silicon and Nitrogen decomposition does not progress, silicon and hydrogen bonds remain, defects increase, and roughness occurs. For these reasons, the source gas should be ammonia-free. The flow rate ratio of nitrogen to oxygen is preferably 5 or more and 50 or less, and more preferably 10 or more and 50 or less.

[0169] In this embodiment, the insulating film 118 is formed by depositing silane, nitrogen, and the like using a PECVD apparatus. A silicon nitride film with a thickness of 50 nm is formed from the source gases of hydrogen and ammonia. , silane 50sccm, nitrogen 5000sccm, ammonia 100sccm The pressure in the processing chamber was 100 Pa, the substrate temperature was 350°C, and a high frequency of 27.12 MHz was used. A high-frequency power of 1000 W is supplied to the parallel plate electrodes using a high-frequency power supply. The polar area is 6000 cm 2 It is a parallel plate type PECVD device, and the supplied power is measured as This translates to 1.7 x 10 power per area (power density). -1 W / cm 2 is.

[0170] Through the above steps, the transistor 100 shown in FIG. 1 can be formed.

[0171] <Method 2 for manufacturing semiconductor device> Next, a manufacturing method of the transistor 170 of one embodiment of the present invention will be described below with reference to FIGS. 7A to 7C are cross-sectional views illustrating a method for manufacturing a semiconductor device. 7A, 7C, 7E, and 7G show the structure of the transistor 170 in the channel length direction during fabrication. 7B, 7D, 7F, and 7H are cross-sectional views of the transistor 170 during fabrication. FIG. 1 is a cross-sectional view in the width direction of the panel.

[0172] First, the same steps as in the manufacturing method of the transistor 100 described above (the steps shown in FIGS. 4 to 6) were performed. ) is performed, and the conductive film 104, the insulating films 106 and 107, and the oxide semiconductor film 108 are formed on the substrate 102. , conductive films 112a and 112b and insulating films 114, 116, and 118 are formed (FIG. 7(A) )(see B)).

[0173] Next, a mask is formed on the insulating film 118 by a lithography process, and the insulating films 114 and 11 An opening 142c is formed in a desired region of the insulating film 118. A mask is formed by a film process, and the desired insulating films 106, 107, 114, 116, and 118 are formed. The openings 142a and 142b are formed in the conductive film 112. The openings 142a and 142b are formed so as to reach the conductive film 10 4 (see Figures 7(C) and (D)).

[0174] The openings 142a, 142b and the opening 142c may be formed in the same process or in different processes. The openings 142a, 142b and the opening 142c may be formed in the same process. When forming the mask, for example, a gray-tone mask or a half-tone mask may be used. The openings 142a and 142b may be formed in multiple steps. , the insulating films 106 and 107 are processed, and then the insulating films 114, 116 and 118 are processed.

[0175] Next, a conductive film 12 is formed on the insulating film 118 so as to cover the openings 142a, 142b, and 142c. 0 (see Figures 7(E) and (F)).

[0176] The conductive film 120 may be made of, for example, indium (In), zinc (Zn), or tin (Sn). In particular, the conductive film 120 may be made of a material containing one selected from the group consisting of: Indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide , indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Indium tin oxide (ITO), indium zinc oxide, indium stannate with silicon oxide A conductive material having light-transmitting properties, such as an ITSO (Insulator-Titanium Dioxide), can be used. The layer 120 can be formed by using, for example, a sputtering method. In this embodiment, an ITSO film having a thickness of 110 nm is formed by sputtering.

[0177] Next, a mask is formed on the conductive film 120 by a lithography process, and the conductive film 112 is By processing the conductive film 120a into the shape shown in FIG. 7(G) and FIG. 7(H), the conductive film 120a and the conductive film 120b are formed. ).

[0178] The conductive films 120a and 120b can be formed by dry etching or wet etching. Examples include a dry etching method, or a combination of dry etching and wet etching. In this embodiment, the conductive film 120 is formed by wet etching. The conductive films 120a and 120b are then processed.

[0179] Through the above steps, the transistor 170 shown in FIGS.

[0180] As described above, the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiments. They can be used in combination.

[0181] (Embodiment 2) In this embodiment, a structure of an oxide semiconductor included in a semiconductor device of one embodiment of the present invention will be described. A detailed explanation will be given below.

[0182] <Oxide semiconductor structure> Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconductor) uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous l Examples include amorphous oxide semiconductors, amorphous oxide semiconductors, and amorphous oxide semiconductors.

[0183] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxides. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC- Examples include OS, polycrystalline oxide semiconductor, and nc-OS.

[0184] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angle is flexible and the bond is short-range. This can also be described as a structure that has a high degree of order but no long-range order.

[0185] On the other hand, in the case of an essentially stable oxide semiconductor, it is possible to obtain a completely amorphous structure. It cannot be called an oxide semiconductor (isotropic amorphous). The oxide semiconductor is then oxidized to form a completely amorphous structure. However, a-like OS is a semiconductor that can be used in a microscopic area. Although it has a periodic structure, it has voids and is an unstable structure. It can be said that the physical properties are similar to those of an amorphous oxide semiconductor.

[0186] <caac-os> First, let me explain about CAAC-OS.

[0187] CAAC-OS is an oxide having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0188] Transmission Electron Microscope (TEM) A combined analysis image (high resolution) of the bright-field image and diffraction pattern of CAAC-OS was obtained by using a microscope. When observing a high-resolution TEM image, multiple pellets can be confirmed. On the other hand, high-resolution TEM images reveal the boundaries between pellets, i.e., grain boundaries. Therefore, the CAAC-OS is not clearly characterized by the grain boundaries. It can be said that the resulting decrease in electron mobility is unlikely to occur.

[0189] Below, we will explain the CAAC-OS observed by TEM. 1 shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction is required. The spherical aberration correction function was used to obtain high-resolution TEM images. , specifically referred to as a Cs-corrected high-resolution TEM image. Cs-corrected high-resolution TEM images can be obtained, for example, This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. It is possible.

[0190] An enlarged Cs-corrected high-resolution TEM image of region (1) in Figure 34(A) is shown in Figure 34(B). From Figure 34(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also referred to as the surface on which the film is to be formed). Or it reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0191] As shown in Figure 34(B), CAAC-OS has a characteristic atomic arrangement. ) shows the characteristic atomic arrangement with auxiliary lines. ) the size of each pellet can be 1 nm or more, or 3 nm or more. It can be seen that the size of the gap caused by the tilt between the sintered body and the pellet is about 0.8 nm. Therefore, the pellets can also be called nanocrystals (nc). CAAC-OS is also used for CANC (C-Axis Aligned Nanoclip). The semiconductor may also be referred to as an oxide semiconductor having metals.

[0192] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on the substrate 5120 were The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 34(D)). Between the pellets observed in FIG. 34(C), The portion where the tilt occurs corresponds to the area 5161 shown in FIG.

[0193] FIG. 35(A) shows the C of the plane of the CAAC-OS observed from a direction approximately perpendicular to the sample surface. s-corrected high-resolution TEM images are shown. Regions (1), (2), and (3) in Figure 35(A). ) are enlarged Cs-corrected high-resolution TEM images shown in Figure 35(B), Figure 35(C), and As shown in Figure 35(D), Figure 35(B), Figure 35(C) and Figure 35(D) show that the pellet It can be seen that the metal atoms are arranged in a triangular, quadrangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0194] Next, C analyzed by X-ray diffraction (XRD) For example, CAAC-O with InGaZnO4 crystals When S is subjected to structural analysis using the out-of-plane method, the results are as shown in Figure 36(A). As shown in the figure, a peak may appear at a diffraction angle (2θ) of around 31°. Since this is attributed to the (009) plane of the ZnO4 crystal, it is believed that the CAAC-OS crystal is c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0195] In addition, in the structural analysis of CAAC-OS using the out-of-plane method, 2θ is 31 In addition to the peak around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks in the vicinity indicate that some of the CAAC-OS crystals do not have a c-axis orientation. The more preferable CAAC-OS is a structure produced by the out-of-plane method. The analysis shows a peak at 2θ around 31°, but no peak at 2θ around 36°.

[0196] On the other hand, in-pla, X-rays are incident on the CAAC-OS from a direction almost perpendicular to the c-axis. When structural analysis is performed using the NE method, a peak appears at 2θ around 56°. This peak is due to I It is attributed to the (110) plane of the nGaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 5 The sample is fixed at approximately 6° and analyzed while rotating around the normal vector of the sample surface (φ axis). Even if a (φ scan) is performed, no clear peak appears as shown in Figure 36(B). On the other hand, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ When scanned, it is assigned to a crystal plane equivalent to the (110) plane as shown in Figure 36(C). Six peaks are observed. Therefore, from the structural analysis using XRD, CAAC-OS It can be seen that the orientation of the a-axis and b-axis is irregular.

[0197] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, the probe diameter is 300 nm parallel to the sample surface. When an electron beam is incident on the sample, a diffraction pattern (selected area transmission electron diffraction) as shown in FIG. This diffraction pattern may appear due to the presence of InGaZnO4 This includes spots due to the (009) plane of the crystal. The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis faces the surface to be formed or the upper surface. On the other hand, when the probe was applied to the same sample perpendicular to the sample surface, The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in Figure 37(B). 7(B), a ring-shaped diffraction pattern is confirmed. Therefore, electron diffraction It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. The first ring in FIG. 37(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and the like. This is thought to be due to the (110) surface.

[0198] As described above, CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the incorporation of impurities or the generation of defects, so the opposite view can be taken. Therefore, CAAC-OS can be considered an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0199] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon are more oxidative than metal elements that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0200] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0201] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Such an oxide semiconductor is a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. CAAC-OS has low impurity concentration and low defect level density. In other words, it has stable characteristics. It can be said that the oxide semiconductor has the following structure.

[0202] <nc-os> Next, we will explain nc-OS.

[0203] In the high-resolution TEM image, nc-OS has two distinct regions: one where crystals can be confirmed and the other where clear crystals can be confirmed. The crystalline part contained in nc-OS is The size is often between 1 nm and 10 nm, or more than 1 nm. The oxide semiconductor having a size of more than 10 nm and not more than 100 nm is called a microcrystalline oxide semiconductor. For example, in high-resolution TEM images, the grain boundaries of nc-OS are clearly visible. It should be noted that the nanocrystals may have the same origin as the pellets in CAAC-OS. Therefore, in the following, the crystalline part of nc-OS may be called a pellet. be.

[0204] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the layers. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. For example, in contrast to nc-OS, there are cases where it is difficult to distinguish the particles from the pellets. When X-rays are used, the peaks that indicate the crystal planes are In addition, for nc-OS, a probe diameter larger than the pellet (e.g., 50 When electron diffraction is performed using an electron beam of 1000 nm or more, a halo-like diffraction pattern is produced. On the other hand, for nc-OS, pellets with sizes close to or smaller than the pellets were observed. When nanobeam electron diffraction is performed using an electron beam with a lobe diameter, spots are observed. When nanobeam electron diffraction is performed on nc-OS, high brightness regions are observed in a circular (ring-like) pattern. In addition, multiple spots may be observed within a ring-shaped area. This may be the case.

[0205] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc -OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) The semiconductor may also be referred to as an oxide semiconductor having a structure (s).

[0206] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, in nc-OS, there is no regularity in the crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0207] <a-like OS> The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a semiconductor.

[0208] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystalline parts can be clearly seen, and areas where crystalline parts can be seen. and areas where it is not possible to

[0209] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0210] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS (hereinafter referred to as Sample B) and CAAC-OS (hereinafter referred to as Sample C) are prepared. Both samples are In-Ga-Zn oxides.

[0211] First, high-resolution cross-sectional TEM images of each sample are acquired. It can be seen that all the materials have crystalline parts.

[0212] The determination of which part is to be regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, six of which are stacked in layers in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The areas where the spacing is 0.28 nm or more and 0.30 nm or less are considered to be InGaZnO4 crystal parts. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0213] Figure 38 shows an example of investigating the average size of the crystal parts (22 to 45 locations) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystalline part of ke OS grows in size according to the cumulative amount of electron irradiation. Specifically, as shown by (1) in Figure 38, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was 4.2 × 10 8 e - / n m 2 On the other hand, in the nc-O For S and CAAC-OS, the cumulative electron irradiation dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystal part within the range of As shown in (2) and (3) in Figure 38, regardless of the cumulative electron dose, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. It can be seen that...

[0214] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in nc-OS and CAAC-OS, the growth of the crystals by electron irradiation is almost nonexistent. In other words, a-like OS is not as good as nc-OS and CAAC- It is clear that it has an unstable structure compared to the OS.

[0215] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal of the same composition. The density of the nc-OS is 78.6% or more and less than 92.3% of that of the normal crystal. The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0216] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It will be less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0217] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions may be used in any proportion. By combining single crystals with the desired composition, the density equivalent to that of a single crystal can be estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate by combining different types of single crystals.

[0218] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the above-mentioned compounds.

[0219] <Film formation model> An example of a film formation model for CAAC-OS and nc-OS will be described below.

[0220] FIG. 39(A) shows a process of forming a CAAC-OS film by sputtering. Schematic diagram of the inside of the membrane chamber.

[0221] The target 5130 is glued to a backing plate. A plurality of magnets are arranged at positions facing the target 5130 through the magnets. The magnetic field is generated by a number of magnets. The arrangement and configuration of the magnets are as described above. Please refer to the description of the film deposition chamber mentioned above. The ring method is called a magnetron sputtering method.

[0222] The target 5130 has a polycrystalline structure, and each grain contains a cleavage plane.

[0223] As an example, the cleavage surface of target 5130 having In-Ga-Zn oxide is described. FIG. 40(A) shows the crystal structure of InGaZnO4 contained in the target 5130. In addition, in FIG. 40(A), the c-axis is directed upward, and InGaZn This is the structure of an O4 crystal.

[0224] As shown in Figure 40(A), in two adjacent Ga-Zn-O layers, It can be seen that the oxygen atoms are arranged close to each other. By doing so, two adjacent Ga-Zn-O layers repel each other. The aZnO4 crystal has a cleavage plane between two adjacent Ga-Zn-O layers.

[0225] The substrate 5120 is disposed so as to face the target 5130, and the distance therebetween is d( The target-substrate distance (also called the TS distance) is preferably 0.01 m or more and 1 m or less. The thickness of the film deposition chamber is 0.02m or more and 0.5m or less. oxygen, argon, or a gas mixture containing 5% or more by volume of oxygen) and The pressure is controlled to 1 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. By applying a voltage above a certain level to the target 5130, a discharge begins and plasma is generated. It is confirmed that a high density plasma region is generated near the target 5130 by the magnetic field. In the high density plasma region, the deposition gas is ionized, and ions 5101 The ions 5101 are, for example, positive ions of oxygen (O + ) and argon cations ( Ar + ) etc.

[0226] The ions 5101 are accelerated toward the target 5130 by the electric field, and eventually At this time, flat or pellet-shaped sputter particles are ejected from the cleavage plane. The pellets 5100a and 5100b are separated and knocked out. The pellet 5100a and the pellet 5100b are formed by the impact of the collision of the ion 5101. distortion may occur.

[0227] The pellet 5100a is a flat plate or pellet having a triangular, for example, equilateral triangular, plane. The pellet 5100b is a sputtered particle having a hexagonal shape, for example, a regular hexagonal plane. The pellets 5100a and 5100b are sputtered particles in the form of plates or pellets. Sputter particles in the form of flat or pellets, such as pellets 5100b, are collectively called pellets. The planar shape of the pellet 5100 is not limited to a triangle or a hexagon, for example. For example, there are cases where the shape is made up of multiple triangles. In some cases, two squares (or polygons) may join together to form a quadrilateral (for example, a rhombus).

[0228] The thickness of the pellet 5100 is determined depending on the type of deposition gas, etc. The reason for this will be explained later. It is preferable that the thickness of the pellet 5100 is uniform. Thin pellets are preferable to thick cubes. The thickness of the PET 5100 is 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. The pellet 5100 has a width of 1 nm or more. 100 corresponds to the initial nucleus explained in (1) in FIG. 38. For example, In-Ga- When ions 5101 are bombarded onto a target 5130 having Zn oxide, the ions 5101 are collided with the target 5130. ) has three layers: Ga-Zn-O layer, In-O layer, and Ga-Zn-O layer. The pellet 5100 pops out. Note that FIG. 40(C) shows the pellet 5100 aligned along the c-axis. This is the structure when viewed from a parallel direction. Therefore, the pellet 5100 has two G A nano-sized sandwich structure with a-Zn-O layer (bread) and In-O layer (stuffing) It can also be called construction.

[0229] The pellet 5100 receives a charge as it passes through the plasma, causing the sides to become negative or The pellet 5100 has oxygen atoms on the side, and the oxygen atoms In this way, the sides can be charged with the same polarity, The loads repel each other, allowing the flat shape to be maintained. When S is an In-Ga-Zn oxide, the oxygen atoms bonded to the indium atoms are negatively charged. Or, the compound bonded to an indium atom, a gallium atom, or a zinc atom may The oxygen atoms may become negatively charged. Also, as the pellet 5100 passes through the plasma, When this happens, the atoms bond with indium, gallium, zinc, and oxygen, etc., and grow. This corresponds to the difference in size between (2) and (1) in Figure 38 above. Here, when the substrate 5120 is at room temperature, the pellet 5100 does not grow any further. As a result, it becomes nc-OS (see Figure 39(B)). Since the temperature at which film formation is possible is around room temperature, Therefore, even if the substrate 5120 has a large area, the nc-OS film can be formed. In order to grow 5100 in plasma, the film formation power in the sputtering method must be increased. It is effective to increase the film formation power to stabilize the structure of the pellet 5100. It is possible.

[0230] As shown in Figures 39(A) and 39(B), for example, the pellet 5100 is a plasma It flies like a kite through the air and flutters up to the top of the board 5120. Since the pellet 100 is electrically charged, it will be attracted to an area where other pellets 5100 are already deposited. Here, on the upper surface of the substrate 5120, a repulsive force is generated in a direction parallel to the upper surface of the substrate 5120. A horizontal magnetic field (also called a horizontal magnetic field) is generated between the substrate 5120 and the target 5120. Since a potential difference is applied between the substrate 5120 and the target 5130, Therefore, the pellet 5100 is on the upper surface of the substrate 5120. , and is subjected to a force (Lorentz force) due to the action of a magnetic field and an electric current. This can be understood using Gu's left-hand rule.

[0231] The pellet 5100 has a larger mass than an atom. In order to move the surface, it is important to apply some kind of force from the outside. One of these forces is It may be a force generated by the action of a magnetic field and an electric current. In order to increase the force, the upper surface of the substrate 5120 is The magnetic field is 10 G or more, preferably 20 G or more, more preferably 30 G or more, and more preferably Alternatively, it is preferable to provide an area where the resistance is 50 G or more. A magnetic field oriented parallel to the top surface of the plate 5120 is 1. 5 times or more, preferably 2 times or more, more preferably 3 times or more, and even more preferably 5 times or more. It is advisable to set up an area where

[0232] At this time, the magnet unit and / or the substrate 5120 move relatively. By rotating the substrate 5120, the direction of the horizontal magnetic field on the upper surface of the substrate 5120 continues to change. Therefore, on the upper surface of the substrate 5120, the pellet 5100 is subjected to forces in various directions. can be received and moved in various directions.

[0233] Also, when the substrate 5120 is heated as shown in FIG. 39(A), the pellet 510 0 and the substrate 5120, the resistance due to friction etc. is small. The pellet 5100 glides over the top surface of the substrate 5120. The transfer occurs with the flat surface facing the substrate 5120. When the particles reach the side of the pellet 5100, the sides are joined together. The oxygen atom on the side of 00 is released. The released oxygen atom causes the Since oxygen vacancies may be filled, a CAAC-OS with a low density of defect states is obtained. The temperature of the upper surface of the plate 5120 is, for example, 100°C or higher and lower than 500°C, or 150°C or higher and 450°C. The temperature may be less than 170°C and less than 400°C, or 170°C and more and 350°C and less. Therefore, it is possible to form a CAAC-OS film even when the substrate 5120 has a large area.

[0234] Furthermore, when the pellet 5100 is heated on the substrate 5120, the atoms are rearranged, The structural distortion caused by the collision of the ions 5101 is relaxed. Pellet 5100 becomes almost single crystal. Even if the 5100 is heated after bonding, the pellet 5100 itself hardly expands or contracts. Therefore, the gaps between the pellets 5100 widen, and the grain boundaries and other No defects or crevasses will form.

[0235] In addition, the CAAC-OS is not made of a single-crystal oxide semiconductor. The aggregates of pellets 5100 (nanocrystals) resemble bricks or blocks stacked on top of each other. In addition, there are no grain boundaries between them. Even if deformation such as shrinkage occurs in CAAC-OS due to subsequent heating or bending, local stress It is therefore possible to provide a flexible semi-conductor. The structure is suitable for semiconductor devices. nc-OS is a collection of pellets 5100 (nanocrystals). The resulting arrangement is like a chaotic pile of combined particles.

[0236] When the target is sputtered with ions, not only pellets but also zinc oxide etc. fly out. Since zinc oxide is lighter than the pellets, it may reach the top surface of the substrate 5120 first. And it reaches 0.1nm to 10nm, 0.2nm to 5nm, or 0. A zinc oxide layer 5102 having a thickness of 5 nm or more and 2 nm or less is formed. A cross-sectional schematic diagram is shown in FIG.

[0237] As shown in FIG. 41(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are deposited. The pellets 5105c are arranged so that their sides are in contact with each other. After being deposited on pellet 5105b, the pellet 510 slides on pellet 5105b. In another aspect of FIG. 05a, a plurality of particles 51 ejected from the target along with zinc oxide. The substrate 5120 is heated and crystallized to form a region 5105a1. The particles 5103 may include oxygen, zinc, indium, gallium, and the like.

[0238] As shown in FIG. 41(B), the region 5105a1 is assimilated with the pellet 5105a. The pellet 5105c has a side surface that is the same as that of the pellet 5105a. It is arranged so as to be in contact with another side surface of 105b.

[0239] Next, as shown in FIG. 41(C), a pellet 5105d is further added to the pellet 5105a2. After being deposited on pellet 5105a2 and pellet 5105b, It slides on the other side of the pellet 5105c. The pellet 5105e slides on the zinc oxide layer 5102.

[0240] As shown in FIG. 41(D), the pellet 5105d has a side surface similar to that of the pellet 51. The pellet 5105d is placed so that its side faces the pellet 5105a2. Also, the other side of the pellet 5105d is placed in contact with the other side of the pellet 5105c. At the surface, a plurality of particles 5103 that have been ejected from the target together with zinc oxide are deposited on the substrate 51. The film is crystallized by heating at 20 to form a region 5105d1.

[0241] As described above, the piled pellets are arranged so that they come into contact with each other, and the side surfaces of the pellets are Crystal growth occurs, forming a CAAC-OS on the substrate 5120. CAAC-OS has larger pellets than nc-OS. This corresponds to the difference in size between (3) and (2) in Figure 38.

[0242] In addition, the gaps between the 5100 pellets are extremely small, making it appear as if they were one large pellet. Large pellets may form. Large pellets have a single crystal structure. The pellet size, as viewed from the top, is 10 nm to 200 nm, 15 nm to 100 nm m or less, or 20 nm to 50 nm. If the channel formation area of ​​the pellet is smaller than that of the large pellet, the single crystal is used as the channel formation area. In addition, the pellets can be enlarged to allow for the formation of a region with a crystalline structure. The transistor has a channel forming region, a source region, and a drain region each having a single crystal structure. In some cases, a region can be used.

[0243] In this way, the channel formation region of the transistor and the like are formed in a region having a single crystal structure. By doing so, it may be possible to improve the frequency characteristics of the transistor.

[0244] Based on the above model, it is assumed that the pellet 5100 is deposited on the substrate 5120. Therefore, unlike epitaxial growth, if the surface on which the film is to be formed does not have a crystalline structure, It can be seen that CAAC-OS film formation is possible even in the case of a substrate 5120. Even if the structure of the top surface (surface to be formed) is amorphous (e.g., amorphous silicon oxide), It is possible to form an AC-OS film.

[0245] In addition, even if the upper surface of the substrate 5120 on which the formation is performed is uneven, the CAAC-OS It can be seen that the pellets 5100 are arranged along the shape of the substrate 5120. If the surface is atomically flat, the pellet 5100 will be placed on a flat surface that is parallel to the ab plane. Since the layers are aligned toward each other, a layer with uniform thickness, flatness, and high crystallinity is formed. By stacking these layers n times (n is a natural number), CAAC-OS can be obtained. Cut.

[0246] On the other hand, even if the upper surface of the substrate 5120 has irregularities, the CAAC-OS can be easily formed by the pellet 51 The structure is made up of n layers (n is a natural number) of 00 arranged side by side along the convex surface. Because the surface of the CAAC-OS is uneven, gaps tend to form between the pellets. However, intermolecular forces act between the pellets 5100, so even if there are irregularities, the pellets Therefore, even if there are irregularities, high crystallinity can be achieved. The CAAC-OS may have the following characteristics:

[0247] Therefore, CAAC-OS does not require laser crystallization and can be grown on large-area glass substrates. Even if the thickness is small, a uniform film can be formed.

[0248] Since the CAAC-OS film is formed using this model, the sputtered particles are distributed evenly across the film thickness. It is preferable that the sputtered particles are in the form of thick dices. In this case, the surface facing the substrate 5120 is not uniform, and the thickness and crystal orientation cannot be made uniform. There is.

[0249] The film formation model shown above allows for highly crystalline films to be formed even on a surface with an amorphous structure. Therefore, a CAAC-OS having the desired properties can be obtained.

[0250] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0251] (Embodiment 3) In this embodiment, a display device including the transistor described in the previous embodiment will be described. An example will be described below with reference to FIGS.

[0252] 8 is a top view showing an example of a display device. The display device 700 shown in FIG. A pixel portion 702 provided on the first substrate 701 and a source driver circuit provided on the first substrate 701 are connected to the pixel portion 702. The path section 704 and the gate driver circuit section 706, the pixel section 702, the source driver circuit section 7 704, and a seal material 712 arranged to surround the gate driver circuit section 706, and a second substrate 705 provided to face the first substrate 701. The substrate 701 and the second substrate 705 are sealed with a sealant 712. The pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are The first substrate 701, the sealant 712, and the second substrate 705 are sealed. Although not shown in the figure, a display element is provided between the first substrate 701 and the second substrate 705. .

[0253] The display device 700 is surrounded by a sealant 712 on the first substrate 701. The pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are provided in a region different from the region. FPC terminal parts 708 (FPC: Flexible Printed Circuit) electrically connected to the circuit parts 706 The FPC terminal section 708 is provided with a , FPC 716 is connected, and the pixel section 702 and the source driver circuit section Various signals are supplied to the pixel section 704 and the gate driver circuit section 706. 2, the source driver circuit section 704, the gate driver circuit section 706, and the FPC terminal section 70 8 are connected to signal lines 710. Various signals, etc., supplied by FPC 716 7, the pixel section 702, the source driver circuit section 704, the gate driver circuit section 706, and the like are connected to each other via a signal line 710. The power supply 704 is provided to a power supply circuit portion 706 and an FPC terminal portion 708 .

[0254] Furthermore, the display device 700 may be provided with a plurality of gate driver circuits 706. The device 700 includes a source driver circuit section 704 and a gate driver circuit section 706. Although an example in which the pixel portion 702 is formed on the same first substrate 701 is shown, the present invention is not limited to this configuration. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit etc. is formed (for example, A driving circuit board formed of a monocrystalline semiconductor film or a polycrystalline semiconductor film is mounted on a first substrate 701. The method of connecting the separately formed drive circuit board is not particularly limited. Instead of COG (Chip On Glass) method, wire bonding method, etc. can be used.

[0255] The display device 700 also includes a pixel section 702, a source driver circuit section 704, and a gate The driver circuit portion 706 includes a plurality of transistors. A transistor having a specific position can be applied.

[0256] The display device 700 can also include various elements, such as: Liquid crystal elements, EL (electroluminescence) elements (EL elements including organic and inorganic materials, Organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs) ED, etc.), transistors (transistors that emit light according to the current), electron-emitting elements, electron Ink, electrophoretic element, grating light valve (GLV), plasma display (PDP), display element using MEMS (microelectromechanical systems) Digital Micromirror Device (DMD), DMS (Digital MicroShutter) MIRASOL (registered trademark), IMOD (Interference Modulation shutter-type MEMS display elements, optical interference-type MEMS display elements, Using electrowetting elements, piezoelectric ceramic displays, and carbon nanotubes In addition to these, it has at least one electrical or magnetic function. Even if the display medium has a variable contrast, brightness, reflectance, transmittance, etc. depending on the use, An example of a display device using an EL element is an EL display. An example of a display device using an emission element is a field emission display (FED) ) or SED type flat panel display (SED: Surface-conduction Electron-emitter Displays (ELDs) are also available. An example of a display device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). LCD, reflective LCD, direct-view LCD, projection LCD An example of a display device using electronic ink or electrophoretic elements is an electronic pen. In addition, there are also other LCDs that can be used to realize semi-transmissive LCDs and reflective LCDs. In this case, a part or all of the pixel electrodes should function as a reflective electrode. For example, a part or the whole of the pixel electrode may contain aluminum, silver, etc. Furthermore, in this case, a memory circuit such as an SRAM may be provided under the reflective electrode. This makes it possible to further reduce power consumption.

[0257] The display method of the display device 700 may be a progressive method or an interlace method. In addition, the color elements controlled by pixels when displaying colors include R It is not limited to the three colors GB (R stands for red, G stands for green, B stands for blue). For example, It may be composed of four pixels: a pixel, a B pixel, and a W (white) pixel. As in the column, two colors of RGB make up one color element, and different two You can also select a color and configure it by adding one or more colors such as yellow, cyan, magenta, etc. to RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, but also to monochrome display devices. It can also be applied to a display device.

[0258] In addition, the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) uses white light ( In order to display full color on the display device, a colored layer (also called a color filter) is used. The colored layer may be, for example, red (R), green (G), blue (B) Yellow (Y) and other colors can be used in combination as appropriate. The color reproducibility can be improved compared to when no color layer is used. By arranging a region having a colored layer and a region not having a colored layer, the region not having a colored layer can be The white light in the region may be directly used for display. This reduces the decrease in brightness caused by the colored layer during bright display, reducing power consumption by 20%. However, it may be possible to reduce the light emission by about 30%. When using a device to display full color, R, G, B, Y, and white (W) are It is also possible to emit light from an element having a luminescent color. In some cases, power consumption can be reduced even further than when the

[0259] In this embodiment, a liquid crystal element and an EL element are used as display elements. 9 and 10. Note that FIG. 9 shows the relationship between the dashed line QR in FIG. 10 is a cross-sectional view of the display device shown in FIG. 1 is a cross-sectional view taken along dashed dotted line QR, and shows a configuration in which EL elements are used as display elements.

[0260] First, the common parts shown in Fig. 9 and Fig. 10 will be explained, and then the different parts will be explained. The following is an explanation.

[0261] <Explanation of common parts of display devices> The display device 700 shown in FIGS. 9 and 10 includes a wiring portion 711, a pixel portion 702, and The display panel 700 includes a source driver circuit section 704 and an FPC terminal section 708. The pixel portion 702 includes a transistor 750 and a capacitor 711. The source driver circuit portion 704 includes a transistor 752. do.

[0262] The transistors 750 and 752 may be the transistors shown above. can.

[0263] The transistor used in this embodiment is made of a highly purified oxide in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The transistor has a low current value in an off state (off-state current value). Therefore, the retention time of the electric signals such as the image signals can be extended, and the power supply When it is on, the write interval can be set longer. Therefore, the frequency of refresh operations can be reduced. This has the effect of reducing power consumption.

[0264] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed driving can be used in a liquid crystal display. By using this in a display device, the switching transistor in the pixel section and the driver circuit section can be In other words, the driver transistor can be formed on the same substrate as a separate driver circuit. Therefore, it is not necessary to use a semiconductor device formed from a silicon wafer or the like. The number of components can be reduced. By using a register, high quality images can be provided.

[0265] The capacitor 790 has a structure in which a dielectric is provided between a pair of electrodes. One electrode of the transistor 790 is a conductive film that functions as a gate electrode of the transistor 750. The other electrode of the capacitor 790 is formed using a conductive film formed in the same process as that of the transistor. A conductive film is used to function as a source electrode and a drain electrode of the transistor 750. The dielectric sandwiched between the electrodes functions as the gate insulating film of the transistor 750. An insulating film is used.

[0266] 9 and 10, a transistor 750, a transistor 752, and a capacitor Over the element 790, insulating films 764, 766, and 768, an oxide semiconductor film 767, and a planarizing insulating film A veneer 770 is provided.

[0267] The insulating films 764, 766, and 768 are the same as the insulating film 114 shown in the previous embodiment. , 116, 118 can be formed using the same materials and manufacturing methods. The oxide semiconductor film 767 may be formed using the same material as the oxide semiconductor film 108 described in the above embodiment. The planarization insulating film 770 can be formed by the same method as above. resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin Heat-resistant organic materials such as grease and epoxy resin can be used. The planarization insulating film 770 may be formed by stacking a plurality of insulating films formed from the same material. The planarization insulating film 770 may not be provided.

[0268] The signal line 710 is connected to the source and drain electrodes of the transistors 750 and 752. The signal line 710 is formed in the same process as the conductive film that functions as the transistor 75. 0, 752 source electrode and drain electrode, a conductive film formed in a different process, such as a gate The signal line 710 may be formed of a conductive film containing, for example, copper. When this material is used, there is little signal delay caused by wiring resistance, making it possible to display on a large screen. do.

[0269] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 71. 6. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed in the same process as the conductive film that functions as the drain electrode. The terminal of the PC 716 is electrically connected via an anisotropic conductive film 780 .

[0270] The first substrate 701 and the second substrate 705 may be made of, for example, glass. The first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. do.

[0271] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film. The distance (cell gap) between the first substrate 701 and the second substrate 705 is controlled. It should be noted that a spherical spacer may be used as the structure 778. In this embodiment, the structure 778 is provided on the first substrate 701 side. For example, a structure 778 may be provided on the second substrate 705 side, or Alternatively, the structure 778 may be provided on both the first substrate 701 and the second substrate 705. .

[0272] On the second substrate 705 side, there is a light-shielding film 738 that functions as a black matrix, A colored film 736 that functions as a color filter, a light-shielding film 738, and a film that contacts the colored film 736 An insulating film 734 is provided.

[0273] <Configuration example of a display device using a liquid crystal element as a display element> The display device 700 shown in FIG. 9 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 7 The conductive film 774 is disposed on the second substrate 705 side. The display device 700 shown in FIG. The alignment state of the liquid crystal layer 776 changes depending on the voltage applied to the conductive film 774. This allows light transmission or non-transmission to be controlled, making it possible to display an image.

[0274] The conductive film 772 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is connected to a conductive film that functions as a pixel electrode. The conductive film 772 functions as a reflective electrode, that is, one of the electrodes of the display element. The display device 700 shown in FIG. 9 uses external light and converts the light into a conductive film 772. This is a so-called reflective color liquid crystal display device that reflects and displays through the colored film 736.

[0275] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. A conductive film having a light-transmitting property in visible light can be used. For example, a material containing one of the elements selected from indium (In), zinc (Zn), and tin (Sn) As a conductive film that is reflective in visible light, for example, aluminum In this embodiment, the conductive film 772 may be formed using a material containing silver or silver. A conductive film that is reflective in visible light is used.

[0276] In addition, when a conductive film that is reflective to visible light is used as the conductive film 772, the conductive film The film may have a laminated structure. For example, an aluminum film having a thickness of 100 nm is formed as a lower layer, A 30 nm thick silver alloy film (e.g., an alloy film containing silver, palladium, and copper) is formed on the upper layer. The above-described structure provides the following excellent effects.

[0277] (1) The adhesiveness between the base film and the conductive film 772 can be improved. (2) The chemical solution This allows the aluminum film and the silver alloy film to be etched at the same time. The cross-sectional shape of the conductive film 772 can be made into a good shape (for example, a tapered shape). The reason for this is that the etching rate of aluminum films with chemicals is slower than that of silver alloy films. Or, after etching the upper silver alloy film, when the lower aluminum film is exposed, the silver alloy The electrons are taken from aluminum, which is a metal less noble than gold, in other words, a metal with a high tendency to ionize. The etching of the silver alloy film is suppressed by pulling out the film, and the etching of the underlying aluminum film is suppressed. This is because the progression is faster.

[0278] In the display device 700 shown in FIG. 9, a part of the planarization insulating film 770 of the pixel section 702 The unevenness is formed by forming the planarization insulating film 770 with an organic resin film or the like, for example. The reflective electrode can be formed by forming a reflective electrode on the surface of the organic resin film and providing irregularities on the surface of the organic resin film. The conductive film 772, which functions as a conductive film, is formed along the unevenness. When light enters the conductive film 772, the light can be diffused on the surface of the conductive film 772. This can improve visibility.

[0279] Although the display device 700 shown in FIG. 9 is an example of a reflective color liquid crystal display device, For example, the conductive film 772 may be a conductive film that transmits visible light. By using the same, a transmissive color liquid crystal display device can be obtained. In this case, the unevenness provided in the planarization insulating film 770 does not necessarily have to be provided.

[0280] Although not shown in FIG. 9, the conductive films 772 and 774 are Although not shown in FIG. 9, the polarizing section Optical members (optical substrates) such as a retardation member, a phase difference member, and an anti-reflection member may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. Lights, side lights, etc. may also be used.

[0281] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, The liquid crystals that can be used include polymer dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, the liquid crystal material can be in a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0282] In addition, when the in-plane switching method is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. Therefore, in order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent is used in a liquid crystal layer. It has a short response time and is optically isotropic. It also contains a liquid crystal that exhibits a blue phase and a chiral agent. The liquid crystal composition does not require alignment treatment and has little viewing angle dependency. Since the rubbing process is unnecessary, electrostatic breakdown caused by the rubbing process can be prevented. Therefore, defects and damage to the liquid crystal display device during the manufacturing process can be reduced. do.

[0283] When a liquid crystal element is used as a display element, a TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferrero) lectric Liquid Crystal) mode, AFLC (AntiFerr It can be used in dielectric liquid crystal mode. .

[0284] Furthermore, normally black type liquid crystal display devices, such as those employing vertical alignment (VA) mode, The vertical alignment mode may be a transmission type liquid crystal display device. For example, MVA (Multi-Domain Vertical Alignment) ) mode, PVA (Patterned Vertical Alignment) mode Mode, ASV mode, etc. can be used.

[0285] <Display device using light-emitting elements as display elements> The display device 700 shown in FIG. 10 includes a light-emitting element 782. The light-emitting element 782 is made of a conductive film 10 includes a light-emitting layer 784, an EL layer 786, and a conductive film 788. The EL layer 786 of the light element 782 emits light, thereby displaying an image. do.

[0286] The conductive film 784 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 784 is connected to a conductive film that functions as a pixel electrode. The conductive film 784 functions as an electrode, that is, one electrode of the display element. In this case, a conductive film that is light-transmitting or a conductive film that is reflective to visible light can be used. Examples of conductive films that are transparent to visible light include indium (In) and zinc (Zn). It is recommended to use a material containing one of the following elements: (Zn) and tin (Sn). As the reflective conductive film, for example, a material containing aluminum or silver is preferably used. stomach.

[0287] 10, an insulating film is formed on the planarization insulating film 770 and the conductive film 784. An insulating film 730 is provided. The insulating film 730 covers part of the conductive film 784. 782 has a top emission structure. Therefore, the conductive film 788 has a light transmitting property, and It transmits light emitted by the L layer 786. In this embodiment, the top emission The structure is exemplified, but is not limited to, for example, a bottom emission structure in which light is emitted to both the conductive film 784 and the conductive film 788; It can also be applied to al-emission structures.

[0288] A colored film 736 is provided at a position overlapping the light-emitting element 782, and a colored film 736 is provided at a position overlapping the insulating film 730. A light-shielding film 738 is provided in the position where the light-shielding film 738 is to be drawn, the wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. In addition, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 1, a configuration in which a colored film 736 is provided is exemplified. For example, when the EL layer 786 is formed by coloring, The film 736 may not be provided.

[0289] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0290] (Fourth embodiment) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0291] The display device shown in FIG. 11A has a region having pixels of a display element (hereinafter referred to as a pixel portion 502). ) and a circuit section ( hereinafter referred to as a drive circuit section 504), and a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 50 6) and a terminal portion 507. Note that the protection circuit 506 is not provided. That's fine.

[0292] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. When a part or all of the pixel portion 502 is not formed on the same substrate, the driving circuit A part or the whole of the path portion 504 is COG or TAB (Tape Automated Bearing). It can be implemented by

[0293] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The display device has a circuit for driving a plurality of display elements (hereinafter referred to as pixel circuit 501), The path section 504 is a circuit (hereinafter referred to as a gate driver) that outputs a signal (scanning signal) for selecting a pixel. 504a), for supplying signals (data signals) for driving the display elements of the pixels. The source driver 504b includes a driving circuit such as the circuit (hereinafter referred to as a source driver 504b).

[0294] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is inputted through the terminal section 507, and a signal for outputting the shift register is outputted. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc. The gate driver 504a receives a scanning signal and outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 504a are provided, and the plurality of gate drivers 504a drive the scanning lines GL_1 to Alternatively, the gate driver 504a may control the GL_X by dividing it into the initialization signal However, the gate driver 50 has a function of supplying 4a may also provide other signals.

[0295] The source driver 504b includes a shift register and the like. Through the terminal section 507, signals for driving the shift register as well as the source of the data signal are transmitted. The source driver 504b receives a signal (image signal) that is to be output from the pixel circuit The source driver 504b has a function of generating a data signal to be written to the source driver 501. A data signal is generated in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of a data signal. The data lines DL_1 to DL_Y are connected to the data lines DL_2 through DL_Y. Alternatively, the source driver 504b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b may also supply other signals. It is possible.

[0296] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a plurality of analog switches, The image signal can be time-divided and output as a data signal. The source driver 504b may be configured using the same.

[0297] Each of the plurality of pixel circuits 501 is connected to one of the plurality of scanning lines GL to which a scanning signal is applied. A pulse signal is input via the data line DL, and a data signal is given via one of the data lines DL. A data signal is input to each of the pixel circuits 501. 504a controls writing and holding of data of the data signal. The second pixel circuit 501 is connected to a gate driver GL_m (where m is a natural number equal to or less than X) via a scanning line GL_m. A pulse signal is input from 504a, and the data line DL_n ( A data signal is input from the source driver 504b via the input terminal 504a (n is a natural number equal to or less than Y).

[0298] The protection circuit 506 shown in FIG. 11A is, for example, a gate driver 504a and a pixel circuit 5 01. Alternatively, the protection circuit 506 is connected to the scanning line GL, which is the wiring between the source driver The data line DL is connected between the driver 504b and the pixel circuit 501. The protection circuit 506 can be connected to the wiring between the gate driver 504a and the terminal section 507. Alternatively, the protection circuit 506 may be formed by wiring between the source driver 504b and the terminal section 507. The terminal section 507 can be connected to a power supply and a line from an external circuit to the display device. This refers to the part where terminals for inputting control signals and image signals are provided.

[0299] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit 506 This is a circuit that brings one wire into electrical continuity with another wire.

[0300] As shown in FIG. 11A, a pixel section 502 and a driver circuit section 504 are provided with a protection circuit 50. 6, ESD (Electro Static Discharge: This can improve the resistance of the display device to overcurrents caused by electrostatic discharges and the like. However, the configuration of the protection circuit 506 is not limited to this. For example, A configuration in which a protection circuit 506 is connected, or a configuration in which the protection circuit 506 is connected to the source driver 504b Alternatively, a configuration in which a protection circuit 506 is connected to the terminal portion 507 may be used. It can also be done as follows.

[0301] In FIG. 11(A), the gate driver 504a and the source driver 504b Therefore, although an example in which the driver circuit portion 504 is formed is shown, the present invention is not limited to this configuration. For example, only the gate driver 504a is formed, and a separately prepared source driver circuit is formed. A substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is implemented. It may also be configured to be equipped with

[0302] 11(A)。 In addition, the plurality of pixel circuits 501 shown in FIG. 11(A) may be, for example, the configuration shown in FIG. 11(B). It can be said that:

[0303] The pixel circuit 501 shown in FIG. 11B includes a liquid crystal element 570, a transistor 550, and a capacitor. The transistor 550 may be any of the transistors described in the previous embodiments. can be applied.

[0304] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 included in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. One of the electrodes may be given a different potential.

[0305] For example, the display device including the liquid crystal element 570 can be driven in a TN mode, an STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned Mode) Micro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid Crystal id Crystal) mode, AFLC (AntiFerroelectric Li Quid Crystal) mode, MVA mode, PVA (Patterned Ve Vertical Alignment mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode may also be used. In addition to the above-mentioned driving method, the display device can also be driven by an ECB (Electric Carrier Board) or the like. Ally Controlled Birefringence mode, PDLC (P Polymer Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest However, there are various types of liquid crystal elements and their driving methods, and they are not limited to these. A variety of materials can be used.

[0306] In the pixel circuit 501 in the mth row and the nth column, the source electrode or the drain electrode of the transistor 550 One of the electrodes is electrically connected to the data line DL_n, and the other is connected to a pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the other of the electrodes of the scan line G. L_m. The transistor 550 can be turned on or off. This provides a function of controlling the writing of data signals.

[0307] One of the pair of electrodes of the capacitor 560 is connected to a wiring to which a potential is supplied (hereinafter, a potential supply line VL ) and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

[0308] For example, in a display device having the pixel circuit 501 of FIG. 11(B), The pixel circuits 501 in each row are sequentially selected by the gate driver 504a shown in FIG. 550 is turned on and data of the data signal is written.

[0309] The pixel circuit 501 in which data has been written is turned off by turning off the transistor 550. By repeating this process for each row, an image can be displayed.

[0310] Furthermore, the plurality of pixel circuits 501 shown in FIG. 11(A) may be, for example, a configuration shown in FIG. 11(C). It can be said that:

[0311] The pixel circuit 501 shown in FIG. 11C includes transistors 552 and 554 and a capacitor. The transistor 552 and the transistor 554 The transistor described in the above embodiment can be used for either one or both of the above. .

[0312] One of the source and drain electrodes of the transistor 552 is supplied with a data signal. The transistor 55 is electrically connected to a wiring (hereinafter referred to as a signal line DL_n). The gate electrode 2 is electrically connected to the wiring to which the gate signal is given (hereinafter referred to as the scanning line GL_m). are connected to the network.

[0313] Transistor 552 is turned on or off to transfer the data of the data signal. It has the function of controlling the writing of data.

[0314] One of the pair of electrodes of the capacitor 562 is connected to a wiring to which a potential is applied (hereinafter, a potential supply line VL _a), and the other is electrically connected to the source electrode and drain electrode of the transistor 552. The second electrode is electrically connected to the other of the first and second electrodes.

[0315] The capacitor 562 functions as a storage capacitor for holding written data.

[0316] One of the source electrode and the drain electrode of the transistor 554 is connected to the potential supply line VL_a. Furthermore, the gate electrode of transistor 554 is electrically connected to the It is electrically connected to the other of the source electrode and the drain electrode.

[0317] One of the anode and cathode of the light emitting element 572 is electrically connected to the potential supply line VL_b. The other is electrically connected to the other of the source electrode and drain electrode of the transistor 554. will be done.

[0318] The light emitting element 572 may be, for example, an organic electroluminescence element (also known as an organic EL element). However, the light emitting element 572 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0319] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0320] In a display device having the pixel circuit 501 of FIG. 11(C), for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written by turning it on.

[0321] The pixel circuit 501 to which the data has been written is turned off by turning off the transistor 552. Furthermore, the transistor 554 is held in a holding state in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 The light is emitted at a brightness that corresponds to the flow rate. By repeating this process row by row, an image can be displayed.

[0322] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0323] (Embodiment 5) In this embodiment, a display module and an electronic device including a semiconductor device according to one embodiment of the present invention will be described. This will be explained with reference to FIGS. 12 and 13.

[0324] The display module 8000 shown in FIG. 12 includes an upper cover 8001 and a lower cover 8002. Between them, touch panel 8004 connected to FPC8003 and Display panel 8006, backlight 8007, frame 8009, printed circuit board 801 0, has battery 8011.

[0325] The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0326] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel The shape and dimensions can be changed as needed to fit the size of the 8006.

[0327] The touch panel 8004 is a resistive or capacitive touch panel. The display panel 8006 can be used by overlapping it with the opposing substrate (sealing substrate). It is also possible to provide the display panel 8 with a touch panel function. It is also possible to provide an optical sensor in each pixel of 006 to make it an optical touch panel.

[0328] The backlight 8007 has a light source 8008. In FIG. Although the configuration in which the light source 8008 is disposed on the base 8007 has been illustrated, the present invention is not limited to this. For example, a light source 8008 is arranged at the end of a backlight 8007, and a light diffusion plate is further used. In addition, when a self-luminous light emitting element such as an organic EL element is used, or when a reflective In the case of a flat panel or the like, the backlight 8007 may not be provided.

[0329] The frame 8009 has a function of protecting the display panel 8006 and also a function of preventing the movement of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the The frame 8009 may also function as a heat sink.

[0330] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. This can be omitted if a commercial power source is used.

[0331] In addition, the display module 8000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may also be provided in addition.

[0332] 13(A) to 13(G) are diagrams showing electronic devices. These electronic devices are housed in a housing. A body 9000, a display unit 9001, a speaker 9003, operation keys 9005 (power switch, includes an operation switch), a connection terminal 9006, a sensor 9007 (force, displacement, position, speed, Acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electricity Measures field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared It may have a microphone 9008, etc.

[0333] The electronic devices shown in FIGS. 13A to 13G can have various functions. For example, functions to display various information (still images, videos, text images, etc.) on the display, Touch panel function, calendar, date or time display function, various software ( It has the function of controlling processing by using a program, wireless communication function, and various functions using wireless communication function. Functions for connecting to computer networks, transmitting various data using wireless communication functions, or receiving the program or data recorded on the recording medium, and It is to be noted that the functions shown in FIGS. 13(A) to 13(G) can be implemented. The functions that the electronic device shown in the figure can have are not limited to these, and it may have various functions. Although not shown in FIGS. 13A to 13G, the electronic device may include: The electronic device may have a plurality of display units. The function to take pictures, take videos, and save the images to a recording medium (external or built-in to the camera) ) and a function to display the captured image on the display unit.

[0334] The electronic devices shown in FIGS. 13A to 13G will be described in detail below.

[0335] FIG. 13A is a perspective view showing a mobile information terminal 9100. The display portion 9001 is flexible. The display unit 9001 can be incorporated along the screen. It is equipped with a touch panel, and can be operated by touching the screen with a finger or a stylus. By touching the icon displayed on the display 9001, the application can be started. can.

[0336] 13B is a perspective view showing a portable information terminal 9101. For example, the device has one or more functions selected from a telephone, a notebook, an information viewing device, etc. Specifically, it can be used as a smartphone. Although the speaker 9003, the connection terminal 9006, the sensor 9007, etc. are omitted in the illustration, It can be installed in the same position as the mobile information terminal 9100 shown in FIG. The information terminal 9101 can display text and image information on multiple surfaces. For example, Three operation buttons 9050 (also called operation icons or simply icons) are displayed on the display unit 900. 9051 shown in a dashed rectangle can be displayed on one side of the display unit 90. 01. An example of the information 9051 is an e-mail A display that notifies you of incoming calls, SNS (social networking services), etc. , subject of email or SNS, sender name of email or SNS, date and time, time, The remaining battery level, antenna reception strength, etc. Or, information 9051 is displayed. In place of the information 9051, an operation button 9050 or the like may be displayed.

[0337] 13C is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 is , and has the function of displaying information on three or more surfaces of the display unit 9001. An example is shown in which information 9053 and information 9054 are displayed on different sides. The user of the portable information terminal 9102 stores the portable information terminal 9102 in the breast pocket of his / her clothes. In this state, the display (information 9053 in this case) can be confirmed. The telephone number or name of the caller is displayed in a position that can be observed from above the mobile information terminal 9102. The user can view the display without taking the mobile information terminal 9102 out of his pocket. You can check the call and decide whether to accept it or not.

[0338] 13(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The 9200 is suitable for mobile phone calls, e-mail, document browsing and writing, music playback, and internet communications. It is possible to run various applications such as computer games. The display surface of the display unit 9001 is curved, and the display is performed along the curved display surface. In addition, the portable information terminal 9200 can perform short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, handset The mobile information terminal 9200 also has a connection terminal 9006. It has a connector and can directly exchange data with other information terminals. Charging can also be performed via the connection terminal 9006. It may also be possible to supply power wirelessly without going through 6.

[0339] 13(E), (F), and (G) are perspective views showing a foldable portable information terminal 9201. FIG. 13(E) is a perspective view of the portable information terminal 9201 in an unfolded state, and FIG. (F) shows the mobile information terminal 9201 being changed from one of the unfolded state and the folded state to the other. 13(G) is a perspective view of the portable information terminal 9201 in a folded state. The portable information terminal 9201 is highly portable when folded, and is easily portable when unfolded. When the display is turned on, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 01 is made up of three housings 9000 connected by hinges 9055. The two housings 9000 are supported by the hinge 9055. This allows the portable information terminal 9201 to be reversibly transformed from an unfolded state to a folded state. For example, the portable information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less. It can be done.

[0340] The electronic device described in this embodiment has a display unit for displaying some information. However, the semiconductor device of one embodiment of the present invention is an electronic device that does not have a display portion. The present invention can also be applied to the display unit of the electronic device described in this embodiment. In the case of a display device, it is possible to use a flexible display device that can display information along a curved display surface, or a folding display device. Although a foldable display unit has been exemplified, the present invention is not limited to this. A display may be provided on the surface.

[0341] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done. [Example]

[0342] In this example, analytical samples of specimens A1 to A3 were prepared. SIMS analysis was carried out.

[0343] First, the analytical sample prepared in this example will be described below.

[0344] (Samples A1 to A3) First, an oxide semiconductor film having a thickness of 100 nm was formed on a glass substrate having a thickness of 0.7 mm. Note that Sample A1, Sample A2, and Sample A3 have different compositions of the oxide semiconductor films. .

[0345] The oxide semiconductor film of Sample A1 was prepared by using a gas having a substrate temperature of 170° C. and a flow rate of 100 sccm. Argon gas and oxygen gas at a flow rate of 100 sccm were introduced into the chamber, and the pressure was set to 0.6 Polycrystalline metal oxide sputtering targets with Pa The target (In:Ga:Zn=1:1:1.2 [atomic ratio]) was irradiated with 2500W AC Electric power was applied to form a film.

[0346] The oxide semiconductor film of Sample A2 was prepared by using a gas having a substrate temperature of 170° C. and a flow rate of 100 sccm. Argon gas and oxygen gas at a flow rate of 100 sccm were introduced into the chamber, and the pressure was set to 0.6 The sputtering target was a polycrystalline metal oxide (In:Ga:Zn=3:1: 2 [atomic ratio]) and an AC power of 2500 W was applied to form the film.

[0347] The oxide semiconductor film of Sample A3 was prepared by using a gas having a substrate temperature of 170° C. and a flow rate of 100 sccm. Argon gas and oxygen gas at a flow rate of 100 sccm were introduced into the chamber, and the pressure was set to 0.6 The sputtering target was a polycrystalline metal oxide (In:Ga:Zn=4:2: The film was formed by applying 2500 W of AC power to a sample with a 4.1 atomic ratio.

[0348] Next, a heat treatment was carried out at 450°C for 1 hour in a nitrogen atmosphere. This was followed by a heat treatment at 450°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen. In this example, in order to reduce the hydrogen concentration in the oxide semiconductor film, The samples were heat-treated, but in the actual transistor manufacturing process, the heat treatment was performed at 350°C or less. It is preferable to process it.

[0349] Through the above steps, samples A1 to A3 of this example were fabricated.

[0350] Next, in order to measure the hydrogen concentrations in the oxide semiconductor films of Samples A1 to A3 fabricated as described above, The analysis results of samples A1 to A3 are shown in FIG. 4, the vertical axis is the hydrogen concentration (atoms / cm 3 ) and the horizontal axis represents the depth (nm), respectively. Represents.

[0351] From the results shown in FIG. 14, the hydrogen concentration in the oxide semiconductor film of Sample A1 was 6.33×10 1 9 atoms / cm 3 The hydrogen concentration in the oxide semiconductor film of Sample A2 was 8. 64×10 18 atoms / cm 3 In addition, the hydrogen in the oxide semiconductor film of Sample A3 The concentration is 1.46 x 10 19 atoms / cm 3 In addition, the oxide semiconductor The hydrogen concentration in the film was measured at a film thickness of 50 nm.

[0352] For example, by forming the oxide semiconductor film of Sample A1 on the oxide semiconductor film of Sample A2, , IGZO film (In:Ga:Zn=3:1:2)\IGZO film (In:Ga:Zn=1: Alternatively, the oxide semiconductor film of Sample A1 is formed on the oxide semiconductor film of Sample A3. By forming a semiconductor film, IGZO film (In:Ga:Zn=4:2:4.1)\IGZ The structure is an O film (In:Ga:Zn=1:1:1.2).

[0353] As described above, the semiconductor device according to one embodiment of the present invention has a stacked-layer structure including oxide semiconductor films. It is preferable to form the oxide semiconductor film so that the hydrogen concentration of the oxide semiconductor film above the oxide semiconductor film is higher than that of the oxide semiconductor film. In addition, the atomic ratio of In in the lower oxide semiconductor film is greater than the atomic ratio of Ga, and The atomic ratio of In in the upper oxide semiconductor film is smaller than that in the lower oxide semiconductor film. By using a stacked structure of oxide semiconductor films, it is possible to obtain high field-effect mobility and high reliability. The semiconductor device can be a semiconductor device having high conductivity.

[0354] The configuration shown in this embodiment may be used in appropriate combination with other embodiments or other embodiments. good. [Example]

[0355] In this example, hydrogen and water are released from an insulating film included in a semiconductor device according to one embodiment of the present invention. The amount of insulating material in the semiconductor device of one embodiment of the present invention was evaluated by TDS. The defects that become carrier traps in the film were evaluated using ESR. prepared the following samples B1 to B4 and samples C1 to C4.

[0356] First, the details of Samples B1 to B4 will be described.

[0357] <Sample B1> Sample B1 has a structure in which a silicon nitride film with a thickness of 100 nm is formed on a glass substrate. do.

[0358] The conditions for forming the silicon nitride film of sample B1 were a substrate temperature of 350° C. and a flow rate of 200 silane gas at a flow rate of 2000 sccm, nitrogen gas at a flow rate of 100 sccm, and Ammonia gas was introduced into the chamber, the pressure was set to 100 Pa, and the pressure was set to 100 Pa. The film was formed by supplying RF power of 2000 W between the electrodes of the parallel plates placed on the substrate.

[0359] <Sample B2> Sample B2 has a structure in which a silicon nitride film with a thickness of 100 nm is formed on a glass substrate. .

[0360] The conditions for forming the silicon nitride film of sample B2 were as follows: ammonia gas flow rate of 2000 sc The silicon nitride film was formed at a temperature of 1000 K. The conditions other than the flow rate of the ammonia gas were the same. The sample was the same as sample B1.

[0361] <Sample B3> Sample B3 has a structure in which a silicon oxynitride film with a thickness of 200 nm is formed on a glass substrate. be.

[0362] For the film formation conditions of the silicon oxynitride film of Sample B3, the substrate temperature was 350 °C, and a flow rate of 2 0 sccm of silane gas and 3000 sccm of dinitrogen monoxide gas were introduced into the chamber and the pressure was set to 40 Pa. 10 00 W of RF power was supplied between the parallel plate electrodes installed in the PECVD apparatus to form the film.

[0363] <Sample B4> Sample B4 has a structure in which a silicon oxynitride film with a thickness of 200 nm is formed on a glass substrate and there is.

[0364] For the film formation conditions of the silicon oxynitride film of Sample B4, RF power was set to 100 W to form a silicon oxynitride film. Regarding the conditions other than RF power, they were the same as those of Sample B3 and it was.

[0365] <TDS Measurement> Next, TDS measurements were performed on Samples B1 to B4 prepared above. In the TDS measurement , each sample was heated from 50 °C to 550 °C, and the amount of gas released from the insulating film in each sample was evaluated. In Samples B1 and B2, the amount of hydrogen released from the silicon nitride film was evaluated. Regarding the amount of hydrogen released, the amount of gas released corresponding to a mass-to-charge ratio (M / z) of 2 was measured. Also, in Samples B3 and B4, the amount of H2O released from the silicon oxynitride film was evaluated. Regarding the amount of H2O released, the amount of gas released corresponding to a mass-to-charge ratio (M / z) of 18 was measured. In Fig. 15(A), the TDS measurement results of Sample B1 are shown, in Fig. 15(B) the TDS measurement

[0366] results of Sample B2 are shown, in Fig. 16(A) the TDS measurement results of Sample B3 are shown, and in Fig. 16(B) the TDS measurement results of Sample B4 are shown. results of Sample B4 are shown in Fig. 16(B). The measurement results are shown in Figs. 15(A)(B) and 16(A)(B). The vertical axis represents the intensity (arbitrary unit) and the horizontal axis represents the substrate temperature (°C).

[0367] From the results shown in Figure 15(A)(B), it can be seen that the hydrogen It was found that a silicon nitride film with a low emission amount could be formed.

[0368] From the results shown in Figures 16(A) and 16(B), it can be seen that increasing the RF power reduces the amount of water released. It was found that a thin silicon oxynitride film could be formed.

[0369] Next, samples C1 to C4 will be described in detail.

[0370] <Sample C1> Sample C1 has a structure in which a silicon nitride film with a thickness of 100 nm is formed on a glass substrate. .

[0371] The conditions for forming the silicon nitride film of sample C1 were a substrate temperature of 350° C. and a flow rate of 200 silane gas at a flow rate of 2000 sccm, nitrogen gas at a flow rate of 100 sccm, and Ammonia gas was introduced into the chamber, the pressure was set to 100 Pa, and the chamber was placed in the PECVD device. A RF power of 2000 W was supplied between the parallel plate electrodes to form the film.

[0372] <Sample C2> Sample C2 has a structure in which a silicon nitride film with a thickness of 100 nm is formed on a glass substrate. .

[0373] The conditions for forming the silicon nitride film of sample C2 were a substrate temperature of 280° C. and a flow rate of 100 silane gas at a flow rate of 1000 sccm, nitrogen gas at a flow rate of 50 sccm, and A monia gas was introduced into the chamber, the pressure was set to 100 Pa, and 750 W of RF power was supplied between the parallel plate electrodes installed in the PECVD apparatus to form a film. It was formed by supplying 750 W of RF power between the parallel plate electrodes installed in the PECVD apparatus.

[0374] <Sample C3> Sample C3 has a structure in which a silicon oxynitride film with a thickness of 100 nm is formed on a glass substrate. There is.

[0375] As the film formation conditions for the silicon oxynitride film, the substrate temperature was set to 280 °C, and silane gas with a flow rate of 50 sccm and dinitrogen monoxide gas with a flow rate of 1250 sccm were introduced into the chamber. The pressure was set to 20 Pa, and 750 W of RF power was supplied between the parallel plate electrodes installed in the PECVD apparatus to form a film. The pressure was set to 20 Pa, and 750 W of RF power was supplied between the parallel plate electrodes installed in the PECVD apparatus to form a film. It was formed by supplying power.

[0376] <Sample C4> Sample C4 has a structure in which a silicon oxynitride film with a thickness of 100 nm is formed on a glass substrate. There is.

[0377] As Sample C4, under the film formation conditions of the silicon oxynitride film of Sample C3, RF power was set to 2 50 W, and a silicon oxynitride film was formed. Regarding the conditions other than RF power, they were the same as those of Sample C3. It was the same as Sample C3.

[0378] <ESR measurement> Next, ESR measurements were performed on Samples C1 to C4 prepared above. The ESR measurement uses the equation g = hν / βH0 from the value of the magnetic field (H0) at which microwave absorption occurs at a predetermined temperature to obtain a parameter called the g value. Here, ν is the frequency of the microwave. h is the Planck constant, and β is the Bohr magneton, both of which are constants. It is a constant, and β is the Bohr magneton, both of which are constants.

[0379] For Samples C1 and C2, ESR measurements were performed under the following conditions. The measurement temperature was room temperature (25°C), the high frequency power (microwave power) of 9.2 GHz was set to 0.1 mW, and the magnetic The direction of the field was parallel to the film surface of the fabricated sample. The detection limit for the spin density of the signal due to enter is 1.5 × 10 16 spins / cm 3 It was.

[0380] For samples C3 and C4, ESR measurements were performed under the following conditions: (25°C), and the 9.2 GHz high frequency power (microwave power) was set to 0.005 mW. The direction of the magnetic field was parallel to the film surface of the prepared sample. The detection limit for the spin density of the signal due to the E'-center is 1.5 × 10 16 s pins / cm 3 It was.

[0381] FIG. 17 shows ESR spectra obtained by measuring the ESR of samples C1 and C2. Figure 18 shows the ESR spectra obtained by measuring the ESR of samples C3 and C4. be.

[0382] As shown in Figure 17, sample C1 exhibited a higher K-center-induced oxidative stress than sample C2. It can be seen that the intensity of the signal is small. This defect is caused by dangling bonds of silicon. By applying a higher temperature and a higher RF power, the dangling bonds of silicon are reduced. It was found that a silicon nitride film could be formed without any problem.

[0383] As shown in Figure 18, sample C3 exhibited a larger increase in the E'-center than sample C4. As shown in Figure 18, the E'-center is These defects are caused by dangling bonds of silicon. By supplying a higher RF power, the dangling bonds of silicon are reduced, and oxynitride is formed. It was found that a silicon dioxide film could be formed.

[0384] The configuration shown in this embodiment may be used in appropriate combination with other embodiments or other embodiments. good. [Example]

[0385] In this example, a transistor corresponding to the transistor 170 shown in FIG. The ID-VG characteristics of the transistor were evaluated. Samples D1 to D3 were prepared and evaluated. Samples D1 and D2 are comparative examples. The sample D3 is a sample having a transistor according to one embodiment of the present invention. In addition, samples D1 to D3 each have a channel length L of 2 μm and a channel width A transistor with W=50 μm and a transistor with channel length L=3 μm and channel width W=50 μm A total of three types of transistors were used: a 1000-V transistor with a channel length of L = 6 μm and a channel width of W = 50 μm. This is a structure in which a star is formed.

[0386] The sample prepared in this example will be described below. The description will be given using the reference numerals attached to the transistor 170 shown in FIG.

[0387] <Method for preparing sample D1> First, a conductive film 104 was formed on a substrate 102. A glass substrate was used as the substrate 102. The conductive film 104 was a tungsten film having a thickness of 100 nm, which was deposited by sputtering. The film was formed using a magnetron sputtering device.

[0388] Next, insulating films 106 and 107 were formed on the substrate 102 and the conductive film 104. As the layer 6, a silicon nitride film having a thickness of 400 nm was formed using a PECVD apparatus. The insulating film 107 is a silicon oxynitride film having a thickness of 50 nm, which is grown using a PECVD apparatus. It was formed by

[0389] The conditions for forming the insulating film 106 were a substrate temperature of 350° C. and a flow rate of 200 sccm. Run gas, nitrogen gas with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 100 sccm The pressure was set to 100 Pa, and the parallel flat plate installed in the PECVD device was A 2000 W RF power was supplied between the electrodes of the plate to form a silicon nitride film with a thickness of 50 nm. Next, the flow rate of ammonia gas was changed to 2000 sccm, and a nitride silicon layer with a thickness of 300 nm was formed. Then, the flow rate of ammonia gas was changed to 100 sccm to form a silicon film with a thickness of 50 A silicon nitride film with a thickness of nm was deposited.

[0390] The conditions for forming the insulating film 107 are a substrate temperature of 350° C. and a flow rate of 20 sccm. Silane gas at a flow rate of 3000 sccm and nitrous oxide gas at a flow rate of 3000 sccm were introduced into the chamber. The pressure was set to 40 Pa, and a 100 W RF voltage was applied between the parallel plate electrodes installed in the PECVD device. A force was applied to form the film.

[0391] Next, an oxide semiconductor film 108 was formed over the insulating film 107. A single layer of IGZO film was formed using a sputtering system. An IGZO film having a thickness of 35 nm was formed as the oxide semiconductor film 108. The film formation conditions were a substrate temperature of 170°C, argon gas at a flow rate of 100 sccm, and Oxygen gas was introduced into the chamber at a rate of 100 sccm, and the pressure was set to 0.6 Pa. Metal oxide sputtering target (In:Ga:Zn=1:1:1.2 [atomic ratio] ) was supplied with 2500 W of AC power to form a film.

[0392] Next, a first heat treatment was carried out at 450° C. for 1 hour in a nitrogen atmosphere. This was followed by a heat treatment at 450°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen. Ta.

[0393] Next, conductive films 112a and 112b are formed over the insulating film 107 and the oxide semiconductor film 108. The conductive films 112a and 112b were made of a tungsten film having a thickness of 50 nm and a SiO 2 film having a thickness of 400 nm. nm thick aluminum film and 100 nm thick titanium film were deposited using a sputtering device. The layers were formed successively in a vacuum.

[0394] Next, an insulating film was formed over the insulating film 107, the oxide semiconductor film 108, and the conductive films 112a and 112b. The insulating film 114 and the insulating film 116 were formed. The insulating film 114 was a 50 nm thick oxynitride film. The silicon film was formed using a PECVD apparatus. A silicon oxynitride film having a thickness of 1000 nm was formed using a PECVD apparatus. The insulating film 4 and the insulating film 116 were formed successively in a vacuum using a PECVD apparatus.

[0395] The conditions for forming the insulating film 114 were a substrate temperature of 220° C. and a silica flow rate of 50 sccm. Nitrogen gas and nitrous oxide gas at a flow rate of 2000 sccm were introduced into the chamber, and the pressure was increased to 2 The pressure was set to 0 Pa, and 100 W of RF power was applied between the parallel plate electrodes installed in the PECVD device. The insulating film 116 was formed under the conditions of a substrate temperature of 220° C. and a flow rate of 1000 kJ / cm. Silane gas at a flow rate of 160 sccm and nitrous oxide gas at a flow rate of 4000 sccm were introduced into the chamber. The pressure was set to 200 Pa, and the gas was introduced into the chamber between the parallel plate electrodes installed in the PECVD device. The film was formed by supplying RF power of 1500 W to the substrate.

[0396] Next, a second heat treatment was carried out at 350° C. in a nitrogen gas atmosphere. It was set to one hour.

[0397] Next, the following two steps were carried out.

[0398] (1, ITSO film formation process) An ITSO film having a thickness of 5 nm was formed on the insulating film 116 using a sputtering device. The conditions for forming the ITSO film were: the substrate temperature was room temperature, and the flow rate of argon gas was 72 sccm. The pressure was set to 0.15 Pa, and oxygen gas with a flow rate of 5 sccm was introduced into the chamber. A metal oxide target (In2O3:SnO2:SiO2) was placed in the sputtering system. 2 = 85:10:5 [wt %]) and a DC power of 1000 W was supplied to form the film.

[0399] (2. Oxygen addition treatment process) Next, oxygen was introduced into the oxide semiconductor film 108 and the insulating films 114 and 116 through the ITSO film. The oxygen addition treatment was carried out using an ashing device, with the substrate temperature set at 40°C. Oxygen gas was introduced into the chamber at a flow rate of 250 sccm, the pressure was set to 15 Pa, and the base A bias was applied to the plate side between the parallel plate electrodes installed in the ashing device. RF power of 4500 W was supplied for 600 seconds.

[0400] Next, the substrate temperature was set to 350°C and heat treatment was performed in a nitrogen atmosphere of 175 Pa. An insulating film 118 was formed on the film. The insulating film 118 was a silicon nitride film having a thickness of 100 nm. The film was formed using a PECVD apparatus.

[0401] Next, an opening 142c reaching the conductive film 112b and an opening 142b reaching the conductive film 104 are formed. The openings 142a, 142b, and 142c were formed by dry etching. The film was formed using a chipping apparatus.

[0402] Next, a conductive film is formed on the insulating film 118 so as to cover the openings 142a, 142b, and 142c. The conductive film was then processed to form conductive films 120a and 120b. , 120b is formed by using a sputtering device to form an ITSO film with a thickness of 100 nm. The composition of the target used for the ITSO film was the same as that used in the ITSO film formation process described above. The composition was the same as that of the previous one.

[0403] Next, a third heat treatment was carried out at 250° C. in a nitrogen gas atmosphere. It was set to one hour.

[0404] The sample D1 of this example was fabricated through the above steps. The temperature was 450°C.

[0405] <Method for preparing sample D2> Sample D2 differs from Sample D1 in the following steps. The same as in sample D1.

[0406] In sample D2, the first heat treatment was not performed.

[0407] In addition, in (2, oxygen addition treatment step) of sample D2, the oxygen addition treatment time was 120 s Next, the ITSO film was removed to expose the insulating film 116. The removal method is to use a wet etching device and a 5% oxalic acid solution. After etching for 300 seconds, the specimen was washed with 0.5% hydrofluoric acid for 15 minutes. Etching was performed for sec.

[0408] Next, an insulating film 118 was formed on the insulating film 116 without performing a heat treatment.

[0409] Sample D2 of this example was fabricated through the above steps. The temperature was 350°C.

[0410] <Method for preparing sample D3> Sample D3 differs from Sample D1 in the following steps. The same as in sample D1.

[0411] In Sample D3, the oxide semiconductor film 108 is formed on the conductive film 104 which functions as a gate electrode. a first oxide semiconductor film 108a on the side of the first oxide semiconductor film 108a and a second oxide semiconductor film 108b on the first oxide semiconductor film 108a. The first oxide semiconductor film 108a was formed by stacking a first oxide semiconductor film 108b and a second oxide semiconductor film 108c. Then, a 10 nm thick IGZO film is formed as the second oxide semiconductor film 108b. nm thick IGZO film was formed.

[0412] The first oxide semiconductor film 108a was formed under the following conditions: a substrate temperature of 170° C. Argon gas at a flow rate of 100 sccm and oxygen gas at a flow rate of 100 sccm were introduced into the chamber. The pressure was set to 0.6 Pa, and a polycrystalline metal oxide sputtering target (In: The film was formed by applying 2500 W of AC power to a Ga:Zn=4:2:4.1 (atomic ratio). .

[0413] The second oxide semiconductor film 108b was formed under the following conditions: a substrate temperature of 170° C. Argon gas at a flow rate of 100 sccm and oxygen gas at a flow rate of 100 sccm were introduced into the chamber. The pressure was set to 0.6 Pa, and a polycrystalline metal oxide sputtering target (In: The film was formed by applying 2500 W of AC power to a Ga:Zn=1:1:1.2 (atomic ratio). .

[0414] Furthermore, the first heat treatment was not performed on sample D3.

[0415] In addition, in (2, oxygen addition treatment step) of sample D3, the oxygen addition treatment time was 120 s Next, the ITSO film was removed to expose the insulating film 116. The removal method is to use a wet etching device and a 5% oxalic acid solution. After etching for 300 seconds, the specimen was washed with 0.5% hydrofluoric acid for 15 minutes. Etching was performed for sec.

[0416] Next, an insulating film 118 was formed on the insulating film 116 without performing a heat treatment.

[0417] Sample D3 of this example was fabricated through the above steps. The temperature was 350°C.

[0418] Next, the ID-VG characteristics of the samples D1 to D3 prepared above were measured. The ID-VG characteristics of sample D3 are shown in FIGS. 19 to 21. Note that FIG. 19 shows the ID-VG characteristics of sample D1. 20 shows the ID-VG characteristics of sample D1, and FIG. 21 shows the ID-VG characteristics of sample D2. 19 to 21 show the ID-VG characteristic results of sample D3. The horizontal axis represents D(A), and the horizontal axis represents VG(V). A) shows the ID-VG characteristics of a transistor with a channel length L=2 μm and a channel width W=50 μm. (B) shows the performance results of a transistor with a channel length L=3 μm and a channel width W=50 μm. (C) shows the ID-VG characteristics of the MOSFET with a channel length of L=6 μm and a channel width of W=50 μm. This shows the ID-VG characteristics of a 1000-μm transistor.

[0419] In addition, the conductive film 104 serving as the first gate electrode of the transistor 170 is A voltage (hereinafter also referred to as gate voltage (VG)) and a conductive layer that functions as a second gate electrode. The voltage (VBG) applied to the conductive film 120b is set to 0.25V from −15V to +20V. The voltage applied to the conductive film 112a functioning as the source electrode was (hereinafter referred to as source voltage (VS)) is set to 0V (common), and the drain electrode The voltage applied to the conductive film 112b that functions as a drain voltage (hereinafter also referred to as drain voltage (VD)) was set to 1V or 10V.

[0420] From the results shown in Figures 19 to 21, it is possible to reduce the maximum temperature in the process from 450°C to 350°C. It was confirmed that there was no significant difference in the ID-VG characteristics of the transistor even when the temperature was lowered to In addition, compared with Sample D2, Sample D3 has improved electrical characteristics by using a stacked structure of oxide semiconductor films. The variation is reduced. In addition, the on-state current is improved and the S value (subth Thus, the semiconductor device according to one embodiment of the present invention has a low threshold swing value. The device was found to have excellent electrical properties.

[0421] Next, the reliability of the samples D1 to D3 was evaluated. A bias-thermal stress test (hereinafter referred to as a GBT test) was used.

[0422] In this example, the GBT test conditions were a gate voltage (VG) of ±30 V and a drain voltage of ±10 V. The on-chip voltage (VD) and source voltage (VS) are set to 0V (COMMON), and the stress temperature is set to 60 The temperature was set to °C, the stress application time was set to 1 hour, and the measurement environment was set to a dark environment and a light irradiation environment (white L The experiment was carried out in two environments: one with a 10000lx light source and the other with a 10000lx light source. The source electrode and drain electrode of the transistor are set to the same potential, and the gate electrode is connected to the source electrode and drain electrode. A potential different from that of the gate electrode was applied for a certain period of time (here, 1 hour). When the applied potential is higher than the potential of the source electrode and the drain electrode, it is considered a positive stress. When the potential applied to the gate electrode is lower than the potential of the source electrode and drain electrode, it is called a negative Therefore, in accordance with the measurement environment, plus GBT stress (dark), Negative GBT stress (dark), positive GBT stress (light exposure), and negative G Reliability evaluation was carried out under a total of four conditions of BT stress (light irradiation).

[0423] The GBT test results for samples D1 to D3 are shown in FIG. 22. In FIG. 22, the vertical axis represents the The change in the threshold voltage (ΔVth) and the change in the shift value (ΔShift) of the transistor are The horizontal axis indicates the sample name, process conditions, etc. The drain current (ID)-gate voltage (VG) characteristic of a transistor is expressed as a logarithm. The maximum slope of the tangent to the in-current (ID) is 1×10 -12 The gate voltage at the intersection with the A axis (V G). Also, ΔShift is the amount of change in the Shift value.

[0424] From the results shown in FIG. 22, it can be seen that the sample D2 has a smaller change in threshold voltage (Δ On the other hand, sample D3 according to one embodiment of the present invention had a Vth of about three times that of the conventional sample D1. The change in threshold voltage (ΔVth) was about twice that of sample D1. Even if the maximum temperature is reduced from 450°C to 350°C, the oxide semiconductor film can be formed into a stacked structure. It was confirmed that this can suppress the decline in reliability.

[0425] Next, samples D1 to D3 were subjected to a positive gate BT stress test (Dark +GBT) and negative gate BT stress test (Dark -GBT) are alternately repeated. The amount of change in threshold voltage was measured when the transistor was The D-VG characteristics were measured (initial). Then, a positive gate BT stress test and a The gate BT stress test was performed twice, alternating between the gates. The test was conducted at a stress temperature of 60°C and a stress time of 3600 seconds. The measurements were carried out on a transistor with a channel length L=6 μm and a channel width W=50 μm.

[0426] FIG. 23 shows the results of the samples D1 to D3 before the stress test (initial) and after each test. The vertical axis in FIG. 23 represents the threshold voltage after the drain BT stress test. The horizontal axis shows the stress test name. Also, Figure 23 shows the results before the stress test (initial) and after the positive gate BT stress test. After stress test (+GBT), after negative gate BT stress test (-GBT), after positive gate BT After stress test (+GBT), then after negative gate BT stress test (-GBT). These are the results of GBT tests conducted on both.

[0427] Here, the positive gate BT stress test and the negative gate BT stress test are alternately performed. When the threshold voltage value increases and decreases alternately, The change in threshold voltage due to the trapping and detrapping of carriers into the trap levels On the other hand, if the change in threshold voltage is biased in one direction (e.g. For example, if there is a tendency for the capacitance to gradually increase or decrease, the capacitance is It is speculated that this is due to the threshold voltage fluctuation caused by the rear behaving as a fixed charge.

[0428] From the results shown in Figure 23, the threshold voltage of the transistor after each gate BT stress test is Compared with sample D2, sample D3 according to one embodiment of the present invention has a smaller amount of change in threshold voltage. It can be seen that...

[0429] As described above, one embodiment of the present invention is a transistor that can be fabricated at a low process temperature, like the transistor of Sample D3. However, by using a stacked structure of oxide semiconductor films, reliability can be improved and variations in electrical characteristics can be reduced. It has excellent electrical properties, including suppression of noise, improvement of on-state current, and low S value. was shown.

[0430] The configuration shown in this embodiment may be used in appropriate combination with other embodiments or embodiments. It is possible. [Example]

[0431] In this example, a transistor corresponding to the transistor 170 shown in FIG. The ID-VG characteristics of the transistor were evaluated. Samples E1 and E2 were fabricated and evaluated. Sample E1 is a comparative example of a transistor. Sample E1 is a sample having a transistor according to one embodiment of the present invention, and Sample E2 is a sample having a transistor according to one embodiment of the present invention. In addition, the sample E1 and the sample E2 each have a channel length L=2 μm and a channel width W=50 μm. A transistor with a channel length L=3 μm and a channel width W=50 μm. A total of three types of transistors were formed, each with a channel length of L = 6 μm and a channel width of W = 50 μm. The three types of transistors are mounted on one of three substrates. 40 pieces were formed on each substrate.

[0432] The sample prepared in this example will be described below. The description will be given using the reference numerals attached to the transistor 170 shown in FIG.

[0433] <Preparation method of sample E1> First, a conductive film 104 was formed on a substrate 102. A glass substrate was used as the substrate 102. The glass substrate size was 600mm x 720mm and the thickness was 0.7mm. The conductive film 104 was a tungsten film having a thickness of 100 nm, which was deposited by sputtering. The film was formed using a magnetron sputtering device.

[0434] Next, insulating films 106 and 107 were formed on the substrate 102 and the conductive film 104. As the layer 6, a silicon nitride film having a thickness of 400 nm was formed using a PECVD apparatus. The insulating film 107 is a silicon oxynitride film having a thickness of 50 nm, which is grown using a PECVD apparatus. It was formed by

[0435] The conditions for forming the insulating film 106 were a substrate temperature of 350° C. and a flow rate of 200 sccm. Run gas, nitrogen gas with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 100 sccm The pressure was set to 100 Pa, and the parallel flat plate installed in the PECVD device was A 2000 W RF power was supplied between the electrodes of the plate to form a silicon nitride film with a thickness of 50 nm. Next, the flow rate of ammonia gas was changed to 2000 sccm, and a nitride silicon layer with a thickness of 300 nm was formed. Then, the flow rate of ammonia gas was changed to 100 sccm to form a silicon film with a thickness of 50 A silicon nitride film with a thickness of nm was deposited.

[0436] The conditions for forming the insulating film 107 are a substrate temperature of 350° C. and a flow rate of 20 sccm. Silane gas at a flow rate of 3000 sccm and nitrous oxide gas at a flow rate of 3000 sccm were introduced into the chamber. The pressure was set to 40 Pa, and a 100 W RF voltage was applied between the parallel plate electrodes installed in the PECVD device. A force was applied to form the film.

[0437] Next, the oxide semiconductor film 108 was formed over the insulating film 107. The first oxide semiconductor film 108a on the conductive film 104 side functioning as a gate electrode and the first oxide semiconductor film 108b on the conductive film 104 side functioning as a gate electrode are The second oxide semiconductor film 108b was formed on the oxide semiconductor film 108a. As the first oxide semiconductor film 108a, an IGZO film having a thickness of 10 nm was formed. As the nitride semiconductor film 108b, an IGZO film having a thickness of 15 nm was formed.

[0438] The first oxide semiconductor film 108a was formed under the following conditions: a substrate temperature of 170° C. Argon gas at a flow rate of 140 sccm and oxygen gas at a flow rate of 60 sccm were introduced into the chamber. The pressure was set to 0.6 Pa, and a polycrystalline metal oxide sputtering target (In:G The film was formed by applying 2500 W of AC power to a mixture of aluminum and zinc (Al:Zn=4:2:4.1 [atomic ratio]).

[0439] The second oxide semiconductor film 108b was formed under the following conditions: a substrate temperature of 170° C. Argon gas at a flow rate of 100 sccm and oxygen gas at a flow rate of 100 sccm were introduced into the chamber. The pressure was set to 0.6 Pa, and a polycrystalline metal oxide sputtering target (In: The film was formed by applying 2500 W of AC power to a Ga:Zn=1:1:1.2 (atomic ratio). .

[0440] Next, a first heat treatment was carried out at 450° C. for 1 hour in a nitrogen atmosphere. This was followed by a heat treatment at 450°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen. Ta.

[0441] Next, conductive films 112a and 112b are formed over the insulating film 107 and the oxide semiconductor film 108. The conductive films 112a and 112b were made of a tungsten film having a thickness of 50 nm and a SiO 2 film having a thickness of 400 nm. nm thick aluminum film and 100 nm thick titanium film were deposited using a sputtering device. The layers were formed successively in a vacuum.

[0442] Next, an insulating film was formed over the insulating film 107, the oxide semiconductor film 108, and the conductive films 112a and 112b. The insulating film 114 and the insulating film 116 were formed. The insulating film 114 was a 50 nm thick oxynitride film. The silicon film was formed using a PECVD apparatus. A silicon oxynitride film having a thickness of 1000 nm was formed using a PECVD apparatus. The insulating film 4 and the insulating film 116 were formed successively in a vacuum using a PECVD apparatus.

[0443] The conditions for forming the insulating film 114 were a substrate temperature of 220° C. and a silica flow rate of 50 sccm. Nitrogen gas and nitrous oxide gas at a flow rate of 2000 sccm were introduced into the chamber, and the pressure was increased to 2 The pressure was set to 0 Pa, and 100 W of RF power was applied between the parallel plate electrodes installed in the PECVD device. The insulating film 116 was formed under the conditions of a substrate temperature of 220° C. and a flow rate of 1000 kJ / cm. Silane gas at a flow rate of 160 sccm and nitrous oxide gas at a flow rate of 4000 sccm were introduced into the chamber. The pressure was set to 200 Pa, and the gas was introduced into the chamber between the parallel plate electrodes installed in the PECVD device. The film was formed by supplying RF power of 1500 W to the substrate.

[0444] Next, a second heat treatment was carried out at 350° C. in a nitrogen gas atmosphere. It was set to one hour.

[0445] Next, the following three steps were carried out.

[0446] (1, ITSO film formation process) An ITSO film having a thickness of 5 nm was formed on the insulating film 116 using a sputtering device. The conditions for forming the ITSO film were: the substrate temperature was room temperature, and the flow rate of argon was 72 sccm. Gas and oxygen gas at a flow rate of 5 sccm were introduced into the chamber, and the pressure was set to 0.15 Pa. A metal oxide target (In2O3:SnO2:Si) was placed in the sputtering system. The film was formed by supplying 1000 W of DC power to a mixture of 1000 W and 1000 W of O2 (85:10:5 [wt %]).

[0447] (2. Oxygen addition treatment process) Next, oxygen was introduced into the oxide semiconductor film 108 and the insulating films 114 and 116 through the ITSO film. The oxygen addition treatment was carried out using an ashing device, with the substrate temperature set at 40°C. Oxygen gas was introduced into the chamber at a flow rate of 250 sccm, the pressure was set to 15 Pa, and the base A bias was applied to the plate side between the parallel plate electrodes installed in the ashing device. RF power of 4500 W was supplied for 120 seconds.

[0448] (3, ITSO film removal process) Next, the ITSO film was removed to expose the insulating film 116. A wet etching device was used, and a 5% oxalic acid solution was used for etching. After etching for 15 seconds, 0.5% hydrofluoric acid was used. I performed the patching.

[0449] Next, an insulating film 118 was formed on the insulating film 116. The insulating film 118 had a thickness of 100 The insulating film 118 was formed by using a PECVD apparatus. The substrate temperature in the PECVD apparatus was set to 350°C.

[0450] Next, an opening 142c reaching the conductive film 112b and an opening 142b reaching the conductive film 104 are formed. The openings 142a, 142b, and 142c were formed by dry etching. The film was formed using a chipping apparatus.

[0451] Next, a conductive film is formed on the insulating film 118 so as to cover the openings 142a, 142b, and 142c. The conductive film was then processed to form conductive films 120a and 120b. , 120b is formed by using a sputtering device to form an ITSO film with a thickness of 100 nm. The composition of the target used for the ITSO film was the same as that used in the ITSO film formation process described above. The composition was the same as that of the previous one.

[0452] Next, a third heat treatment was carried out at 250° C. in a nitrogen gas atmosphere. It was set to one hour.

[0453] The sample E1 of this example was fabricated through the above steps. The temperature was 450°C.

[0454] <Preparation method of sample E2> Sample E2 differs from Sample E1 in the following steps. The same as in sample E1.

[0455] In sample E2, the first heat treatment was not performed.

[0456] The sample E2 of this example was fabricated through the above steps. The temperature was 350°C.

[0457] Next, the ID-VG characteristics of the prepared samples E1 and E2 were measured. The ID-VG characteristics of sample E2 are shown in FIGS. 24 and 25. Note that FIG. 24 shows the ID-VG characteristics of sample E1. 25 shows the ID-VG characteristics of sample E1. In Figures 24 and 25, the first vertical axis represents ID (A) and the second vertical axis represents μFE (cm 2 / Vs ) and the horizontal axis represents VG(V). Also, in Figs. 24 and 25, (A) represents ,ID-VG characteristic results of a transistor with channel length L=2μm and channel width W=50μm (B) is the I of a transistor with a channel length L = 3 μm and a channel width W = 50 μm. The D-VG characteristic results are shown in (C), where the channel length L is 6 μm and the channel width W is 50 μm. 24 and 25 show the ID-VG characteristics of the transistor. A total of 10 transistor characteristics are displayed overlapping each other.

[0458] In addition, the conductive film 104 serving as the first gate electrode of the transistor 170 is A voltage (hereinafter also referred to as gate voltage (VG)) and a conductive layer that functions as a second gate electrode. The voltage (VBG) applied to the conductive film 120b is set to 0.25V from −15V to +20V. The voltage was applied in the following steps. The voltage applied to the conductive film 104 and the conductive film 120b is changed from -15V to +15V. In addition, the voltage applied to the conductive film 112a functioning as the source electrode (hereinafter referred to as the source voltage) The voltage (Vs) is set to 0V (common), and the conductive electrode that functions as the drain electrode The voltage applied to the film 112b (hereinafter also referred to as drain voltage (VD)) is set to 0.1 V or The field effect mobility (μFE) was measured at VD=20V. are.

[0459] From the results shown in Figures 24 and 25, it was found that the maximum temperature in the process was reduced from 450°C to 350°C. It was confirmed that there was no significant difference in the ID-VG characteristics of the transistor even when the temperature was reduced to .

[0460] Next, the channel length L of sample E1 and the channel width W of sample E2 were measured. The variation in the transistor substrate surface (600 mm x 720 mm) was evaluated.

[0461] First, the channel length L of sample E1 and sample E2 is 3 μm, and the channel width W is 50 μm. The ID-VG characteristics of the transistors were evaluated. The ID-VG characteristics results for samples E1 and E2 are as follows: The results are shown in Figures 26(A) and 26(B). Note that Figure 26(A) shows the ID-VG characteristics of sample E1. FIG. 26(B) shows the ID-VG characteristics of sample E2. In this figure, the vertical axis represents ID (A) and the horizontal axis represents VG (V). In each of (A) and (B), a total of 40 transistor characteristics are displayed in an overlapping manner. The ID-VG characteristics shown in FIGS. 26(A) and 26(B) are the same as those shown in FIGS. 24 and 25. Specifically, the measurement conditions for the ID-VG characteristics shown in Figures 26(A) and 26(B) are different. The gate voltage (VG) and (VBG) range from -15V to +20V. The source voltage (V The voltage (V) was set to 0V (common) and the drain voltage (VD) was set to 10V.

[0462] Next, the threshold voltages of the transistors of the samples E1 and E2 shown in FIGS. 26(A) and 26(B) were measured. The results of comparing the variations in Vth and on-current (Ion) are shown in Figures 27(A) and 27(B). In addition, Figure 27(A) shows the probability of Vth within the substrate surface (600 mm x 720 mm). 27(B) is a diagram illustrating the distribution of I 27(B) is a diagram illustrating the probability distribution of on. In FIG. 27(B), Ion is The value was taken as 0V.

[0463] From the results shown in Figures 26 and 27, sample E2 has a slightly lower Ion than sample E1. Although this was confirmed, the transistor characteristics were good with little variation within the substrate surface. was confirmed.

[0464] Next, the reliability of the prepared samples E1 and E2 was evaluated. , the GBT test was used.

[0465] In this example, the GBT test conditions were a gate voltage (VG) of ±30 V and a drain voltage of ±10 V. The on-chip voltage (VD) and source voltage (VS) are set to 0V (COMMON), and the stress temperature is set to 60 The temperature was set to °C, the stress application time was set to 1 hour, and the measurement environment was set to a dark environment and a light irradiation environment (white L The experiment was carried out in two environments: one with a 10000lx light source and the other with a 10000lx light source. The source electrode and drain electrode of the transistor are set to the same potential, and the gate electrode is connected to the source electrode and drain electrode. A potential different from that of the gate electrode was applied for a certain period of time (here, 1 hour). When the applied potential is higher than the potential of the source electrode and the drain electrode, it is considered a positive stress. When the potential applied to the gate electrode is lower than the potential of the source electrode and drain electrode, it is called a negative Therefore, in accordance with the measurement environment, plus GBT stress (dark), Negative GBT stress (dark), positive GBT stress (light exposure), and negative G Reliability evaluation was carried out under a total of four conditions of GBT stress (light irradiation). Trace (dark) with PBTS (Positive Bias Temperature Negative GBT stress (dark) is defined as NBTS (Nagativ e Bias Temperature Stress) and plus GBT stress ( PBITS (Positive Bias Illuminations T Negative GBT stress (light irradiation) is defined as NB ITS(Nagative Bias Illuminations Temperat This may be referred to below as "Urage Stress."

[0466] The GBT test results for samples E1 and E2 are shown in FIG. 28. In FIG. 28, the vertical axis represents the The change in the threshold voltage (ΔVth) and the change in the shift value (ΔShift) of the transistor are The horizontal axis indicates the sample name, process conditions, etc.

[0467] From the results shown in FIG. 28, it can be seen that the sample E2 has a smaller change in threshold voltage (Δ Vth) is slightly larger, but the negative fluctuation of the GBT is 1V or less and the positive fluctuation is 2V or less. It was confirmed that this was the case.

[0468] Next, when PBTS and NBTS were alternately repeated for samples E1 and E2, The change in threshold voltage was measured. The G characteristics were measured (initial). Then, PBTS and NBTS were alternately applied twice. Each GBT stress test was performed at a stress temperature of 60°C and for a stress time of 3600 In this example, the channel length L is 6 μm and the channel width W is 50 μm. The measurements were taken on the star.

[0469] Before the stress test (initial) and after each GBT stress test for sample E1 The threshold voltage is shown in Figure 29(A) for sample E2 before the stress test (initial) and after the stress test. The threshold voltages after each GBT stress test are shown in FIG. 29(B). In Figure 9(A) and (B), the vertical axis represents the threshold voltage (Vth) when the drain voltage is 10V. The horizontal axis shows the stress test name. Also, Fig. 29(A)(B) shows the results before the stress test. (initial), PBTS, NBTS, PBTS, NBTS in the order of GBT test This is the result of the above.

[0470] From the results shown in FIGS. 29(A) and 29(B), the amount of change in the threshold voltage of the transistor of sample E2 is larger than the change in threshold voltage of the transistor of sample E1, but the change is within ±4V. The amount was confirmed.

[0471] As described above, one embodiment of the present invention is a transistor that can be fabricated at a low process temperature, as in the transistor of Sample E2. However, by using a stacked structure of oxide semiconductor films, reliability can be improved and variations in electrical characteristics can be reduced. It has excellent electrical properties, including suppression of noise, improvement of on-state current, and low S value. was shown.

[0472] The configuration shown in this embodiment may be used in appropriate combination with other embodiments or embodiments. It is possible. [Example]

[0473] In this embodiment, the transistor 100 shown in FIG. 1 and the transistor 100 shown in FIG. A transistor corresponding to No. 70 was fabricated, and a display device including the transistor was fabricated.

[0474] First, Table 1 shows the specifications of the display device fabricated in this example.

[0475] [Table 1]

[0476] Next, top views of the pixel portion of the display device manufactured in this example are shown in Figures 30(A) and 30(B). FIG. 30(A) shows the upper surface of the pixel portion 840A when the minimum processing dimension of the process is set to 2 μm. FIG. 30(B) shows the pixel area when the minimum processing dimension of the process is 3.5 μm. 30(A) and 30(B), each of which is for three pixels. It represents.

[0477] 31(A) and 31(B) are top views of the gate driver section of the display device manufactured in this example. FIG. 31(A) is a top view when the minimum processing dimension of the process is set to 2 μm. FIG. 31(B) is a top view when the minimum processing dimension of the process is 3.5 μm. In FIG. 31(A), an area 800 is the frame width, an area 801 is the dummy pixel area, The region 802 is a protection circuit section, the region 803 is a gate driver circuit section, and the region 804 is a separation In FIG. 31(B), the area 850 indicates the frame width, region 851 indicates the dummy pixel section, region 852 indicates the protection circuit section, and region 853 indicates the gate The area 854 represents the margin area for separation. .

[0478] In this embodiment, the area 800 shown in FIG. 31(A) is 0.7 mm. 801 is 0.05 mm, area 802 is 0.08 mm, and area 803 is 0.41 mm In this example, the area 804 is set to 0.16 mm. Let area 850 be 0.8 mm, area 851 be 0.05 mm, and area 852 be 0.0 7 mm, area 853 was 0.55 mm, and area 854 was 0.13 mm.

[0479] In this embodiment, as shown in FIGS. 31(A) and 31(B), the protection circuit section (area 80 2 or region 852) is provided as an example, but the present invention is not limited to this. In this case, the protection circuit can be omitted, so the frame width can be further reduced. For example, the area 800 shown in FIG. 31(A) can be reduced to 0.6 mm. The area 850 shown in FIG. 31(B) can be reduced to 0.7 mm.

[0480] As described above, the transistor of one embodiment of the present invention has high field-effect mobility and high reliability. Therefore, the gate driver circuit is built in and the frame width (here, the area 800 and the area 8 50) is 1 mm or less, preferably 0.8 mm or less, more preferably 0.6 mm or less. Therefore, a display device with a narrow frame can be manufactured.

[0481] 32 is a cross-sectional view corresponding to the cut surface taken along the dashed line M1-N1 shown in FIG. 30(A). 3A is a cross-sectional view corresponding to the cut surface between the dashed line M2-N2 shown in FIG. 31A. 2(B) shows the results.

[0482] The pixel portion 840A shown in FIG. 32A includes a conductive film 904a on a substrate 902 and a and an insulating film 906 on the conductive film 904, an insulating film 907 on the insulating film 906, and an insulating film 907. an oxide semiconductor film 908 on the insulating film 907; an oxide semiconductor film 909 on the insulating film 907; a conductive film 912a electrically connected to the oxide semiconductor film 908 and functioning as a source electrode; A conductive film 912b electrically connected to the insulating film 908 and functioning as a drain electrode, 7, an insulating film 914 over the oxide semiconductor films 908 and 909, and an insulating film 9 16, an insulating film 916, an insulating film 918 over the oxide semiconductor film 909, and The conductive film 920a serving as a pixel electrode, the insulating film 918, and the insulating film 920a and a membrane 924.

[0483] Note that the oxide semiconductor film 908 is composed of a first oxide semiconductor film 908a and a second oxide semiconductor film 908b. The oxide semiconductor film 909 is a first oxide semiconductor film 908b. The second oxide semiconductor film 909a and the second oxide semiconductor film 909b are included.

[0484] The insulating film 918 is formed so as to cover the openings provided in the insulating films 914 and 916. The conductive film 920 serving as a pixel electrode is , and the insulating films 914, 916, and 918 are formed so as to cover the openings. It is electrically connected to the conductive film 912b which functions as an electrode.

[0485] In addition, in Figures 32(A) and 32(B), the liquid crystal element, the element on the opposing substrate side, etc. are omitted. is doing.

[0486] 32B. The region 802 functioning as a protective circuit portion shown in FIG. 32B is a conductive region on the substrate 902. A conductive film 904b, a conductive film 904c on the substrate 902, and insulating films on the conductive films 904b and 904c. a film 906, an insulating film 907 over the insulating film 906, and an oxide semiconductor film 910 over the insulating film 907; a conductive film 912c electrically connected to the oxide semiconductor film 910; 0, a conductive film 912e on the insulating film 907, and an insulating film 907, the insulating film 9 over the oxide semiconductor film 910, and the conductive films 912c, 912d, and 912e. 14, an insulating film 916 on the insulating film 914, an insulating film 918 on the insulating films 907 and 916, a conductive film 920b provided over the insulating film 918 and overlapping with the oxide semiconductor film 910; The conductive film 920c over the insulating film 918 and the conductive film 912e, and the insulating film 918 and the conductive film 920b , and an insulating film 924 on 920c.

[0487] The conductive films 904a, 904b, and 904c are formed by processing the same conductive film. The oxide semiconductor film 908, the oxide semiconductor film 909, and the oxide semiconductor film 909 were formed through a process. The oxide semiconductor film 910 was formed through the same process of processing an oxide semiconductor film. The conductive film 912a, the conductive film 912b, the conductive film 912c, the conductive film 912d, and the conductive film 91 The conductive film 920a and the conductive film 92e were formed through the same process of processing the conductive film. The conductive film 20b and the conductive film 920c were formed through the same process of processing a conductive film.

[0488] The transistor used in the region 803 functioning as the gate driver circuit portion shown in FIG. 31(A) The transistor structure is the same as that of the transistor 170 shown in FIG. It can be used.

[0489] A glass substrate was used as the substrate 902. Conductive films 904a, 904b, and 904 For c, a tungsten film with a thickness of 200 nm was formed using a sputtering device. As the insulating film 906, a silicon nitride film having a thickness of 400 nm is formed by a PECVD apparatus. As the insulating film 907, a silicon oxynitride film having a thickness of 50 nm was deposited by a PECVD apparatus. It was formed by.

[0490] The first oxide semiconductor films 908a, 909a, and 910a were made of 10-nm-thick oxide semiconductor films. IGZO film (In:Ga:Zn=3:1:2 [atomic ratio]) was formed using a sputtering device. The second oxide semiconductor films 908b, 909b, and 910b were formed by depositing oxide semiconductor layers having a thickness of 1500 nm. nm IGZO film (In:Ga:Zn=1:1:1.2 [atomic ratio]) sputtered It was formed in the device.

[0491] The conductive films 912a, 912b, 912c, 912d, and 912e are made of a 50 nm thick tungsten film, 400 nm thick aluminum film, and 100 nm thick titanium film A laminated film with the film was formed using a sputtering device.

[0492] As the insulating film 914, a silicon oxynitride film having a thickness of 50 nm was deposited by a PECVD apparatus. The insulating film 916 was formed of a silicon oxynitride film having a thickness of 400 nm. The insulating film 918 was formed by a PECVD apparatus. The SiO2 film was formed using a PECVD apparatus.

[0493] The conductive films 920a, 920b, and 920c are ITSO films with a thickness of 100 nm. The film was formed using a sputtering device.

[0494] In addition, a region 802 functioning as a protection circuit portion shown in FIG. 32(B) includes a so-called diode. A transistor is provided that functions as a protection circuit shown in FIG. FIG. 33 shows an example of a circuit diagram of a protection circuit that can be provided in the region 802.

[0495] The protection circuit 870 shown in FIG. 33 includes a first wiring 861 that functions as a gate line and a low potential The second wiring 862 functions as a power supply line, and the third wiring 86 functions as a high-potential power supply line. 3, a transistor 871, and a transistor 872. 71 and transistor 872 have two gate electrodes, that is, a so-called dual gate structure. The two gate electrodes are supplied with the same potential.

[0496] The gate of the transistor 871 is connected to the source or drain of the transistor 871. The other side is electrically connected to the first wiring 861. Alternatively, one of the drains may be electrically connected to one of the source and drain of the transistor 872. The other of the source and the drain of the transistor 871 is connected to the second wiring 8 62. The other of the source and drain of the transistor 872 is The gate of the transistor 872 and the third wiring 863 are electrically connected to each other.

[0497] The protection circuit 870 shown in FIG. 33 is formed by dividing the area 801 and the area 803 as shown in this embodiment. By providing the insulating film between the insulating film and the insulating film, that is, in the region 802, the reliability of the display device can be improved. However, the display device of one embodiment of the present invention is not limited thereto. For example, In this case, the frame width of the display device can be further reduced. .

[0498] The configuration shown in this embodiment may be used in appropriate combination with other embodiments or embodiments. It is possible. [Explanation of symbols]

[0499] 100 transistors 102 Circuit Board 104 Conductive film 106 insulating film 107 Insulating film 108 Oxide semiconductor film 108a Oxide semiconductor film 108b Oxide semiconductor film 112 Conductive film 112a Conductive film 112b Conductive film 114 insulating film 116 Insulating film 118 insulating film 120 Conductive film 120a Conductive film 120b Conductive film 131 Oxide Conductive Film 138 Etching gas 139 Oxygen 140a Mask 140b mask 142 Etchant 142a opening 142b opening 142c opening 170 transistors 501 pixel circuit 502 pixel section 504 Drive circuit section 504a Gate Driver 504b source driver 506 Protection circuit 507 Terminal section 550 transistors 552 transistor 554 Transistor 560 Capacitor 562 Capacitor 570 Liquid Crystal Devices 572 Light-emitting element 700 Display device 701 PCB 702 pixel section 704 Source driver circuit section 705 PCB 706 Gate driver circuit section 708 FPC terminal section 710 Signal Line 711 Wiring section 712 Sealing material 716 FPC 730 insulating film 732 Sealing film 734 Insulating Film 736 Colored film 738 Light-shielding film 750 transistors 752 transistors 760 connecting electrode 764 insulating film 766 Insulating Film 767 Oxide semiconductor film 768 insulating film 770 Planarization insulating film 772 Conductive film 774 Conductive film 775 Liquid Crystal Elements 776 Liquid Crystal Layer 778 Structure 780 Anisotropic Conductive Film 782 Light-emitting element 784 Conductive Film 786 EL layer 788 Conductive Film 790 Capacitor 800 areas 801 area 802 area 803 area 804 area 840A pixel section 840B pixel section 850 areas 851 area 852 areas 853 areas 854 area 861 Wiring 862 Wiring 863 Wiring 870 Protection circuit 871 Transistor 872 transistors 902 PCB 904 Conductive film 904a Conductive film 904b Conductive film 904c conductive film 906 Insulating film 907 Insulating film 908 Oxide semiconductor film 908a Oxide semiconductor film 908b Oxide semiconductor film 909 Oxide semiconductor film 909a Oxide semiconductor film 909b Oxide semiconductor film 910 Oxide semiconductor film 910a Oxide semiconductor film 910b Oxide semiconductor film 912a Conductive film 912b Conductive film 912c conductive film 912d Conductive film 912e conductive film 914 Insulating film 916 Insulating film 918 Insulating film 920 Conductive film 920a Conductive film 920b Conductive film 920c conductive film 924 insulating film 5100 pellets 5100a pellets 5100b pellets 5101 AEON 5102 Zinc oxide layer 5103 particles 5105a Pellets 5105a1 area 5105a2 pellets 5105b Pellets 5105c Pellets 5105d Pellets 5105d1 area 5105e Pellets 5120 board 5130 Target 5161 area 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Display Panel 8007 Backlight 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery 9000 chassis 9001 Display section 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9100 Mobile Information Terminal 9101 Mobile Information Terminal 9102 Mobile Information Terminal 9200 Mobile Information Terminal 9201 Mobile Information Terminal

Claims

1. a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a ninth conductive layer, and a tenth conductive layer; the first conductive layer functions as a gate electrode of a transistor in a pixel portion; the second conductive layer and the third conductive layer are disposed in a protection circuit section; the first insulating layer has a region in contact with an upper surface of the first conductive layer, a region in contact with an upper surface of the second conductive layer, and a region in contact with an upper surface of the third conductive layer; the second insulating layer has a region located above the first insulating layer; the first oxide semiconductor layer has a channel formation region of the transistor, the first oxide semiconductor layer has a region overlapping with the first conductive layer with the first insulating layer and the second insulating layer sandwiched therebetween; the second oxide semiconductor layer is disposed in the protection circuit section; the second oxide semiconductor layer has a region overlapping with the second conductive layer with the first insulating layer and the second insulating layer sandwiched therebetween; the fourth conductive layer functions as one of a source electrode and a drain electrode of the transistor, the fourth conductive layer has a region in contact with a top surface of the first oxide semiconductor layer, a region in contact with a side surface of the first oxide semiconductor layer, and a region in contact with a top surface of the second insulating layer; the fifth conductive layer functions as the other of the source electrode and the drain electrode of the transistor, the fifth conductive layer has a region in contact with a top surface of the first oxide semiconductor layer, a region in contact with a side surface of the first oxide semiconductor layer, and a region in contact with a top surface of the second insulating layer; the sixth conductive layer has a region in contact with a top surface of the second oxide semiconductor layer, a region in contact with a side surface of the second oxide semiconductor layer, and a region in contact with a top surface of the second insulating layer; the seventh conductive layer has a region in contact with a top surface of the second oxide semiconductor layer, a region in contact with a side surface of the second oxide semiconductor layer, and a region in contact with a top surface of the second insulating layer; the eighth conductive layer has a region overlapping with the third conductive layer with the first insulating layer and the second insulating layer sandwiched therebetween; the third insulating layer has a region in contact with the first oxide semiconductor layer, a region in contact with the fourth conductive layer, a region in contact with the fifth conductive layer, a region in contact with the sixth conductive layer, a region in contact with the second oxide semiconductor layer, a region in contact with the seventh conductive layer, and a region in contact with the eighth conductive layer; the fourth insulating layer has a region located above the third insulating layer; the fifth insulating layer comprises silicon nitride; the fifth insulating layer has a region located above the fourth insulating layer, a region that contacts the third insulating layer in a region that overlaps with the fifth conductive layer, a first region that contacts the third insulating layer in a region that overlaps with the third conductive layer, and a second region that contacts the third insulating layer in a region that overlaps with the eighth conductive layer, the ninth conductive layer has a region located above the fifth insulating layer and functions as a pixel electrode of the pixel portion; A display device, wherein the tenth conductive layer has a region located above the fifth insulating layer, a region overlapping with the first region, a region in contact with the third conductive layer, a region in contact with the eighth conductive layer, and a region overlapping with the second region.

2. In claim 1, the first oxide semiconductor layer has a third oxide semiconductor layer and a fourth oxide semiconductor layer located above the third oxide semiconductor layer; the second oxide semiconductor layer includes a fifth oxide semiconductor layer and a sixth oxide semiconductor layer located above the fifth oxide semiconductor layer; the third oxide semiconductor layer, the fourth oxide semiconductor layer, the fifth oxide semiconductor layer, and the sixth oxide semiconductor layer each contain In and M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf); the fourth oxide semiconductor layer has a lower atomic ratio of In than the third oxide semiconductor layer, the sixth oxide semiconductor layer has a lower atomic ratio of In than the fifth oxide semiconductor layer.

Images