Transmitting system, receiving system, and transmission system

Abstract

To reduce the output delay of video signals while achieving high-precision synchronization between a plurality of devices.SOLUTION: A transmitting system includes a master transmitting device 1A and a slave transmitting device 1B, and transmits a video signal using the master transmitting device 1A and the slave transmitting device 1B. The master transmitting device 1A includes a synchronization unit 12 that outputs a synchronization signal including a PTP clock generated based on a PTP packet and a PTP counter value to the slave transmitting device, and a conversion unit 11 that converts a video signal input to the master transmitting device into a packet and transmits the packet, using the PTP clock. The slave transmitting device 1B includes a synchronization unit 12 that, when the synchronization signal is received from the master transmitting device 1A, replaces its own PTP clock and PTP counter value with the PTP clock and PTP counter value of the synchronization signal, and a conversion unit 11 that converts a video signal input to the slave transmitting device 1B into a packet and transmits the packet, using its own PTP clock.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a transmitting system, a receiving system, and a transmission system. [Background technology]

[0002] In recent years, there has been rapid development in systems for program production in which video signals are converted to IP and transmitted over networks. For example, uncompressed video signals, such as SDI (Serial Digital Interface) signals, are converted to IP packets and transmitted over Ethernet. The Society of Motion Picture and Television Engineers (SMPTE) is working on standardizing such systems, and the standards are constantly being revised.

[0003] Patent Document 1 discloses a technique for reducing the output delay of a video signal conforming to SMPTE and for avoiding degradation of video quality due to fluctuations in the phase of the video signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2023-180769 Summary of the Invention [Problem to be solved by the invention]

[0005] In the transmission system of Patent Document 1, the transmitting device and the receiving device perform PTP synchronization using PTP packets from a PTP server, thereby synchronizing the video signals between the transmitting device and the receiving device.

[0006] When transmitting a video signal that exceeds the transmission capacity of a single device, it is necessary to transmit the video signal using multiple transmitting devices and multiple receiving devices on both the transmitting and receiving sides.Synchronization between multiple transmitting devices and between multiple receiving devices depends on the PTP packets received by each device (transmitting device, receiving device), so there will be some deviation.

[0007] Therefore, it is difficult for multiple transmitting devices to output IP packets that are strictly PTP synchronized on the transmitting side. Also, on the receiving side, it is necessary to place a frame synchronizer or other device after multiple receiving devices to synchronize the output of video signals between multiple receiving devices, but this causes a processing delay of up to one frame in the timing of the video signal output.

[0008] The present disclosure has been made in consideration of the above-mentioned problems, and aims to reduce the output delay of a video signal while realizing highly accurate synchronization between multiple devices. [Means for solving the problem]

[0009] In order to achieve the above-mentioned object, one aspect of the present disclosure is a transmission system comprising a master transmitting device and at least one slave transmitting device, and transmitting a video signal using the master transmitting device and the slave transmitting device, wherein the master transmitting device comprises a synchronization unit that outputs a synchronization signal including a PTP clock generated based on a PTP packet and a PTP counter value to the slave transmitting device, and a conversion unit that uses the PTP clock to convert a video signal input to the master transmitting device into a packet and transmits the packet, and the slave transmitting device comprises a synchronization unit that, when receiving the synchronization signal from the master transmitting device, replaces its own PTP clock and PTP counter value with the PTP clock and PTP counter value of the synchronization signal, and a conversion unit that uses its own PTP clock to convert a video signal input to the slave transmitting device into a packet and transmits the packet.

[0010] One aspect of the present disclosure is a receiving system comprising a master receiving device and at least one slave receiving device, and receiving a video signal using the master receiving device and the slave receiving device, wherein the master receiving device comprises a synchronization unit that outputs a synchronization signal including a PTP clock generated based on a PTP packet and a PTP counter value to the slave receiving device, and a conversion unit that uses the PTP clock to convert packets received by the master receiving device into a video signal and output the video signal, and the slave receiving device comprises a synchronization unit that, when receiving the synchronization signal from the master receiving device, replaces its own PTP clock and PTP counter value with the PTP clock and PTP counter value of the synchronization signal, and a conversion unit that uses its own PTP clock to convert packets received by the slave receiving device into a video signal and output the video signal.

[0011] One aspect of the present disclosure is a transmission system including the transmitting system and the receiving system. [Effects of the Invention]

[0012] According to the present disclosure, it is possible to reduce the output delay of a video signal while realizing highly accurate synchronization between multiple devices. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a transmission system according to an embodiment. [Figure 2] FIG. 2 is a diagram illustrating an example of the configuration of a master transmission modulator. [Figure 3] FIG. 3 is a diagram illustrating an example of the configuration of a slave transmission modulator. [Figure 4] FIG. 4 is a diagram illustrating an example of the configuration of the master receiving modulator. [Figure 5] FIG. 5 is a diagram illustrating an example of the configuration of a slave receiving modulator. [Figure 6] FIG. 6 is a diagram showing the flow of synchronization signals between two transmitting modulators. [Figure 7]FIG. 7 is a diagram showing the flow of synchronization signals among three transmission modulators. [Figure 8] FIG. 8 is a sequence diagram showing the switching operation to PTP synchronization between modulators. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings, the same reference numerals are used to denote the same parts, and descriptions thereof will not be repeated.

[0015] <Video transmission using multiple modulators> Modulators (transmission devices) that transmit video signals (SDI signals) based on SMPTE ST2110 over IP must synchronize with the PTP server via PTP. PTP synchronization means matching the frequency of the clock that keeps the PTP time in the modulator with the frequency of the clock in the PTP server. Hereafter, the clock that keeps the PTP time will be called the PTP clock, and the counter that runs on the PTP clock will be called the PTP counter. The PTP counter value will be the PTP time. PTP time consists of a 48-bit integer part and a 32-bit decimal part. PTP synchronization is achieved when each modulator communicates PTP packets with the PTP server.

[0016] When transmitting a video signal that exceeds the transmission capacity of a single modulator, multiple modulators are used to transmit the video. Examples of video transmission using multiple modulators include the following:

[0017] When the number of SDI signals that make up the video exceeds the number of video signal input / output terminals on one modulator. When the image size or image frame exceeds the transmission capacity of one modulator Table 1 shows examples of the number of video frames and video sizes that exceed the transmission capacity of a modulator when the transmission capacity is 8K59.94P and four 12G-SDI channels.

[0018] [Table 1]

[0019] For example, if multiple modulators are used and each modulator is PTP synchronized, it will be possible to synchronously display four 8K59.94P screens on four 8K monitors using four 12G-SDI cables, and it will also be possible to transmit 16K59.94P video with a pixel size of 17,280 pixels horizontally and 8,640 pixels vertically.

[0020] When multiple modulators are used to transmit video signals, it is desirable that each modulator be PTP synchronized, and that the PTP clock and PTP time (PTP counter value) of the multiple modulators be the same.

[0021] By matching the PTP clocks and PTP times of a group of modulators, the RTP timestamp values ​​of IP packets transmitting the same video frame can be matched between multiple modulators on the transmitting side, and the output timing of SDI signals for the same video frame can be matched between multiple modulators on the receiving side.

[0022] RTP is a standard for real-time transmission of media such as video and audio, and is composed of an RTP header, payload, etc. The RTP timestamp is one of the components of the RTP header. The modulator has a 27MHz clock generated from the PTP clock. When the SDI signal (beginning of a video frame) is input, the transmitting modulator samples the 27MHz clock value and stamps it into the RTP timestamp of the packet transmitting the same video frame. The receiving modulator uses the RTP timestamp as a trigger to output the video signal.

[0023] In video transmission using multiple modulators, if each modulator is independently synchronized via PTP, the accuracy of the PTP synchronization depends on the accuracy of each modulator. Since PTP packets sent and received between the PTP server and modulator are affected by propagation delays on the network path, processing delays in routers, etc., and packet loss in each transmission device, there are limits to the ability to stably and accurately synchronize modulators with independent PTP synchronization in each modulator.

[0024] Therefore, to synchronize multiple video signals output from multiple modulators on the receiving side with high precision, a frame synchronizer that synchronizes the multiple video signals, or a frame synchronization process that aligns the output of each modulator, is required before the video monitor. However, because this synchronization process is performed in video frame units, there can be a delay of up to one frame before the video signal is output, making it unsuitable for low-latency transmission.

[0025] In this embodiment, a modulator is provided with a terminal capable of inputting and outputting a PTP synchronization signal, and multiple modulators are synchronized with high precision by transmitting and receiving synchronization signals between them. Specifically, when multiple modulators are used for video transmission, the master modulator issues a PTP clock and PTP counter value generated by its own modulator using PTP packets as synchronization signals. Synchronization signals such as PTP counter values ​​are transmitted at the same cycle (approximately 1 / 8 second cycle) as the sync message of the PTP packet.

[0026] When a slave modulator receives a synchronization signal issued by a master modulator, it quickly replaces its own PTP clock and PTP counter values ​​with the PTP clock and PTP counter values ​​of the synchronization signal. This makes it possible to achieve stable video transmission even when multiple modulators are used to perform the low-latency video transmission (not tied to the timing of the alignment points of the video signals) described in Patent Document 1.

[0027] <Transmission system configuration> FIG. 1 is a diagram showing an example of a transmission system according to this embodiment. The transmission system according to this embodiment includes a plurality of modulators on each of the transmitting and receiving sides, and transmits video signals using these modulators. Here, the modulators arranged on the transmitting side are referred to as transmitting modulators 1A and 1B (transmitting devices), and the modulators arranged on the receiving side are referred to as receiving modulators 2A and 2B (receiving devices). The plurality of transmitting modulators 1A and 1B on the transmitting side are also referred to as a transmission system. The plurality of receiving modulators 2A and 2B on the receiving side are also referred to as a receiving system.

[0028] The transmitting modulators 1A and 1B are transmission devices that encapsulate and convert video signals (SDI signals) transmitted from the video generation device 3 into IP packets for transmission. The receiving modulators 2A and 2B are transmission devices that receive IP packets, convert the IP packets into video signals, and output the signals to the monitor 5.

[0029] The transmitting system includes a transmitting modulator 1A that functions as a master and at least one transmitting modulator 1B that functions as a slave. The receiving system includes a receiving modulator 2A that functions as a master and at least one receiving modulator 2B that functions as a slave. In Fig. 1, there is only one transmitting modulator 1B and one receiving modulator 2B that function as slaves, but there may be multiple transmitting modulators 1B and multiple receiving modulators 2B.

[0030] The transmission system shown in the figure transmits a video signal input from a video generation device 3 using multiple transmission modulators 1A, 1B and multiple reception modulators 2A, 2B. Currently, the upper limit for video size for broadcasting is 8K@59.94P, but in the future, to transmit video sizes of 8K@119.88P, if a modulator capable of transmitting 8K@59.94P video is used, two modulators will be required on each of the transmitting and receiving sides.

[0031] The transmitting modulators 1A and 1B each have four video terminals 13 and one synchronization terminal 14. The video terminal 13 is an input / output terminal for video signals. The synchronization terminal 14 is an input / output terminal for transmitting a synchronization signal from the master transmitting modulator 1A to the slave transmitting modulator 1B. The synchronization terminal 14 is a pair of terminals including a receiving (input) terminal and a transmitting (output) terminal. The receiving modulators 2A and 2B each have four video terminals 23 and one synchronization terminal 24. The video terminals 23 and synchronization terminal 24 are the same as the video terminals 13 and synchronization terminal 14 of the transmitting modulator. To allow for scalability, even when three or more modulators are used on the transmitting and receiving sides, each modulator can be supported by a pair of synchronization terminals for receiving and transmitting. This will be described later.

[0032] The video generation device 3 is composed of a camera or the like, and outputs a video signal on which video, audio, and auxiliary data are superimposed. Hereinafter, the video signal will also be referred to as an SDI signal. The transmission system transmits this SDI signal via a network (IP network). When transmitting the SDI signal via the network, the transmission system converts it into IP packets (video packets, IP signals) that comply with the SMPTE ST2110 or SMPTE ST2022-8 standard and transmits them.

[0033] The PTP server 4 is, for example, a PTP Grand Master (GM) or a PTP Boundary Clock (BC), and is a device that distributes highly accurate time in accordance with the Precision Time Protocol (PTP). PTP is a protocol defined in IEEE 1588 that synchronizes clocks and times with high precision. The PTP server 4 periodically transmits PTP packets to each of the modulators 1A, 1B, 2A, and 2B. This allows each of the modulators 1A, 1B, 2A, and 2B to synchronize with the PTP clock and PTP counter of the PTP server 4. At this time, by synchronizing the clock of the PTP server 4 with a GPS (Global Positioning System) signal, the PTP server 4 and the modulators 1A, 1B, 2A, and 2B can be synchronized with absolute time such as TAI (International Atomic Time) or UTC (Coordinated Universal Time) with an error of nanoseconds.

[0034] The SMPTE ST2059-1 and ST2059-2 standards stipulate that the transmission of SDI signals should be based on the time of 00:00:00 (SMPTE_EPOCH) on January 1, 1970. These standards define alignment points indicated by times based on SMPTE_EPOCH as video synchronization signals for SDI signals. In other words, when generating or playing back SDI signals, each frame of the SDI signal is generally generated and output at the timing of the alignment points. The alignment points are calculated from a high-precision clock synchronized with the PTP clock of the PTP server 4.

[0035] The PTP server 4 distributes a video synchronization signal to the video production device 3. The video synchronization signal is an analog video synchronization signal based on the SMPTE EPOCH defined in SMPTE ST 2059-1, such as a black burst signal or Tri-sync. The video production device 3 uses the video synchronization signal to adjust the output timing of the SDI signal so that the SDI signal is output at the same timing as the video synchronization signal. At this time, each frame of the SDI signal is generated in association with the timing of an alignment point based on the SMPTE EPOCH.

[0036] In Figure 1, one PTP server 4 distributes PTP packets to the transmitting modulators 1A, 1B and the receiving modulators 2A, 2B, but it is also possible to have a first PTP server for the transmitting modulators 1A, 1B and a second PTP server for the receiving modulators 2A, 2B.

[0037] The transmission modulators 1A and 1B convert the SDI signal on which the video, audio, and auxiliary data from the video generation device 3 are superimposed into IP packets conforming to the SMPTE ST2110 or SMPTE ST2022-8 standard, and transmit them as Ethernet frames over the network. The IP packets may be stamped with a timestamp representing the timing of an alignment point based on SMPTE_EPOCH associated with the time each frame is generated, rather than the time at which the SDI signal frame is input to the transmission modulators 1A and 1B, as in the transmission system of Patent Document 1.

[0038] The receiving modulators 2A and 2B receive the IP packets as Ethernet frames, convert them into SDI signals on which video, audio, and auxiliary data are superimposed, and output them to the monitor 5. Each frame of the SDI signal may be output immediately at a timing obtained by adding a predetermined offset to the alignment point corresponding to the timestamp stamped on each frame, as in the transmission system of Patent Document 1. That is, the receiving modulators 2A and 2B may output the frame without waiting for the timing of the nearest (next) alignment point. The predetermined offset includes the processing time of the modulator and the transmission delay time. This enables frame output with less delay than a method that waits for the timing of the next alignment point. The monitor 5 outputs the SDI signal output by the receiving modulators 2A and 2B.

[0039] <Configuration of the transmission modulator> 2 is a diagram showing an example of the configuration of a master transmission modulator 1A. The transmission modulator 1A includes a conversion circuit 11 and a synchronization circuit 12. The conversion circuit 11 converts an SDI signal (video signal) input to the transmission modulator 1A into an IP packet using a PTP clock generated by the synchronization circuit 12, and transmits the IP packet. The conversion circuit 11 shown in the figure is the same as that in Patent Document 1, and includes an SDI signal receiving circuit 111, an RTP packetizing circuit 112, a timestamp adding circuit 113, and an IP signal transmitting circuit 114.

[0040] The SDI signal receiving circuit 111 receives an SDI signal, in which each frame is generated in association with the timing of an alignment point based on SMPTE_EPOCH, from the video generation device 3 via a video terminal. Specifically, the SDI signal receiving circuit 111 receives this SDI signal in synchronization with an internal PTP clock, and sends the received SDI signal to the RTP packetization circuit 112. The internal PTP clock is input from the synchronization circuit 12.

[0041] The RTP packetization circuit 112 converts the SDI signal into a plurality of packets on a frame-by-frame basis. Specifically, the RTP packetization circuit 112 converts the SDI signal supplied from the SDI signal receiving circuit 111 into RTP packets specified in SMPTE ST2110-20 / 30 / 40 or ST2022-8. Here, the RTP packetization circuit 112 divides the SDI signal into media payloads every predetermined number of bytes, adds a payload header and an RTP header, and encapsulates the media payloads into RTP packets.

[0042] RTP stands for Real-time Transport Protocol, defined in IETF RFC3550, and is a data communications protocol for dividing video, audio, and other data streams into a series of RTP packets and transmitting them in real time. The series of RTP packets constitutes an RTP stream of data. The RTP stream is composed of frames, each consisting of multiple RTP packets. These frames are the same as the frames defined in SDI signals. The RTP stream is then IP packetized in the downstream IP signal transmission circuit 114 to become an IP signal, which is then transmitted to the destination receiving modulator 2A via the network.

[0043] The timestamp assignment circuit 113 assigns to each RTP packet a timestamp corresponding to the timing of the alignment point set in the corresponding frame at the time of generation. Here, the timestamp assignment circuit 113 stamps a timestamp on the RTP packets sent from the RTP packetization circuit 112. The timestamp is set in the RTP header. Specifically, a series of RTP packets generated from an SDI signal are stamped with a timestamp value indicating the timing of the alignment point at the time of generation of the frames of the SDI signal.

[0044] The IP signal transmitting circuit 114 transmits each RTP packet with a timestamp as an IP signal (IP packet). Specifically, the IP signal transmitting circuit 114 converts the RTP stream with a timestamp into IP packets, places the IP signal on an Ethernet frame, and outputs the frame to a network at a timing conforming to SMPTE ST2110-10. The network may be, for example, the Internet, but any network (IP network) capable of transmitting IP signals may be used.

[0045] In the conversion circuit 11 of this embodiment, by stamping the timing of the alignment point based on the SMPTE_EPOCH associated with the generation of each frame of the SDI signal as a timestamp, even if there is temporal fluctuation in the video signal input to each circuit, it is possible to always set the timestamp to indicate the ideal frame timing, thereby avoiding degradation of video quality due to fluctuation in the phase of the video signal.

[0046] The synchronization circuit 12 communicates with the PTP server 4 to achieve PTP synchronization. The synchronization circuit 12 also outputs a synchronization signal, including a PTP clock generated based on the PTP packet and a PTP counter value, to the slave transmission modulator 1B. The synchronization circuit 12 includes an adjustment circuit 121, a clock 122, and a selector 123.

[0047] The adjustment circuit 121 generates (adjusts) its own PTP clock and PTP counter value based on the PTP packet transmitted from the PTP server 4, and outputs the PTP clock and PTP counter value as a synchronization signal to the slave transmission modulator 1B. Specifically, the adjustment circuit 121 has a PTP clock and a PTP counter. The PTP counter is a counter that operates with the PTP clock, and the PTP counter value becomes the PTP time (the time elapsed since SMPTE_EPOCH). The adjustment circuit 121 matches the frequency of the PTP clock that keeps its own PTP time to the frequency of the PTP clock of the PTP packet from the PTP server 4, generates a synchronization signal including the matched PTP clock and a PTP counter value synchronized with the PTP clock, and outputs the generated synchronization signal to the slave transmission modulator 1B. The adjustment circuit 121 periodically (for example, every time a PTP packet is received) generates a synchronization signal and outputs it to the transmission modulator 1B. The synchronization signal is transmitted and received via synchronization terminals 14 of the transmission modulators 1A and 1B shown in FIG.

[0048] The synchronization signal may include a synchronization flag in addition to the PTP clock and PTP counter value. The synchronization flag is a flag that indicates whether PTP synchronization between modulators is enabled. When the PTP synchronization of the transmitting modulator 1A is functioning normally, the adjustment circuit 121 enables PTP synchronization between the modulators and sets a normal flag (for example, ON) indicating normality to the synchronization flag. On the other hand, when an abnormality is detected in the PTP synchronization of the transmitting modulator 1A, the adjustment circuit 121 disables PTP synchronization between the modulators and sets an abnormality flag (for example, OFF) indicating an abnormality to the synchronization flag.

[0049] Furthermore, the adjustment circuit 121 multiplies the PTP clock to generate a media clock 122. Specifically, the adjustment circuit 121 multiplies the PTP clock to generate a 90 KHz media clock and counter and a 48 KHz media clock and counter. The 90 KHz media clock is a clock for the video and auxiliary data of the SDI signal. The 48 KHz media clock is a clock for the audio data. The SDI signal is managed in a form in which video, audio, and auxiliary data are multiplexed on a frame-by-frame basis, but the ST2110 packets are separated and transmitted and received as different packets, and therefore are managed in association with the counters of the adjustment circuit 121. The media clocks are used by each of the circuits 111 to 114 of the conversion circuit 11.

[0050] The adjustment circuit 121 may multiply the PTP clock and generate an SDI output clock 122 (27 MHz, 74.18 MHz, 74.25 MHz, 148.35 MHz, 148.5 MHz) corresponding to the video format of the SDI signal. Because the SDI output clock is used by the receiving modulators 2A and 2B, the adjustment circuits 121 of the transmitting modulators 1A and 1B do not need to generate the SDI output clock. In the example shown in the figure, the synchronization signal is transmitted to the slave receiving modulator 2A via a selector 123, but the selector 123 may be omitted.

[0051] 3 is a diagram showing an example of the configuration of a slave transmission modulator 1B. The transmission modulator 1B includes a conversion circuit 11 and a synchronization circuit 12. The conversion circuit 11 is similar to the conversion circuit 11 of the transmission modulator 1A, and uses its own PTP clock to convert the video signal input to the transmission modulator 1B into packets and transmit them.

[0052] When the synchronization circuit 12 receives a synchronization signal from the master transmission modulator 1A, it replaces its own PTP clock and PTP counter value, which were generated based on the PTP packet, with the PTP clock and PTP counter value of the synchronization signal.When the synchronization circuit 12 receives a synchronization signal in which a synchronization flag indicating an abnormality is set, it may generate its own PTP clock and PTP counter value based on the PTP packet.

[0053] The synchronization circuit 12 includes an adjustment circuit 121, a clock 122, and a selector 123. The adjustment circuit 121 has a PTP clock and a PTP counter, and matches the frequency of its own PTP clock to the frequency of the PTP clock of the PTP packet transmitted from the PTP server 4. Furthermore, upon receiving a synchronization signal from the transmission modulator 1A, the adjustment circuit 121 replaces its own PTP clock and PTP counter value with the PTP clock and PTP counter value of the synchronization signal. This allows PTP synchronization between the modulators. By receiving the synchronization signal, the slave transmission modulator 1B operates with the same PTP counter value as the master transmission modulator 1A. Therefore, when PTP synchronization is performed between modulators, it is possible to reduce the output phase error of the SDI signal compared to when each modulator performs PTP synchronization independently using PTP packets. Note that PTP synchronization between modulators is performed when the synchronization flag of the synchronization signal is valid (normal flag).

[0054] Similar to the transmitting modulator 1A, the adjustment circuit 121 multiplies its own PTP clock to generate a media clock and an SDI output clock 122. Note that since the SDI output clock is used by the receiving modulators 2A and 2B, the adjustment circuit 121 does not need to generate the SDI output clock.

[0055] In the illustrated example, the synchronization signal transmitted from the transmitting modulator 1A is input to both the adjustment circuit 121 and the selector 123. If there are multiple slave transmitting modulators 1B, the synchronization signal input to the selector 123 is transmitted to the next transmitting modulator 1B. If there is only one slave transmitting modulator 1B, the selector 123 may not be required.

[0056] <Configuration of receiving modulator> 4 is a diagram showing an example of the configuration of the master receiving modulator 2A. The receiving modulator 2A receives the IP signal (IP packet) sent from the transmitting modulator 1A via the network. The receiving modulator 2A includes a conversion circuit 21 and a synchronization circuit 22.

[0057] The conversion circuit 21 converts the IP signal received by the receiving modulator 2A into a video signal and outputs it, using a PTP clock generated by a synchronization circuit 22. The conversion circuit 21 is similar to that described in Patent Document 1, and includes an IP signal receiving circuit 211, an RTP depacketizing circuit 212, an offset control circuit 213, and an SDI signal transmitting circuit 214.

[0058] The IP signal received by the receiving modulator 2A is supplied to an IP signal receiving circuit 211. The IP signal receiving circuit 211 receives the IP signal. Specifically, the IP signal receiving circuit 211 extracts an RTP stream made up of RTP packets from the IP signal carried in an Ethernet frame and sends it to an RTP depacketizing circuit 212.

[0059] The RTP depacketization circuit 212 reproduces frames of an SDI signal from the received IP signal. Specifically, the RTP depacketization circuit 212 generates a bit string (frame data) constituting an SDI signal from the RTP stream supplied from the IP signal receiving circuit 211, based on the SMPTE ST2110-20 / 30 / 40 or ST2022-8 specifications. This SDI signal is sent to the offset control circuit 213.

[0060] The offset control circuit 213 outputs the frames of the reproduced SDI signal at an output timing obtained by adding a predetermined offset to the alignment point of the timestamp added to the corresponding RTP packet. That is, the offset control circuit 213 sends the SDI signal to the subsequent SDI signal transmission circuit 214 at a timing obtained by adding an offset to the time of the timestamp value stamped by the transmission modulator 1A. The offset used is a time equal to or greater than the total delay time obtained by adding the transmission delay time and the SDI / IP conversion processing time on the transmitting and receiving sides.

[0061] The SDI signal transmission circuit 214 outputs the frames output from the offset control circuit 213 as SDI signals. In other words, the SDI signal transmission circuit 214 immediately outputs the SDI signal output from the offset control circuit 213. The conversion circuit 21 of this embodiment outputs the SDI signal at a timing obtained by adding an offset that takes into account processing time and transmission delay time to the alignment point corresponding to the timestamp stamped on each frame. This enables output with less delay than a method that waits for the timing of the next alignment point before outputting.

[0062] The synchronization circuit 22 communicates with the PTP server 4 to achieve PTP synchronization. The synchronization circuit 22 also outputs a synchronization signal including a PTP clock generated based on the PTP packet and a PTP counter value to the slave receiving modulator 2B. When an abnormality is detected, the synchronization circuit 22 may transmit a synchronization signal in which a synchronization flag indicating the abnormality is set.

[0063] The synchronization circuit 22 includes an adjustment circuit 221, a clock 222, and a selector 223. The adjustment circuit 221 has the same functions as the adjustment circuit 121 of the transmitting modulator 1A. The adjustment circuit 221 has a PTP clock and a PTP counter, and generates (adjusts) its own PTP clock and PTP counter value based on PTP packets transmitted from the PTP server 4, and synchronizes its own PTP clock with the PTP clock of the PTP server 4. The adjustment circuit 221 then outputs the generated PTP clock and PTP counter value as a synchronization signal to the slave receiving modulator 2B. The adjustment circuit 221 periodically (for example, each time a PTP packet is received) generates and outputs a synchronization signal. The synchronization signal is transmitted and received via synchronization terminals 24 of the receiving modulators 2A and 2B. The synchronization information may include the above-mentioned synchronization flag in addition to the PTP clock and PTP counter value of the PTP packet.

[0064] The adjustment circuit 221 multiplies its own PTP clock to generate a media clock and an SDI output clock 222. The media clock is used by each circuit 211-214 of the conversion circuit 21. The SDI output clocks (27 MHz, 74.18 MHz, 74.25 MHz, 148.35 MHz, 148.5 MHz) are used by the SDI signal transmission circuit 214. The SDI signal transmission circuit 214 outputs the beginning of each frame of the SDI signal at a synchronization timing generated using the SDI output clock. In the example shown in the figure, the synchronization signal is transmitted to the slave receiving modulator 2B via a selector 223, although the selector 223 may be omitted.

[0065] 5 is a diagram showing an example of the configuration of a slave receiving modulator 2B. The receiving modulator 2B includes a conversion circuit 21 and a synchronization circuit 22. The conversion circuit 11 is similar to the conversion circuit 11 of the receiving modulator 2A, and uses its own PTP clock to convert packets received by the receiving modulator 2B into video signals and output them.

[0066] When the synchronization circuit 22 receives a synchronization signal from the receiving modulator 2A, it replaces its own PTP clock and PTP counter value with the PTP clock and PTP counter value of the synchronization signal. When the synchronization circuit 22 receives a synchronization signal in which a synchronization flag indicating an abnormality is set, it may generate its own PTP clock and PTP counter value based on the PTP packet.

[0067] The synchronization circuit 22 includes an adjustment circuit 221, a clock 222, and a selector 223. The adjustment circuit 221 has the same function as the adjustment circuit 121 of the transmitting modulator 1B, and includes a PTP clock and a PTP counter. The adjustment circuit 221 matches the frequency of its own PTP clock to the frequency of the PTP clock of the PTP packet transmitted from the PTP server 4. Furthermore, upon receiving a synchronization signal from the receiving modulator 2A, the adjustment circuit 221 replaces its own PTP clock and PTP counter value with the PTP clock and PTP counter value included in the synchronization signal. This achieves PTP synchronization between the modulators. By receiving the synchronization signal, the slave receiving modulator 2B behaves with the same PTP counter value as the master receiving modulator 2A. Therefore, when performing PTP synchronization between modulators, it is possible to reduce the output phase error of the SDI signal compared to when each modulator performs PTP synchronization independently using PTP packets. Note that PTP synchronization between modulators is performed when the synchronization flag of the synchronization signal is valid (normal flag).

[0068] Similar to the receiving modulator 2A, the adjustment circuit 221 multiplies its own PTP clock to generate a media clock and an SDI output clock 222. In the example shown, the synchronization information transmitted from the receiving modulator 2A is input to both the adjustment circuit 221 and the selector 223. If there are multiple slave receiving modulators 2B, the synchronization information input to the selector 223 is transmitted to the next receiving modulator 2B. If there is one slave receiving modulator 2B, the selector 223 may be omitted.

[0069] <Flow of synchronization information between modulators> FIG. 6 shows the flow of synchronization signals (PTP clock, PTP counter value, synchronization flag) between two transmitting modulators 1A and 1B. In FIG. 6, only the synchronization circuits 12 of the transmitting modulators 1A and 1B are shown, and the conversion circuit 11 is omitted. The adjustment circuit 121 of the master transmitting modulator 1A transmits a synchronization signal generated based on a PTP packet to the slave transmitting modulator 1B via the selector 123. The synchronization signal is transmitted and received via synchronization terminals (not shown) provided in each of the transmitting modulators 1A and 1B. The synchronization signal input to the slave transmitting modulator 1B is input to the adjustment circuit 121 and also to the selector 123. The adjustment circuit 121 uses the synchronization signal to replace its own PTP clock and PTP counter value. Because there is only one slave receiving modulator 2B, the synchronization signal input to the selector 123 remains stored in the selector 123 without being transmitted to the next transmitting modulator 1B.

[0070] FIG. 7 shows the flow of synchronization signals between three transmitting modulators 1A, 1B-1, and 1B-2. Here, as in FIG. 6, only the synchronization circuit 12 of each transmitting modulator is shown. The adjustment circuit 121 of the master transmitting modulator 1A generates a synchronization signal based on the PTP packet and transmits it to the transmitting modulator 1B-1 of the slave 1 via the selector 123. The synchronization signal is transmitted and received via synchronization terminals (not shown) provided in each of the transmitting modulators 1A, 1B-1, and 1B-2. The synchronization signal input to the transmitting modulator 1B-1 is input to the adjustment circuit 121 and also to the selector 123. The adjustment circuit 121 uses the synchronization signal to replace its own PTP clock and PTP counter value. Because there are multiple slave transmitting modulators in this example, the synchronization signal input to the selector 123 is transmitted to the next transmitting modulator 1B-2 via the synchronization terminal. That is, the transmitting modulator 1B-1 transmits the received synchronization signal to the modulator 1B-2 at the next stage.

[0071] The synchronization signal input to the transmission modulator 1B-2 of slave 2 is input to the adjustment circuit 121 and also to the selector 123. The adjustment circuit 121 replaces its own PTP clock and PTP counter value using the synchronization signal. In Figure 7, there is no transmission modulator of the next slave, so the synchronization information input to the selector 123 remains stored in the selector 123.

[0072] In the illustrated example, the transmitting modulator 1A is the master, but the transmitting modulator 1B-2 may be the master instead. In this case, the transmitting modulators 1A and 1B-1 are slaves, and the synchronization signal output from the transmitting modulator 1B-2 may be transmitted in the order of the transmitting modulator 1B-1 → the transmitting modulator 1A.

[0073] The image generation device 3 that serves as the input to the transmission modulator is usually considered to be one or more image generation devices 3 located nearby, so the multiple transmission modulators are assumed to be located nearby one another. Therefore, it is possible to route a synchronization signal between multiple transmission modulators using a daisy chain method. As a result, even when multiple transmission modulators are provided, each transmission modulator only needs to be provided with one synchronization terminal. Although an example of three transmission modulators is shown in Figure 7, the number of transmission modulators may be four or more.

[0074] 6 and 7 show the flow of synchronization signals between multiple transmitting modulators, but the flow of synchronization signals between multiple receiving modulators is similar. Since one or more monitors 5, which are the output destinations of the receiving modulators, are usually located nearby, multiple receiving modulators are also assumed to be located nearby. Therefore, it is possible to route synchronization signals among multiple receiving modulators.

[0075] <Switching to PTP synchronization between modulators> When transmitting SDI signals (video signals) synchronized using multiple modulators on the transmitting and receiving sides, the master transmitting modulator 1A sends SDP file packets recommended by SMPTE RP 2110-23 along with IP packets (video packets) to the master receiving modulator 2A. The SDP file contains parameters such as the video size and frame rate of the IP packets. This allows the master receiving modulator 2A to recognize that PTP synchronization is being performed between the modulators.

[0076] Figure 8 is a sequence diagram showing the operation of switching to PTP synchronization between modulators. Switching to PTP synchronization between modulators is the same operation on the transmitting side (between transmitting modulators) and the receiving side (between receiving modulators). Therefore, Figure 8 is a sequence diagram common to the transmitting side and the receiving side, and the master shown in the figure means transmitting modulator 1A or receiving modulator 2A, and the slave shown in the figure means transmitting modulator 1B or receiving modulator 2B.

[0077] In the initial state, the master modulator and the slave modulator each perform independent PTP synchronization (single PTP synchronization) using PTP packets transmitted from the PTP server 4 .

[0078] In order to perform PTP synchronization between the modulators, the master modulator transmits a synchronization signal (PTP clock, PTP counter value, synchronization flag) to the slave modulator via the synchronization terminal (S11). At this time, a normal flag (for example, ON) is set in the synchronization flag to enable PTP synchronization between the modulators.

[0079] When the slave modulator receives the synchronization signal, it switches from independent PTP synchronization to PTP synchronization between modulators (S12). That is, the slave modulator replaces its own PTP clock and PTP count value with the PTP clock and PTP count value of the synchronization signal. This starts PTP synchronization between modules. While the master modulator is sending a synchronization signal (synchronization flag: ON) (S13), the slave modulator performs PTP synchronization between modules using the synchronization signal.

[0080] When the master modulator detects an abnormality in its own PTP synchronization (S14), it transmits a synchronization signal with an abnormality flag (e.g., OFF) that disables PTP synchronization between modulators to the slave modulator (S15). An example of a PTP synchronization abnormality is when the PTP counter value is not updated for a certain period of time. When the slave modulator receives the synchronization signal (synchronization flag: OFF), it switches from PTP synchronization between modulators to independent PTP synchronization (S16). That is, the slave modulator synchronizes its own PTP clock and PTP count value with the PTP server 4 using PTP packets from the PTP server 4. While the master modulator is transmitting a synchronization signal (synchronization flag: OFF) (S17), the slave modulator performs independent PTP synchronization. This allows the slave modulator to maintain standalone operation.

[0081] When the master modulator detects recovery from the PTP synchronization abnormality (S18), it sends to the slave modulator a synchronization signal with a normal flag (for example, ON) that enables PTP synchronization between modulators (S19). When the slave modulator receives the synchronization signal (synchronization flag: ON), it switches from independent PTP synchronization to PTP synchronization between modulators (S20). In other words, the slave modulator synchronizes its own PTP clock and PTP count value with the synchronization signal. While the synchronization signal (synchronization flag: ON) is being sent from the master modulator (S21), PTP synchronization between modules is performed in the slave modulator.

[0082] <Action and effect> The transmission system of this embodiment described above comprises a master transmission modulator 1A and at least one slave transmission modulator 1B transmission device, and is a transmission system that transmits video signals using the master and slave transmission modulators 1A, 1B, wherein the master transmission modulator 1A comprises a synchronization circuit 12 that outputs a synchronization signal including a PTP clock generated based on a PTP packet and a PTP counter value to the slave transmission modulator 1B, and a conversion circuit 11 that converts the video signal input to the transmission modulator 1A into packets using the PTP clock and transmits the packets, and the slave transmission modulator 1B comprises a synchronization circuit 22 that, when receiving the synchronization signal from the master transmission modulator 1A, replaces its own PTP clock and PTP counter value with the PTP clock and PTP counter value of the synchronization signal, and the conversion circuit 11 that converts the video signal input to the slave transmission modulator 1B into packets using its own PTP clock.

[0083] The receiving system of this embodiment comprises a master receiving modulator 2A and at least one slave receiving modulator 2B, and receives video signals using the master and slave receiving modulators 2A, 2B. The master receiving modulator 2A comprises a synchronization circuit 22 that outputs a synchronization signal including a PTP clock generated based on PTP packets and a PTP counter value to the slave receiving modulator 2B, and a conversion circuit 21 that uses the PTP clock to convert the packets received by the master receiving modulator 2A into a video signal and output the video signal. The slave receiving modulator 2B comprises a synchronization circuit 22 that, when receiving the synchronization signal from the master receiving modulator 2A, replaces its own PTP clock and PTP counter value with the PTP clock and PTP counter value of the synchronization signal, and a conversion circuit 21 that uses its own PTP clock to convert the packets received by the slave receiving modulator 2B into a video signal and output the video signal.

[0084] As a result, in this embodiment, it is possible to reduce the output delay of the video signal while achieving highly accurate synchronization between multiple modulators. That is, by achieving PTP synchronization between multiple modulators, the timestamps in the RTP headers of the IP packets of multiple transmitting modulators match on the transmitting side, and the video signals synchronized between multiple receiving modulators can be output on the receiving side. Therefore, even when video is transmitted using multiple modulators, highly accurate frame-synchronized output can be achieved, making it possible to, for example, output multi-view 8K@59.94P video.

[0085] Specifically, by performing PTP synchronization between modulators, on the transmitting side, if the SDI signals input to each transmitting modulator are synchronized, each transmitting modulator will synchronize with the PTP synchronization signal of the master transmitting modulator, so the timestamps stamped on the IP packets converted from the SDI signals will be approximately the same value, and it will be possible to output IP packets that are strictly PTP synchronized between transmitting modulators.

[0086] Also, on the receiving side, the output timing of the SDI signal output from each receiving modulator can be controlled using the PTP time of the master receiving modulator, making it possible to align the synchronization timing at each receiving modulator and eliminating the need for processing or equipment for frame synchronization.As a result, no extra processing delay occurs in the timing of the SDI output from the receiving modulator, and stable SDI signals can be output in high-precision synchronization.

[0087] <Hardware configuration> The above-described transmit modulator and receive modulator may be mounted, for example, in a white-box switch. A white-box switch is a network device that combines an x86 server architecture, including a CPU, memory, and storage, with an Ethernet ASIC, client transceiver, etc. The hardware and software are separated, allowing users to select and install the network OS / software that provides the required functions.

[0088] Furthermore, a general-purpose computer system can be used for the above-described transmitting modulator and receiving modulator. The computer system includes, for example, a CPU (Central Processing Unit, processor), memory, storage (HDD: Hard Disk Drive, SSD: Solid State Drive), a communication device, an input device, and an output device. The memory and storage are storage devices. In this computer system, the CPU executes a program for the transmitting modulator or a program for the receiving modulator 2A loaded into the memory, thereby realizing each function of the transmitting modulator or receiving modulator. In this case, each function of the transmitting modulator or receiving modulator is implemented by a program rather than a circuit.

[0089] The transmitting modulator and the receiving modulator may be implemented on one computer or on multiple computers. The transmitting modulator and the receiving modulator may be virtual machines implemented on a computer. The programs for the transmitting modulator and the receiving modulator 2 may be stored on a computer-readable recording medium such as a HDD, SSD, USB (Universal Serial Bus) memory, CD (Compact Disc), or DVD (Digital Versatile Disc), or may be distributed via a network.

[0090] It should be noted that the present disclosure is not limited to the above-described embodiment and modifications, and various modifications are possible within the scope of the gist thereof. For example, although the conversion circuit 11 of the transmitting modulator and the conversion circuit 21 of the receiving modulator in this embodiment use the method disclosed in Patent Document 1, other methods may be used to convert between SDI signals and IP signals. [Explanation of symbols]

[0091] 1A, 1B: Transmitting modulator (transmitting device) 11: Conversion circuit (conversion section) 111: SDI signal receiving circuit 112: RTP packetization circuit 113: Time stamp assignment circuit 114: IP signal transmission circuit 12: Synchronization circuit (synchronization section) 13: Video terminal 14: Synchronization terminal 2A, 2B: Receiving modulator (receiving device) 21: Conversion circuit (conversion unit) 211: IP signal receiving circuit 212: RTP depacketization circuit 213: Offset control circuit 214: SDI signal transmission circuit 22: Synchronization circuit (synchronization section) 23: Video terminal 24: Synchronization terminal 3: Image generation device 4: PTP server 5: Monitor

Claims

1. A transmission system comprising a master transmission device and at least one slave transmission device, the transmission system transmitting a video signal using the master transmission device and the slave transmission device, The master transmitting device a synchronization unit that outputs a synchronization signal including a PTP clock generated based on a PTP packet and a PTP counter value to the slave transmission device; a conversion unit that converts a video signal input to the master transmission device into packets using the PTP clock and transmits the packets; The slave transmitting device a synchronization unit that, when receiving the synchronization signal from the master transmission device, replaces its own PTP clock and PTP counter value with the PTP clock and PTP counter value of the synchronization signal; a conversion unit that converts a video signal input to the slave transmission device into a packet and transmits the packet using the PTP clock of the slave transmission device. Transmission system.

2. The master transmitting device and the slave transmitting device are provided with input / output terminals for transmitting or receiving the synchronization signal. The transmission system of claim 1 .

3. the synchronization signal includes a synchronization flag; a synchronization unit of the master transmitting device that, when detecting an abnormality, transmits a synchronization signal with a synchronization flag indicating the abnormality set; When the synchronization unit of the slave transmitting device receives a synchronization signal with a synchronization flag indicating an abnormality set, the synchronization unit generates its own PTP clock and PTP counter value based on the PTP packet. The transmission system of claim 1 .

4. A receiving system comprising a master receiving device and at least one slave receiving device, the receiving system receiving a video signal using the master receiving device and the slave receiving device, The master receiving device a synchronization unit that outputs a synchronization signal including a PTP clock generated based on a PTP packet and a PTP counter value to the slave receiving device; a conversion unit that converts the packets received by the master receiving device into a video signal using the PTP clock and outputs the video signal; The slave receiving device a synchronization unit that, when receiving the synchronization signal from the master receiving device, replaces its own PTP clock and PTP counter value with the PTP clock and PTP counter value of the synchronization signal; a conversion unit that converts the packets received by the slave receiving device into a video signal using the PTP clock of the slave receiving device and outputs the video signal. Receiving system.

5. The master receiving device and the slave receiving device are provided with input / output terminals for transmitting or receiving the synchronization signal.

5. The receiving system according to claim 4.

6. the synchronization signal includes a synchronization flag; a synchronization unit of the master receiving device that, when detecting an abnormality, transmits a synchronization signal with a synchronization flag indicating the abnormality set; When the synchronization unit of the slave receiving device receives a synchronization signal with a synchronization flag indicating an abnormality set, the synchronization unit generates its own PTP clock and PTP counter value based on the PTP packet.

5. The receiving system according to claim 4.

7. The transmitting system according to claim 1 and the receiving system according to claim 4 are provided. Transmission system.

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