Method of manufacturing fan-out packaging device and fan-out packaging device manufactured thereby

Abstract

To improve thermal, electrical, and mechanical characteristics by introducing a preformer containing a metal via and forming a rear metal layer on a fan-out packaging substrate.SOLUTION: A method includes: attaching a die 120 on a temporary adhesive layer 240 formed on a carrier substrate 220 such that an active side of the die faces the temporary adhesive layer; after attaching a preformer 320 including a metal via 326 in an area other than a die area of the temporary adhesive layer, molding the die and the preformer on the temporary adhesive layer to form a fan-out packaging substrate 100; separating the fan-out packaging substrate; forming a temporary protective layer 420 on the active side of the separated fan-out packaging substrate; forming a rear metal layer 520 connected to the metal via on a rear surface of the fan-out packaging substrate; removing the temporary protective layer; and forming a re-distribution line structure connected to the metal via at the active side of the fan-out packaging substrate and ground-connected to the rear metal layer, and a bump structure connected to the re-distribution line structure.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a fan-out packaging device and a fan-out packaging device manufactured thereby, and relates to a fan-out packaging device having improved thermal, electrical, and mechanical properties by introducing a preformer including metal vias into a fan-out packaging substrate and forming a rear metal layer. [Background technology]

[0002] The eight major processes in semiconductor manufacturing are the wafer process, oxidation process, photo process, etching process, thin film process, wiring process, test process and packaging process, which are carried out in this order.

[0003] The present invention relates to a packaging process in a semiconductor manufacturing process, and generally, the semiconductor packaging process includes the steps of wafer dicing, die attach, die interconnection, molding, and packaging test.

[0004] While the traditional semiconductor packaging process involves cutting wafers and then carrying out the packaging process, the recent trend is to carry out the "Wafer Level Packaging (WLP)" process while maintaining the die in wafer form. This process involves carrying out the packaging process and testing at once in wafer form, and then cutting the die (chips), which has the advantage of reducing package production costs compared to conventional methods.

[0005] In addition, research into the Panel Level Packaging (PLP) process, which goes beyond wafer level packaging, is also active. This has the advantage of being able to package a larger number of dies than the WLP process, further reducing production costs.

[0006] Meanwhile, as semiconductor devices become more highly integrated, perform better, and smaller, various packaging technologies are evolving based on the wafer level packaging or panel level packaging method, and fan-in (wafer or panel level packaging) and fan-out (wafer or panel level packaging) technologies are being actively researched.

[0007] In particular, Fan-Out Wafer or Panel Level Packaging (hereinafter referred to as Fan-Out Wafer Level Packaging for convenience, and also referred to as "Fan Out WLP" or "FO-WLP" as needed) technology is a fan-out technology that increases the number of I / O pins. It uses a Re-Distribution Layer (RDL) process to expand the wiring formation area outside the die area, thereby securing a wiring formation surface that is larger than the die size.

[0008] In such fan-out wafer level packaging, the RDL process forms a dielectric layer on the surface of the die, then forms a wiring layer using copper plating, and if necessary, repeats these processes to extend the wiring formation area outside the die.

[0009] Here, in order to improve the yield and contact resistance of the wiring layer in the RDL process, it is very important to improve the quality of the plating layer in the copper plating process.

[0010] In order to improve the quality of such plating layers, attempts have been made to slow down the plating speed or improve the plating process conditions, but this slows down the process speed and does not ensure process reproducibility.

[0011] Furthermore, when forming such RDL wiring layers in multiple layers, a dielectric layer is formed during the plating process, which can lead to problems such as unevenness of the dielectric layer and deterioration of surface topology due to deterioration of the quality of the plating layer, ultimately resulting in defects in the wiring layer during the subsequent RDL process, which in turn leads to increased contact resistance and impedance and a low operating frequency.

[0012] In addition, the existing fan-out packaging process is susceptible to the effects of process temperature and stress during the process when forming a redistribution layer, which can cause the packaged device to bend or warp (occurrence of wafer warpage), resulting in serious device defects. Also, depending on the type of fan-out packaging device, the size, number, arrangement, shape and type of the die embedded in the fan-out packaging substrate can cause an overall stress imbalance in the fan-out packaging substrate.

[0013] Meanwhile, heat generated in the die is dissipated through the active side and backside of the die, and a heat spreader must be attached to the backside of the die, which results in complex processes and increases the bulk of the packaged device.

[0014] As such, there is still a lack of technology for improving the thermal, electrical, and mechanical properties of the conventional fan-out packaging process and the fan-out packaging device. Summary of the Invention [Problem to be solved by the invention]

[0015] An object of the present invention is to provide a fan-out packaging device with improved thermal, electrical, and mechanical properties by introducing a preformer containing metal vias into a fan-out packaging substrate and forming a rear metal layer. [Means for solving the problem]

[0016] In order to achieve the above object, the present invention provides a method for manufacturing a packaging device using a wafer-level packaging process or a panel-level packaging process, the method comprising: forming a temporary adhesive layer on a carrier substrate; attaching a die to the temporary adhesive layer with an active side of the die facing the temporary adhesive layer; attaching a preformer including metal vias on the temporary adhesive layer in an area other than the die region; molding the die and the preformer on the temporary adhesive layer to form a fan-out packaging substrate; separating the fan-out packaging substrate from the carrier substrate and the temporary adhesive layer; forming a temporary protective layer on the active side of the separated fan-out packaging substrate; forming a rear metal layer on a rear side of the fan-out packaging substrate, the rear metal layer being connected to the metal vias; and removing the temporary protective layer, forming a redistribution layer structure connected to the metal vias and grounded to the rear metal layer, and a bump structure connected to the redistribution layer structure, on the active side of the fan-out packaging substrate.

[0017] Another technical feature of the present invention is a packaging device using a wafer level packaging process or a panel level packaging process, comprising: a fan-out packaging substrate in which a preform including a die and metal vias is embedded; a rear metal layer formed on a rear surface of the fan-out packaging substrate and connected to the metal vias; a redistribution layer structure formed on an active side of the fan-out packaging substrate, connected to the metal vias and grounded to the rear metal layer; and a bump structure connected to the redistribution layer structure.

[0018] The preformer may be formed by forming a metallization pattern on the support substrate, or by dicing the metallization pattern on the support substrate into a predetermined size so as to include one or more of the metallization patterns.

[0019] The preformer may include a support, one or more through holes formed in an array so as to penetrate vertically inside the support, and metal vias for electrical connection formed vertically inside the through holes.

[0020] The metal via may be formed on the inner wall of the through hole by a plating process, and the metal via may include a hole or may be formed to fill the through hole.

[0021] The preformer may include a contact pad connected to the metal via and formed around the through hole, and one or more preformers may be disposed symmetrically with respect to the die.

[0022] The rear metal layer may include copper (Cu) material. The rear metal layer may be realized by forming a copper layer on a titanium (Ti) or titanium tungsten (TiW) layer. The rear metal layer is preferably formed to have a thickness of 1 to 2.2 μm. [Effects of the Invention]

[0023] The present invention provides a fan-out packaging device with improved thermal, electrical, and mechanical properties by introducing a preformer containing metal vias into a fan-out packaging substrate and forming a rear metal layer.

[0024] In addition, in order to resolve the problem of stress imbalance caused by the process, die size, placement, etc., the preformer according to the present invention can play a role in dispersing stress generated in the packaging device by maintaining stress balance by being placed at a specific position on the temporary adhesive layer.

[0025] In addition, the back metal layer according to the present invention has a base metal layer that serves as a seed layer during electrolytic plating for forming a redistribution layer and a bump structure in a subsequent process, thereby providing a very low impedance connection during the plating process, thereby enabling uniform plating thickness in the redistribution layer and the bump structure without the need to significantly reduce the plating speed, and by providing a large-area seed layer, a maximized conductive layer can be provided, improving the quality of the redistribution layer and the bump structure, which can be more usefully applied when forming multiple redistribution layers.

[0026] Furthermore, when the rear metal layer according to the present invention is used as a ground plate, it provides a low impedance signal return path for the redistribution layer, enabling very high frequency operation.

[0027] Furthermore, the rear metal layer according to the present invention is connected to the metal vias of the preformer and is grounded to cover the die, thereby providing an electrical shielding function and enabling stable electrical operation.

[0028] Meanwhile, heat generated in the die is dissipated through the active side and backside of the die, and for this reason, a heat spreader is attached to the backside of the die. The backside metal layer according to the present invention serves as such a heat spreader, thereby improving the thermal characteristics of the packaged device. [Brief explanation of the drawings]

[0029] [Figure 1]1A to 1C are side schematic views illustrating a method for manufacturing a fan-out packaging element according to an embodiment of the present invention. [Figure 2A] 1A to 1C are schematic side views showing various embodiments of the main part of a fan-out packaging device according to the present invention; [Figure 2B] 1A to 1C are schematic side views showing various embodiments of the main part of a fan-out packaging device according to the present invention; [Figure 3A] 1A to 1C are schematic side views showing various embodiments of the main part of a fan-out packaging device according to the present invention; [Figure 3B] 1A to 1C are schematic side views showing various embodiments of the main part of a fan-out packaging device according to the present invention; [Figure 4] 1A to 1C are schematic plan views showing various embodiments of the main part of a fan-out packaging device according to the present invention; [Figure 5] 1A to 1C are schematic plan views showing various embodiments of the main part of a fan-out packaging device according to the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0030] The present invention relates to a fan-out packaging device using a wafer level packaging process or a panel level packaging process, and provides a fan-out packaging device with improved thermal, electrical, and mechanical properties by introducing a preformer including metal vias into a fan-out packaging substrate and forming a rear metal layer.

[0031] Hereinafter, embodiments of the present invention will be described in detail with reference to the right side of the accompanying drawings. Figure 1 is a side view showing a method for manufacturing a fan-out packaging element according to an embodiment of the present invention, Figures 2 and 3 are side views showing various embodiments of the main part of the fan-out packaging element according to the present invention, and Figures 4 and 5 are plan views showing various embodiments of the main part of the fan-out packaging element according to the present invention.

[0032] As shown in FIG. 1, in a method for manufacturing a packaging device using a wafer level packaging process or a panel level packaging process, the method includes forming a temporary adhesive layer 240 on a carrier substrate 220, attaching a die 120 on the temporary adhesive layer 240 so that an active side of the die 120 faces the temporary adhesive layer 240, attaching a preformer 320 including a metal via 326 on the temporary adhesive layer 240 other than the area of ​​the die 120, molding 160 the die 120 on the temporary adhesive layer 240 and the preformer 320 to form a fan-out packaging substrate 100, and The method includes the steps of separating the fan-out packaging substrate 100 from the base substrate 220 and the temporary adhesive layer 240, forming a temporary protective layer 420 on the active side of the separated fan-out packaging substrate 100, forming a rear metal layer 520 connected to the metal via 326 on the rear side of the fan-out packaging substrate 100, and removing the temporary protective layer 420, and then forming a redistribution layer structure 620 connected to the metal via 326 and grounded to the rear metal layer 520, and a bump structure 720 connected to the redistribution layer structure 620, on the active side of the fan-out packaging substrate 100.

[0033] The fan-out packaging device according to one embodiment of the present invention manufactured by this method comprises a fan-out packaging substrate in which a preformer 320 including a die 120 and metal vias 326 is embedded in a packaging device using a wafer level packaging process or a panel level packaging process, a rear metal layer 520 formed on the rear side of the fan-out packaging substrate 100 and connected to the metal vias 326, a redistribution layer structure 620 formed on the active side of the fan-out packaging substrate 100, connected to the metal vias 326 and grounded to the rear metal layer 520, and a bump structure 720 connected to the redistribution layer structure 620.

[0034] The present invention manufactures a packaging device using a wafer level packaging process or a panel level packaging process. First, a temporary adhesive layer 240 is formed on a carrier substrate 220.

[0035] The carrier substrate 220 is a temporary substrate for reconstructing the die 120 and preformer 320, which will be described later, and may be made of a rigid material such as metal, glass, oxide, or PCB.

[0036] A temporary adhesive layer 240 (release tape, die attach film) is formed on the carrier substrate 220. The temporary adhesive layer 240 separates the carrier substrate 220 from the structure formed thereon. The temporary adhesive layer 240 according to an embodiment of the present invention may be an epoxy adhesive material or a photosensitive material that is decomposed by heat or light. The temporary adhesive layer 240 may be formed by being laminated or coated on the carrier substrate 220, and may be cured and attached by heat or light after the die 120 is attached, if necessary.

[0037] Then, the die 120 is attached onto the temporary adhesive layer 240 with its active side facing the temporary adhesive layer 240. The active side of the die 120 refers to the surface of the die 120 where the signal pads 140 are exposed, and the active side of the die 120 contacts the temporary adhesive layer 240 (Die Face Down process). Then, the die 120 is reassembled on the temporary adhesive layer 240 and implemented by a pick-and-place process or the like.

[0038] Then, a preformer 320 including metal vias 326 is attached to the temporary adhesive layer 240 in an area other than the die 120. The die 120 is attached on the temporary adhesive layer 240, and the preformer 320 is attached at an appropriate distance from the die 120. One or more preformers 320 may be attached depending on the size of the fan-out packaging substrate 100, the size of the die 120, the number of the die 120, the arrangement of the die 120, the shape and type of the die 120, etc.

[0039] In the existing fan-out packaging process, stress occurs during the formation of the redistribution layer due to process temperature and CTE (Coefficient of Thermal Expansion) mismatch during the process, which can cause the packaged device to bend or warp (occurrence of wafer warpage), resulting in serious device defects. Also, depending on the type of fan-out packaging device, stress imbalance can occur throughout the fan-out packaging substrate depending on the size, number, arrangement, shape, and type of die embedded in the fan-out packaging substrate. In other words, warpage of the packaged device occurs due to thermal and mechanical stresses generated during the fan-out packaging process.

[0040] In order to solve the problem of such stress imbalance, the preformers 320 according to the present invention can be arranged on the temporary adhesive layer 240 in a specific position, in a specific number, in a specific shape, and in a specific size.

[0041] In one embodiment of the present invention, one or more preformers 320 may be arranged symmetrically with respect to the die 120 (see FIGS. 4 and 5). That is, they may be arranged on one side of the die 120, at the center of the arranged die 120, on both sides of the die 120, or along the periphery of the die 120, or when dies 120 of different sizes are arranged, they may be arranged to reduce stress imbalance and serve to distribute stress generated in the packaging device.

[0042] The preformer 320 according to the embodiment of the present invention includes a metal via 326 therein. That is, the metal via 326 is disposed apart from the die 120 and is formed in the vertical direction of the preformer 320 to electrically connect the upper and lower structures.

[0043] The preformer 320 is formed by a metallization pattern on a support substrate (not shown), or by dicing the support substrate into a predetermined size to include one or more of the metallization patterns.

[0044] The preformer 320 according to an embodiment of the present invention may stack metal layers on the upper and lower surfaces of a support substrate, form through holes 324 in a predetermined pattern, and then form a plating layer in the through holes 324 to implement metal vias 326. Here, contact pads 328 are formed on the upper and lower surfaces of the support substrate around the through holes 324 by the stacked metal layers.

[0045] In addition, the preformer 320 according to an embodiment of the present invention may form a through hole 324 in a support substrate, form a metal via 326 inside the through hole 324 by a patterning process, and form contact pads 328 connected to the metal via 326 along the upper and lower peripheries of the through hole 324. The contact pads 328 are preferably formed in a ring shape along the shape of the through hole 324.

[0046] The preformer 320 can be provided by forming a plurality of through holes 324 and via metals on the support substrate (not shown) and then dicing it to an appropriate size. That is, preformers 320 of various sizes are provided so that an appropriate size of preformer 320 can be selected to maintain the stress balance of the packaging device. The through holes 324 are formed by an etching process using a laser or patterning, and metal vias 326 are formed in the through holes 324. This is referred to as a metallization patterning process in the present invention.

[0047] Thus, the preformer 320 including a single metal via 326 or a preformer 320 including a plurality of metal vias 326 of an appropriate size after dicing includes a support portion 322, one or more through holes 324 arranged vertically inside the support portion 322, and metal vias 326 for electrical connection arranged vertically inside the through holes 324.

[0048] The support substrate, i.e., the support part 322 according to an embodiment of the present invention, may be a PCB, a silicon substrate, ceramic, or other organic material, as long as it is a material that can easily form the metal vias 326 and the through holes 324, can eliminate stress imbalance in the packaging device, and can be easily attached to the temporary adhesive layer 240.

[0049] According to an embodiment of the present invention, the metal via 326 is formed on the inner wall of the through hole 324 by a plating process, and the metal via 326 may include a hole or may be formed so that the through hole 324 is filled.

[0050] The metal vias 326 may be plated and filled with various metal materials such as aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), etc., and may be implemented by an electroplating process, or may be filled by processes such as sputtering, atomic layer deposition (ALD), CVD, etc. In the present embodiment, electroplating is used, which has good step coverage and is cost-effective and highly productive, and copper is used as the metal material.

[0051] The die 120 and the preformer 320 on the temporary adhesive layer 240 are then molded 160 to form the fan-out packaging substrate 100. That is, the fan-out packaging substrate 100 is provided with the die 120 and the preformer 320 embedded therein using EMC (Epoxy Molding Compound), etc. In this manner, the embedded die 120 is realized on the wafer or panel, and the outer region of the die 120 is provided as a fan-out region.

[0052] Then, the fan-out packaging substrate 100 is separated from the carrier substrate 220 and the temporary adhesive layer 240. That is, as described above, the fan-out packaging substrate 100 is separated by the temporary adhesive layer 240 including an epoxy adhesive material or a photosensitive material that is decomposed by heat or light.

[0053] A temporary protective layer 420 is formed on the active side of the separated fan-out packaging substrate 100. The temporary protective layer 420 is for temporarily protecting the active side of the fan-out packaging substrate 100 from subsequent processes, and may be an adhesive protective film.

[0054] A rear metal layer 520 connected to the metal vias 326 is formed on the rear surface of the fan-out packaging substrate 100. The rear metal layer 520 is formed on the entire rear surface of the fan-out packaging substrate 100 and is electrically connected to the metal vias 326. The rear metal layer 520 is formed by a known physical or chemical thin film deposition method, and in one embodiment of the present invention, is formed by a sputtering process.

[0055] In addition, holes or uneven patterns may be formed in a portion or the entire area of ​​the rear metal layer 520. The holes are intended to distribute mechanical or thermal stress throughout the rear metal layer 520 (to prevent warpage of the wafer or panel).

[0056] In addition, in this embodiment of the present invention, it is preferable that the diameter of the holes and uneven patterns is less than twice the thickness of the rear metal layer 520. This is to have the effect of dispersing the mechanical or thermal stress.

[0057] The rear metal layer 520 is formed of a metal having excellent electrical conductivity and thermal conductivity, and copper is used in this embodiment of the present invention. In addition, in order to improve coating properties and adhesion to the surface of the fan-out packaging substrate 100, the rear metal layer 520 may be implemented as a composite metal layer in which a titanium (Ti) or titanium tungsten (TiW) layer is first formed and a copper layer is then formed thereon.

[0058] Overall, the thickness of the rear metal layer 520 may be formed to a thickness of 2.2 μm or less, preferably 1 to 2 μm, taking into consideration the thickness and function of the device, and in the case of the composite metal layer, the thickness of the titanium (Ti) or titanium tungsten (TiW) layer may be formed to a thickness of 0.05 to 0.1 μm.

[0059] The rear metal layer 520 serves as a seed layer during electrolytic plating for forming the redistribution layer structure 620 and the bump structure 720 in the subsequent process. This provides a very low impedance connection during the plating process, thereby enabling uniform plating thickness of the redistribution layer structure 620 and the bump structure 720 without significantly reducing the plating speed. Furthermore, by providing a wide-area seed layer, a maximized conductive layer can be provided, improving the quality of the redistribution layer structure 620 and the bump structure 720. This can be more effectively applied when forming multiple redistribution layers 300.

[0060] Furthermore, when the rear metal layer according to the present invention is used as a ground plate, it provides a low impedance signal return path for the redistribution layer, enabling operation at very high frequencies.

[0061] In addition, the rear metal layer 520 according to the present invention is connected to the metal via 326 of the preformer 320 and is also connected to ground, covering the die 120, thereby providing an electrical shielding (EMI (Electromagnetic Interference) shielding) function, thereby enabling stable electrical operation.

[0062] Meanwhile, heat generated in the die 120 is dissipated through the active side and backside of the die 120. For this purpose, a heat spreader is attached to the backside of the die 120. The backside metal layer 520 according to the present invention serves as such a heat spreader, improving the thermal characteristics of the packaging device.

[0063] Then, after removing the temporary protective layer 420, a redistribution layer structure 620 connected to the metal via 326 and grounded to the rear metal layer 520, and a bump structure 720 connected to the redistribution layer structure 620 are formed on the active side of the fan-out packaging substrate 100.

[0064] First, in forming the redistribution layer structure 620, a first dielectric layer is formed on the active side of the fan-out packaging substrate 100, the first dielectric layer is patterned to form via holes, and a redistribution layer is formed on the first dielectric layer and the via holes.

[0065] The first dielectric layer may be made of an organic or inorganic dielectric material, such as a polymer material such as polyimide, PBO (Polybenzoxazole), or BCB (Benzocyclobutene), or an inorganic material such as an oxide or nitride. Preferably, silicon nitride or silicon oxide may be used. In various embodiments, SiO2, SiO x , oxides such as Al2O3, ZrO2, Ta2O5, SiN xNitrides such as Si3N4, ZrN, AlN, BN, TaN, and TaN can be used, and two or more materials can be mixed as needed. Also, the second dielectric layer can be made of the same or different material as the second dielectric layer described below.

[0066] Such a dielectric layer can be formed by a process such as spin coating, CVD (Chemical Vapor Deposition), sputtering, laminating, or a combination thereof, and can be formed by suitable physical and chemical vapor deposition processes. The first dielectric layer is then patterned to form via holes, which are formed by an etching process during a patterning process, and filled with metal to form electrical connection paths between upper and lower components.

[0067] A plurality of via holes are formed in the first dielectric layer, thereby exposing the metal vias 326 and the signal pads 140 of the preformer 320. The via holes are also formed in the signal pad 140 area of ​​the die 120. That is, a plurality of via holes are formed at appropriate positions on the first dielectric layer, thereby exposing the metal vias 326 of the preformer 320 and the signal pad 140 area, and may also be formed in other required areas.

[0068] The via holes can be filled with various metal materials such as aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), etc., and can be filled by sputtering, atomic layer deposition (ALD), CVD, or electroplating processes.

[0069] According to an embodiment of the present invention, electrolytic plating is used, which has good step coverage and is excellent in cost and productivity, and copper is used as the metal material.

[0070] Then, a redistribution layer is formed on the first dielectric layer and the via hole, so that the redistribution layer is electrically connected to the metal via 326 or the signal pad 140 of the die 120. The redistribution layer is realized by forming a metal layer on the first dielectric layer during or after the formation of the via hole, and forming a metallization pattern thereof.

[0071] That is, the redistribution layer according to one embodiment of the present invention is formed by electroplating a copper layer, and then patterning and etching the copper layer to form signal lines for redistribution of electrical connection wiring of the signal pads 140 exposed from the die 120.

[0072] The redistribution layer can be implemented as a single, multiple, or double-sided redistribution layer, i.e., by repeatedly forming a dielectric layer and a metal layer, a multiple redistribution layer / dielectric layer is implemented (the first dielectric forming process to the redistribution layer 300 forming process are repeated) to form a redistribution signal line in the fan-out region.

[0073] As described above, according to an embodiment of the present invention, by forming the rear metal layer 520 on the rear surface of the fan-out packaging substrate 100, the rear metal layer 520 acts as a seed layer during electrolytic plating for forming the redistribution layer and bump structure in the subsequent process, thereby providing an additional path for current to flow, thereby improving the plating speed due to the low impedance of the redistribution layer structure 620 and the bump structure 720, and by providing a large-area seed layer, the uniformity of the plating layer can be improved, thereby improving the quality of the redistribution layer structure and the bump structure 720.

[0074] A second dielectric layer is then formed on the redistribution layer, and the second dielectric layer is patterned to form a bump structure 720 connected to the redistribution layer.

[0075] When multiple redistribution layers are formed, via holes are formed in the second dielectric layer by patterning, similar to the first dielectric layer, and the redistribution layers are formed by a plating process, and then the redistribution layers are connected to each other. Here, the redistribution layers are connected to the rear metal layer 520 as a ground.

[0076] 2a, 2b, 3a and 3b show a first dielectric layer formed on the active side of the fan-out packaging substrate 100, a via hole and a redistribution layer formed thereon, a second dielectric layer formed thereon, and a bump structure formed at a predetermined position by a patterning process.

[0077] Figure 2a shows a state in which a first dielectric layer is formed on a fan-out packaging substrate 100 in which a preformer 320 having a metal via 326 whose through hole is completely filled is embedded, and a metal layer for forming a redistribution layer is formed on top of it, and Figure 2b shows a state in which patterning for forming the redistribution layer is completed to form a redistribution layer structure 620, and a bump structure 720 is formed on top of it.

[0078] FIG. 3a shows a redistribution layer structure 620 formed on a fan-out packaging substrate 100 in which a preformer 320 having a metal via 326 formed on the inner wall of a through hole 324 and including the hole is embedded, and FIG. 3b shows a bump structure 720 formed on top of it.

[0079] The bump structure 720 according to the embodiment of the present invention is formed by forming an Under Bump Metallization (UBM) (depositing and patterning a Ti / Cu layer) on the pattern (or via hole) of the second dielectric layer, removing the solder plating and photoresist, removing unnecessary metal layers, and forming a solder bump by reflow. For the sake of convenience, such a solder bump and UBM are referred to as a bump structure in the present invention.

[0080] In this way, solder bumps can be formed at the wafer level or panel level, and after performing additional or general packaging processes, the unit fan-out packaging elements can be separated by a dicing process.

[0081] The present invention provides a fan-out packaging device with improved thermal, electrical, and mechanical properties by introducing a preformer containing metal vias into the fan-out packaging substrate and forming a rear metal layer.

[0082] In addition, the preformer according to the present invention is placed at a specific position on the temporary adhesive layer to maintain stress balance and thereby disperse stress generated in the packaging device in order to resolve the problem of stress imbalance caused by the process, die size, and arrangement.

[0083] In addition, the rear metal layer according to the present invention serves as a seed layer during electrolytic plating for forming a redistribution layer and a bump structure in a subsequent process, thereby providing a very low impedance connection during the plating process, thereby enabling uniform plating thickness of the redistribution layer and the bump structure without the need to significantly reduce the plating speed, and by providing a large-area seed layer, it is possible to provide a maximized conductive layer and improve the quality of the redistribution layer and the bump structure, which can be more effectively applied when forming multiple redistribution layers.

[0084] Furthermore, when the rear metal layer according to the present invention is used as a ground plate, it provides a low impedance signal return path for the redistribution layer, enabling operation at very high frequencies.

[0085] Furthermore, the base metal layer according to the present invention provides an electrical shielding function between the redistribution layer and the die, thereby enabling stable electrical operation.

[0086] Furthermore, the rear metal layer according to the present invention is connected to the metal vias of the preformer and is also connected to ground, thereby covering the die and providing an electrical shielding function, thereby enabling stable electrical operation.

[0087] Meanwhile, heat generated in the die is dissipated through the active side and backside of the die. To this end, a heat spreader is attached to the backside of the die. The backside metal layer according to the present invention serves as such a heat spreader, improving the thermal characteristics of the packaged device.

Claims

1. A method for manufacturing a packaging device using a wafer level packaging process or a panel level packaging process, forming a temporary adhesive layer on a carrier substrate; attaching a die onto the temporary adhesive layer with an active side of the die facing the temporary adhesive layer; depositing a preformer including metal vias on the temporary adhesive layer in areas other than the die; molding the die on the temporary adhesive layer and the preformer to form a fan-out packaging substrate; separating the fan-out packaging substrate from the carrier substrate and the temporary adhesive layer; forming a temporary protective layer on an active side of the separated fan-out packaging substrate; forming a rear metal layer connected to the metal vias on a rear surface of the fan-out packaging substrate; removing the temporary protective layer, and then forming a redistribution layer structure connected to the metal via and grounded to the rear metal layer on the active side of the fan-out packaging substrate, and a bump structure connected to the redistribution layer structure; A method for manufacturing a fan-out packaging element, comprising:

2. 2. The method for manufacturing a fan-out packaging element according to claim 1, wherein the preformer is formed by a metallization pattern of a support substrate, or by dicing the metallization pattern of the support substrate into a predetermined size so as to include one or more of the metallization patterns.

3. The preformer is A support part; one or more through holes formed in an array so as to penetrate vertically inside the support; Metal vias for electrical connection provided above and below the through-hole; 10. The method for manufacturing a fan-out packaging element according to claim 1, comprising:

4. The metal via is formed on the inner wall of the through hole by a plating process, The method for manufacturing a fan-out packaging element according to claim 3 , wherein the metal vias include holes or are formed so that the through holes are filled.

5. The method of claim 4 , wherein the preformer includes contact pads connected to the metal vias and formed along the periphery of the through holes.

6. The method of claim 1 , wherein one or more preformers are arranged at positions symmetrical with respect to the die.

7. The method for manufacturing a fan-out packaging element according to claim 1 , wherein the rear metal layer comprises a copper (Cu) material.

8. 8. The method of claim 7, wherein the rear metal layer is realized by a copper layer on a titanium (Ti) or titanium tungsten (TiW) layer.

9. 2. The method of claim 1, wherein the rear metal layer is formed to have a thickness of 1 to 2.2 μm.

10. A packaging device using a wafer level packaging process or a panel level packaging process, a fan-out packaging substrate having a die and a preform including metal vias embedded therein; a rear metal layer formed on a rear surface of the fan-out packaging substrate and connected to the metal via; a redistribution layer structure formed on an active side of the fan-out packaging substrate, the redistribution layer structure being connected to the metal via and being grounded with the rear metal layer, and a bump structure being connected to the redistribution layer structure; A fan-out packaging element comprising:

11. The fan-out packaging element of claim 10, wherein the preformer is formed by a metallization pattern of a support substrate, or by dicing the metallization pattern of the support substrate into a predetermined size to include one or more of the metallization patterns.

12. The preformer is A support part; one or more through holes formed in an array so as to penetrate vertically inside the support; Metal vias for electrical connection provided above and below the through-hole; The fan-out packaging element of claim 11 , comprising:

13. The metal via is formed on the inner wall of the through hole by a plating process, The fan-out packaging element of claim 12 , wherein the metal vias include holes or are formed to fill the through holes.

14. The fan-out packaging device of claim 13 , wherein the preformer includes contact pads connected to the metal vias and formed along the periphery of the through-holes.

15. The fan-out packaging element of claim 10 , wherein one or more preformers are arranged at symmetrical positions with respect to the die.

16. The fan-out packaging element of claim 10 , wherein the rear metal layer comprises a copper (Cu) material.

17. 17. The fan-out packaging device of claim 16, wherein the rear metal layer is realized by a copper layer on a titanium (Ti) or titanium tungsten (TiW) layer.

18. 11. The fan-out packaging device of claim 10, wherein the rear metal layer is formed to have a thickness of 1 to 2.2 μm.

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