Field effect transistor

Abstract

To provide a technique of achieving a higher withstanding voltage in a field effect transistor including a plurality of p-type deep layers.SOLUTION: A field effect transistor 10 includes a p-type trench lower layer 35 disposed on a lower side of a trench 14 and extending along a longitudinal direction of the trench when a semiconductor substrate 12 is viewed from above, a plurality of p-type deep layers 36, and a plurality of n-type deep layers 37. The p-type deep layers protrude downward from a body layer 34, extend in a first direction intersecting with the trench when the semiconductor substrate is viewed from above, are disposed with a space part therebetween in a second direction that is orthogonal to the first direction, and are in contact with the p-type trench lower layer disposed on a lower side of the trench. Each n-type deep layer is disposed in the corresponding space part and is in contact with a gate insulating film on a side surface of the trench existing on a lower side of the body layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a field effect transistor and a method for manufacturing the same.

[0002] Patent Document 1 discloses a trench-gate field-effect transistor. This field-effect transistor has multiple p-type deep layers protruding downward from a body layer. Each p-type deep layer extends so as to intersect with the trench when viewed from above the semiconductor substrate. The multiple p-type deep layers are arranged with gaps in their width direction. Each p-type deep layer extends from the body layer to below the bottom of the trench. In one example of a field-effect transistor disclosed in Patent Document 1, each p-type deep layer contacts a gate insulating film on the side and bottom of the trench located below the body layer. The field-effect transistor also has an n-type drift layer contacting the body layer and each p-type deep layer. When this field-effect transistor is turned off, a depletion layer extends from the body layer into the drift layer. The depletion layer extending in the drift layer maintains the source-drain voltage. When this field-effect transistor is turned off, a depletion layer also extends from each deep p-layer into the drift layer. Since each deep p layer contacts the gate insulating film at the bottom of the trench, the depletion layer extending from each deep p layer depletes the drift layer around the bottom of the trench. In this way, the depletion layer extending from each deep p layer to the periphery of the bottom of the trench suppresses electric field concentration in the gate insulating film and drift layer around the bottom of the trench. Therefore, this field effect transistor has a high breakdown voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-194065 Summary of the Invention [Problem to be solved by the invention]

[0004] In such a field-effect transistor having multiple p-type deep layers, a technology is required to further alleviate the electric field concentration in the gate insulating film around the bottom of the trench and to achieve a high breakdown voltage. This specification proposes a technology to achieve a high breakdown voltage in a field-effect transistor having multiple p-type deep layers. [Means for solving the problem]

[0005] The field-effect transistor (10) disclosed herein may include a semiconductor substrate (12) having a trench (14) formed on its upper surface, a gate insulating film (16) covering the inner surface of the trench, and a gate electrode (18) disposed within the trench and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate may include an n-type source layer (30) in contact with the gate insulating film on a side surface of the trench, a p-type body layer (34) located below the source layer and in contact with the gate insulating film on the side surface of the trench, a p-type trench lower layer (35) disposed below the trench and extending along the longitudinal direction of the trench when viewed from above, a plurality of p-type deep layers (36), and a plurality of n-type deep layers (37). Each of the p-type deep layers protrudes downward from the body layer, extends from the body layer to a position below the bottom of the trench, extends along a first direction intersecting the trench when the semiconductor substrate is viewed from above, is arranged with a gap in a second direction perpendicular to the first direction when the semiconductor substrate is viewed from above, and is in contact with the p-type trench lower layer arranged below the trench. Each of the n-type deep layers is arranged in the corresponding gap, and is in contact with the gate insulating film at the side of the trench located below the body layer.

[0006] This field-effect transistor has a p-type trench lower layer disposed below the trench. Therefore, when the field-effect transistor is turned off, the electric field concentration around the bottom surface of the trench is alleviated. As a result, this field-effect transistor can have a high breakdown voltage. Furthermore, in this field-effect transistor, the p-type trench lower layer is electrically connected to the body layer via multiple p-type deep layers. Therefore, the potential of the p-type trench lower layer is stabilized, and deterioration of the switching characteristics of this field-effect transistor is suppressed. Thus, in this field-effect transistor, by combining the p-type trench lower layer and multiple p-type deep layers, it is possible to improve the breakdown voltage while suppressing deterioration of the switching characteristics.

[0007] The method for manufacturing a field effect transistor (10) disclosed in this specification includes a deep layer formation step of forming a plurality of p-type deep layers (36) and a plurality of n-type deep layers (37) in an n-type epitaxial layer (50), wherein each of the p-type deep layers extends along a first direction when the epitaxial layer is viewed from above and is arranged with gaps in a second direction perpendicular to the first direction when the epitaxial layer is viewed from above, and each of the n-type deep layers is arranged within the corresponding gap; The method may include a trench formation step of forming a trench (14) having a depth not exceeding the p-type deep layers, the trench intersecting the plurality of p-type deep layers and the plurality of n-type deep layers when the epitaxial layer is viewed from above; a body layer formation step of introducing p-type impurities toward the surface of the epitaxial layer using ion implantation technology to form a body layer (34) above the plurality of p-type deep layers and the plurality of n-type deep layers; and a p-type trench lower layer formation step of forming a p-type trench lower layer (35) below the bottom surface of the trench using ion implantation technology.

[0008] According to this method for manufacturing a field effect transistor, a field effect transistor having a p-type trench lower layer and a plurality of p-type deep layers can be manufactured. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a cross-sectional perspective view of a MOSFET 10 (a view showing an xz cross section not including a p-type deep layer 36). [Figure 2] FIG. 1 is a cross-sectional perspective view of a MOSFET 10 in which a source electrode 22 and an interlayer insulating film 20 are omitted (a view showing an xz cross section not including a p-type deep layer 36). [Figure 3] FIG. 1 is an enlarged xy cross-sectional view of a MOSFET 10 including a p-type trench lower layer 35, a p-type deep layer 36, and an n-type deep layer 37, showing the arrangement of the p-type trench lower layer 35, the p-type deep layer 36, and the n-type deep layer 37 when the semiconductor substrate 12 is viewed from above. [Figure 4] An enlarged xy cross-sectional view of MOSFET 10 including trench 14, p-type deep layer 36, and n-type deep layer 37, showing the arrangement of trench 14, p-type deep layer 36, and n-type deep layer 37 when viewing semiconductor substrate 12 from above. [Figure 5] 1 is an enlarged yz cross-sectional view of a MOSFET 10 including a p-type deep layer 36 and an n-type deep layer 37. FIG. [Figure 6] FIG. 1 is a cross-sectional perspective view of a MOSFET 10 (a view showing an xz cross section including a p-type deep layer 36). [Figure 7] An enlarged xy cross-sectional view of a modified example of MOSFET 10 including trench 14, p-type deep layer 36, and n-type deep layer 37, showing the arrangement of trench 14, p-type deep layer 36, and n-type deep layer 37 when viewed from above on semiconductor substrate 12. [Figure 8] An enlarged xy cross-sectional view of a modified example of MOSFET 10 including trench 14, p-type deep layer 36, and n-type deep layer 37, showing the arrangement of trench 14, p-type deep layer 36, and n-type deep layer 37 when viewed from above on semiconductor substrate 12. [Figure 9]FIG. 1 is an enlarged xy cross-sectional view of a modified example of MOSFET 10, including a p-type trench lower layer 35, a p-type deep layer 36, and an n-type deep layer 37, showing the arrangement of the p-type trench lower layer 35, the p-type deep layer 36, and the n-type deep layer 37 when the semiconductor substrate 12 is viewed from above. [Figure 10] 1 is a cross-sectional perspective view of a modification of the MOSFET 10 in which the source electrode 22 and the interlayer insulating film 20 are omitted (a view showing an xz cross section not including the p-type deep layer 36). [Figure 11] 10 is a cross-sectional perspective view of a modification of the MOSFET 10 (a view showing an xz cross section not including the p-type deep layer 36). FIG. [Figure 12] 10 is a cross-sectional perspective view of a modified example of the MOSFET 10 (a view showing an xz cross section including a p-type deep layer 36). FIG. [Figure 13] 10 is a cross-sectional perspective view of a modification of the MOSFET 10 (a view showing an xz cross section not including the p-type deep layer 36). FIG. [Figure 14] 10 is a cross-sectional perspective view of a modified example of the MOSFET 10 (a view showing an xz cross section including a p-type deep layer 36). FIG. [Figure 15] 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10. [Figure 16] 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10. [Figure 17] 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10. [Figure 18] 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10. [Figure 19] 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10. [Figure 20] 10 is a cross-sectional perspective view of a modification of the MOSFET 10 (a view showing an xz cross section not including the p-type deep layer 36). FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] A MOSFET (metal-oxide-semiconductor field effect transistor) 10 according to an embodiment shown in FIGS. 1 and 2 includes a semiconductor substrate 12. Hereinafter, the thickness direction of the semiconductor substrate 12 is referred to as the z-direction, a direction parallel to the upper surface 12a of the semiconductor substrate 12 (a direction perpendicular to the z-direction) is referred to as the x-direction, and a direction perpendicular to the x-direction and z-direction is referred to as the y-direction. The semiconductor substrate 12 is made of silicon carbide (i.e., SiC). The semiconductor substrate 12 may also be made of other semiconductor materials such as silicon or gallium nitride. A plurality of trenches 14 are provided in the upper surface 12a of the semiconductor substrate 12. As shown in FIG. 2, the plurality of trenches 14 extend elongatedly along the y-direction on the upper surface 12a. The plurality of trenches 14 are spaced apart in the x-direction.

[0011] As shown in FIGS. 1 and 2, the inner surface (i.e., the side and bottom surfaces) of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is disposed in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. As shown in FIG. 1, the upper surface of each gate electrode 18 is covered with an interlayer insulating film 20. A source electrode 22 is provided on the upper part of the semiconductor substrate 12. The source electrode 22 covers each interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. The source electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12 at a position where the interlayer insulating film 20 is not present. A drain electrode 24 is disposed on the lower part of the semiconductor substrate 12. The drain electrode 24 is in contact with the entire lower surface 12b of the semiconductor substrate 12.

[0012] As shown in Figures 1 and 2, the semiconductor substrate 12 has a plurality of source layers 30, a plurality of contact layers 32, a body layer 34, a plurality of p-type trench lower layers 35, a plurality of p-type deep layers 36, a plurality of n-type deep layers 37, a drift layer 38, and a drain layer 40.

[0013] Each source layer 30 is an n-type layer having a high n-type impurity concentration. Each source layer 30 is disposed in an area that partially includes the upper surface 12a of the semiconductor substrate 12. Each source layer 30 is in ohmic contact with the source electrode 22. Each source layer 30 is in contact with the gate insulating film 16 at the top of the side surface of the trench 14. Each source layer 30 faces the gate electrode 18 via the gate insulating film 16. Each source layer 30 extends longitudinally in the y direction along the side surface of the trench 14. That is, when the semiconductor substrate 12 is viewed from above, each source layer 30 extends parallel to the longitudinal direction of the trench 14, extending from one end to the other end in the longitudinal direction of the trench 14.

[0014] Each contact layer 32 is a p-type layer having a high p-type impurity concentration. Each contact layer 32 is disposed in an area that partially includes the upper surface 12a of the semiconductor substrate 12. Each contact layer 32 is disposed between two corresponding source layers 30. Each contact layer 32 is in ohmic contact with the source electrode 22. Each contact layer 32 extends longitudinally in the y direction. That is, when the semiconductor substrate 12 is viewed from above, each contact layer 32 extends parallel to the longitudinal direction of the trench 14, extending from one end to the other end of the longitudinal direction of the trench 14.

[0015] The body layer 34 is a p-type layer having a lower p-type impurity concentration than the contact layer 32. The body layer 34 is disposed below the source layers 30 and the contact layers 32. The body layer 34 contacts the source layers 30 and the contact layers 32 from below. The body layer 34 contacts the gate insulating film 16 on the side surface of the trench 14 located below the source layer 30. The body layer 34 faces the gate electrode 18 with the gate insulating film 16 interposed therebetween.

[0016] Each p-type trench lower layer 35 is a p-type layer disposed below the corresponding trench 14. As will be described later, each p-type trench lower layer 35 may be formed in the same ion implantation process as the body layer 34. In this case, the concentration profiles of the p-type impurities in the depth direction of each p-type trench lower layer 35 and the body layer 34 are the same, and the depth from the bottom surface of the corresponding trench 14 to the lower surface of each p-type trench lower layer 35 is the same as the depth from the upper surface 12a of the semiconductor substrate 12 to the lower surface of the body layer 34. In this example, each p-type trench lower layer 35 is in contact with the gate insulating film 16 covering the bottom surface of the corresponding trench 14. As shown in FIG. 3 , when the semiconductor substrate 12 is viewed from above, each p-type trench lower layer 35 extends elongatedly along the longitudinal direction of the corresponding trench 14 (the y direction in this example), and may extend continuously from one end to the other end of the longitudinal direction of the trench 14. As will be described later, each p-type trench lower layer 35 extends longitudinally along the longitudinal direction (y direction in this example) of the corresponding trench 14, and may be divided between one end and the other end of the trench 14 in the longitudinal direction.

[0017] Each p-type deep layer 36 is a p-type layer protruding downward from the lower surface of the body layer 34. The p-type impurity concentration of each p-type deep layer 36 is higher than that of the body layer 34 and lower than that of the contact layer 32. When the semiconductor substrate 12 is viewed from above as shown in FIG. 4, each p-type deep layer 36 extends elongately in the x direction and is perpendicular to the longitudinal direction of the trench 14 (in this example, the y direction). The multiple p-type deep layers 36 are arranged with intervals in the y direction. Hereinafter, the portions between the multiple p-type deep layers 36 will be referred to as intervals 39 (see FIGS. 1 and 2). As shown in FIG. 5, the p-type deep layer 36 has a shape elongated in the z direction in the y-z cross section. That is, the dimension of the p-type deep layer 36 in the z direction (hereinafter referred to as depth Dp) is greater than the dimension of the p-type deep layer 36 in the y direction (hereinafter referred to as width Wp). For example, the depth Dp can be 1 to 4 times the width Wp. 6, each p-type deep layer 36 extends from the lower surface of the body layer 34 to a depth below the bottom surface of each trench 14. Each p-type deep layer 36 contacts the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34. Furthermore, as shown in FIG. 3, each p-type deep layer 36 contacts the p-type trench lower layer 35 located below the trench 14 so as to intersect with it.

[0018] Each n-type deep layer 37 has a higher n-type impurity concentration than the drift layer 38. The n-type impurity concentration of each n-type deep layer 37 is lower than the p-type impurity concentration of each p-type deep layer 36. Alternatively, each n-type deep layer 37 may have the same n-type impurity concentration as the drift layer 38. As shown in FIGS. 1 and 2 , each n-type deep layer 37 is disposed in a corresponding gap 39. Each n-type deep layer 37 contacts the lower surface of the body layer 34. Each n-type deep layer 37 contacts the side surfaces of the p-type deep layers 36 on both sides. Each n-type deep layer 37 extends from the lower surface of the body layer 34 to a position lower than the bottom surface of each trench 14 and the lower surface of each p-type deep layer 36. As shown in FIG. 5 , the n-type deep layer 37 in the gap 39 has a shape that is elongated in the z direction in the y-z cross section. That is, the dimension of the n-type deep layer 37 in the z direction (hereinafter referred to as depth Dn) is greater than the dimension of the n-type deep layer 37 in the y direction within the gap 39 (hereinafter referred to as width Wn). For example, the depth Dn can be set to 1 to 4 times the width Wn. In this embodiment, the width Wn of the n-type deep layer 37 is approximately equal to the width Wp of the p-type deep layer 36. Each n-type deep layer 37 has a connection region 37a that extends to just below the lower surface of the adjacent p-type deep layer 36. Each connection region 37a is in contact with the lower surface of the corresponding p-type deep layer 36. The n-type deep layers 37 are connected to each other via the connection regions 37a. The thickness T1 of the portion of the n-type deep layer 37 that protrudes below the lower surface of the p-type deep layer 36 (i.e., the distance in the z direction from the lower surface of the p-type deep layer 36 to the lower surface of the n-type deep layer 37) is approximately 0.1 μm, which is extremely thin. 1 and 2, each n-type deep layer 37 contacts the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34 within each gap 39. Also, as shown in Fig. 3, each n-type deep layer 37 contacts the p-type trench lower layer 35 located below the trench 14 so as to intersect with it.

[0019] The drift layer 38 is an n-type layer having a lower n-type impurity concentration than each of the n-type deep layers 37. The drift layer 38 is disposed below the n-type deep layers 37. The drift layer 38 contacts the n-type deep layers 37 from below.

[0020] The drain layer 40 is an n-type layer having a higher n-type impurity concentration than the drift layer 38 and the n-type deep layer 37. The drain layer 40 is in contact with the drift layer 38 from below. The drain layer 40 is disposed in an area including the lower surface 12b of the semiconductor substrate 12. The drain layer 40 is in ohmic contact with the drain electrode 24.

[0021] Next, the operation of the MOSFET 10 will be described. The MOSFET 10 is used with a higher potential applied to the drain electrode 24 than to the source electrode 22. When a potential equal to or greater than the gate threshold is applied to each gate electrode 18, a channel is formed in the body layer 34 near the gate insulating film 16. The channel connects the source layer 30 and the n-type deep layer 37. As a result, electrons flow from the source layer 30 to the drain layer 40 via the channel, the n-type deep layer 37, and the drift layer 38. In other words, the MOSFET 10 is turned on. When the potential of each gate electrode 18 is reduced from a value equal to or greater than the gate threshold to a value less than the gate threshold, the channel disappears and the flow of electrons stops. In other words, the MOSFET 10 is turned off.

[0022] Next, the operation when the MOSFET 10 is turned off will be described in more detail. When the channel disappears, a reverse voltage is applied to the pn junction at the interface between the body layer 34 and each n-type deep layer 37. Therefore, a depletion layer spreads from the body layer 34 to each n-type deep layer 37. Furthermore, each p-type deep layer 36 is electrically connected to the body layer 34 and has substantially the same potential as the body layer 34. Therefore, when the channel disappears, a reverse voltage is also applied to the pn junction at the interface between each p-type deep layer 36 and each n-type deep layer 37. Therefore, a depletion layer also spreads from each p-type deep layer 36 to each n-type deep layer 37. Furthermore, each p-type trench lower layer 35 is electrically connected to the body layer 34 via each p-type deep layer 36 and has substantially the same potential as the body layer 34. Therefore, when the channel disappears, a reverse voltage is also applied to the pn junction at the interface between each p-type trench lower layer 35 and each n-type deep layer 37. In this way, each n-type deep layer 37 is quickly depleted by the depletion layer spreading from the body layer 34, each p-type trench lower layer 35, and each p-type deep layer 36. In particular, because each p-type trench lower layer 35 is provided below the corresponding trench 14, the periphery of the bottom surface of the trench 14 is depleted well. This significantly alleviates electric field concentration near the bottom surface of the trench 14. Furthermore, each n-type deep layer 37 is entirely depleted by the depletion layer spreading from the body layer 34, each p-type trench lower layer 35, and each p-type deep layer 36. Note that each n-type deep layer 37 has a higher n-type impurity concentration than the drift layer 38, so the depletion layer is less likely to spread within each n-type deep layer 37 than within the drift layer 38. However, because each n-type deep layer 37 is sandwiched between the p-type deep layers 36 and the width Wn of each n-type deep layer 37 is narrow, each n-type deep layer 37 is entirely depleted. The depletion layer also spreads to the drift layer 38 through each n-type deep layer 37. Because the n-type impurity concentration of the drift layer 38 is low, almost the entire drift layer 38 is depleted. The depleted drift layer 38 and each n-type deep layer 37 support a high voltage applied between the drain electrode 24 and the source electrode 22. Therefore, the MOSFET 10 has a high breakdown voltage.

[0023] Furthermore, in the MOSFET 10, the p-type trench lower layer 35 is electrically connected to the body layer 34 via the p-type deep layer 36. This stabilizes the potential of the p-type trench lower layer 35, thereby preventing deterioration of the switching characteristics of the MOSFET 10. In this way, the combination of the p-type trench lower layer 35 and the p-type deep layer in the MOSFET 10 can improve the breakdown voltage while preventing deterioration of the switching characteristics.

[0024] In the MOSFET 10, the p-type trench lower layer 35 is in contact with the gate insulating film 16 covering the bottom surface of the trench 14. This reduces the electrostatic capacitance (i.e., feedback capacitance) between the gate electrode 18 and the drain electrode 24. Furthermore, in the MOSFET 10, each n-type deep layer 37 and each p-type deep layer 36 has a vertically elongated shape. This configuration of each n-type deep layer 37 and each p-type deep layer 36 reduces the feedback capacitance. These factors contribute to improving the switching speed of the MOSFET 10.

[0025] Furthermore, in the MOSFET 10, the depth of the p-type trench lower layer 35 is deeper than the depths of the p-type deep layer 36 and the n-type deep layer 37. The provision of such a deep p-type trench lower layer 35 promotes depletion of the n-type deep layer 37 and the drift layer 38, thereby improving the breakdown voltage of the MOSFET 10. Furthermore, the provision of such a deep p-type trench lower layer 35 ensures that breakdown occurs in the downwardly protruding p-type trench lower layer 35 when an overvoltage is applied, thereby ensuring that breakdown occurs in the cell region. As a result, the avalanche resistance of the MOSFET 10 can also be stabilized. The depth of the p-type trench lower layer 35 may be shallower than the depths of the p-type deep layer 36 and the n-type deep layer 37. In this case, the depletion layer extending from the p-type trench lower layer 35 is suppressed, thereby improving the on-resistance of the MOSFET 10.

[0026] In the MOSFET 10, as shown in FIG. 4 , when the semiconductor substrate 12 is viewed from above, each p-type deep layer 36 and each n-type deep layer 37 extends continuously and elongatedly in the x-direction. Alternatively, as shown in FIG. 7 , each p-type deep layer 36 and each n-type deep layer 37 may be divided in the x-direction. In this example, because each p-type deep layer 36 is divided, a wide current path is ensured, resulting in a reduced on-resistance. However, even in this example, each p-type deep layer 36 and each n-type deep layer 37 is arranged to straddle the trench 14. This allows the above-described effects to be achieved. Alternatively, only one of the p-type deep layers 36 and the n-type deep layer 37 may be divided in the x-direction. Alternatively, as shown in FIG. 8 , a connection p-layer 36a may be provided to connect adjacent p-type deep layers 36. Such a connection p-layer 36a is effective in mitigating the electric field applied to the gate insulating film 16 and improving the breakdown voltage.

[0027] In the MOSFET 10, as shown in FIG. 3 , when the semiconductor substrate 12 is viewed from above, each p-type trench lower layer 35 extends continuously from one end to the other end of the trench 14 in the longitudinal direction. Alternatively, as shown in FIG. 9 , when the semiconductor substrate 12 is viewed from above, each p-type trench lower layer 35 may extend elongatedly along the longitudinal direction of the corresponding trench 14 (the y direction in this example) and be divided between one end and the other end of the trench 14 in the longitudinal direction. In this case, each p-type deep layer 36 passes through the divided portion of the p-type trench lower layer 35. For example, in the example shown in FIG. 3 , damage during ion implantation increases in the overlapping portion between the p-type trench lower layer 35 and the p-type deep layer 36, which raises concerns about an increase in leakage current. On the other hand, in the example shown in FIG. 9 , the overlapping portion between the p-type trench lower layer 35 and the p-type deep layer 36 is small, thereby suppressing an increase in leakage current.

[0028] 2, when the semiconductor substrate 12 is viewed from above, the source layers 30 and contact layers 32 of the MOSFET 10 extend parallel to the longitudinal direction of the trench 14. In particular, because the source layers 30 extend parallel to the longitudinal direction of the trench 14 and contact the side surfaces of the trench 14, the entire side surfaces of the trench 14 can be used as high-concentration channels, thereby reducing the on-resistance of the MOSFET 10. Furthermore, because the entire side surfaces of the trench 14 can be used as channels, the channels and the n-type deep layers 37 are well connected. For example, if the source layers 30 extend so as to intersect the longitudinal direction of the trench 14, particularly so as to be perpendicular to the longitudinal direction of the trench 14, the positions of the source layers 30 contacting the side surfaces of the trench 14 are limited, thereby limiting the positions of the high-concentration channels formed on the side surfaces of the trench 14. Therefore, in this example, a misalignment in the relative positional relationship between the source layer 30 and the n-type deep layer 37 during manufacturing causes a misalignment in the relative positional relationship between the high-concentration channel formed on the side surface of the trench 14 and the n-type deep layer 37, resulting in a problem of large fluctuations in on-resistance. On the other hand, in the MOSFET 10, the entire side surface of the trench 14 can be used as a high-concentration channel, so such fluctuations in on-resistance do not occur. Note that, instead of the example of FIG. 2 , as shown in FIG. 10 , the contact layers 32 may be dispersed and disposed along the longitudinal direction of the trench 14. Even in this example, the contact layers 32 can be considered to extend parallel to the longitudinal direction of the trench 14 when the semiconductor substrate 12 is viewed from above. In this example, a source layer 30 may be provided between the contact layers 32.

[0029] 11 , the n-type deep layer 37 in the MOSFET 10 may include an n-type deep lower layer 137A and an n-type deep upper layer 137B. The n-type deep lower layer 137A is provided below the n-type deep upper layer 137B and has a higher n-type impurity concentration than the drift layer 38 and a lower n-type impurity concentration than the n-type deep upper layer 137B. The n-type impurity concentration of the n-type deep lower layer 137A may be the same as that when the n-type deep lower layer 137A has a substantially single concentration as described above. The n-type deep upper layer 137B is provided between the n-type deep lower layer 137A and the body layer 34, is located above the bottom surface of the trench 14, and is in contact with the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34. The provision of such n-type deep upper layer 137B can suppress the phenomenon (JFET effect) in which a depletion layer extending from both the p-type trench lower layer 35 and the body layer 34 narrows the current path in the region between the p-type trench lower layer 35 and the body layer 34, thereby suppressing an increase in on-resistance. Note that if the entire n-type deep layer 37 is configured to have the same high concentration as the n-type deep upper layer 137B, the aforementioned improvement in breakdown voltage will be reduced. The n-type deep layer 37 has the n-type deep lower layer 137A and the n-type deep upper layer 137B, and further, the n-type deep upper layer 137B is disposed above the bottom surface of the trench 14, thereby effectively suppressing an increase in on-resistance and achieving a high breakdown voltage.

[0030] 12 , the p-type deep layer 36 in the MOSFET 10 may include a p-type deep lower layer 136A and a p-type deep upper layer 136B. The p-type deep lower layer 136A is provided below the p-type deep upper layer 136B and is a p-type layer having a p-type impurity concentration higher than that of the body layer 34 and lower than that of the p-type deep upper layer 136B. The p-type deep upper layer 136B is provided between the p-type deep lower layer 136A and the body layer 34, is located above the bottom surface of the trench 14, and is in contact with the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34. To improve the breakdown voltage of the MOSFET 10, it is desirable for the p-type deep layer 36 to have a high overall impurity concentration. However, in that case, damage during ion implantation increases in the overlapping portion between the p-type deep layer 36 and the p-type trench lower layer 35, raising concerns about an increase in leakage current. In the MOSFET 10 shown in FIG. 12, the concentration of the p-type deep upper layer 136B in the portion not overlapping with the p-type trench lower layer 35 is increased, thereby making it possible to improve the breakdown voltage while suppressing an increase in leakage current.

[0031] 13, in the MOSFET 10, the p-type trench lower layer 35 may include a first p-type trench lower layer 135A and a second p-type trench lower layer 135B. The first p-type trench lower layer 135A is provided below the second p-type trench lower layer 135B and is a p-type layer having a lower p-type impurity concentration than the second p-type trench lower layer 135B. The second p-type trench lower layer 135B is provided between the first p-type trench lower layer 135A and the trench 14 and is in contact with the gate insulating film 16 at the bottom surface of the trench 14. The thickness of the second p-type trench lower layer 135B in the depth direction (z direction) may be smaller than the thickness of the source layer 30 in the thickness direction. Although not particularly limited, the product of the p-type impurity concentration and the thickness of the second p-type trench lower layer 135B may be larger than the product of the n-type impurity concentration and the thickness of the n-type deep layer 37. The provision of the second p-type trench lower layer 135B with a high p-type impurity concentration prevents depletion of the second p-type trench lower layer 135B when the MOSFET 10 is turned off. This reduces the electrostatic capacitance (i.e., feedback capacitance) between the gate electrode 18 and the drain electrode 24, thereby improving the switching speed of the MOSFET 10.

[0032] In some cases, a device with a large feedback capacitance is required. In such cases, the relationship between the p-type impurity concentrations of the first p-type trench lower layer 135A and the second p-type trench lower layer 135B in FIG. 13 may be reversed. That is, the p-type impurity concentration of the second p-type trench lower layer 135B may be lower than the p-type impurity concentration of the first p-type trench lower layer 135A. In this case, too, the thickness of the second p-type trench lower layer 135B in the depth direction (z direction) may be smaller than the thickness of the source layer 30 in the thickness direction.

[0033] In the MOSFET 10, the p-type trench lower layer 35 may be spaced apart from the bottom of the trench 14, as shown in FIG. 14 . The distance between the p-type trench lower layer 35 and the bottom of the trench 14 may be smaller than the thickness of the source layer 30 in the thickness direction. Even if the p-type trench lower layer 35 is provided in this positional relationship, the aforementioned effect of improving the breakdown voltage can be obtained. On the other hand, as will be described later in the manufacturing method, such a p-type trench lower layer 35 reflects the result of reducing the number of ion implantations for the body layer 34 that is simultaneously formed. That is, the MOSFET 10 shown in FIG. 14 has a structure that can be manufactured at low cost.

[0034] In addition, in all of the MOSFETs 10 described above, the depth of the n-type deep layer 37 is deeper than the depth of the p-type deep layer 36. Alternatively, the depth of the n-type deep layer 37 may be equal to the depth of the p-type deep layer 36. Alternatively, the depth of the n-type deep layer 37 may be shallower than the depth of the p-type deep layer 36.

[0035] In addition, in all of the MOSFETs 10 described above, each n-type deep layer 37 has the connection region 37a extending to directly below the p-type deep layer 36. Alternatively, the n-type deep layer 37 may not have the connection region 37a.

[0036] In addition, in all of the MOSFETs 10 described above, when the semiconductor substrate 12 is viewed from above, the p-type deep layers 36 and the n-type deep layers 37 are perpendicular to the trenches 14. Alternatively, the p-type deep layers 36 and the n-type deep layers 37 may be arranged to intersect the trenches 14 at an angle.

[0037] Next, we will explain a method for manufacturing the MOSFET 10. The MOSFET 10 is manufactured from a semiconductor substrate entirely made up of the drain layer 40. First, as shown in FIG. 15, an n-type epitaxial layer 50 is formed on the drain layer 40 using epitaxial growth technology.

[0038] Next, as shown in FIG. 16 , an ion implantation technique is used to introduce n-type impurities and p-type impurities into a predetermined depth range away from the surface of the epitaxial layer 50, thereby forming the n-type deep layer 37 and the p-type deep layer 36 (an example of a deep layer formation process). Specifically, the n-type impurities are introduced planarly to a predetermined depth into the epitaxial layer 50, and then a portion of the area into which the n-type impurities have been introduced is counter-doped with p-type impurities through a mask, thereby forming the n-type deep layer 37 and the p-type deep layer 36. Alternatively, the n-type deep layer 37 and the p-type deep layer 36 may be formed by sequentially introducing n-type impurities and p-type impurities through masks corresponding to the n-type deep layer 37 and the p-type deep layer 36, respectively. Furthermore, by adjusting the concentration of the n-type impurities in advance at a depth corresponding to the area in which the n-type deep layer 37 is to be formed during epitaxial growth of the epitaxial layer 50, the ion implantation for forming the n-type deep layer 37 can be omitted. When forming the n-type deep layer 37 or the p-type deep layer 36 using ion implantation technology or epitaxial growth technology, by changing the concentration in the depth direction, it is possible to form an n-type deep lower layer 137A and an n-type deep upper layer 137B as shown in FIG. 11 or a p-type deep lower layer 136A and a p-type deep upper layer 136B as shown in FIG. 12.

[0039] Next, as shown in FIG. 17, the source layer 30 and the contact layer 32 are formed by introducing n-type impurities and p-type impurities into the surface layer of the epitaxial layer 50 using ion implantation technology.

[0040] 18, an etching technique is used to form trenches 14 that extend from the surface of the epitaxial layer 50 to the n-type deep layers 37 and the p-type deep layers 36 (an example of a trench formation process). The depth of the trenches 14 is adjusted so as not to exceed the n-type deep layers 37 and the p-type deep layers 36. When the epitaxial layer 50 is viewed from above, the trenches 14 intersect with a plurality of p-type deep layers 36 and a plurality of n-type deep layers 37.

[0041] Next, as shown in FIG. 19 , ion implantation is used to introduce p-type impurities in multiple stages toward the surface of the epitaxial layer 50 to form the body layer 34 and the p-type trench lower layer 35 (an example of a body layer formation process and a p-type trench lower layer formation process). The body layer 34 is formed above the n-type deep layer 37 and the p-type deep layer 36, but below the source layer 30 and the contact layer 32. The p-type trench lower layer 35 is formed below the bottom surface of the trench 14. Here, when forming the body layer 34 and the p-type trench lower layer 35 using ion implantation, the concentration in the depth direction can be changed to form a first p-type trench lower layer 135A and a second p-type trench lower layer 135B as shown in FIG. 13 . Furthermore, the depth to which the p-type impurities are introduced to form the second p-type trench lower layer 135B is limited to a range shallower than the source layer 30. This allows the p-type impurity concentration of the second p-type trench lower layer 135B to be freely set while maintaining the desired p-type impurity concentration of the body layer 34. The p-type impurities for forming the second p-type trench lower layer 135B are also introduced into the source layer 30. However, the n-type impurity concentration in the source layer 30 is higher than the introduced p-type impurity concentration, preventing significant fluctuations in the electrical characteristics of the MOSFET 10. Furthermore, by adjusting the number of ion implantation steps so that the p-type impurity is selectively introduced into a region above the n-type deep layer 37 and the p-type deep layer 36 and below the source layer 30 and the contact layer 32, the p-type trench lower layer 35 is formed at a position away from the bottom of the trench 14. The MOSFET 10 shown in FIG. 14 is an example manufactured using this method. Before the p-type impurity ion implantation, a soak prevention shielding film may be formed on the side surface of the trench 14.

[0042] Thereafter, the trench 14, the gate insulating film 16, the gate electrode 18, the interlayer insulating film 20, the source electrode 22, and the drain electrode 24 are formed, thereby completing the MOSFET 10.

[0043] In the above-described manufacturing method, after forming the epitaxial layer 50, various semiconductor regions can be formed using ion implantation technology without performing a re-epi process. To reduce the feedback capacitance, it is desirable to form the n-type deep layer 37 and the p-type deep layer 36 deeply. However, it is difficult to form such deep n-type deep layer 37 and p-type deep layer 36 at a predetermined depth in the epitaxial layer 50 using ion implantation technology, as in the above-described manufacturing method. For this reason, in the conventional example described in the background art, deep n-type deep layer and p-type deep layer are formed on the surface of the epitaxial layer by ion implantation, and then a re-epi process is performed to form the body layer. However, manufacturing methods that include a re-epi process have the problem of increased costs. On the other hand, the MOSFET 10 of this embodiment has a p-type trench lower layer 35, resulting in a low feedback capacitance. Therefore, the MOSFET 10 of this embodiment can achieve a low feedback capacitance without forming the n-type deep layer 37 and the p-type deep layer 36 deeply. Therefore, a MOSFET 10 with low feedback capacitance can be manufactured using the above-described manufacturing method, even without performing a re-epi process. It goes without saying that the MOSFET 10 of this embodiment may be manufactured by performing a re-epi process as necessary.

[0044] The MOSFET 10 described above is an example in which the body layer 34 and the p-type trench lower layer 35 are simultaneously formed using ion implantation technology after the trench 14 is formed. Alternatively, the p-type trench lower layer 35 and the p-type deep layer 36 may be simultaneously formed before the trench 14 is formed. In this case, the body layer 34 is formed by a separate ion implantation process. FIG. 20 shows a MOSFET 10 in which the p-type trench lower layer 35 and the p-type deep layer 36 are simultaneously formed.

[0045] In this MOSFET 10, the width of the p-type trench lower layer 35 is narrower than the width of the trench 14 when measured along the short-side direction (x direction) of the trench 14. This allows for slight misalignment between the p-type trench lower layer 35 and the trench 14, so that the p-type trench lower layer 35 can be disposed so as to contact only the bottom surface of the trench 14 when the trench 14 is formed.

[0046] The features of the technology disclosed in this specification are summarized below. Note that the technical elements described below are independent technical elements that exhibit technical utility either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

[0047] The field-effect transistor disclosed in this specification may include a semiconductor substrate having a trench on its upper surface, a gate insulating film covering the inner surface of the trench, and a gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film. The material of the semiconductor substrate is not particularly limited, but may be, for example, silicon carbide. The semiconductor substrate may include an n-type source layer in contact with the gate insulating film on the side surface of the trench, a p-type body layer located below the source layer in contact with the gate insulating film on the side surface of the trench, a p-type trench lower layer disposed below the trench and extending along the longitudinal direction of the trench when viewed from above, multiple p-type deep layers, and multiple n-type deep layers. Each of the p-type deep layers protrudes downward from the body layer, extends from the body layer to a position below the bottom of the trench, extends along a first direction intersecting the trench when the semiconductor substrate is viewed from above, is arranged with a gap in a second direction perpendicular to the first direction when the semiconductor substrate is viewed from above, and is in contact with the p-type trench lower layer arranged below the trench. Each of the n-type deep layers is arranged in the corresponding gap, and is in contact with the gate insulating film at the side of the trench located below the body layer.

[0048] In the above field effect transistor, the source layer may extend parallel to a longitudinal direction of the trench when the semiconductor substrate is viewed from above. In this field effect transistor, fluctuations in on-resistance are suppressed.

[0049] In the field-effect transistor, the semiconductor substrate may include a contact layer provided on the body layer and having a p-type impurity concentration higher than that of the body layer, wherein the contact layer may extend parallel to a longitudinal direction of the trench when the semiconductor substrate is viewed from above.

[0050] In the above field effect transistor, the p-type trench lower layer may protrude downward beyond each of the p-type deep layers, thereby enabling the field effect transistor to have a high breakdown voltage.

[0051] In the above field effect transistor, the p-type trench lower layer may be shallower than each of the p-type deep layers, and the field effect transistor can have a low on-resistance.

[0052] In the above field-effect transistor, the semiconductor substrate may further include a drift layer disposed below each of the n-type deep layers and having a lower n-type impurity concentration than each of the n-type deep layers. In other words, each of the n-type deep layers may have a higher n-type impurity concentration than the drift layer. This field-effect transistor can have a low on-resistance.

[0053] In the above field-effect transistor, each of the n-type deep layers may include an n-type deep lower layer and an n-type deep upper layer disposed above the n-type deep lower layer and having a higher n-type impurity concentration than the n-type deep lower layer. In this case, the n-type deep upper layer is disposed above the bottom surface of the trench. This field-effect transistor can achieve both a high breakdown voltage and a low on-resistance.

[0054] In the above-described field-effect transistor, each of the p-type deep layers may include a p-type deep lower layer and a p-type deep upper layer disposed above the p-type deep lower layer and having a higher p-type impurity concentration than the p-type deep lower layer. In this case, the p-type deep upper layer is disposed above the bottom surface of the trench. This field-effect transistor can have a high breakdown voltage while suppressing an increase in leakage current.

[0055] In the above field effect transistor, the depth from the bottom surface of the corresponding trench to the lower surface of each p-type trench lower layer may be the same as the depth from the upper surface of the semiconductor substrate to the lower surface of the body layer. This field effect transistor is a result of the p-type trench lower layer and the body layer being simultaneously formed. This field effect transistor has a structure that can be manufactured at low cost.

[0056] In the above field-effect transistor, the p-type trench lower layer may be spaced apart from the bottom surface of the trench. This field-effect transistor is a configuration that reflects the results of reducing the number of ion implantations into the body layer that is simultaneously formed. This field-effect transistor has a structure that can be manufactured at low cost.

[0057] In the above field-effect transistor, the p-type trench lower layer may have a plurality of portions with different impurity concentrations in the depth direction. The p-type trench lower layer may have a first p-type trench lower layer and a second p-type trench lower layer disposed above the first p-type trench lower layer. The second p-type trench lower layer may have a higher impurity concentration than the first p-type trench lower layer, or may have a lower impurity concentration than the first p-type trench lower layer. Furthermore, the thickness of the second p-type trench lower layer in the depth direction may be smaller than the thickness of the source layer in the depth direction. The feedback capacitance can be adjusted by adjusting the impurity concentration of the p-type trench lower layer.

[0058] In the field-effect transistor, the p-type trench lower layer may be divided along the longitudinal direction of the trench. Each of the p-type deep layers may pass through the divided portion of the p-type trench lower layer. In this field-effect transistor, an increase in leakage current is suppressed.

[0059] In the above field effect transistor, the plurality of n-type deep layers may extend from a lower surface of the body layer to a position lower than lower surfaces of the plurality of p-type deep layers.

[0060] In the field effect transistor, the first direction may be perpendicular to the trench when the semiconductor substrate is viewed from above.

[0061] The present specification discloses a method for manufacturing a field effect transistor, comprising: a deep layer forming step of forming a plurality of p-type deep layers and a plurality of n-type deep layers in an n-type epitaxial layer, wherein each of the p-type deep layers extends along a first direction when the epitaxial layer is viewed from above, and is arranged with gaps in a second direction perpendicular to the first direction when the epitaxial layer is viewed from above, and each of the n-type deep layers is arranged within the corresponding gap; and a deep layer forming step of forming the plurality of p-type deep layers and the plurality of n-type deep layers from the surface of the epitaxial layer. The method can include a trench formation step of forming a trench having a depth not exceeding a dope layer, the trench intersecting the plurality of p-type deep layers and the plurality of n-type deep layers when the epitaxial layer is viewed from above; a body layer formation step of introducing p-type impurities toward the surface of the epitaxial layer using ion implantation technology to form a body layer above the plurality of p-type deep layers and the plurality of n-type deep layers; and a p-type trench lower layer formation step of forming a p-type trench lower layer below the bottom surface of the trench using ion implantation technology.

[0062] In the deep layer forming step, the plurality of p-type deep layers and the plurality of n-type deep layers may be formed by introducing n-type impurities and p-type impurities into a predetermined depth range away from the surface of the epitaxial layer using an ion implantation technique. This manufacturing method allows a field effect transistor to be manufactured without performing a re-epi process.

[0063] The body layer forming step and the p-type trench lower layer forming step may be performed simultaneously after the trench forming step. According to this manufacturing method, a field effect transistor can be manufactured at low cost.

[0064] The manufacturing method may further include a source layer formation step of introducing n-type impurities into an upper layer portion of the epitaxial layer using ion implantation technology to form a source layer. In this case, the p-type trench lower layer may include a first p-type trench lower layer and a second p-type trench lower layer disposed above the first p-type trench lower layer. The second p-type trench lower layer may have a higher impurity concentration than the first p-type trench lower layer, or a lower impurity concentration than the first p-type trench lower layer. The second p-type trench lower layer may have a smaller depth thickness than the source layer. This manufacturing method allows for the manufacture of a field-effect transistor with an adjusted feedback capacitance by adjusting the impurity concentration of the p-type trench lower layer.

[0065] The p-type trench lower layer forming step may be performed before the trench forming step. In this case, the width of the p-type trench lower layer may be narrower than the width of the trench. This manufacturing method allows for slight misalignment between the p-type trench lower layer and the trench.

[0066] The p-type trench lower layer forming step may be performed simultaneously with the step of forming the plurality of p-type deep layers in the deep layer forming step. According to this manufacturing method, a field effect transistor can be manufactured at low cost.

[0067] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0068] 10: MOSFET, 12: semiconductor substrate, 14: trench, 16: gate insulating film, 18: gate electrode, 20: interlayer insulating film, 22: source electrode, 24: drain electrode, 30: source layer, 32: contact layer, 34: body layer, 35: p-type trench lower layer, 36: p-type deep layer, 37: n-type deep layer, 38: drift layer, 40: drain layer

Claims

1. A field effect transistor (10), a semiconductor substrate (12) having a trench (14) formed on its upper surface; a gate insulating film (16) covering the inner surface of the trench; a gate electrode (18) disposed in the trench and insulated from the semiconductor substrate by the gate insulating film; and The semiconductor substrate is an n-type source layer (30) in contact with the gate insulating film on the side surface of the trench; a p-type body layer (34) in contact with the gate insulating film on the side surface of the trench located below the source layer; a p-type trench lower layer (35) disposed below the trench and extending along the longitudinal direction of the trench when the semiconductor substrate is viewed from above; a plurality of deep p-type layers (36); a plurality of n-type deep layers (37); and each of the p-type deep layers protrudes downward from the body layer, extends from the body layer to a position lower than the bottom surface of the trench, extends along a first direction intersecting the trench when the semiconductor substrate is viewed from above, is disposed with an interval therebetween in a second direction perpendicular to the first direction when the semiconductor substrate is viewed from above, and is in contact with the p-type trench lower layer disposed below the trench; each n-type deep layer is disposed in the corresponding gap and is in contact with the gate insulating film at the side surface of the trench located below the body layer; Field effect transistor.

2. The field effect transistor according to claim 1 , wherein the source layer extends parallel to a longitudinal direction of the trench when the semiconductor substrate is viewed from above.

3. The semiconductor substrate is a contact layer (32) provided on the body layer and having a p-type impurity concentration higher than that of the body layer; 3. The field effect transistor according to claim 1, wherein the contact layer extends parallel to a longitudinal direction of the trench when the semiconductor substrate is viewed from above.

4. Each of the n-type deep layers is an n-type deep lower layer (137A); an n-type deep upper layer (137B) disposed above the n-type deep lower layer and having a higher n-type impurity concentration than the n-type deep lower layer; and 4. The field effect transistor according to claim 1, wherein the n-type deep upper layer is disposed above a bottom surface of the trench.

5. Each of the p-type deep layers is a p-type deep lower layer (136A); a p-type deep upper layer (136B) disposed above the p-type deep lower layer and having a higher p-type impurity concentration than the p-type deep lower layer; and 5. The field effect transistor according to claim 1, wherein the p-type deep upper layer is disposed above a bottom surface of the trench.

6. The depth from the bottom surface of the corresponding trench to the lower surface of each p-type trench lower layer is the same as the depth from the upper surface of the semiconductor substrate to the lower surface of the body layer. A field effect transistor according to any one of claims 1 to 5.

7. The field effect transistor of claim 6 , wherein the p-type trench underlayer is spaced from a bottom surface of the trench.

8. 7. The field effect transistor according to claim 6, wherein the p-type trench lower layer has a plurality of portions with different concentrations in the depth direction.

9. The p-type trench lower layer is a first p-type trench lower layer (135A); a second p-type trench lower layer (135B) disposed above the first p-type trench lower layer; and The field effect transistor according to claim 8 , wherein the second p-type trench lower layer is more highly doped than the first p-type trench lower layer.

10. The p-type trench lower layer is a first p-type trench lower layer (135A); a second p-type trench lower layer (135B) disposed above the first p-type trench lower layer; and The field effect transistor according to claim 8 , wherein the second p-type trench lower layer has a lower concentration than the first p-type trench lower layer.

11. 11. The field effect transistor according to claim 9, wherein the thickness of the second p-type trench lower layer in the depth direction is smaller than the thickness of the source layer in the depth direction.

12. the p-type trench lower layer is divided along the longitudinal direction of the trench, 12. The field effect transistor according to claim 1, wherein each of the p-type deep layers passes through a divided portion of the p-type trench lower layer.

13. A method for manufacturing a field effect transistor (10), comprising the steps of: a deep layer formation step of forming a plurality of p-type deep layers (36) and a plurality of n-type deep layers (37, 137) in an n-type epitaxial layer (50), wherein each of the p-type deep layers extends along a first direction when the epitaxial layer is viewed from above, and is arranged with gaps in a second direction perpendicular to the first direction when the epitaxial layer is viewed from above, and each of the n-type deep layers is arranged in a corresponding gap; a trench formation step of forming trenches (14) from the surface of the epitaxial layer to a depth not exceeding the plurality of p-type deep layers and the plurality of n-type deep layers, the trenches intersecting the plurality of p-type deep layers and the plurality of n-type deep layers when the epitaxial layer is viewed from above; a body layer formation step of introducing p-type impurities toward a surface of the epitaxial layer using an ion implantation technique to form a body layer (34) above the plurality of p-type deep layers and the plurality of n-type deep layers; a p-type trench lower layer formation step of forming a p-type trench lower layer (35) below the bottom surface of the trench using ion implantation technology; A method for manufacturing a field effect transistor comprising:

14. 14. The method for manufacturing a field effect transistor according to claim 13, wherein in the deep layer formation step, the plurality of p-type deep layers and the plurality of n-type deep layers are formed by introducing n-type impurities and p-type impurities into a predetermined depth range away from the surface of the epitaxial layer using ion implantation technology.

15. 15. The method for manufacturing a field effect transistor according to claim 13, wherein the body layer forming step and the p-type trench lower layer forming step are performed simultaneously after the trench forming step.

16. The method further includes a source layer formation step of introducing an n-type impurity into an upper layer portion of the epitaxial layer using an ion implantation technique to form a source layer (30), The p-type trench lower layer is a first p-type trench lower layer (135A); a second p-type trench lower layer (135B) disposed above the first p-type trench lower layer; and the second p-type trench lower layer has a higher concentration than the first p-type trench lower layer, The method for manufacturing a field effect transistor according to claim 15 , wherein the thickness of the second p-type trench lower layer in the depth direction is smaller than the thickness of the source layer in the depth direction.

17. a source layer formation step of introducing an n-type impurity into an upper layer portion of the epitaxial layer using an ion implantation technique to form a source layer; The p-type trench lower layer is a first p-type trench lower layer (135A); a second p-type trench lower layer (135B) disposed above the first p-type trench lower layer; and the second p-type trench lower layer has a lower concentration than the first p-type trench lower layer, The method for manufacturing a field effect transistor according to claim 15 , wherein the thickness of the second p-type trench lower layer in the depth direction is smaller than the thickness of the source layer in the depth direction.

18. the p-type trench lower layer forming step is performed before the trench forming step, The method for manufacturing a field effect transistor according to claim 13 or 14, wherein the width of the p-type trench lower layer is narrower than the width of the trench.

19. 19. The method for manufacturing a field effect transistor according to claim 18, wherein the p-type trench lower layer forming step is performed simultaneously with the step of forming the plurality of p-type deep layers in the deep layer forming step.

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