Semiconductor device

Abstract

To improve an operation reliability of a logic circuit through diagnosis of a logic circuit.SOLUTION: A semiconductor device (1) comprises: a logic circuit (110); and a diagnostic circuit (120) configured to perform diagnostic process for diagnosing whether the logic circuit can operate normally based on output data of the logic circuit when a test pattern is supplied to the logic circuit. The diagnostic circuit performs a plurality of diagnostic processes with operation conditions of the logic circuit being different from each other.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Built-in self-test (BIST) is a well-known design technique for circuit testability. BIST for logic circuits is sometimes called logic BIST. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-165780

[0004] [overview] In semiconductor devices that have logic circuits and are capable of BIST, the logic circuits are checked for normal operation by BIST diagnosis at startup. However, current BIST diagnostic techniques are not always sufficient from the viewpoint of ensuring reliability.

[0005] A semiconductor device according to one aspect of the present disclosure includes a logic circuit and a diagnostic circuit configured to perform diagnostic processing to diagnose whether the logic circuit is in a state in which it can operate normally based on output data of the logic circuit when a test pattern is supplied to the logic circuit, and the diagnostic circuit executes multiple diagnostic processing operations in which the operating conditions of the logic circuit are different from one another. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure and its surroundings. [Figure 2] FIG. 2 is a partial block diagram of a semiconductor device according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is an operation flowchart of the semiconductor device according to the embodiment of the present disclosure. [Figure 4] FIG. 4 is a flowchart of a diagnostic sequence operation according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is an explanatory diagram of three diagnostic operation conditions according to a first example of an embodiment of the present disclosure. [Figure 6] FIG. 6 is an explanatory diagram of five diagnostic operation conditions according to a second example of the embodiment of the present disclosure. [Figure 7] FIG. 7 is an explanatory diagram of two diagnostic operation conditions according to a third example of the embodiment of the present disclosure. [Figure 8] FIG. 8 is a configuration diagram of a drive voltage generating circuit according to a seventh example of the embodiment of the present disclosure. [Figure 9] FIG. 9 is a diagram showing the relationship between control signals and drive voltages according to a seventh example of the embodiment of the present disclosure. [Figure 10] FIG. 10 is a configuration diagram of a circuit that generates and outputs a control signal according to a seventh example belonging to an embodiment of the present disclosure. [Figure 11] FIG. 11 is a configuration diagram of an oscillator according to an eighth example of the embodiment of the present disclosure. [Figure 12] FIG. 12 is a diagram showing the relationship between control signals and clock frequencies according to an eighth example of the embodiment of the present disclosure. [Figure 13] FIG. 13 is a configuration diagram of a circuit that generates and outputs a control signal according to an eighth example belonging to the embodiment of the present disclosure. [Figure 14] FIG. 14 is a schematic configuration diagram of a power supply device according to a ninth example belonging to the embodiments of the present disclosure. [Figure 15] FIG. 15 is a schematic configuration diagram of a power supply device according to a ninth example belonging to an embodiment of the present disclosure. [Figure 16] FIG. 16 is a configuration diagram of one regulator according to a ninth example belonging to the embodiment of the present disclosure.

[0007] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings referred to, the same parts are given the same reference numerals, and duplicated explanations of the same parts will be omitted as a general rule. In this specification, for the sake of simplicity, by using symbols or signs that refer to information, signals, physical quantities, functional units, circuits, elements, or parts, the names of the information, signals, physical quantities, functional units, circuits, elements, or parts corresponding to the symbols or signs may be omitted or abbreviated. For example, in the case of "VDD" described later, HIGH The high-side voltage, referred to by " (see Figure 5), is the high-side voltage VDD HIGH It may also be written as voltage VDD HIGH They may be abbreviated as "," but they all refer to the same thing.

[0008] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having a reference potential of 0 V (zero volts), or refers to the 0 V potential itself. The reference conductor may be formed using a conductor such as metal. The 0 V potential is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a specific reference represents a potential seen from ground. Level refers to the level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level.

[0009] For any transistor configured as a FET (field-effect transistor), such as a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Additionally, unless otherwise specified, the back gate of any MOSFET can be considered shorted to the source.

[0010] Any switch can be constituted by one or more FETs (field effect transistors). When a certain switch is in the on state, the two ends of the switch are conductive, while when a certain switch is in the off state, the two ends of the switch are non-conductive. Hereinafter, for any transistor or switch, the on state and the off state may also be simply expressed as on and off.

[0011] The connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection unless otherwise specified.

[0012] When any two voltages to be compared are voltage v1 and voltage v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0013] FIG. 1 shows a semiconductor device 1 according to an embodiment of the present disclosure and its peripheral configuration. The semiconductor device 1 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) accommodating the semiconductor chip, and a plurality of external terminals exposed from the housing to the outside of the semiconductor device 1. The semiconductor device 1 is formed by encapsulating the semiconductor chip in a housing (package) made of resin. In FIG. 1, only the power supply terminal PIN and the ground terminal GND included in the plurality of external terminals are shown, but other external terminals are also provided in the semiconductor device 1. Incidentally, the wiring provided outside the semiconductor device 1 may be particularly referred to as external wiring.

[0014] An MPU2 (Micro Processing Unit) is an example of an external device provided outside the semiconductor device 1. A voltage source 3 is a DC voltage source that outputs a positive DC voltage. A system including the semiconductor device 1 and the MPU2 may be mounted on a vehicle such as an automobile, in which case the voltage source 3 may be a battery mounted on the vehicle. The voltage source 3 is provided between the ground and a first terminal of a switch 4, and a second terminal of the switch 4 is connected to a power supply terminal PIN through an external wiring. An input capacitor 5 is also provided between the second terminal of the switch 4 and the ground. The voltage applied to the power supply terminal PIN is set to a power supply voltage V PW The semiconductor device 1 is connected to a power supply voltage V PW The ground terminal GND is connected to ground.

[0015] When the switch 4 is in the off state and there is no charge stored in the input capacitor 5, the power supply voltage V PW is 0V (zero volts). The power supply voltage V PW Starting from a state where V is 0V, when the switch 4 is switched from the off state to the on state, the power supply voltage V PW rises to the output voltage of voltage source 3. The power supply voltage V PW is a positive predetermined voltage V UVLO When this condition is met, the semiconductor device 1 can be started up. The output voltage of the voltage source 3 is set to a predetermined voltage V UVLO Higher.

[0016] MPU2 is connected to the ground. MPU2 is connected to the power supply voltage V PW2 is supplied, and the power supply voltage V PW2 The power supply voltage V for MPU2 is PW2 is the power supply voltage V PW The power supply voltage V PW2 When a power supply device is formed using the semiconductor device 1, one of the output voltages generated by the power supply device may be a power supply voltage V PW2 It may also be used as.

[0017] The semiconductor device 1 and the MPU 2 are connected to each other via one or more external wirings. The semiconductor device 1 and the MPU 2 may be connected in a manner that allows bidirectional communication. In this case, an SPI (Serial Peripheral Interface) may be used as an interface for bidirectional communication between the semiconductor device 1 and the MPU 2, or an I 2 An interface based on C (Inter-Integrated Circuit) or Microwire can also be used.

[0018] The semiconductor device 1 includes a digital block 10, an analog block 20, an internal power supply circuit 30, and an oscillator 40.

[0019] Digital block 10 is composed of a large number of digital circuits. The digital circuits provided in digital block 10 include at least a sequential circuit that operates in synchronization with a clock signal CLK, and may also include a combinational circuit. A drive voltage VDD, which is a positive DC voltage, is supplied to digital block 10, and each digital circuit in digital block 10 operates based on the drive voltage VDD.

[0020] The analog block 20 is made up of a number of analog circuits. A driving voltage V REG1 is supplied, and each analog circuit in the analog block 20 is driven by a driving voltage V REG1 It operates based on.

[0021] The internal power supply circuit 30 supplies the power supply voltage V PW The internal power supply voltages are generated based on the drive voltages VDD, V REG1 and V REG2 The internal power supply circuit 30 supplies a drive voltage VDD to the digital block 10, and a drive voltage V REG1 is supplied to the analog block 20, and the driving voltage V REG2 is supplied to the oscillator 40. The driving voltages VDD and V REG1 and V REG2Both of these have positive DC voltage values. However, the value of the drive voltage VDD is intentionally changed, albeit temporarily (details will be described later). Here, the voltage supplied to the analog block 20 is set to the drive voltage V REG1 The voltage supplied to the oscillator 40 is called the drive voltage V REG2 However, the driving voltage V REG1 and driving voltage V REG2 The drive voltages VDD and V may be a common voltage. REG1 and V REG2 may all be a common voltage.

[0022] Oscillator 40 operates at a drive voltage of V REG2 The clock signal CLK is generated by performing an oscillation operation based on the clock frequency f and the generated clock signal CLK is supplied to the digital block 10. The clock signal CLK is a square wave signal that alternates between high and low signal levels. The frequency of the clock signal CLK is hereinafter referred to as the clock frequency f CLK It is called.

[0023] 2 shows a schematic internal configuration of the digital block 10. The digital block 10 includes a logic circuit 110 and a diagnostic circuit 120. The logic circuit 110 is the logic circuit that is the target of diagnostic processing (target logic circuit). The diagnostic circuit 120 includes a diagnostic controller 121, a test pattern supply circuit 122, and a determination circuit 123. The diagnostic circuit 120 tests the operation of the logic circuit 110 by executing diagnostic processing on the logic circuit 110. By testing the operation of the logic circuit 110, it is diagnosed whether the logic circuit 110 is in a state where it can operate normally.

[0024] The logic circuit 110 has a sequential circuit SQC that operates in synchronization with the clock signal CLK. However, the logic circuit 110 may also include a combinational circuit that operates asynchronously with the clock signal CLK. The diagnostic controller 121, the test pattern supply circuit 122, and the judgment circuit 123 each have a sequential circuit that operates in synchronization with the clock signal CLK. However, the diagnostic controller 121, the test pattern supply circuit 122, or the judgment circuit 123 may also include a combinational circuit that operates asynchronously with the clock signal CLK. The sequential circuit SQC in the logic circuit 110 includes flip-flops, latch circuits, etc. that operate in synchronization with the clock signal CLK. The same applies to the sequential circuits in the diagnostic controller 121, the test pattern supply circuit 122, or the judgment circuit 123.

[0025] In the diagnostic process, under the control of the diagnostic controller 121, the test pattern supply circuit 122 generates a test pattern and supplies it to the logic circuit 110. The test pattern is data (a bundle of digital signals) useful for diagnosing whether or not there is a fault in the logic circuit 110, and is stored in advance in the diagnostic circuit 120. The test pattern supply circuit 122 supplies the test pattern to the logic circuit 110 in synchronization with the clock signal CLK.

[0026] In the diagnostic process, the logic circuit 110 generates test result data by performing digital signal processing on the supplied test pattern. The test result data is output from the logic circuit 110 to the judgment circuit 123. The digital signal processing is executed in synchronization with the clock signal CLK. That is, the digital signal processing is executed using a sequential circuit SQC that operates in synchronization with the clock signal CLK. In the diagnostic process, the logic circuit 110 outputs the test result data to the judgment circuit 123 in synchronization with the clock signal CLK. In the diagnostic process, the judgment circuit 123 can determine whether or not there is a fault in the logic circuit 110 by comparing the test result data with expected data. The expected data is stored in advance in the diagnostic circuit 120 as data corresponding to the test pattern.

[0027] A state in which the logic circuit 110 operates normally (a state in which the logic circuit 110 operates as designed) is called a normal state. A state in which the logic circuit 110 does not operate normally (a state in which the logic circuit 110 cannot operate as designed) is called an abnormal state. The abnormal state corresponds to a state in which normal operation of the logic circuit 110 cannot be guaranteed.

[0028] The expected data corresponds to normal data that is expected to be obtained from the logic circuit 110 when a test pattern is supplied to the logic circuit 110. Therefore, when a test pattern is supplied to the logic circuit 110 in a normal state during diagnostic processing, the test result data matches the expected data. When a test pattern is supplied to the logic circuit 110 in an abnormal state during diagnostic processing, the test result data does not match the expected data. When the test result data matches the expected data, the determination circuit 123 can determine that there is no fault in the logic circuit 110 (i.e., the logic circuit 110 is in a normal state). When the test result data differs from the expected data, the determination circuit 123 can determine that there is a fault in the logic circuit 110 (i.e., the logic circuit 110 is in an abnormal state).

[0029] As a unique operation, the diagnostic circuit 120 performs multiple diagnostic processes under different operating conditions for the logic circuit 110. Each diagnostic process is a built-in self-test (BIST), and each diagnostic process can be realized using BIST technology. BIST using a scan test can be used for each diagnostic process. Note that BIST for logic circuits is called logic BIST. Because BIST itself is well known, detailed explanations of each diagnostic process will be omitted, and explanations of the internal configuration of the logic circuit 110 will also be omitted.

[0030] The diagnostic circuit 120 performs first to n-th diagnostic processes as the multiple diagnostic processes. n represents any integer equal to or greater than 2. The operating conditions of the logic circuit 110 in the ith diagnostic process are referred to as the ith diagnostic operating conditions. i represents any integer. That is, the diagnostic circuit 120 performs the first diagnostic process with the operating conditions of the logic circuit 110 set to the first diagnostic operating conditions, and performs the second diagnostic process with the operating conditions of the logic circuit 110 set to the second diagnostic operating conditions. When "n≧3", the same applies to the third to n-th diagnostic processes. The diagnostic circuit 120 diagnoses whether the logic circuit 110 is in a state in which it can operate normally, based on the results of the first to n-th diagnostic processes.

[0031] 3 shows an operation flowchart of the semiconductor device 1. First, in step S1, the semiconductor device 1 is in a shutdown state. In the shutdown state, the semiconductor device 1 is not activated. In the shutdown state, the power supply voltage V PW is 0V (or a predetermined voltage V UVLO An enable terminal (not shown) that receives an enable signal having a value of "0" or "1" may be provided as one of the external terminals of the semiconductor device 1. In this case, the power supply voltage V PW Regardless of the above, a state in which an enable signal having a value of "0" (for example, an enable signal of 0V) is supplied to the enable terminal may also belong to the shutdown state.

[0032] When the start-up condition is met (Y in step S2) from the shutdown state, the transition to step S3 occurs. The start-up condition is the power supply voltage V PW is the specified voltage V UVLO From a lower voltage to a given voltage V UVLO When the enable terminal is provided in the semiconductor device 1, the power supply voltage V PW is the specified voltage V UVLO The start condition is met when the value of the enable signal changes from "0" to "1" assuming that the value is "1" or higher. PW is the specified voltage V UVLO From a lower voltage to a given voltage V UVLOBy transitioning to the above state, the start condition is met. For example, when the predetermined voltage V UVLO The value of the enable signal having a level above this is "1", and the predetermined voltage V UVLO The value of the enable signal having a level less than may be "0".

[0033] In step S3, the internal power supply circuit 30 supplies the drive voltages VDD and V REG1 and V REG2 The generated drive voltage VDD is supplied to the digital block 10. After the start of the internal power supply voltage generation operation, the drive voltage VDD is maintained at a predetermined reference voltage VDD , except for the period during which the diagnostic sequence operation described below is executed. REF Furthermore, in step S3, the driving voltage V REG2 The generated clock signal CLK is supplied to the digital block 10. After the start of the clock signal CLK generation operation, the clock frequency f CLK is the given reference frequency f REF After step S3, the process proceeds to step S4.

[0034] In step S4, the diagnostic circuit 120 executes a diagnostic sequence operation. A plurality of diagnostic processes are executed in the diagnostic sequence operation. Details of the diagnostic sequence operation will be described later, but during the diagnostic sequence operation, a value of "0" or "1" is set to the flag FLG managed by the diagnostic circuit 120. After the diagnostic sequence operation in step S4, in step S5, the diagnostic controller 121 checks whether the value of the flag FLG is "0." If the value of the flag FLG is "0" (Y in step S5), the process proceeds from step S5 to step S6, and if the value of the flag FLG is "1" (N in step S5), the process proceeds from step S5 to step S10.

[0035] In step S6, a predetermined functional operation is started by the functional circuit provided in the semiconductor device 1. Before reaching step S6, the functional operation is in a non-executing state. The functional circuit includes the logic circuit 110 and each analog circuit in the analog block 20 as components. Therefore, the functional operation is executed using the logic circuit 110. The content of the functional operation varies depending on the type of semiconductor device 1.

[0036] When the functional operation is started, the state of the semiconductor device 1 reaches the normal operation state in step S6. In the normal operation state, the functional operation is continuously executed. In principle, "VDD = VDD REF The semiconductor device 1 is configured so that the drive voltage VDD is equal to or lower than the reference voltage VDD only during the execution of the diagnostic sequence operation. REF In principle, the CLK =f REF The semiconductor device 1 is configured so that the clock frequency f CLK is the reference frequency f REF When the diagnostic sequence operation is completed (when all diagnostic processes are completed in the diagnostic sequence operation), the drive voltage VDD is changed by the logic circuit 110 to the reference voltage VDD REF and the clock frequency f CLK is the reference frequency f REF Therefore, in normal operation, the drive voltage VDD is fixed to the reference voltage VDD REF and the clock frequency f CLK is the reference frequency f REF Matches.

[0037] In step S7 following step S6, it is determined whether the stop condition is met in the semiconductor device 1. If the stop condition is met in step S7 (Y in step S7), a transition from step S7 to step S8 occurs, and the functional circuit stops its functional operation in step S8, and then the process proceeds to step S9. If the stop condition is not met (N in step S7), the normal operating state of the semiconductor device 1 is maintained, and thereafter the determination process of step S7 is repeated. The stop condition isPW is the specified voltage V UVLO From the above state, a predetermined voltage V UVLO If the enable terminal is provided in the semiconductor device 1, the stop condition is also met when the value of the enable signal changes from "1" to "0."

[0038] In step S9, the oscillator 40 stops generating the clock signal CLK, and subsequently or simultaneously, the internal power supply circuit 30 stops generating the internal power supply voltage. As the internal power supply circuit 30 stops generating the internal power supply voltage, the state of the semiconductor device 1 returns to the shutdown state. Stopping the internal power supply circuit 30 from generating the internal power supply voltage corresponds to transitioning to step S1.

[0039] In step S10, the diagnostic circuit 120 performs a predetermined error handling process. However, the entity that executes the error handling process may be an error handling circuit (not shown) provided in the semiconductor device 1, different from the diagnostic circuit 120. In the error handling process, an error signal is sent to the MPU 2. Also, in the error handling process, the diagnostic circuit 120 may store error flag data indicating that an abnormality has been detected in the logic circuit 110 in a memory (not shown) in the semiconductor device 1. Upon receiving the error signal, the MPU 2 can read the data in the memory by sending a command to the semiconductor device 1 to read the data in the memory, and the state of the semiconductor device 1 can be determined from the read data (including the error flag data). When the error handling process is performed, the above-mentioned functional operations are not executed. If the process proceeds to step S10, the semiconductor device 1 is transitioned to a shutdown state, and the process returns to step S1.

[0040] 4 shows a flowchart of the diagnostic sequence operation. In the diagnostic sequence operation, the process of step S41 is first executed. In step S41, the diagnostic controller 121 assigns "1" to a variable i that it manages. Then, the process proceeds to step S42.

[0041] In step S42, the i-th diagnostic process is executed by the diagnostic circuit 120. The i-th diagnostic process is executed in a state where the operating conditions of the logic circuit 110 are set to the i-th diagnostic operating conditions. A and i B are different natural numbers less than or equal to n, then the i A Diagnostic operating conditions and the first B The drive voltage VDD is different from the diagnostic operating conditions, or the clock frequency f CLK Alternatively, the drive voltage VDD and the clock frequency f CLK Each of the i A Diagnostic operating conditions and the first B The diagnostic controller 121 controls the operating states of the internal power supply circuit 30 and the oscillator 40 to set the i-th diagnostic operating condition.

[0042] In the i-th diagnostic processing, under the control of the diagnostic controller 121, the test pattern supply circuit 122 generates a test pattern and supplies it to the logic circuit 110. The test pattern supply circuit 122 supplies the test pattern to the logic circuit 110 in synchronization with the clock signal CLK. In the i-th diagnostic processing, the logic circuit 110 generates test result data by performing digital signal processing on the supplied test pattern. As described above, the digital signal processing is executed in synchronization with the clock signal CLK. That is, the digital signal processing is executed using a sequential circuit SQC that operates in synchronization with the clock signal CLK. In the i-th diagnostic processing, the logic circuit 110 outputs test result data to the judgment circuit 123 in synchronization with the clock signal CLK. In the i-th diagnostic processing, the judgment circuit 123 compares the test result data with expected data.

[0043] After step S42, the process proceeds to step S43. In step S43, the diagnostic controller 121 determines whether the value of the variable i matches the value of n. If "i=n" is true (Y in step S43), the process proceeds from step S43 to step S45. If "i=n" is not true (N in step S43), the process proceeds from step S43 to step S44. In step S44, the diagnostic controller 121 adds "1" to the variable i, and then the process returns to step S42 and executes the process of step S42 again. Therefore, by the time the process proceeds to step S45, the execution of the first to nth diagnostic processes has been completed.

[0044] In step S45, the diagnostic controller 121 evaluates the comparison results of the determination circuit 123 in the first to nth diagnostic processes. In step S45, it is determined whether the test result data matches the expected data in each of the first to nth diagnostic processes. Only if the test result data matches the expected data in each of the first to nth diagnostic processes (Y in step S45), does the process proceed from step S45 to step S46. If the test result data does not match the expected data in one or more of the first to nth diagnostic processes (N in step S45), the process proceeds from step S45 to step S47.

[0045] Therefore, for example, when "n=3", the process proceeds to step S46 only when the test result data in the first diagnostic process matches the expected data, the test result data in the second diagnostic process matches the expected data, and the test result data in the third diagnostic process matches the expected data, and otherwise the process proceeds to step S47. The same applies when the value of n is other than 3.

[0046] In step S46, the diagnostic controller 121 sets the flag FLG to a value of "0." In step S47, the diagnostic controller 121 sets the flag FLG to a value of "1." After the setting in step S46 or S47 is completed, the diagnostic sequence operation ends.

[0047] "FLG = 0" at the end of the diagnostic sequence operation is the first result data derived by the diagnostic circuit 120. The first result data indicates that the logic circuit 110 is in a normal state and that the normal operation of the logic circuit 110 can be ensured even if there are some fluctuations in the drive voltage VDD or the clock frequency f CLK This indicates that. "FLG = 1" at the end of the diagnostic sequence operation is the second result data derived by the diagnostic circuit 120. The second result data indicates that the logic circuit 110 is in an abnormal state or that the normal operation of the logic circuit 110 cannot be ensured when there are fluctuations in the drive voltage VDD or the clock frequency f CLK Although each individual diagnostic process can be said to diagnose whether the logic circuit 110 can operate normally, the diagnostic circuit 120 according to the present embodiment tests the operation of the logic circuit 110 through a diagnostic sequence operation consisting of a plurality of diagnostic processes, and thereby diagnoses whether the logic circuit 110 is in a state where it can operate normally.

[0048] Note that, although different from the flow of the flowchart in FIG. 4, after the start of the diagnostic sequence operation, if the determination circuit 123 detects that the test result data does not match the expected data in the i-th diagnostic process while "i < n" holds, the diagnostic controller 121 may set the value "1" in the flag FLG and end the diagnostic sequence operation at the detection time.

[0049] In many reference semiconductor devices different from the semiconductor device 1, the following reference method is often adopted. In the reference method, BIST is executed while operating the logic circuit under typical single operating conditions (typical operating conditions), and thereby the presence or absence of a failure in the logic circuit is diagnosed. However, after the start of the functional operation using the logic circuit through BIST, the drive voltage or the clock frequency supplied to the logic circuit may fluctuate from the above single operating conditions due to the influence of noise or the like. The reference method cannot ensure that the logic circuit can maintain normal operation against such fluctuations.

[0050] In contrast to this, in the semiconductor device 1 according to this embodiment, the first to n-th diagnostic processes are performed while changing the operating conditions of the logic circuit 110, and the quality of the logic circuit 110 is judged based on the results of the processes (the first result data or the second result data is derived). Therefore, after the above-mentioned first result data is derived and functional operation is started, the drive voltage VDD or the clock frequency f CLK Even if there is some variation in the voltage, the normal operation of the logic circuit 110 is guaranteed (or there is a high possibility that this will be guaranteed), and therefore the semiconductor device 1 can have high reliability.

[0051] Below, several specific operation examples, application techniques, modified techniques, etc. related to the semiconductor device 1 will be described in multiple embodiments. The matters described above in this embodiment are applied to each of the following embodiments unless otherwise specified and unless there is a contradiction. If there are any matters in each embodiment that contradict the matters described above, the description in each embodiment may take precedence. Furthermore, unless there is a contradiction, matters described in any of the multiple embodiments described below can also be applied to any other embodiment (i.e., any two or more of the multiple embodiments can be combined).

[0052] <<First Example>> A first embodiment will be described. In the first embodiment, "n=3". The first to third diagnostic operation conditions are diagnostic operation conditions α REF , α LL and α HH For example, the first, second, and third diagnostic operating conditions are respectively composed of the diagnostic operating condition α REF , α LL , α HH Alternatively, the diagnostic operation condition α REF , α HH , α LL Alternatively, the diagnostic operation condition α LL , α REF , α HH Alternatively, the diagnostic operation condition α HH , α REF , α LL In addition, the diagnostic operation condition α REF , α LL and α HHThe assignment relationship between the first diagnostic operation condition and the first to third diagnostic operation conditions is arbitrary.

[0053] The first, second, and third diagnostic operation conditions are respectively diagnostic operation conditions α REF , α LL , α HH In the case where the diagnostic sequence operation is assigned to the REF The first diagnostic process is first executed under the diagnostic operation condition α LL The second diagnostic process is executed second, and the diagnostic operation condition α HH The third diagnostic process is executed third. The first, second, and third diagnostic operation conditions are respectively the diagnostic operation condition α HH , α REF , α LL In the case where the diagnostic sequence operation is assigned to the HH The first diagnostic process is first executed under the diagnostic operation condition α REF The second diagnostic process is executed second, and the diagnostic operation condition α LL The third diagnostic process is executed third. REF , α LL and α HH The same applies to cases where the assignment relationship between the first to third diagnostic operation conditions is different from the above cases.

[0054] Figure 5 shows the diagnostic operation condition α REF , α LL and α HH The details of the diagnostic operation condition α are shown below. REF are the same as the operating conditions of the logic circuit 110 in the normal operating state (see step S6 in FIG. 3). REF In this case, the drive voltage VDD is the reference voltage VDD REF coincides with the clock frequency f CLK is the reference frequency f REF The diagnostic operation condition α LL In this case, the drive voltage VDD is the low-side voltage VDD LOW coincides with the clock frequency f CLK is the low frequency f LOW The diagnostic operation condition α HHIn this case, the drive voltage VDD is the high-side voltage VDD HIGH coincides with the clock frequency f CLK is the high frequency f HIGH matches.

[0055] Low side voltage VDD LOW , reference voltage VDD REF and high-side voltage VDD HIGH is "0 <VDD LOW <VDD REF <VDD HIGH " are three positive predetermined voltages that satisfy the following conditions, for example, 1.3V (volts), 1.5V, and 1.7V, respectively. LOW , reference frequency f REF , high frequency f HIGH is "0 <f LOW <f REF <f HIGH " are three predetermined frequencies that satisfy the condition, for example, 0.8 MHz (megahertz), 1.0 MHz, and 1.2 MHz, respectively. The diagnostic controller 121 can vary the drive voltage VDD by controlling the operating state of the internal power supply circuit 30. The diagnostic controller 121 can vary the clock frequency f by controlling the operating state of the oscillator 40. CLK can be varied in various ways.

[0056] Diagnostic operation condition α REF is the same as the operating condition of the logic circuit 110 in the normal operating state, so the diagnostic operating condition α REF By executing the diagnostic process by the above, it is possible to accurately determine whether the logic circuit 110 can operate normally under normal operating conditions.

[0057] clock frequency f CLK A decrease in the drive voltage VDD directly leads to a decrease in the operating speed of the logic circuit 110, and a decrease in the drive voltage VDD also acts to decrease the operating speed of the logic circuit 110. Therefore, the diagnostic operating condition α LL Then, the diagnostic operation condition α REF From the viewpoint of the drop in the drive voltage VDD and the clock frequency f CLK The operating speed of the logic circuit 110 decreases due to the decrease in the diagnostic operating condition α LLBy executing the diagnostic process by the drive voltage VDD and the clock frequency f CLK It is possible to evaluate whether the normal operation of the logic circuit 110 (and therefore the normal operation of the functions) is guaranteed even if the voltage drops.

[0058] clock frequency f CLK An increase in the drive voltage VDD directly leads to an increase in the operating speed of the logic circuit 110, and an increase in the drive voltage VDD acts in the direction of increasing the operating speed of the logic circuit 110. Therefore, the diagnostic operating condition α HH Then, the diagnostic operation condition α REF From the viewpoint of the rise in the drive voltage VDD and the clock frequency f CLK The operating speed of the logic circuit 110 increases as the diagnostic operating condition α HH By executing the diagnostic process by the above, the drive voltage VDD and the clock frequency f are increased in a direction that increases the operating speed of the logic circuit 110 during the execution period of the functional operation. CLK It is possible to evaluate whether the normal operation of the logic circuit 110 (and therefore the normal operation of the functions) is guaranteed even if the voltage rises.

[0059] <<Second Example>> A second embodiment will be described. In the second embodiment, "n=5". The first to fifth diagnostic operation conditions are the diagnostic operation conditions α REF , α LL , α HH , α LH , α HL For example, the first, second, third, fourth, and fifth diagnostic operating conditions are respectively composed of the diagnostic operating conditions α REF , α LL , α HH , α LH , α HL Alternatively, the diagnostic operation condition α REF , α HH , α LL , α HL , α LH Alternatively, the diagnostic operation condition α LL , α REF , α HH , α LH , α HLAlternatively, the diagnostic operation condition α HH , α REF , α LL , α HL , α LH In addition, the diagnostic operation condition α REF , α LL , α HH , α LH , α HL The assignment relationship between the first to fifth diagnostic operation conditions is arbitrary.

[0060] The first, second, third, fourth, and fifth diagnostic operation conditions are respectively diagnostic operation conditions α REF , α LL , α HH , α LH , α HL In the case where the diagnostic sequence operation is assigned to the REF The first diagnostic process is first executed under the diagnostic operation condition α LL , α HH , α LH , α HL The second, third, fourth, and fifth diagnostic processes are executed in this order. The first, second, third, fourth, and fifth diagnostic operation conditions are respectively set to the diagnostic operation condition α HH , α REF , α LL , α HL , α LH In the case where the diagnostic sequence operation is assigned to the HH The first diagnostic process is first executed under the diagnostic operation condition α REF , α LL , α HL , α LH The second, third, fourth, and fifth diagnostic processes are executed in this order. REF , α LL , α HH , α LH , α HL The same applies to cases where the assignment relationship between the first to fifth diagnostic operation conditions is different from the above cases.

[0061] Figure 6 shows the diagnostic operation condition α REF , α LL , αHH , α LH and α HL The details of these five operating conditions are shown below. REF , α LL and α HH The contents of the diagnostic operation condition α are as described in the first embodiment. LH In this case, the drive voltage VDD is the low-side voltage VDD LOW coincides with the clock frequency f CLK is the high frequency f HIGH The diagnostic operation condition α HL In this case, the drive voltage VDD is the high-side voltage VDD HIGH coincides with the clock frequency f CLK is the low frequency f LOW As described in the first embodiment, "0 <VDD LOW <VDD REF <VDD HIGH " and "0 <f LOW <f REF <f HIGH " is satisfied.

[0062] Diagnostic operation condition α REF , α LL and α HH The significance of executing the diagnostic processing according to the first embodiment is as described in the first embodiment. In the second embodiment, diagnostic processing under two operating conditions is further added, which is expected to further improve reliability. However, since the time required to execute the diagnostic sequence operation increases as the value of n increases, if shortening the execution time of the diagnostic sequence operation is given priority, the first embodiment is preferable to the second embodiment.

[0063] <<Third Example>> A third embodiment will be described. In the third embodiment, "n=2". The first and second diagnostic operating conditions are the diagnostic operating conditions α LL and α HH In this case, the first diagnostic operation condition is the diagnostic operation condition α LL and the second diagnostic operating condition is the diagnostic operating condition α HH Alternatively, the first diagnostic operation condition may be the diagnostic operation condition α HHand the second diagnostic operating condition is the diagnostic operating condition α LL It may be.

[0064] The first and second diagnostic operation conditions are diagnostic operation conditions α LL , α HH In the case where the diagnostic sequence operation is assigned to the LL The first diagnostic process is first executed under the diagnostic operation condition α HH The second diagnostic process is executed second. The first and second diagnostic operation conditions are respectively the diagnostic operation condition α HH , α LL In the case where the diagnostic sequence operation is assigned to the HH The first diagnostic process is first executed under the diagnostic operation condition α LL The second diagnostic process is executed second.

[0065] Figure 7 shows the diagnostic operation condition α LL and α HH The details of these two diagnostic operation conditions α LL and α HH The contents of this are as described in the first embodiment.

[0066] Diagnostic operation condition α LL and α HH The significance of executing the diagnostic process using the diagnostic operation condition α is as described in the first embodiment. REF Compared with the diagnostic operating condition α LL In the case where the operating speed of the logic circuit 110 is shifted downward, the diagnostic operating condition α HH In this case, the operating speed of the logic circuit 110 is shifted upward. LL and α HH If it is confirmed that the logic circuit 110 operates normally by executing the diagnostic process under the diagnostic operation condition α, it is expected that the logic circuit 110 will operate normally in the normal operating state. In the second embodiment, the execution time of the diagnostic sequence operation is shortened compared to the first embodiment. However, in the normal operating state, the logic circuit 110 is basically operated under the diagnostic operation condition α REFConsidering that the diagnostic operation condition α REF However, it can be said that it is preferable to carry out diagnostic processing.

[0067] <<Fourth Example>> A fourth embodiment will be described. If "n≧2" and the first to nth diagnostic operating conditions are different from each other, the first to nth diagnostic operating conditions are not limited to those described in the first to third embodiments. For example, if "n=2", the first and second diagnostic operating conditions are the diagnostic operating conditions α REF and α HH Alternatively, the diagnostic operation condition α REF and α LL It is also possible to set "n≧6".

[0068] <<Fifth Example>> A fifth embodiment will be described. A diagnostic controller 121 according to the fifth embodiment operates at a clock frequency f CLK is the reference frequency f REF When “n=3”, one of the first to third diagnostic operation conditions is “VDD=VDD REF " and another diagnostic operating condition is "VDD = VDD LL " and another diagnostic operation condition is "VDD = VDD HH " is all you need to do.

[0069] When “n=2”, one of the first and second diagnostic operation conditions is “VDD=VDD LL " and another diagnostic operating condition is "VDD = VDD HH Or, when "n=2", one of the first and second diagnostic operation conditions may be set to "VDD=VDD REF " and another diagnostic operating condition is "VDD = VDD LL " or "VDD=VDD HH " is all you need to do.

[0070] According to the diagnostic process of the fifth embodiment, even if the drive voltage VDD fluctuates during the execution period of the functional operation, it is possible to evaluate whether the normal operation of the logic circuit 110 (and therefore the normal operation of the functional operation) is guaranteed.

[0071] <<Sixth Example>> A sixth embodiment will be described. A diagnosis controller 121 according to the sixth embodiment sets the drive voltage VDD to the reference voltage VDD in the first to n-th diagnostic processes. REF and the clock frequency f CLK When "n=3", only "f" is varied in one of the first to third diagnostic operation conditions. CLK =f REF " and one other diagnostic operating condition is "f CLK =f LOW " and another diagnostic operating condition is "f CLK =f HIGH " is all you need to do.

[0072] When "n=2", one of the first and second diagnostic operation conditions is "f CLK =f LOW " and one other diagnostic operating condition is "f CLK =f HIGH Or, when "n=2", one of the first and second diagnostic operation conditions may be set to "f CLK =f REF " and one other diagnostic operating condition is "f CLK =f LOW " or "f CLK =f HIGH " is all you need to do.

[0073] According to the diagnostic process of the sixth embodiment, the clock frequency f CLK It is possible to evaluate whether the normal operation of the logic circuit 110 (and therefore the normal operation of the functions) is guaranteed even if the voltage fluctuates.

[0074] <<Seventh Example>> A seventh embodiment will be described. Fig. 8 shows the configuration of a drive voltage generation circuit 31 that generates a drive voltage VDD. The drive voltage generation circuit 31 can be provided in the internal power supply circuit 30. The drive voltage generation circuit 31 includes a DAC 31a and a buffer circuit 31b. The DAC 31a and the buffer circuit 31b are connected to the power supply voltage V PW Driven based on.

[0075] A control signal Sa[3:0] is supplied to the DAC 31a from the digital block 10. The control signal Sa[3:0] may be a signal output by the logic circuit 110. However, during the execution of the diagnostic sequence operation, the content of the control signal Sa[3:0] is determined by the diagnostic controller 121. The control signal Sa[3:0] is a multi-bit digital signal, and is assumed to be a 4-bit digital signal here.

[0076] DAC31a is a digital-to-analog converter that converts the digital control signal Sa[3:0] into an analog signal and outputs it. Buffer circuit 31b generates the drive voltage VDD by converting the impedance of the output signal of DAC31a. That is, buffer circuit 31b outputs the analog signal from DAC31a with sufficiently low impedance. The output signal of buffer circuit 31b functions as the drive voltage VDD. Therefore, the voltage value of the output signal of DAC31a is equal to the value of the drive voltage VDD. Note that the configuration of drive voltage generation circuit 31 shown in FIG. 8 is merely an example. Any drive voltage generation circuit that generates drive voltage VDD in an adjustable manner may be provided in the internal power supply circuit 30.

[0077] Figure 9 shows the relationship between the control signal Sa[3:0] and the drive voltage VDD. The control signal Sa[3:0] is made up of signals Sa[3] to Sa[0]. Each of the signals Sa[3] to Sa[0] is a 1-bit digital signal, and has a value of "0" or "1". For any integer i, the signal Sa[i+1] has a value of the most significant bit than the signal Sa[i]. The value of the control signal Sa[3:0] expressed in decimal notation is represented by the symbol "VAL_Sa[3:0]". Then, "VAL_Sa[3:0]=2 3 ×Sa[3]+22 ×Sa[2]+2 1 ×Sa[1]+2 0 ×Sa[0]”. Then, conversion processing is performed in DAC31a so that the conversion formula “VDD=0.05×VAL_Sa[3:0]+1.15” holds (the unit in this conversion formula is volts).

[0078] Also, here, the reference voltage VDD REF is 1.50V and the low-side voltage VDD LOW is 1.30V and the high-side voltage VDD HIGH Therefore, when the control signal Sa[3:0] that satisfies the following formula (1a) is supplied to the DAC 31a, the drive voltage VDD is equal to the reference voltage VDD REF When the control signal Sa[3:0] that satisfies the following formula (1b) is supplied to the DAC31a, the drive voltage VDD becomes the low-side voltage VDD LOW When the control signal Sa[3:0] that satisfies the following formula (1c) is supplied to the DAC31a, the drive voltage VDD becomes the high-side voltage VDD HIGH matches. (Sa[3],Sa[2],Sa[1],Sa[0])=(0,1,1,1) (1a) (Sa[3],Sa[2],Sa[1],Sa[0])=(0,0,1,1) (1b) (Sa[3],Sa[2],Sa[1],Sa[0])=(1,0,1,1) (1c)

[0079] Therefore, in a normal operation state, the digital block 10 supplies the DAC 31a with a control signal Sa[3:0] that satisfies the formula (1a). During the execution of the diagnostic sequence operation, the diagnostic controller 121 supplies the DAC 31a with a control signal Sa[3:0] that satisfies any one of the formulas (1a), (1b), and (1c) according to the required drive voltage VDD.

[0080] Figure 10 shows the relationship between the drive voltage VDD and the reference voltage VDD REFand the drive voltage VDD is set to the high-side voltage VDD HIGH 10 shows an example of a circuit configuration for setting the normal DAC control circuit 111. The digital block 10 according to the example of FIG. 10 is provided with a normal DAC control circuit 111, a diagnostic DAC control circuit 121a, and a control signal output circuit 130. The normal DAC control circuit 111 and the control signal output circuit 130 are provided within the logic circuit 110 (see FIG. 2). However, the control signal output circuit 130 may be considered to be provided outside the logic circuit 110. The diagnostic DAC control circuit 121a is provided within the diagnostic controller 121. The control signal output circuit 130 includes circuits 131[3], 131[1], and 131[0], which are two-input OR circuits, and circuit 131[2], which is a two-input AND circuit. Each of the circuits 131[3] to 131[0] has a first and second input terminal and an output terminal. For each integer i satisfying "0≦i≦3", a signal Sa[i] is output from the output terminal of the circuit 131[i].

[0081] The normal DAC control circuit 111 outputs a signal Sa[3] to the first input terminals of the circuits 131[3], 131[2], 131[1], and 131[0], respectively. NML , Sa[2] NML , Sa[1] NML , Sa[0] NML The diagnostic DAC control circuit 121a supplies a signal Sa in common to the second input terminals of the circuits 131[3] to 131[0]. BIST Signal Sa[3] NML ~Sa[0] NML and Sa BIST are 1-bit digital signals each having a value of "0" or "1."

[0082] Circuit 131[3] outputs signal Sa[3] NML and Sa BIST If at least one of the signals has a value of "1", the signal Sa[3] is output as "1", and the signal Sa[3] NML and Sa BIST and both have a value of "0", the circuit 131[2] outputs a signal Sa[3] of "0". NML has a value of "1" and the signal Sa BISTThe circuit 131[1] outputs the signal Sa[2] of "1" only if the signal Sa[1] has a value of "0", otherwise it outputs the signal Sa[2] of "0". NML and Sa BIST If at least one of the signals has a value of "1", the signal Sa[1] is output as "1", and the signal Sa[1] NML and Sa BIST If both of the signals Sa[0] and Sa[1] have a value of "0", the circuit 131[0] outputs a signal Sa[1] of "0". NML and Sa BIST If at least one of the signals has a value of "1", a signal Sa[0] of "1" is output, and the signal Sa[0] NML and Sa BIST If both of these have a value of "0", the signal Sa[0] of "0" is output.

[0083] The normal DAC control circuit 111 is a circuit that functions significantly only in the normal operating state. In the normal operating state, the normal DAC control circuit 111 controls the “(Sa[3] NML ,Sa[2] NML ,Sa[1] NML ,Sa[0] NML )=(0,1,1,1)” NML ~Sa[0] NML to the control signal output circuit 130. Meanwhile, the diagnostic DAC control circuit 121a outputs the drive voltage VDD to the high-side voltage VDD HIGH During the period when the signal Sa is set to "1", BIST to the control signal output circuit 130. In the normal operating state, the diagnostic DAC control circuit 121a outputs the signal Sa BIST The value is fixed at "0".

[0084] In this case, the output signals Sa[3] to Sa[0] of the control signal output circuit 130 in the normal operating state are the signal Sa[3] NML ~Sa[0] NML In normal operation, it is determined by "(Sa[3] NML ,Sa[2] NML ,Sa[1] NML ,Sa[0] NML)=(Sa[3],Sa[2],Sa[1],Sa[0])=(0,1,1,1)” so “VDD=VDD REF " (See also Figure 9). On the other hand, "Sa BIST During the period when "=1", the signal Sa[3] NML ~Sa[0] NML Regardless of the logic of the control signal output circuit 130, the output signals Sa[3] to Sa[0] of the control signal output circuit 130 are fixed at "(Sa[3], Sa[2], Sa[1], Sa[0]) = (1, 0, 1, 1)". BIST =1” during which “VDD=VDD HIGH " (See also Figure 9).

[0085] Normally, when the DAC control circuit 111 is a component of the logic circuit 110, the output signal of the circuit 111 may fluctuate in various ways during the execution of the diagnostic process. However, if the DAC control circuit 111 is configured as shown in FIG. 10, the values ​​of the signals Sa[3] to Sa[0] can be fixed to the desired values ​​regardless of fluctuations in the output signal of the circuit 111.

[0086] In Figure 10, “VDD=VDD HIGH " is shown, but the control signal output circuit (130) for realizing the diagnostic process that satisfies "VDD=VDD LOW " and a control signal output circuit to realize diagnostic processing that satisfies "VDD=VDD REF A control signal output circuit for realizing a diagnostic process that satisfies "VDD=VDD" can also be formed by changing the logical configuration of the control signal output circuit from that shown in FIG. HIGH ", a control signal output circuit to realize diagnostic processing that satisfies "VDD=VDD LOW " and a control signal output circuit to realize diagnostic processing that satisfies "VDD=VDD REF By combining the control signal output circuit to realize the diagnostic process that satisfies ", the voltage VDD HIGH , VDD LOW and VDD REF Either of these can be selectively set relative to the drive voltage VDD.

[0087] <<Eighth Example>> An eighth embodiment will now be described. FIG. 11 shows the configuration of an oscillator 41. The oscillator 41 is an example of the oscillator 40 (see FIG. 2). The oscillator 41 includes a DAC 41a and a VCO 41b. The DAC 41a and the VCO 41b are connected to a power supply voltage V PW Driven based on.

[0088] A control signal Sb[3:0] is supplied to the DAC 41a from the digital block 10. The control signal Sb[3:0] may be a signal output by the logic circuit 110. However, during the execution of the diagnostic sequence operation, the content of the control signal Sb[3:0] is determined by the diagnostic controller 121. The control signal Sb[3:0] is a multi-bit digital signal, and is assumed to be a 4-bit digital signal here.

[0089] The DAC 41a is a digital-to-analog converter that converts the digital control signal Sb[3:0] into an analog signal and outputs it. The VCO 41b is a voltage-controlled oscillator that generates and outputs a square wave signal having a frequency corresponding to the output signal of the DAC 41a. The square wave signal output from the VCO 41b is used as the clock signal CLK. Therefore, the frequency of the square wave signal output from the VCO 41b is the clock frequency f CLK The VCO 41b increases the clock frequency f as the voltage value of the output signal from the DAC 41a increases. CLK As the voltage value of the output signal of DAC41a decreases, the clock frequency f CLK Reduces.

[0090] Figure 12 shows the control signal Sb[3:0] and the clock frequency f CLK The control signal Sb[3:0] is made up of signals Sb[3] to Sb[0]. Each of the signals Sb[3] to Sb[0] is a 1-bit digital signal, and has a value of "0" or "1". For any integer i, the signal Sb[i+1] has a value of the more significant bit than the signal Sb[i]. The value of the control signal Sb[3:0] expressed in decimal notation is represented by the symbol "VAL_Sb[3:0]". Then, "VAL_Sb[3:0]=2 3 ×Sb[3]+22 ×Sb[2]+2 1 ×Sb[1]+2 0 ×Sb[0]”. And the conversion formula “f CLK =0.05×VAL_Sb[3:0]+0.65” is satisfied (the unit in this conversion formula is MHz).

[0091] Also, here, the reference frequency f REF is 1.00MHz and the low frequency f LOW is 0.80MHz and the high side frequency f HIGH Therefore, when the control signal Sb[3:0] that satisfies the following formula (2a) is supplied to the DAC 41a, the clock frequency f CLK is the reference frequency f REF When the control signal Sb[3:0] that satisfies the following formula (2b) is supplied to the DAC 41a, the clock frequency f CLK is the low frequency f LOW When the control signal Sb[3:0] that satisfies the following formula (2c) is supplied to the DAC 41a, the clock frequency f CLK is the high frequency f HIGH matches. (Sb[3],Sb[2],Sb[1],Sb[0])=(0,1,1,1) (2a) (Sb[3],Sb[2],Sb[1],Sb[0])=(0,0,1,1) (2b) (Sb[3],Sb[2],Sb[1],Sb[0])=(1,0,1,1) (2c)

[0092] Therefore, in a normal operation state, the digital block 10 supplies the control signal Sb[3:0] that satisfies the formula (2a) to the DAC 41a. During the execution of the diagnostic sequence operation, the diagnostic controller 121 controls the required clock frequency f CLK In response to this, the control signal Sb[3:0] that satisfies one of the equations (2a), (2b), and (2c) may be supplied to the DAC 41a.

[0093] Figure 13 shows the clock frequency f CLK is the reference frequency f REF and the clock frequency f CLK The high frequency f HIGH 13 shows an example of a circuit configuration for setting the normal DAC control circuit 112, the diagnostic DAC control circuit 121b, and the control signal output circuit 140. The normal DAC control circuit 112 and the control signal output circuit 140 are provided in the logic circuit 110 (see FIG. 2). However, the control signal output circuit 140 may be considered to be provided outside the logic circuit 110. The diagnostic DAC control circuit 121b is provided in the diagnostic controller 121. The control signal output circuit 140 includes circuits 141[3], 141[1], and 141[0], which are two-input OR circuits, and circuit 141[2], which is a two-input AND circuit. Each of the circuits 141[3] to 141[0] has a first and second input terminal and an output terminal. For each integer i satisfying "0≦i≦3", a signal Sb[i] is output from the output terminal of the circuit 141[i].

[0094] The normal DAC control circuit 112 outputs a signal Sb[3] to the first input terminals of the circuits 141[3], 141[2], 141[1], and 141[0], respectively. NML , Sb[2] NML , Sb[1] NML , Sb[0] NML The diagnostic DAC control circuit 121b supplies a signal Sb to the second input terminals of the circuits 141[3] to 141[0] in common. BIST Signal Sb[3] NML ~Sb[0] NML and Sb BIST are 1-bit digital signals each having a value of "0" or "1."

[0095] Circuit 141[3] outputs signal Sb[3] NML and Sb BIST If at least one of the signals Sb[3] and Sb[4] has a value of "1", the signal Sb[4] is output as "1", and the signal Sb[4] is output as "1". NML and Sb BISTIf both of the signals Sb[2] and Sb[3] have a value of "0", the circuit 141[2] outputs a signal Sb[3] of "0". NML has a value of "1" and the signal Sb BIST The circuit 141[1] outputs the signal Sb[2] of "1" only if the signal Sb[1] has a value of "0", otherwise it outputs the signal Sb[2] of "0". NML and Sb BIST If at least one of the signals Sb[1] and Sb[2] has a value of "1", the signal Sb[1] is output as "1", and the signal Sb[2] NML and Sb BIST If both of the inputs have a value of "0", the circuit 141[0] outputs a signal Sb[1] of "0". NML and Sb BIST If at least one of these has a value of "1", a signal Sb[0] of "1" is output, and a signal Sb[0] NML and Sb BIST If both of these have a value of "0", the signal Sb[0] of "0" is output.

[0096] The normal DAC control circuit 112 is a circuit that functions significantly only in the normal operating state. In the normal operating state, the normal DAC control circuit 112 controls the “(Sb[3] NML ,Sb[2] NML ,Sb[1] NML ,Sb[0] NML )=(0,1,1,1)” NML ~Sb[0] NML to the control signal output circuit 140. Meanwhile, the diagnostic DAC control circuit 121b outputs the clock frequency f CLK The high frequency f HIGH During the period when the signal Sb is set to "1", BIST to the control signal output circuit 140. In the normal operating state, the diagnostic DAC control circuit 121b outputs the signal Sb BIST The value is fixed at "0".

[0097] In this case, the output signals Sb[3] to Sb[0] of the control signal output circuit 140 in the normal operating state are the signal Sb[3] NML ~Sb[0] NMLIn normal operation, it is determined by "(Sb[3] NML ,Sb[2] NML ,Sb[1] NML ,Sb[0] NML )=(Sb[3],Sb[2],Sb[1],Sb[0])=(0,1,1,1)” so “f CLK =f REF " (See also Figure 12). On the other hand, "Sb BIST During the period when "=1", the signal Sb[3] NML ~Sb[0] NML Regardless of the logic of the control signal output circuit 140, the output signals Sb[3] to Sb[0] of the control signal output circuit 140 are fixed at "(Sb[3], Sb[2], Sb[1], Sb[0]) = (1, 0, 1, 1)". BIST In the period when f = 1, CLK =f HIGH " (See also Figure 12).

[0098] Normally, when the DAC control circuit 112 is a component of the logic circuit 110, the output signal of the circuit 112 may fluctuate in various ways during the execution of the diagnostic process. However, if the DAC control circuit 112 is configured as shown in FIG. 13, the values ​​of the signals Sb[3] to Sb[0] can be fixed to the desired value regardless of fluctuations in the output signal of the circuit 112.

[0099] In Figure 13, “f CLK =f HIGH " is shown, but the control signal output circuit (140) for realizing the diagnostic process that satisfies "f CLK =f LOW " and a control signal output circuit for realizing a diagnostic process that satisfies "f CLK =f REF The control signal output circuit for realizing the diagnostic process that satisfies "f" can also be formed by changing the logic configuration of the control signal output circuit from that shown in FIG. CLK =f HIGH ", a control signal output circuit for realizing a diagnostic process that satisfies "f CLK =f LOW " and a control signal output circuit for realizing a diagnostic process that satisfies "f CLK =f REFBy combining the control signal output circuit to realize the diagnostic process that satisfies ", the frequency f HIGH , f LOW and f REF Either of these is set to the clock frequency f CLK can be selectively set for

[0100] <<Ninth Example>> A ninth embodiment will now be described. An example of the configuration of a power supply device using a semiconductor device 1 will be given. FIG. 14 is a schematic block diagram of a power supply device 510 according to the ninth embodiment. The power supply device 510 includes a power supply control device 511 and a discrete component group 512 made up of a plurality of discrete components externally connected to the power supply control device 511. The semiconductor device 1 in the ninth embodiment is the power supply control device 511. The power supply control device 511 may be an electronic component classified as a PMIC (Power Management IC).

[0101] 15, power supply device 510 is provided with regulators 513 for m channels, i.e., m regulators 513 are provided. m represents any integer equal to or greater than 2. Regulators 513 for m channels can also be expressed as a power supply device for m channels, in which case power supply device 510 can also be called a composite power supply device having power supply devices (513) for m channels.

[0102] The m channels are comprised of the first to mth channels. Each regulator 513 supplies an input voltage V IN is supplied, and the input voltage V IN is converted into power to produce an output voltage V OUT The input voltage V IN and output voltage V OUT are different DC voltages. A total of m output voltages V OUT are different DC voltages. However, m output voltages V OUT Among these, two or more output voltages V OUT The values ​​of the m input voltages V in the first to mth channels may be the same. INmay be different DC voltages, or m input voltages V IN Among these, two or more input voltages V IN can be a common DC voltage. The input voltage V IN is the power supply voltage of the power supply control device 511 (power supply voltage V PW (equivalent to

[0103] The regulators 513 of one or more of the first to m-th channels may be switching regulators. IN By stepping down the input voltage V IN Lower output voltage V OUT A step-down switching regulator that generates an input voltage V IN By boosting the input voltage V IN Higher output voltage V OUT The regulators 513 of one or more channels in the first to m-th channels may be linear regulators. The total m regulators 513 in the first to m-th channels may all be switching regulators or may all be linear regulators. The total m regulators 513 in the first to m-th channels may include a mixture of one or more switching regulators and one or more linear regulators.

[0104] 16 shows the configuration of a regulator 530 that can be used as the regulator 513 of one or more channels. The regulator 530 is a step-down switching regulator, and includes transistors 531 and 532, a control drive circuit 533, a coil 534, and a capacitor 535. The transistors 531 and 532 and the control drive circuit 533 are provided in the power supply control device 511. The control drive circuit 533 is part of a functional circuit. The transistors 531 and 532 are included as components of the analog block 20. The coil 534 and the capacitor 535 are included as components of the discrete component group 512. The transistor 531 is a P-channel MOSFET, and the transistor 532 is an N-channel MOSFET. An input voltage V IN is supplied. The drains of the transistors 531 and 532 are connected to a first end of a coil 534. The source of the transistor 532 is connected to ground. The second end of the coil 534 is connected to an output node 536. A first end of a capacitor 535 is connected to the output node 536, and a second end of the capacitor 535 is connected to ground. During the period when the regulator 530 is performing power conversion, the control drive circuit 533 supplies an output voltage V OUT By performing switching control to alternately turn on and off the transistors 531 and 532 based on the feedback information, an output voltage V OUT The output voltage V OUT itself or the output voltage V OUT The divided voltage is the output voltage V OUT The feedback information is input to the control drive circuit 533.

[0105] The power supply 510 receives an input voltage V IN to output voltage V OUT In the power supply control device 511 serving as the semiconductor device 1, a functional circuit configured with the logic circuit 110 and the analog block 20 controls the power conversion of the regulator 513 for each channel. That is, in the functional operation according to the ninth embodiment (see step S6 in FIG. 3), the power conversion of the regulator 513 is controlled for each channel.

[0106] Control of power conversion also includes control of whether or not to perform power conversion. Before reaching step S6, the regulators 513 of all channels are stopped. When the process moves from step S5 to step S6, the functional circuit configured by the logic circuit 110 and the analog block 20 starts power conversion of the regulators 513 of the first to m-th channels in a predetermined order. For example, when "m=3", when the process moves from step S5 to step S6, the functional circuit starts power conversion of the regulators 513 of the i-th channel. A The power conversion of the regulator 513 of the channel i is started. A Channel output voltage V OUT After increasing to the target voltage, B The power conversion of the regulator 513 of the channel i is started. B Channel output voltage V OUT to the target voltage, and then C The power conversion of the regulator 513 of the channel i is started. C Channel output voltage V OUT to the target voltage (where i A , i B and i C are different natural numbers equal to or less than 3). However, in step S6, the functional circuit may simultaneously start power conversion in the regulators 513 of two or more channels. In a normal operating state, power conversion in the regulators 513 of the first to m-th channels is continuously performed.

[0107] When the process proceeds from step S5 to step S10, the functional circuit does not start functional operation. That is, when the process proceeds from step S5 to step S10, the functional circuit inhibits power conversion by regulator 513 in channels 1 to m (in other words, power conversion by regulator 513 in channels 1 to m is not performed). In regulator 530 in Fig. 16, power conversion by regulator 530 is inhibited by control drive circuit 533 maintaining both transistors 531 and 532 in the off state.

[0108] <<Tenth Example>> A tenth embodiment will now be described.

[0109] In the ninth embodiment, the semiconductor device 1 is configured as a power supply control device 511, but the type of semiconductor device 1 is arbitrary as long as it is a semiconductor device having a logic circuit to which a BIST diagnostic process is to be applied. For example, the semiconductor device 1 may be a motor driver that drives and controls a three-phase motor, in which case the functional operation is to drive and control the three-phase motor by supplying a three-phase AC voltage to the three-phase motor. Alternatively, for example, the semiconductor device 1 may be an LED driver that drives and controls an LED (light-emitting diode), in which case the functional operation is to control the light emission of the LED by supplying a current to the LED. Other functional operations are also arbitrary.

[0110] The channel types of the FETs (field effect transistors) shown in the above embodiments are merely examples, and the channel type of any FET may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0111] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0112] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0113] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0114] A semiconductor device (1) according to one aspect of the present disclosure includes a logic circuit (110) and a diagnostic circuit (120) configured to perform a diagnostic process to diagnose whether the logic circuit is in a state in which it can operate normally, based on output data of the logic circuit when a test pattern is supplied to the logic circuit, and the diagnostic circuit is configured (first configuration) to perform multiple diagnostic processes in which the operating conditions of the logic circuit are different from each other.

[0115] This makes it possible to diagnose whether the logic circuit is in a state in which it can operate normally, even when the operating conditions change, thereby providing the semiconductor device with high reliability.

[0116] In the semiconductor device according to the first configuration, the logic circuit has a sequential circuit (SQC) configured to operate in synchronization with a clock signal, the plurality of diagnostic processes include a first diagnostic process, a second diagnostic process, and a third diagnostic process, and the diagnostic circuit makes a drive voltage (VDD) of the logic circuit different from each other and changes the frequency (f) of the clock signal between the first diagnostic process, the second diagnostic process, and the third diagnostic process. CLK ) may be different from each other (second configuration).

[0117] In the semiconductor device according to the second configuration, in the first diagnostic process, the drive voltage of the logic circuit is a reference voltage (VDD REF) and the frequency of the clock signal is a reference frequency (f REF ) and in the second diagnostic process, the drive voltage of the logic circuit is lower than the reference voltage and the frequency of the clock signal is lower than the reference frequency, and in the third diagnostic process, the drive voltage of the logic circuit is higher than the reference voltage and the frequency of the clock signal is higher than the reference frequency (third configuration).

[0118] In the semiconductor device according to the third configuration, the plurality of diagnostic processes may further include a fourth diagnostic process and a fifth diagnostic process, and in the fourth diagnostic process, the drive voltage of the logic circuit may be lower than the reference voltage and the frequency of the clock signal may be higher than the reference frequency, and in the fifth diagnostic process, the drive voltage of the logic circuit may be higher than the reference voltage and the frequency of the clock signal may be lower than the reference frequency (fourth configuration).

[0119] In the semiconductor device according to the first configuration, the logic circuit has a sequential circuit (SQC) configured to operate in synchronization with a clock signal, the plurality of diagnostic processes include a first diagnostic process and a second diagnostic process, and the diagnostic circuit makes a drive voltage (VDD) of the logic circuit different from each other and changes the frequency (f) of the clock signal between the first diagnostic process and the second diagnostic process. CLK ) may be different from each other (fifth configuration).

[0120] In the semiconductor device according to the fifth configuration, the drive voltage of the logic circuit in the second diagnostic process may be higher than the drive voltage of the logic circuit in the first diagnostic process, and the frequency of the clock signal in the second diagnostic process may be higher than the frequency of the clock signal in the first diagnostic process (sixth configuration).

[0121] In the semiconductor device according to the first configuration, the diagnostic circuit may be configured to cause the drive voltage (VDD) of the logic circuit to differ from one another among the plurality of diagnostic processes (seventh configuration).

[0122] In the semiconductor device according to the first configuration, the logic circuit has a sequential circuit (SQC) configured to operate in synchronization with a clock signal, and the diagnostic circuit is configured to change the frequency (f CLK ) may be different from each other (eighth configuration).

[0123] Regarding the semiconductor device according to any one of the first to eighth configurations, the semiconductor device is a power supply control device (511) configured to control the operation of a power supply device (510) using the logic circuit, and the power supply device has a regulator (513) for multiple channels, and controls an input voltage (V IN ) to the output voltage (V OUT ), the diagnostic circuit derives first result data (FLG of "0") or second result data (FLG of "1") through the plurality of diagnostic processes, and the semiconductor device may be configured to start the power conversion in each channel after the first result data is derived by the diagnostic circuit, and to inhibit the power conversion in each channel when the second result data is derived by the diagnostic circuit (ninth configuration). [Explanation of symbols]

[0124] 1. Semiconductor device 2 MPU 3. Voltage Source 4 Switch 5 Input Capacitor 10 Digital Blocks 20 Analog Blocks 30 Internal power circuit 40 oscillators PIN power terminal GND Ground terminal V PW Power supply voltage VDD, V REG1 , V REG2 Drive voltage CLK Clock signal 110 Logic Circuits SQC sequential circuit 120 Diagnostic Circuit 121 Diagnostic Controller 122 Test pattern supply circuit 123 Judgment circuit 31 Drive voltage generation circuit 31a DAC 31b Buffer circuit 111, 112 Normal DAC control circuit 121a, 121b diagnostic DAC control circuit 130, 140 control signal output circuit 41 Oscillators 41a Oscillator 41b VCO 510 Power Supply 511 Power supply control device 512 Discrete Components 513, 530 Regulator V IN Input voltage V OUT Output Voltage 531, 532 transistors 533 Control drive circuit 534 Coil 535 Capacitor 536 output nodes

Claims

1. A logic circuit; a diagnostic circuit configured to perform a diagnostic process to diagnose whether the logic circuit is in a normal operable state based on output data of the logic circuit when a test pattern is supplied to the logic circuit; The diagnostic circuit executes a plurality of diagnostic processes under different operating conditions of the logic circuit. , semiconductor device.

2. the logic circuit has a sequential circuit configured to operate in synchronization with a clock signal; the plurality of diagnostic processes include a first diagnostic process, a second diagnostic process, and a third diagnostic process, The diagnostic circuit varies the drive voltage of the logic circuit and the frequency of the clock signal between the first diagnostic process, the second diagnostic process, and the third diagnostic process. The semiconductor device according to claim 1 .

3. In the first diagnostic process, a drive voltage of the logic circuit is a reference voltage and a frequency of the clock signal is a reference frequency; In the second diagnostic process, the drive voltage of the logic circuit is lower than the reference voltage and the frequency of the clock signal is lower than the reference frequency; In the third diagnostic process, the drive voltage of the logic circuit is higher than the reference voltage and the frequency of the clock signal is higher than the reference frequency. The semiconductor device according to claim 2 .

4. the plurality of diagnostic processes further include a fourth diagnostic process and a fifth diagnostic process; In the fourth diagnostic process, the drive voltage of the logic circuit is lower than the reference voltage and the frequency of the clock signal is higher than the reference frequency; In the fifth diagnostic process, the drive voltage of the logic circuit is higher than the reference voltage and the frequency of the clock signal is lower than the reference frequency. The semiconductor device according to claim 3 .

5. the logic circuit has a sequential circuit configured to operate in synchronization with a clock signal; the plurality of diagnostic processes include a first diagnostic process and a second diagnostic process, The diagnostic circuit causes the drive voltage of the logic circuit to be different from that of the first diagnostic process and the frequency of the clock signal to be different from that of the second diagnostic process. The semiconductor device according to claim 1 .

6. a drive voltage of the logic circuit in the second diagnostic process is higher than a drive voltage of the logic circuit in the first diagnostic process; and The frequency of the clock signal in the second diagnostic process is higher than the frequency of the clock signal in the first diagnostic process. The semiconductor device according to claim 5 .

7. The diagnostic circuit varies the drive voltage of the logic circuit among the plurality of diagnostic processes. The semiconductor device according to claim 1 .

8. the logic circuit has a sequential circuit configured to operate in synchronization with a clock signal; The diagnostic circuit varies the frequency of the clock signal between the plurality of diagnostic processes. The semiconductor device according to claim 1 .

9. The semiconductor device is a power supply control device configured to control the operation of a power supply device using the logic circuit, the power supply device has a regulator for each of the multiple channels and is configured to perform power conversion for generating an output voltage from an input voltage for each of the channels; the diagnostic circuit derives first result data or second result data through the plurality of diagnostic processes; The semiconductor device starts the power conversion in each channel after the first result data is derived by the diagnostic circuit, and inhibits the power conversion in each channel when the second result data is derived by the diagnostic circuit.

9. The semiconductor device according to claim 1.

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