Semiconductor device

Abstract

To be able to switch between operation modes without requiring an installation and the like of a dedicated external terminal.SOLUTION: A semiconductor device (2) comprises: an internal power source circuit (20) configured to generate an internal power source voltage (VREG) based on an input power source voltage (VCC); a functional circuit (30) configured to operate based on the internal power source voltage; a housing for storing the internal power source circuit and the functional circuit; a specific terminal (REG) which is a terminal exposed from the housing, and is configured to receive the internal power source voltage; and a mode setting circuit (40) configured to set an operation mode of the functional circuit in response to a terminal current (IEX) flowing through the specific terminal.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] A power supply device (see Patent Document 1) that generates an output voltage from an input voltage by power conversion can be formed using a semiconductor device. When the operation or setting of a semiconductor device is to be varied, a method of manufacturing and selling multiple types of semiconductor devices with different operation or setting is adopted or considered. Alternatively, a method of providing one or more dedicated external terminals on a semiconductor device and specifying the operation or setting by varying the voltage level to the dedicated external terminal is adopted or considered. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2021 / 054027

[0004] [overview] However, the former method requires manufacturing multiple types of semiconductor devices as separate products, which increases the burden of manufacturing and inventory management. The latter method requires dedicated external terminals, which increases the component size and cost of the semiconductor device. Furthermore, given the recent demand for miniaturization, providing dedicated external terminals can be difficult. In relation to differentiating operation or setting contents, it is hoped that technologies will be developed that will reduce the burden of manufacturing and inventory management, or contribute to reducing component size and cost.

[0005] A semiconductor device according to one embodiment of the present disclosure includes an internal power supply circuit configured to generate an internal power supply voltage based on an input power supply voltage, a functional circuit configured to operate based on the internal power supply voltage, a housing that houses the internal power supply circuit and the functional circuit, a specific terminal exposed from the housing and configured to receive the internal power supply voltage, and a mode setting circuit configured to set the operating mode of the functional circuit in accordance with a terminal current flowing through the specific terminal. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic configuration block diagram of a power supply device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is an external perspective view of a power supply control device according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram showing a state in which a regulator with multiple channels is provided in a power supply device according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram showing a state in which a regulator with multiple channels is provided in a power supply device according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a configuration diagram of two regulators in a power supply device according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a partial block diagram of a power supply control device according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a partial block diagram of a power supply control device according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a partial configuration diagram of a power supply control device according to a first example of an embodiment of the present disclosure. [Figure 9] FIG. 9 is a timing chart showing the period around the start-up of the power supply control device according to a first example of an embodiment of the present disclosure. [Figure 10] FIG. 10 is an explanatory diagram of a method for determining a mode determination value according to a first example belonging to an embodiment of the present disclosure. [Figure 11]FIG. 11 is an explanatory diagram of a method for determining a mode determination value according to a first example belonging to an embodiment of the present disclosure. [Figure 12] FIG. 12 is a timing chart showing a period around the start-up of a power supply control device according to a second example of an embodiment of the present disclosure. [Figure 13] FIG. 13 is a circuit diagram of a detection circuit that can be provided in a determination circuit according to a third example of the embodiment of the present disclosure. [Figure 14] FIG. 14 is a circuit diagram of a detection circuit that can be provided in a determination circuit according to a third example of the embodiment of the present disclosure. [Figure 15] FIG. 15 is a circuit diagram of a detection circuit that can be provided in a determination circuit according to a third example of the embodiment of the present disclosure. [Figure 16] FIG. 16 is a conceptual diagram showing a change in the order in which output voltages are generated according to a fourth example belonging to an embodiment of the present disclosure. [Figure 17] FIG. 17 is a diagram showing a state in which devices are connected via a communication bus according to a fourth example of the embodiment of the present disclosure.

[0007] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, the same parts are designated by the same reference numerals, and duplicate descriptions of the same parts will be omitted as a general rule. In this specification, for the sake of simplicity, symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components may be used, and the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs may be omitted or abbreviated.

[0008] First, some terms used in the description of the embodiments of the present disclosure will be explained. "Ground" refers to a reference conductor having a reference potential of 0V (zero volts) as a reference or the 0V potential itself. The reference conductor may be formed using a conductor such as metal. The 0V potential may also be referred to as the ground potential. In the embodiments of the present disclosure, a voltage shown without particularly setting a reference represents a potential viewed from the ground. "Level" refers to the level of potential, and for any signal or voltage of interest, the high level has a higher potential than the low level.

[0009] Regarding any transistor configured as a FET (field-effect transistor) exemplified by a MOSFET, the "on state" refers to a state in which the drain and source of the transistor are conducting, and the "off state" refers to a state in which the drain and source of the transistor are non-conducting (blocked state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-type MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor". Also, unless otherwise specified, in any MOSFET, the back gate may be considered to be short-circuited to the source. Hereinafter, for any transistor, the on state and off state may also be simply expressed as "on" and "off".

[0010] Regarding the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., unless otherwise specified, it may be understood to refer to an electrical connection.

[0011] When any two voltages to be compared are v1 and v2, "v1>v2" represents that the voltage v1 is higher than the voltage v2, "v1<v2" represents that the voltage v1 is lower than the voltage v2, and "v1=v2" represents that the value of the voltage v1 is the same as the value of the voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0012] 1 is a schematic block diagram of a power supply device 1 according to an embodiment of the present disclosure. The power supply device 1 includes a power supply control device 2 and a discrete component group 3 made up of a plurality of discrete components externally connected to the power supply control device 2. The power supply control device 2 may be an electronic component classified as a PMIC (Power Management IC). Note that wiring provided inside the power supply control device 2 is sometimes specifically referred to as internal wiring, and wiring provided outside the power supply control device 2 is sometimes specifically referred to as external wiring.

[0013] Figure 2 shows an external perspective view of the power supply control device 2. The power supply control device 2 is an electronic component that includes a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing CS (package) that houses the semiconductor chip, and a plurality of external terminals that are exposed from the housing CS to the outside of the power supply control device 2. The power supply control device 2 is formed by sealing the semiconductor chip in a housing CS made of resin. Note that the number of external terminals of the power supply control device 2 and the type of housing CS of the power supply control device 2 shown in Figure 2 are merely examples, and can be designed as desired.

[0014] 3, the power supply device 1 is provided with n channels of regulators 4, i.e., n regulators 4. In this embodiment, unless otherwise specified, n represents any integer equal to or greater than 2. The n channels of regulators 4 can also be expressed as n channels of power supply devices, in which case the power supply device 1 can also be referred to as a composite power supply device having n channels of power supply devices (4).

[0015] Each regulator 4 is provided with a control block 10. The n channels are made up of first to n-th channels. Each regulator 4 receives an input voltage V IN is supplied, and the input voltage V IN is converted into power to produce an output voltage V OUT The input voltage V IN and output voltage V OUT are different DC voltages. The input voltage V IN or output voltage V OUTcan be a negative DC voltage, but in the following, the input voltage V IN and output voltage V OUT is a positive DC voltage.

[0016] The regulators 4 of one or more of the first to n-th channels may be switching regulators. IN By stepping down the input voltage V IN Lower output voltage V OUT A step-down switching regulator that generates an input voltage V IN By boosting the input voltage V IN Higher output voltage V OUT The regulators 4 of one or more of the first to n-th channels may be linear regulators. The total of n regulators 4 of the first to n-th channels may all be switching regulators or all be linear regulators. The total of n regulators 4 of the first to n-th channels may include a mixture of one or more switching regulators and one or more linear regulators.

[0017] A total of n output voltages V for the first to nth channels OUT are different DC voltages. A Output voltage V at the channel OUT and the value of the i B Output voltage V at the channel OUT There may be cases where the value of i A and i B represents any different natural numbers less than or equal to n.

[0018] A total of n input voltages V for the first to nth channels IN may be the same DC voltage. That is, the common DC voltage is the input voltage V IN It can be used as both. A Input voltage V at the channel IN is the iB Input voltage V at the channel IN The input voltage V of any one of the first to nth channels may be the same as or different from IN may be the power supply voltage of the power supply control device 2 (power supply voltage VCC, described later).

[0019] A total of n control blocks 10 for the first to n-th channels are provided in the power supply control device 2. In each channel, a regulator 4 is formed by the control block 10 and discrete components connected to the control block 10. As shown in FIG. 4, the regulator 4, the control block 10, and the input voltage V IN , output voltage V OUT , respectively, in particular the regulator 4[i], the control block 10[i], and the input voltage V IN [i], output voltage V OUT It is written as [i], where i represents any integer (e.g., any natural number less than or equal to n).

[0020] Power supply 1 has an input voltage V IN to output voltage V OUT The power supply control device 2 controls the operation (power conversion) of the power supply device 1. That is, the power supply control device 2 controls the operation (power conversion) of the regulator 4 for each channel. In detail, the operation (power conversion) of the regulator 4 for the i-th channel is controlled by the control block 10[i].

[0021] FIG. 5 shows the relationship between two arbitrary regulators 4[i] among the regulators 4[1] to 4[n]. A ] and 4[i B ] is shown below. A ] is the control block 10[i A ] and output coil L[i A ] and output capacitor C[i A ] is a step-down switching regulator equipped with regulator 4 [i B ] is control block 10[i B ] and output capacitor C[i B]. Regulator 4 [i B ] may be an LDO (Low Dropout) regulator. A ] and 10[i B ] is provided in the power supply control device 2. The output coil L[i A ] and output capacitor C[i A ] and C[i B ] are components of the discrete component group 3 (see Figure 1).

[0022] Terminal VS[i A ], SW[i A ], PGND[i A ], VO[i A ], VS[i B ], VO[i B ] and GND are external terminals (seven external terminals in total) provided on the power supply control device 2. The terminal GND is a ground terminal. The ground terminal GND is connected to the ground. The terminal VS[i A ], SW[i A ], PGND[i A ], VO[i A ] is regulator 4[i A ] are the input terminal, switch terminal, ground terminal, and feedback terminal. A ] is connected to ground. The ground terminal GND is connected to the ground terminal PGND[i A ]. Terminal VS[i B ], VO[i B ] is regulator 4[i B ] are the input and output terminals that make up the

[0023] Control Block 10[i A ] includes transistors 11 and 12 and a control drive circuit 13. The transistor 11 is a P-channel MOSFET, and the transistor 12 is an N-channel MOSFET. An input voltage V having a positive DC voltage value is input from a voltage source (not shown) provided outside the power supply device 1. IN [i A ] is connected to the input terminal VS[iA The source of the transistor 11 is connected to the input terminal VS[i A ] is connected to the input voltage V IN [i A The drains of the transistors 11 and 12 are connected to the switch terminals SW[i A ], and externally to the power supply control device 2, the switch terminal SW[i A ] is the output coil L[i A ] is connected to the first end of the output coil L[i A ] is connected to the output node OUT[i A The source of the transistor 12 is connected to the ground terminal PGND[i A ] and therefore connected to ground. The output node OUT[i A ] and ground, an output capacitor C[i A That is, an output capacitor C[i A ] is connected to the output node OUT[i A ] and the output capacitor C[i A The second end of the output node OUT[i A ] is the output voltage V OUT [i A ].

[0024] Output voltage V to the control drive circuit 13 OUT [i A ] is input. In Figure 5, the feedback information of the feedback terminal VO[i A ] is connected to the output node OUT[i A ] and connected to the control drive circuit 13 through internal wiring (i.e., the output node OUT[i A ] is the feedback terminal VO[i A ] to the control drive circuit 13, OUT [i A ] itself is the output voltage V OUT [i A ] is input to the control drive circuit 13 as feedback information. OUT [i A ] feedback information is the output voltage V OUT [iA ] may be a partial pressure of

[0025] The control drive circuit 13 is connected to the gates of the transistors 11 and 12, and controls the gate potentials of the transistors 11 and 12 to individually turn the transistors 11 and 12 on or off. OUT [i A ], the output voltage V OUT [i A ] is the predetermined target voltage V TG [i A ], the transistors 11 and 12 are alternately switched on and off (switching control). By this switching drive, the switch terminal SW[i A ] to the square wave voltage (approximately 0V and input voltage V IN [i A ]) is generated. A ] and output capacitor C[i A ] rectifies and smoothes the square wave voltage, and the output node OUT[i A ] to output voltage V OUT [i A It is also possible to use a modification in which the transistor 11 is configured as an N-channel MOSFET. In this case, a known boost circuit is added to increase the input voltage V IN [i] A higher boosted voltage may be generated and the transistor 11 may be turned on using the boosted voltage.

[0026] Control Block 10[i B ] includes a transistor 14 and a control drive circuit 15. The transistor 14 is a P-channel MOSFET. An input voltage V having a positive DC voltage value is input from a voltage source (not shown) provided outside the power supply device 1. IN [i B ] is connected to the input terminal VS[i B The source of the transistor 14 is connected to the input terminal VS[i B ] is connected to the input voltage V IN [iB The drain of transistor 14 is connected to output terminal VO[i B ] and the output terminal VO[i B ] is connected to the output node OUT[i B ] is connected to the output node OUT[i B ] and ground, an output capacitor C[i B That is, an output capacitor C[i B ] is connected to the output node OUT[i B ] and the output capacitor C[i B The second end of the output node OUT[i B ] (and therefore the voltage at the output terminal VO[i B ]) is the output voltage V OUT [i B ].

[0027] Output voltage V to the control drive circuit 15 OUT [i B ] is input. In Figure 5, the output terminal VO[i B ] is connected to the control drive circuit 15, the output voltage V OUT [i B ] itself is the output voltage V OUT [i B ] is input to the control drive circuit 15 as feedback information. OUT [i B ] feedback information is the output voltage V OUT [i B The control drive circuit 15 is connected to the gate of the transistor 14. The control drive circuit 15 outputs an output voltage V OUT [i B ], the gate potential of the transistor 14 is controlled based on the feedback information of the output node OUT[i B ], which controls the magnitude of the current supplied to the output voltage V OUT [i B ] to a predetermined target voltage V TG [i B ] to stabilize it.

[0028] Regulator 4[i A ] may be provided in the power supply device 1. B ] may be provided in the power supply device 1.

[0029] FIG. 6 shows a partial block diagram of the power supply control device 2 viewed from a different perspective than that of FIG. 5. The power supply control device 2 comprises an internal power supply circuit 20, a functional circuit 30, and a mode setting circuit 40. The power supply control device 2 comprises a group of circuits configured from semiconductors. The group of circuits configured from semiconductors in the power supply control device 2 includes the internal power supply circuit 20, the functional circuit 30, and the mode setting circuit 40, and are housed in the above-mentioned housing CS. Any other circuits and elements provided in the power supply control device 2 and any internal wiring (wiring W described later) may also be included. REG The internal power supply circuit 20, the function circuit 30, and the mode setting circuit 40 are also housed in the housing CS. The internal power supply circuit 20, the function circuit 30, and the mode setting circuit 40 are each connected to a ground terminal GND (see FIG. 5), and are therefore connected to the ground. The power supply terminal IN and the terminal REG (specific terminals) shown in FIG. 6 are external terminals (two external terminals in total) provided on the power supply control device 2. The capacitor C shown in FIG. REG are components of the discrete component group 3 (see Figure 1).

[0030] A power supply voltage VCC (input power supply voltage) having a positive DC voltage value is supplied to a power supply terminal IN through an external wiring from a voltage source (not shown) provided outside the power supply device 1. The internal power supply circuit 20 is connected to the power supply terminal IN and the wiring W. REG (internal power supply wiring), and the internal power supply voltage V is generated based on the power supply voltage VCC. REG Generates the internal power supply voltage V REG Wiring W REG The internal power supply circuit 20 supplies the internal power supply voltage V REG is the desired regulated voltage V REG0 (internal power supply voltage V REG and stabilization voltage V REG0 The difference between the voltage V and the voltage V approaches zero. REG0 has a predetermined positive DC voltage value. The internal power supply circuit 20 may be a series regulator.REG is connected to the internal power supply terminal REG. The internal power supply voltage V REG To keep the voltage stable, a capacitor C is connected between the terminal REG and ground. REG That is, a capacitor C is provided outside the power supply control device 2. REG The first end of the capacitor C is connected to the terminal REG. REG The second end of the is connected to ground.

[0031] The functional circuit 30 is connected to the wiring W REG connected to the internal power supply voltage V REG The functional circuit 30 operates based on the internal power supply voltage V REG In addition, the internal supply voltage V REG The functional circuit 30 has control blocks 10[1] to 10[n], and therefore the functional circuit 30 controls the power conversion for each channel (controls the power conversion of the regulators 4[1] to 4[n]).

[0032] The mode setting circuit 40 is connected to the wiring W REG connected to the internal power supply voltage V REG The mode setting circuit 40 controls switching of the operation of the functional circuit 30. The operation of the functional circuit 30 is determined by the operation mode of the functional circuit 30. There are first to m-th modes (first to m-th candidate modes) as candidates for the operation mode of the functional circuit 30. m represents any integer equal to or greater than 2. The mode setting circuit 40 sets one of the first to m-th modes as the operation mode of the functional circuit 30, and the functional circuit 30 operates in the set operation mode.

[0033] As shown in FIG. 7, an external resistor R EX As shown in Figure 6, an external resistor R EX As shown in Figure 6, the external resistor R EX The case where the external resistance R EX Hereinafter, the case in which the external resistor R EXis a component of discrete component group 3 (see Figure 1). In the resistor installation case, the external resistor R EX The first end of is connected to the terminal REG, and the second end of the external resistor R EX The second end of the resistor R EX is the capacitor C REG connected in parallel).

[0034] Immediately after the internal power supply circuit 20 is started, the capacitor C REG The voltage across the REG0 During the process of rising to , the voltage is supplied from the internal power supply circuit 20 to the capacitor C REG A relatively large charging current is supplied to the capacitor C REG The voltage across the terminals is the regulated voltage V REG0 In the state after the voltage rises to REG The charge and discharge current is very small. In the steady state, the case with resistors installed has a higher current value (V REG0 / R EX ) for the wiring W REG The current flowing from the inside of the power supply control device 2 to the outside via the terminal REG increases. REG0 / R EX ) is the regulated voltage V REG0 is the external resistance R EX When an external resistance R is applied across EX Hereinafter, the current flowing through the terminal REG is referred to as the terminal current I EX However, the terminal current I EX The internal wiring W REG from the outside of the power supply control device 2 (capacitor C REG or external resistor R EX ) terminal current I EX has positive polarity.

[0035] The mode setting circuit 40 controls the terminal current I EXIt has the function of detecting the terminal current I EX Depending on the setting, the operation mode of the functional circuit 30 is set to one of the first to m-th modes.

[0036] When "m=2", the mode setting circuit 40 determines the terminal current I EX a single threshold current I TH Compared with the terminal current I EX is a single threshold current I TH If it is less than the jth A While the mode is set to the operation mode of the functional circuit 30, the terminal current I EX is a single threshold current I TH If it is equal to or greater than the jth B The mode can be set to the operation mode of the functional circuit 30. A ,j B )=(1,2), or (j A ,j B )=(2,1).

[0037] When "m≧3", the mode setting circuit 40 determines the terminal current I EX With a plurality of threshold currents, the mode setting circuit 40 can set one of the first to m-th modes as the operation mode of the functional circuit 30. That is, for example, when "m=3", the mode setting circuit 40 calculates the terminal current I EX Two threshold currents I TH1 and I TH2 Compare with (here "0 TH1 TH2 " holds). The mode setting circuit 40 then determines the terminal current I EX is the threshold current I TH1 If it is less than the jth A The mode is set to the operation mode of the functional circuit 30, and the terminal current I EX is the threshold current I TH1 and the threshold current I TH2 If it is less than the jth B The mode is set to the operation mode of the functional circuit 30, and the terminal current I EX is the threshold current I TH2 If it is equal to or greater than the jth​​C The mode can be set to the operation mode of the functional circuit 30. A , j B and j C represent different natural numbers less than or equal to 3. The same applies when "m≧4".

[0038] When "m=2", the designer or manufacturer of the power supply 1 should specify the external resistance R EX The operation mode of the functional circuit 30 can be switched between the first and second modes simply by switching whether or not the external resistor R is provided. When "m≧3", the designer or manufacturer of the power supply device 1 may EX and external resistance R EX When installing an external resistance R EX By determining the value of , the operation mode of the functional circuit 30 can be switched between the first to m-th modes.

[0039] In electronic components classified as PMICs, various operational or configuration settings (e.g., the order in which output voltages are generated, the target values ​​for each output voltage, and device addresses for communication) must be determined before generating multiple output voltages. When multiple types of PMICs with different operational or configuration settings are required, the following first or second reference methods are typically used. In the first reference method, multiple types of PMICs with different operational or configuration settings are manufactured and sold. However, the first reference method requires the multiple types of PMICs to be manufactured as separate products, which increases the burden of manufacturing and inventory management. In the second reference method, one or more dedicated external terminals are provided on the PMIC, and the operational or configuration settings are specified by selectively applying high or low voltages to the dedicated external terminals. However, the second reference method requires dedicated external terminals, which increases the size and cost of the electronic component as a PMIC. Furthermore, providing dedicated external terminals can be difficult due to recent demands for miniaturization.

[0040] In contrast, in the power supply control device 2 according to this embodiment, the internal power supply voltage V originally required for the operation of the internal circuit (functional circuit 30) isREG The operating mode is set (mode switching) using the terminal REG for the MOSFET. This reduces the burden of manufacturing and inventory management compared to the first reference method, and is expected to reduce component size and cost compared to the second reference method.

[0041] Below, several specific configuration examples, operation examples, application techniques, modified techniques, etc. related to the power supply device 1 will be described in multiple embodiments. The matters described above in this embodiment apply to each of the following embodiments unless otherwise specified and unless contradicted. If there are any matters in each embodiment that contradict the matters described above, the description in that embodiment may take precedence. Furthermore, unless contradicted, matters described in any of the multiple embodiments described below can also be applied to any of the other embodiments (i.e., any two or more of the multiple embodiments can be combined).

[0042] <<First Example>> A first embodiment will now be described. Fig. 8 shows a partial configuration diagram of a power supply control device 2, including an example of the internal configuration of an internal power supply circuit 20 and a mode setting circuit 40. The internal power supply circuit 20 includes an output transistor 21, an operational amplifier 22, voltage dividing resistors 23 and 24, and a reference voltage source 25. The mode setting circuit 40 includes a sense transistor 41, a sense resistor 42, and a determination circuit 43. The output transistor 21 and the sense transistor 41 are P-channel MOSFETs.

[0043] The sources of the output transistor 21 and the sense transistor 41 are commonly connected to a power supply terminal IN. The gates of the output transistor 21 and the sense transistor 41 are connected to each other. The drain of the output transistor 21 is connected to a wiring W REG (and therefore connected to the terminal REG). The drain of the sense transistor 41 is connected to ground via the sense resistor 42. That is, the drain of the sense transistor 41 is connected to a first terminal of the sense resistor 42, and the second terminal of the sense resistor 42 is connected to ground.

[0044] The first end of the voltage dividing resistor 23 is connected to the wiring W REG(and therefore connected to the terminal REG). The second end of the voltage dividing resistor 23 is connected to the first end of the voltage dividing resistor 24 at a node 26. The second end of the voltage dividing resistor 24 is connected to the ground. The reference voltage source 25 generates a predetermined reference voltage V based on the power supply voltage VCC. REF Generates the reference voltage V REF has a positive DC voltage value lower than the power supply voltage VCC. The non-inverting input terminal of the operational amplifier 22 is connected to a node 26. A reference voltage V is applied to the inverting input terminal of the operational amplifier 22 from a reference voltage source 25. REF The output terminal of the operational amplifier 22 is connected to the gates of the output transistor 21 and the sense transistor 41. The operational amplifier 22 operates based on the power supply voltage VCC with respect to the ground potential.

[0045] The drain current of the output transistor 21 is referred to as a current Ia. The current Ia corresponds to the output current of the output transistor 21. The terminal current I EX flows through the output transistor 21 and the terminal REG. At this time, part of the current Ia flows into the terminal current I EX The drain current of the sense transistor 41 is referred to as current Ib. The output transistor 21 and the sense transistor 41 form a current mirror circuit. Therefore, the current Ib is proportional to the current Ia. Therefore, the current Ib is expressed as "Ib = k × Ia" using a proportionality coefficient k between the currents Ia and Ib. The mode setting circuit 40 calculates the current Ib by dividing the current Ia and the terminal current I EX However, the size of the sense transistor 41 is much smaller than the size of the output transistor 21, so k has a positive value that is sufficiently smaller than 1 (for example, several hundredths). The voltage at the drain of the sense transistor 41 is used as a reference current to estimate the sense voltage V SNS The sense voltage V SNS is a voltage drop that occurs across the sense resistor 42 when the current Ib flows through the sense resistor 42, and has a voltage value that is proportional to the current Ib.

[0046] The decision circuit 43 is connected to the drain of the sense transistor 41 and supplies a sense voltage V SNSThe input impedance of the decision circuit 43 as viewed from the drain of the sense transistor 41 is sufficiently large, and the current between the drain of the sense transistor 41 and the decision circuit 43 can be considered to be zero. REG connected to the internal power supply voltage V REG The determination circuit 43 receives the internal power supply voltage V REG Before the functional circuit 30 is started, the determination circuit 43 determines the terminal current I EX Sense voltage V according to SNS The determination circuit 43 determines the operation mode of the functional circuit 30 based on the mode determination signal MD. The determination circuit 43 outputs a mode determination signal MD indicating its own determination to the functional circuit 30, and outputs an active-level signal EN2 to the functional circuit 30 to start up the functional circuit 30 simultaneously with or immediately after the output of the mode determination signal MD. The signal EN2 corresponds to an enable signal for the functional circuit 30. In response to the active-level signal EN2, the functional circuit 30 starts up and begins operating in the operation mode specified by the mode determination signal MD.

[0047] The mode setting circuit 40 is connected to the internal power supply voltage V REG is the regulated voltage V REG0 The terminal current I after reaching EX Based on the magnitude of the external resistance R EX In order to detect the presence or absence of terminal current I EX The proportional current Ib of the current Ia is referred to as the external resistance R EX In order to reduce unnecessary power consumption due to the installation of an external resistor R EX On the other hand, when the functional circuit 30 is in operation, the current consumed by the functional circuit 30 is supplied through the output transistor 21 (however, transiently, the capacitor C REG Therefore, after the functional circuit 30 is started, the proportion of the current consumed by the functional circuit 30 in the current Ia becomes considerably large, and the current Ib is supplied from the external resistor R EXFurthermore, the operation mode of the functional circuit 30 should be determined before the functional circuit 30 is started. Therefore, the determination circuit 43 determines the sense voltage V SNS The operation mode of the functional circuit 30 is determined based on the above.

[0048] FIG. 9 shows a timing chart of the power supply control device 2 near its startup. As time progresses, times t0, t1, t2, t3, t4, and t5 occur in this order. In a steady state, a power supply voltage VCC having a positive DC voltage value is supplied to the power supply terminal IN, but in the example of FIG. 9, the supply voltage to the power supply terminal IN is 0V or is in the process of rising until just before time t3. At time t0, the supply voltage to the power supply terminal IN is 0V. Therefore, at time t0, the internal power supply circuit 20 is stopped, and the internal power supply voltage V REG is 0V (zero volts). After time t0, between times t2 and t3, the power supply voltage VCC supplied to the power supply terminal IN rises from 0V to a sufficiently high positive DC voltage, and then the power supply voltage VCC supplied to the power supply terminal IN becomes constant.

[0049] The power supply control device 2 receives the power supply voltage VCC and a predetermined low voltage detection voltage V UVLO A low voltage detection circuit (not shown) is provided to detect the high / low relationship between UVLO >0). The low voltage detection circuit generates and outputs an internal signal EN1 that has a value of "0" or "1". When the power supply voltage VCC is sufficiently low, the internal signal EN1 has a value of "0". The low voltage detection circuit generates and outputs an internal signal EN1 that has a value of "0" or "1". When the power supply voltage VCC is sufficiently low, the internal signal EN1 has a value of "0". <V UVLO " to "VCC ≥ V UVLO ", the value of the internal signal EN1 is changed from "0" to "1". The internal power supply circuit 20 is configured to stop when the internal signal EN1 has a value of "0", and to start up in response to the value of the internal signal EN1 changing from "0" to "1". In the example of FIG. 9, time t1 corresponds to the timing when the value of the internal signal EN1 changes from "0" to "1", and therefore the internal power supply circuit 20 is started up (the internal power supply circuit 20 starts operating) at time t1, and the internal power supply voltage V REG Starts rising from 0V. VCC ≥ VUVLO ", the internal power supply circuit 20 can operate normally.

[0050] The operational amplifier 22 controls the gate voltage of the output transistor 21 so as to reduce the potential difference between its non-inverting input terminal and inverting input terminal, thereby controlling the current Ia (the output current of the output transistor 21). In detail, the operational amplifier 22 controls the gate voltage of the output transistor 21 so that the gate voltage of the output transistor 21 increases when the voltage at its non-inverting input terminal is higher than the voltage at its inverting input terminal, and decreases when the voltage at its non-inverting input terminal is lower than the voltage at its inverting input terminal. Immediately after time t1, the internal power supply voltage V REG is substantially near 0V, the voltage at node 26 is also near 0V, and the reference voltage V REF Therefore, the operational amplifier 22 reduces the gate voltage of the output transistor 21. As a result, a current Ia is generated immediately after the time t1, and the capacitor C REG As the internal power supply voltage V REG The internal power supply voltage V REG The rise in the internal power supply voltage V REG is the regulated voltage V REG0 Reaching "V REG =V REG0 ", the voltage at node 26 is equal to the reference voltage V REF is equal to.

[0051] In this way, the operational amplifier 22 is connected to the resistors 23 and 24 in accordance with the resistance ratio of the voltage dividing resistors 23 and 24 and the reference voltage V REF The specified voltage (stabilized voltage V REG0 ) internal power supply voltage V REG 9, the rise in the power supply voltage VCC stops after time t2 and before time t3, but the time at which the rise in the power supply voltage VCC stops can be any time after time t1.

[0052] At time t2 and thereafter, the capacitor C REG The voltage across the terminals is the regulated voltage V REG0 After the internal power supply circuit 20 is started, the determination circuit 43 determines whether the internal power supply voltage V REG The internal power supply voltage V REG is the regulated voltage V REG0 The determination circuit 43 sets the time t3, which is after the time t2, as the determination timing. The time t3 is set after the time t2 by a waiting time ΔT WAIT This is the time after the

[0053] Waiting time ΔT WAIT does not need to be measured precisely, and the determination circuit 43 determines whether the internal power supply voltage V REG is the regulated voltage V REG0 It is sufficient to set the determination timing (time t3) to a time when it is fully expected that the internal power supply voltage V REG is the regulated voltage V REG0 The timing at which it is expected that the internal power supply voltage V REG is the regulated voltage V REG0 The time elapsed since reaching this point is the waiting time ΔT WAIT The determination circuit 43 may be provided with a measurement circuit for determining whether the internal power supply voltage Vcc or the internal power supply voltage Vcc has been reached. In this case, the determination circuit 43 can determine the determination timing using the measurement circuit. The measurement circuit can be formed by a well-known analog circuit or digital circuit for measuring time. The measurement circuit is REG Hereinafter, the sense voltage V at the determination timing (time t3) SNS In particular, the sense voltage V SNS It is written as [t3].

[0054] At the determination timing (time t3), the functional circuit 30 has not yet started up. Therefore, the current Ia at the determination timing is a sum of the current flowing through the voltage dividing resistors 23 and 24, the current consumed by the determination circuit 43, and the terminal current I EX It is the sum of "V" and "V". REG =V REG0 ” the current flowing through the voltage dividing resistors 23 and 24 is constant, and the current consumption of the determination circuit 43 can also be considered to be approximately constant. Therefore, the current Ia at the determination timing in the resistor installation case is larger in current value (V REG0 / R EX As a result, the sense voltage V SNS [t3] is the sense voltage V in the reference case SNS From [t3], the current value (V REG0 / R EX ) will be higher by the voltage corresponding to

[0055] The determination circuit 43 detects the sense voltage V SNS [t3] is the threshold voltage V TH [1]~V TH Compared with [m-1], the sense voltage V SNS [t3] and threshold voltage V TH [1]~V TH Based on the level relationship with [m-1], it is determined which of the first to m-th modes should be set as the operation mode of the functional circuit 30. If "m=2", the sense voltage V SNS The threshold voltage compared with [t3] is the threshold voltage V TH [1] is the only option. If m≧3, the sense voltage V SNS The total number of threshold voltages compared with [t3] is 2 or more. TH [1]>0” and for any integer j, “V TH [j] <V TH [j+1]” holds.

[0056] The determination circuit 43 generates a mode determination signal MD indicating the result of the determination. The mode determination signal MD is a digital signal, and the value of the mode determination signal MD is expressed as a mode determination value MD VAL It is called.

[0057] When "m=2", the mode determination value MD VAL has either "1" or "2" (see FIG. 10). When "m=2", the decision circuit 43 determines whether "V SNS [t3] <V TH When [1]" is established, the mode determination value MD VAL Set "1" to "V TH [1]≦V SNS When [t3] is established, the mode determination value MD VAL Set to “2”.

[0058] When "m=3", the mode determination value MD VAL has one of "1", "2" and "3" (see FIG. 11). When "m=3", the decision circuit 43 determines whether "V SNS [t3] <V TH When [1]" is established, the mode determination value MD VAL Set "1" to "V TH [1]≦V SNS [t3] <V TH When [2]" is established, the mode determination value MD VAL Set "2" to "V TH [2]≦V SNS When [t3] is established, the mode determination value MD VAL Similarly, for "m=4", set the sense voltage V SNS [t3] and threshold voltage V TH [1]~V TH Depending on the relationship between [m-1] and the mode judgment value MD VAL Set an integer between 1 and m.

[0059] The mode determination signal MD is a signal that specifies which of the first to m-th modes the operation mode of the functional circuit 30 is to be set to. At time t4, the determination circuit 43 determines whether the sense voltage V SNS [t3] and threshold voltage V TH [1]~V TH Mode judgment value MD according to the high / low relationship with [m-1] VALThe determination circuit 43 outputs a mode determination signal MD having a value of "0" to the functional circuit 30. Time t4 is an infinitesimal time after time t3, and may be considered to substantially coincide with time t3. The mode determination signal MD has no significant value before time t4. At time t5, which is an infinitesimal time after time t4, the determination circuit 43 changes the value of the signal EN2 that it supplies to the functional circuit 30 from "0" to "1." The determination circuit 43 maintains the value of the signal EN2 at "0" until just before time t5.

[0060] When the signal EN2 is at "0", it has a non-active level, and when the signal EN2 has a value of "0", the functional circuit 30 is in a stopped state (the functional circuit 30 stops its own operation). When the signal EN2 is at "1", it has an active level, and in response to the value of the signal EN2 changing from "0" to "1", the functional circuit 30 starts up (the operation of the functional circuit 30 begins), and thereafter, as long as the value of the signal EN2 is "1", the functional circuit 30 continues to operate. Therefore, before time t5, power conversion is not being performed in any of the control blocks 10[1] to 10[n] (see FIG. 4), and the output voltage V OUT [1]~V OUT [n] are all 0V. After time t5, the control blocks 10[1] to 10[n] start power conversion according to a predetermined sequence, and the output voltage V OUT [1]~V OUT In the example of Figure 9, all or part of [n] rises from 0V. OUT [1], V OUT [2], V OUT [3] in order of each output voltage V OUT It is shown that the rate of increase is

[0061] The operation mode of the functional circuit 30 is determined according to the mode determination signal MD. VAL If "MD VAL If "m=2", the operation mode of the functional circuit 30 is set to the second mode. VALIf "MD VAL If .intg.=2", the operation mode of the functional circuit 30 is set to the first mode.

[0062] When "m=3", "MD VAL =1”, “MD VAL =2”, “MD VAL If "m=3", the operation modes of the functional circuit 30 are set to the first, second, and third modes, respectively. VAL =1”, “MD VAL =2”, “MD VAL = 3”, the operation modes of the functional circuit 30 are set to the first, third, and second modes, or the second, first, and third modes, or the second, third, and first modes, or the third, first, and second modes, or the third, second, and first modes. The same applies when “m≧4”, and the mode determination value MD VAL In any case, the functional circuit 30 is activated in the operation mode corresponding to the mode determination signal MD.

[0063] When "m=2", the mode setting circuit 40 controls the terminal current I EX Depending on the EX is connected, and sets the operation mode of the functional circuit 30 based on the result of the determination. EX The sense voltage V is obtained by converting the current Ib corresponding to SNS [t3] is generated and the sense voltage V SNS By binarizing [t3], the operation mode of the functional circuit 30 is set to the first mode or the second mode.

[0064] When "m≧3", the mode setting circuit 40 outputs a terminal current I EXIn the reference case (FIG. 6), the magnitude of the resistance component is set to the value of the capacitor C REG If we ignore the leakage current of the capacitor C REG (It can also be considered that the magnitude of the resistance component is the magnitude of the external resistance R EX In the resistor installation case, the terminal current I EX is the external resistance R EX It varies depending on the value of

[0065] <<Second Example>> The second embodiment will be described. The second embodiment is a partial modification of the first embodiment, and the description of the first embodiment also applies to the second embodiment unless otherwise specified.

[0066] Although the change in value of the internal signal EN1 from "0" to "1" has been cited as the startup condition for the internal power supply circuit 20, the startup condition for the internal power supply circuit 20 is not limited to this. For example, as shown in Figure 12, the startup condition for the internal power supply circuit 20 may be the change in value of the enable signal EN0 from "0" to "1."

[0067] FIG. 12 is a timing chart showing the period around the start-up of the power supply control device 2 according to the second embodiment. In the example of FIG. 12, a sufficiently high power supply voltage VCC is continuously supplied to the power supply terminal IN from before time t0. The power supply control device 2 is provided with an enable terminal (not shown) as one of its external terminals, and an enable signal EN0 is supplied to this enable terminal from an external circuit of the power supply control device 2. The enable signal EN0 is a binary signal having a value of "0" or "1." Here, a high-level enable signal EN0 (e.g., an enable signal EN0 having the level of the power supply voltage VCC) has a value of "1," and a low-level enable signal EN0 (e.g., an enable signal EN0 having the level of the ground) has a value of "0."

[0068] The enable signal EN0 has a value of "0" until just before time t1. In the second embodiment, the value of the enable signal EN0 changes from "0" to "1" at time t1. The internal power supply circuit 20 according to the second embodiment stops when the enable signal EN0 has a value of "0" and starts up in response to the value of the enable signal EN0 changing from "0" to "1". Therefore, the internal power supply circuit 20 starts up (the internal power supply circuit 20 starts operating) at time t1, and the internal power supply voltage V REG starts to rise from 0 V. The operation after time t1 is the same as that described in the first embodiment.

[0069] The power supply voltage VCC itself may be input to the enable terminal, although this differs from the situation shown in Fig. 12. In this case, the time when the voltage (VCC) supplied to the power supply terminal IN and the enable terminal rises from 0V to a predetermined positive DC voltage corresponds to time t1.

[0070] <<Third Example>> A third embodiment will be described below. In the third embodiment, some examples of the internal circuit of the determination circuit 43 will be given.

[0071] 13 may be provided in the determination circuit 43. The detection circuit 110 includes an inverter circuit 111 and a latch circuit 112. The inverter circuit 111 and the latch circuit 112 are connected to the internal power supply voltage V REG The inverter circuit 111 is driven based on the sense voltage V SNS The inverter circuit 111 receives the sense voltage V SNS is equal to or greater than the threshold voltage of the inverter circuit 111, a low level signal is output, and the sense voltage V SNS is less than the threshold voltage of the inverter circuit 111. The threshold voltage of the inverter circuit 111 is the internal power supply voltage V REG It has a lower positive voltage value and is roughly the internal power supply voltage V REG In the configuration of FIG. 13, the threshold voltage of the inverter circuit 111 is 1 / 2 of the above threshold voltage V TH Equivalent to [1].

[0072] The latch circuit 112 latches (holds) the level of the output signal of the inverter circuit 111 at the determination timing. The determination circuit 43 having the detection circuit 110 generates and outputs the mode determination signal MD based on the level latched by the latch circuit 112 (i.e., based on the output signal of the inverter circuit 111 at the determination timing).

[0073] Alternatively, when "m=2", the detection circuit 120 shown in Fig. 14 may be provided in the determination circuit 43. The detection circuit 120 includes a resistor 121, a resistor 122, a comparator 123, and a latch circuit 124. The comparator 123 and the latch circuit 124 are connected to the internal power supply voltage V REG The first end of the resistor 121 is connected to the wiring W REG The second terminal of the resistor 121 is connected to a first terminal of a resistor 122 at a node 125, and the second terminal of the resistor 122 is connected to ground. SNS is supplied to the comparator 123, and the inverting input terminal of the comparator 123 is connected to a node 125. In the detection circuit 120 of FIG. 14, the voltage of the node 125 is equal to the threshold voltage V TH [1]. The comparator 123 detects the sense voltage V SNS The voltage at node 125, V TH Compared with [1], the sense voltage V SNS and the voltage at node 125, V TH The comparator 123 outputs a signal indicating the level relationship with [1]. TH [1]≦V SNS When "V TH [1]>V SNS When the condition "is met," a low level signal is output.

[0074] The latch circuit 124 latches (holds) the level of the output signal of the comparator 123 at the determination timing. The determination circuit 43 having the detection circuit 120 generates and outputs the mode determination signal MD based on the level latched by the latch circuit 124 (i.e., based on the output signal of the comparator 123 at the determination timing).

[0075] 15 may be provided in the determination circuit 43. The detection circuit 130 includes resistors 131 to 133, comparators 134 and 135, and a latch circuit 136. The comparators 134 and 135 and the latch circuit 136 are connected to the internal power supply voltage V REG The first end of the resistor 131 is connected to the wiring W REG The second end of the resistor 131 is connected to a first end of a resistor 132 at a node 137, the second end of the resistor 132 is connected to a first end of a resistor 133 at a node 138, and the second end of the resistor 133 is connected to ground. SNS The inverting input terminal of the comparator 134 is connected to a node 137, and the inverting input terminal of the comparator 135 is connected to a node 138. In the detection circuit 130 of FIG. 15, the voltage at the node 137 is equal to the threshold voltage V TH [2], and the voltage at node 138 is equal to the threshold voltage V TH [1]. The comparator 134 detects the sense voltage V SNS The voltage at node 137, V TH Compared with [2], the sense voltage V SNS and the voltage at node 137, V TH The comparator 134 outputs a signal indicating the level relationship with [2]. TH [2]≦V SNS When "V TH [2]>V SNS When the condition "is met," the comparator 135 outputs a low-level signal. SNS The voltage at node 138, V TH Compared with [1], the sense voltage V SNS and the voltage at node 138, V TH The comparator 135 outputs a signal indicating the high or low relationship with [1]. TH [1]≦V SNS When "V TH [1]>V SNS When the condition "is met," a low level signal is output.

[0076] The latch circuit 136 latches (holds) the levels of the output signals of the comparators 134 and 135 at the determination timing. The determination circuit 43 having the detection circuit 130 generates and outputs the mode determination signal MD based on the levels latched by the latch circuit 136 (i.e., based on the output signals of the comparators 134 and 135 at the determination timing).

[0077] Even when m≧4, prepare the required number of comparators and calculate the sense voltage and threshold voltage V TH [1]~V TH All you have to do is determine the relationship between [m-1] and [m-2].

[0078] <<Fourth Example>> A fourth embodiment will now be described. Methods MTD1 to MTD4 will be given below as examples of methods for making the operation of the functional circuit 30 different based on differences in operation modes.

[0079] The functional circuit 30 according to the method MTD1 calculates the output voltage V OUT is made different when the operation mode is the xth mode and when the operation mode is the yth mode. x and y represent different natural numbers equal to or less than m, for example, (x, y)=(1, 2) or (x, y)=(2, 1). That is, for example, the functional circuit 30 according to the method MTD1 makes the output voltage V of the regulator 4[i] OUT [i] is set to be different when the operating mode is the xth mode and when the operating mode is the yth mode. OUT [i] is the target voltage V TG In detail, the functional circuit 30 according to the method MTD1 stabilizes the output voltage V of the regulator 4[i]. OUT Target voltage V for [i] TG [i] is made different when the operation mode is the xth mode and when the operation mode is the yth mode.

[0080] For example, when the operation mode of the functional circuit 30 is the xth mode, the output voltage V OUT[i] is the target voltage V of 1.8V TG When the regulator 4[i] operates to stabilize at [i] and the operation mode of the functional circuit 30 is the y-th mode, the output voltage V OUT [i] is the target voltage V of 2.5V TG The regulator 4[i] operates to stabilize the voltage at [i].

[0081] Method MTD1 allows a designer of a system incorporating Power Control Unit 2 to generate the voltage desired from a particular channel.

[0082] The functional circuit 30 according to the method MTD2 generates an output voltage V OUT [1]~V OUT The order of generation of the output voltage V[n] is made different when the operation mode is the xth mode and when the operation mode is the yth mode. After the functional circuit 30 itself is started, it operates the control blocks 10[1] to 10[n] in a predetermined order, thereby generating the output voltage V OUT [1]~V OUT The functional circuit 30 according to the method MTD2 sequentially generates [n] in a predetermined order. The functional circuit 30 according to the method MTD2 switches this generation order depending on the operation mode.

[0083] A specific example of the method MTD2 will be given with reference to FIG. 16. Focusing only on the first and second channels, when the operation mode of the functional circuit 30 is set to the x-th mode, the functional circuit 30 first causes only the control block 10[1] of the control blocks 10[1] and 10[2] to start power conversion and output voltage V OUT [1] is the target voltage V TG [1] or after reaching the target voltage V TG [1], the control block 10[2] starts power conversion and outputs the output voltage V OUT [2] Change the voltage from 0V to the target voltage V TG On the other hand, when the operation mode of the functional circuit 30 is set to the y-th mode, the functional circuit 30 first starts power conversion in only the control block 10[2] of the control blocks 10[1] and 10[2], thereby increasing the output voltage V OUT [2] is the target voltage V TG[2] or after reaching the target voltage V TG [2], the control block 10[1] starts power conversion and outputs the output voltage V OUT [1] Change the voltage from 0V to the target voltage V TG Increase towards [1].

[0084] Method MTD2 allows the designer of a system incorporating power supply control device 2 to determine the output voltages V OUT can be generated.

[0085] The functional circuit 30 according to the method MTD3 performs power conversion (output voltage V OUT When the operation mode is the y-th mode, the power conversion (output voltage V OUT (the generation operation of the

[0086] For example, when the operation mode of the functional circuit 30 is the xth mode, the regulator 4[i] performs power conversion and outputs the output voltage V OUT While [i] occurs ("V OUT [i]=V TG [i]” output voltage V OUT When the operation mode of the functional circuit 30 is the y-th mode, the power conversion by the regulator 4[i] is not performed, and the output voltage V OUT [i] is maintained at 0V.

[0087] Method MTD3 reduces the unwanted output voltage V OUT By using the power supply control device 2, it is possible to stop the generation of the output voltage V OUT However, in some systems, the output voltage V OUT In some cases, only (n-1) channels are required. Using method MTD3, the output voltage V OUT and the output voltage V OUT A common power supply control device 2 can be applied to systems requiring (n-1) channels.

[0088] The functional circuit 30 according to the method MTD4 assigns different addresses to the power control device 2 in communication between the power control device 2 and another device when the operation mode is the xth mode and when the operation mode is the yth mode.

[0089] Method MTD4 will be described in detail with reference to Fig. 17. A system relating to method MTD4 comprises a power supply control device 2, an MCU (Micro Controller Unit) 210, and one or more devices 220 (three devices 220 in Fig. 17). The MCU 210, power supply control device 2, and each device 220 are connected to one another via a communication bus 230. The MCU 210 and power supply control device 2 are capable of bidirectional communication via the communication bus 230. The MCU 210 and each device 220 are capable of bidirectional communication via the communication bus 230. Communication between the MCU 210 and the power supply control device 2 and each device 220 is serial communication, and an I / O is used as an interface for serial communication. 2 An interface using C (Inter-Integrated Circuit) is used.

[0090] In communication in the system of FIG. 17, the MCU 210 functions as a master device, and the power supply control device 2 and each device 220 function as slave devices. Here, it is assumed that the total number of devices 220 is three. Therefore, a total of four slave devices exist in the system of FIG. 17. In this case, the MCU 210 as the master device can communicate with only one of the four slave devices at any given time. The MCU 210 associates unique addresses with the four slave devices. The four slave devices are referred to as first to fourth slave devices, and in the system of FIG. 17, it is assumed that the first to fourth addresses are assigned to the first to fourth slave devices, respectively. When communicating with the first slave device, the MCU 210 outputs a first command signal including an address signal indicating the first address to the communication bus 230. The first command signal is received by each slave device, but of the first to fourth slave devices, only the first slave device assigned the first address responds to the first command signal and performs an operation in accordance with the first command signal. Similarly, when communicating with the second slave device, the MCU 210 outputs a second command signal including an address signal indicating the second address to the communication bus 230. The second command signal is received by each slave device, but of the first to fourth slave devices, only the second slave device assigned the second address responds to the second command signal and performs an operation in accordance with the second command signal. The same applies when communicating with the third or fourth slave device.

[0091] The functional circuit 30 according to the method MTD4 determines the address assigned to the power control device 2 in communication between the power control device 2 and the MCU 210 according to the operation mode. For example, when the first operation mode is set, the functional circuit 30 according to the method MTD4 recognizes that the address assigned to the power control device 2 is the first address and then performs communication. When the second operation mode is set, the functional circuit 30 recognizes that the address assigned to the power control device 2 is the second address and then performs communication. Therefore, when the first operation mode is set, the functional circuit 30 performs an operation in response to a first command signal but does not respond to a second command signal (does not perform an operation in response to the second command signal). When the second operation mode is set, the functional circuit 30 performs an operation in response to a second command signal but does not respond to a first command signal (does not perform an operation in response to the first command signal). The functional circuit 30 according to the method MTD4 can also recognize that the address assigned to the power control device 2 is the third or fourth address according to the operation mode.

[0092] By using method MTD4, it is possible to reduce the number of external terminals required for address setting or to reduce the number of external terminals required for address setting. Note that one or more devices 220 may be power supply control devices having the same configuration as the power supply control device 2. That is, for example, the first to fourth stave devices in the configuration of FIG. 17 may be four power supply control devices 2.

[0093] <<Fifth Example>> A fifth embodiment will be described. The power supply device 1 outputs output voltages V OUT The technology according to the present disclosure has been described assuming that the power supply device 1 is a composite power supply device capable of generating an output voltage V OUT The power supply device 1 may generate only one signal. That is, the value of n may be "1." The above-described techniques can also be applied to a power supply device 1 where "n=1." However, the methods MTD2 and MTD3 shown in the fourth embodiment are only effective when "n≧2."

[0094] <<Sixth Example>> A sixth embodiment will be described. In the sixth embodiment, modifications or supplements to the above-described techniques will be described.

[0095] The power supply control device 2 is a type of semiconductor device. Although an example has been given in which the technology according to the present disclosure is applied to a semiconductor device related to power supply control, the technology according to the present disclosure, including the operation mode setting technology, can also be applied to any semiconductor device (motor driver, LED driver, high-side switch, low-side switch, etc.).

[0096] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0097] The channel types of the FETs (field effect transistors) shown in the above embodiments are merely examples, and the channel type of any FET may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0098] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0099] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0100] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0101] A semiconductor device (2) according to one aspect of the present disclosure generates an internal power supply voltage (V REG ), a functional circuit (30) configured to operate based on the internal power supply voltage, a housing (CS) that houses the internal power supply circuit and the functional circuit, a specific terminal (REG) that is exposed from the housing and configured to receive the internal power supply voltage, and a terminal current (I EX and a mode setting circuit (40) configured to set the operation mode of the functional circuit in accordance with the

[0102] This reduces the burden of manufacturing and inventory management compared to the first reference method described above, and is expected to reduce component size and cost compared to the second reference method described above.

[0103] In the semiconductor device according to the first configuration, after the internal power supply circuit starts generating the internal power supply voltage, the mode setting circuit operates based on the internal power supply voltage to generate a determination signal (MD) corresponding to the terminal current, and thereafter the functional circuit is started up in an operation mode corresponding to the determination signal (second configuration).

[0104] This allows the generation of a determination signal according to the terminal current without being affected by the current consumption of the functional circuit after the functional circuit is started up.

[0105] In the semiconductor device according to the second configuration, the internal power supply circuit may have an output transistor (21) arranged between a power supply terminal (IN) configured to receive the input power supply voltage and the specific terminal, and controls an output current (Ia) flowing through the output transistor so that the internal power supply voltage is stabilized at a predetermined voltage, the terminal current flows through the output transistor and the specific terminal, and the mode setting circuit may be configured (third configuration) to set the operating mode of the functional circuit based on the output current at a determination timing (t3) after the start of the internal power supply voltage generation operation and before the activation of the functional circuit.

[0106] In the semiconductor device according to the third configuration, the mode setting circuit may be configured (fourth configuration) to set the operating mode of the functional circuit based on a reference current (Ib) corresponding to the output current at the judgment timing.

[0107] In the semiconductor device according to the fourth configuration, the mode setting circuit may have a sense transistor (41) that forms a current mirror circuit together with the output transistor, and the reference current may be a current that flows through the sense transistor and is proportional to the output current (fifth configuration).

[0108] In the semiconductor device according to any one of the first to fifth configurations, the mode setting circuit is configured to connect an external resistor (R EX ) is connected to the input terminal of the functional circuit, the operational mode of the functional circuit may be set by determining whether the input terminal of the functional circuit is connected to the input terminal of the functional circuit (sixth configuration).

[0109] This allows the operation mode to be switched depending on whether or not an external resistor is installed.

[0110] In the semiconductor device according to any one of the first to fifth configurations, the mode setting circuit sets the operation mode of the functional circuit in accordance with the terminal current that depends on the magnitude of a resistance component between the specific terminal and ground outside the semiconductor device. The seventh configuration may also be used.

[0111] This allows the operation mode to be switched depending on whether an external resistor is installed or the value of the external resistor when an external resistor is installed.

[0112] In the semiconductor device according to any one of the first to seventh configurations, the semiconductor device is a power supply control device (2) configured to control the operation of a power supply device (1), the power supply device having a regulator (4) of multiple channels, and adjusting an input voltage (V IN ) to the output voltage (V OUT ), and the power conversion may be controlled for each of the channels by the functional circuit (eighth configuration).

[0113] In the semiconductor device according to the eighth configuration (see method MTD1), the mode setting circuit may set the operating mode of the functional circuit to one of a plurality of modes including a first mode and a second mode depending on the terminal current, and the functional circuit may be configured to make the output voltage of a regulator of a specific channel different between the first mode and the second mode (ninth configuration).

[0114] In the semiconductor device according to the eighth configuration (see method MTD2), the mode setting circuit may set the operating mode of the functional circuit to one of a plurality of modes including a first mode and a second mode depending on the terminal current, and the functional circuit may be configured (tenth configuration) such that, in one of the first mode and the second mode, it starts power conversion by a regulator of a first channel before starting power conversion by a regulator of a second channel, and in the other of the first mode and the second mode, it starts the power conversion by the regulator of the second channel before starting the power conversion by the regulator of the first channel.

[0115] In the semiconductor device according to the eighth configuration (see method MTD3), the mode setting circuit may set the operating mode of the functional circuit to one of a plurality of modes including a first mode and a second mode depending on the terminal current, and the functional circuit may perform power conversion by a regulator of a specific channel in one of the first mode and the second mode, and stop power conversion by the regulator of the specific channel in the other of the first mode and the second mode (eleventh configuration).

[0116] In a semiconductor device according to the eighth configuration (see method MTD4), the mode setting circuit may set the operating mode of the functional circuit to one of a plurality of modes including a first mode and a second mode depending on the terminal current, and the functional circuit may perform communication by recognizing that an address assigned to the semiconductor device in communication between the semiconductor device and another device is a first address in the first mode, and a second address in the second mode (twelfth configuration).

[0117] In the semiconductor device according to any one of the first to seventh configurations (see the fifth embodiment), the semiconductor device is a power supply control device configured to control the operation of a power supply device (1), and the power supply device is configured to receive an input voltage (V IN ) to the output voltage (V OUT), and the power conversion may be controlled by the functional circuit (thirteenth configuration).

[0118] In the semiconductor device according to the thirteenth configuration, the mode setting circuit may set the operating mode of the functional circuit to one of a plurality of modes including a first mode and a second mode depending on the terminal current, and the functional circuit may be configured to make the output voltage different between the first mode and the second mode (fourteenth configuration).

[0119] In the semiconductor device according to the thirteenth configuration, the mode setting circuit may set the operating mode of the functional circuit to one of a plurality of modes including a first mode and a second mode depending on the terminal current, and the functional circuit may recognize that the address assigned to the semiconductor device in communication between the semiconductor device and another device is a first address in the first mode and perform the communication, and recognize that the address assigned to the semiconductor device is a second address in the second mode and perform the communication (fifteenth configuration). [Explanation of symbols]

[0120] 1 Power supply 2 Power supply control device 3 Disc lead parts group 4, 4[1]~4[n], 4[i A ], 4[i B ] Regulator 10, 10[1]~10[n], 10[i A ], 10[i B ] Control Block 11, 12, 14 Transistors 13, 15 Control drive circuit L[i A ] Output coil C[i A ], C[i B ] Output capacitor V IN , V IN [1]~V IN [n], V IN [i A ], VIN [i B ] Input voltage V OUT , V OUT [1]~V OUT [n], V OUT [i A ], V OUT [i B ] Output voltage OUT[i A ], OUT[i B ] Output node VS[i A ] Input terminal SW[i A ] Switch terminal PGND[i A ] Ground terminal VO[i A ] Feedback terminal VS[i B ] Input terminal VO[i B ] Output terminal GND Ground terminal 20 Internal power circuit 21 Output transistor 23, 24 Voltage dividing resistor 25 Reference voltage source 30 Functional Circuits 40 Mode setting circuit 41 Sense transistor 42 Sense resistor 43 Judgment circuit C REG capacitor R EX External Resistor IN power supply terminal REG terminal V REG Internal Power Supply Voltage V SNS Sense Voltage Ia, Ib current I EX terminal current EN2 signal MD mode determination signal 110, 120, 130 Detection circuit 111 Inverter circuit 112, 124, 136 Latch circuit 121, 122, 131-133 Resistor 123, 134, 135 Comparators 210 MCU 220 Equipment 230 Communication Bus

Claims

1. an internal power supply circuit configured to generate an internal power supply voltage based on an input power supply voltage; a functional circuit configured to operate based on the internal power supply voltage; a housing that houses the internal power supply circuit and the functional circuit; a specific terminal exposed from the housing, the specific terminal being configured to receive the internal power supply voltage; a mode setting circuit configured to set an operation mode of the functional circuit in accordance with a terminal current flowing through the specific terminal; , semiconductor device.

2. After the internal power supply circuit starts generating the internal power supply voltage, the mode setting circuit operates based on the internal power supply voltage to generate a determination signal corresponding to the terminal current, and then the functional circuit is started in an operation mode corresponding to the determination signal. The semiconductor device according to claim 1 .

3. the internal power supply circuit has an output transistor provided between a power supply terminal configured to receive the input power supply voltage and the specific terminal, and controls an output current flowing through the output transistor so that the internal power supply voltage is stabilized at a predetermined voltage; the terminal current flows through the output transistor and the specific terminal; The mode setting circuit sets the operation mode of the functional circuit based on the output current at a determination timing after the start of the generation operation of the internal power supply voltage and before the activation of the functional circuit. The semiconductor device according to claim 2 .

4. The mode setting circuit sets the operation mode of the functional circuit based on a reference current corresponding to the output current at the determination timing. The semiconductor device according to claim 3 .

5. the mode setting circuit has a sense transistor that configures a current mirror circuit together with the output transistor; The reference current is a current that flows through the sense transistor and is proportional to the output current. The semiconductor device according to claim 4 .

6. The mode setting circuit determines whether or not an external resistor is connected between the specific terminal and ground outside the semiconductor device in accordance with the terminal current, thereby setting an operation mode of the functional circuit.

6. The semiconductor device according to claim 1.

7. The mode setting circuit sets the operation mode of the functional circuit in accordance with the terminal current that depends on the magnitude of a resistance component between the specific terminal and ground outside the semiconductor device.

6. The semiconductor device according to claim 1.

8. The semiconductor device is a power supply control device configured to control the operation of a power supply device, the power supply device has a regulator for each of the multiple channels, and performs power conversion for generating an output voltage from an input voltage for each of the channels; The power conversion is controlled for each of the channels by the functional circuit.

6. The semiconductor device according to claim 1.

9. the mode setting circuit sets an operation mode of the functional circuit to one of a plurality of modes including a first mode and a second mode in accordance with the terminal current; The functional circuit causes the output voltage of the regulator of the specific channel to differ between the first mode and the second mode. The semiconductor device according to claim 8 .

10. the mode setting circuit sets an operation mode of the functional circuit to one of a plurality of modes including a first mode and a second mode in accordance with the terminal current; The functional circuit starts power conversion by a regulator of a first channel before starting power conversion by a regulator of a second channel in one of the first mode and the second mode, and starts the power conversion by the regulator of the second channel before starting the power conversion by the regulator of the first channel in the other of the first mode and the second mode. The semiconductor device according to claim 8 .

11. the mode setting circuit sets an operation mode of the functional circuit to one of a plurality of modes including a first mode and a second mode in accordance with the terminal current; The functional circuit executes power conversion by a regulator of a specific channel in one of the first mode and the second mode, and stops power conversion by the regulator of the specific channel in the other of the first mode and the second mode. The semiconductor device according to claim 8 .

12. the mode setting circuit sets an operation mode of the functional circuit to one of a plurality of modes including a first mode and a second mode in accordance with the terminal current; The functional circuit recognizes that an address assigned to the semiconductor device in communication between the semiconductor device and another device is a first address in the first mode and recognizes that the address is a second address in the second mode and performs the communication. The semiconductor device according to claim 8 .

13. The semiconductor device is a power supply control device configured to control the operation of a power supply device, the power supply performs power conversion to generate an output voltage from an input voltage; The functional circuit controls the power conversion.

6. The semiconductor device according to claim 1.

14. the mode setting circuit sets an operation mode of the functional circuit to one of a plurality of modes including a first mode and a second mode in accordance with the terminal current; The functional circuit causes the output voltage to differ between the first mode and the second mode. The semiconductor device according to claim 13 .

15. the mode setting circuit sets an operation mode of the functional circuit to one of a plurality of modes including a first mode and a second mode in accordance with the terminal current; The functional circuit recognizes that an address assigned to the semiconductor device in communication between the semiconductor device and another device is a first address in the first mode and recognizes that the address is a second address in the second mode and performs the communication. The semiconductor device according to claim 13 .

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