Display device, photoelectric conversion device, and electronic apparatus

Abstract

To provide a display device that has further reduced a data amount of display data (data used for display in the end).SOLUTION: A display device has a substrate, a plurality of pixels arranged in a display region on the substrate, and a control circuit controlling signals to be supplied to the pixels. The display region includes a first region and a second region surrounding the first region. A part of the first region is set as a third region, a position of which is variable. By controlling the signals to be supplied to the pixels, the display resolution of a fourth region other than the third region in the first region becomes lower than the display resolution of the third region. By the circuit configuration of the pixels, the display resolution of the second region becomes equal to or lower than the display resolution of the fourth region.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a display device, a photoelectric conversion device, and an electronic device. [Background technology]

[0002] There are a variety of display devices with different applications, including liquid crystal display elements and organic electroluminescence (OLED) display elements, including large display devices such as digital signage, medium-sized display devices such as laptops and smartphones, and small display devices used in XR devices. For all display devices, the number of pixels is increasing to improve display quality. However, increasing the number of pixels increases power consumption and the processing load (computational volume) using display data. To resolve these issues, active development of display control technologies is underway.

[0003] Patent Document 1 describes that in a display device having two-dimensionally arranged display elements, the peripheral display elements are larger than the central display elements in order to reduce the number of pixels relative to the display area. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-117553 Summary of the Invention [Problem to be solved by the invention]

[0005] Patent Document 1 describes a technique for reducing the number of pixels. Reducing the number of pixels can reduce the amount of display data (data ultimately used for display), but there is room for improvement in reducing the amount of data in areas with small pixels.

[0006] The present invention has been made in view of the above-mentioned problems, and has an object to provide a display device in which the amount of display data (data ultimately used for display) is further reduced. [Means for solving the problem]

[0007] The display device of the present invention comprises a substrate, a plurality of pixels arranged in a display area on the substrate, and a control circuit that controls signals supplied to the pixels, wherein the display area includes a first area and a second area surrounding the first area, a portion of the first area is set as a third area whose position can be changed, and by controlling the signals supplied to the pixels, the display resolution of a fourth area in the first area that is not the third area becomes lower than the display resolution of the third area, and the circuit configuration of the pixels makes the display resolution of the second area lower than the display resolution of the fourth area. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a display device in which the amount of display data (data ultimately used for display) is further reduced. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic diagram illustrating an example of a display device. [Figure 2] FIG. 2 is a schematic diagram illustrating an example of a display area. [Figure 3] FIG. 2 is a schematic diagram showing an example of an arrangement of light-emitting elements and sub-pixels. [Figure 4] FIG. 2 is a circuit diagram showing an example of a basic configuration of a sub-pixel circuit. [Figure 5] FIG. 10 is a circuit diagram showing an example of the configuration of a sub-pixel circuit in a high-definition displayable area. [Figure 6] FIG. 2 is a circuit diagram showing an example of the configuration of a sub-pixel circuit in a low-definition display area. [Figure 7] FIG. 10 is a circuit diagram showing a modified example of the configuration of the sub-pixel circuit in the low-definition display area. [Figure 8]10 is a timing chart showing an example of the timing of writing and light emission. [Figure 9] FIG. 2 is a circuit diagram showing an example of the configuration of a vertical scanning circuit. [Figure 10] 10 is a timing chart showing an example of a resolution control signal and a scanning control signal. [Figure 11] FIG. 10 is a schematic diagram showing a modified example of the display area. [Figure 12] FIG. 2 is a circuit diagram showing an example of the configuration of a sub-pixel circuit in a low-definition display area. [Figure 13] FIG. 10 is a circuit diagram showing a modified example of the configuration of the sub-pixel circuit in the low-definition display area. [Figure 14] FIG. 10 is a circuit diagram showing a modified example of the configuration of the sub-pixel circuit in the low-definition display area. [Figure 15] FIG. 10 is a circuit diagram showing a modified example of the configuration of the sub-pixel circuit in the low-definition display area. [Figure 16] FIG. 10 is a circuit diagram showing a modified example of the configuration of the sub-pixel circuit in the low-definition display area. [Figure 17] FIG. 1 is a schematic diagram showing an example of a cross section of a part of a display device. [Figure 18] FIG. 2 is a schematic diagram illustrating an example of a cross section of a pixel. [Figure 19] FIG. 2 is a schematic diagram illustrating an example of a display component. [Figure 20] FIG. 1 is a schematic diagram illustrating an example of an imaging device and an electronic device. [Figure 21] FIG. 1 is a schematic diagram illustrating an example of an image display device. [Figure 22] FIG. 1 is a schematic diagram showing an example of glasses. [Figure 23] FIG. 1 is a schematic diagram showing an example of an image observation device. DETAILED DESCRIPTION OF THE INVENTION

[0010] (Embodiment 1) Hereinafter, a first embodiment of the present invention will be described. Fig. 1 is a schematic diagram showing an example of a display device according to the first embodiment. The display device 100 has a substrate 101, a pixel array unit 102, a vertical scanning circuit 103, a signal output circuit 104, and a control circuit 105. The pixel array unit 102, the vertical scanning circuit 103, the signal output circuit 104, and the control circuit 105 are provided on the substrate 101.

[0011] The pixel array unit 102 has a plurality of pixels 106. The area in which the plurality of pixels 106 are arranged functions as a display area for displaying an image. Each pixel 106 has a sub-pixel 107A that displays red (R), a sub-pixel 107B that displays green (G), and a sub-pixel 107C that displays blue (B). Hereinafter, the sub-pixels 107A to 107C will be referred to as sub-pixel 107 without distinction. Note that each pixel 106 may have three or more sub-pixels 107. The size of each pixel 106 and the size of each sub-pixel 107 are not particularly limited, but in the first embodiment, the size of one pixel 106 and the size of one sub-pixel 107 differ depending on the position in the display area. Details of this will be described later.

[0012] The vertical scanning circuit 103 and the plurality of sub-pixels 107 are connected to one another by a plurality of scanning lines 108 (vertical scanning signal lines). The vertical scanning circuit 103 switches among the plurality of scanning lines 108 to which a scanning signal (vertical scanning signal) is supplied, to scan (sequentially select) the plurality of sub-pixels 107 in the vertical direction (from top to bottom or from bottom to top). For example, the vertical scanning circuit 103 is configured using a shift register that sequentially shifts (transfers) a start pulse in synchronization with a clock pulse. The scanning lines 108 include light-emitting control lines and write control lines, which will be described later.

[0013] The signal output circuit 104 and the plurality of sub-pixels 107 are connected to one another by a plurality of signal lines 109 (horizontal scanning signal lines). The signal output circuit 104 supplies signals (horizontal scanning signals, voltages) corresponding to image data to the plurality of signal lines 109, thereby supplying the signals to the sub-pixels 107 selected by the vertical scanning circuit 103. As a result, the sub-pixels 107 selected by the vertical scanning circuit 103 emit light with a luminance corresponding to the image data. An image is displayed by scanning the plurality of sub-pixels 107 and causing them to emit light sequentially.

[0014] The control circuit 105 controls the signals to be supplied to each pixel via the vertical scanning circuit 103 and the signal output circuit 104 based on image data and the like.

[0015] 2A and 2B are schematic diagrams showing an example of a display area according to the first embodiment. The display area 200 includes a high-definition displayable area 201 and a low-definition display area 202 surrounding the high-definition displayable area 201. In the first embodiment, a portion of the high-definition displayable area 201 is set as the high-definition display area 203. For example, based on the detection results of a gaze detection unit that detects the user's gaze, the area where the gaze of the user viewing the video is directed may be set as the high-definition display area 203. The area where a predetermined object, such as a person's face or a road sign, is displayed in an image captured by an imaging unit (captured image) may be set as the high-definition display area 203. The area specified by a region designation unit having information designated by the video creator or user may be set as the high-definition display area 203. As shown in FIG. 2A, one high-definition display area 203 may be set, or as shown in FIG. 2B, multiple high-definition display areas 203 may be set. The position, size, and number of the high-definition display areas 203 are changeable.

[0016] The setting of the high-definition display area 203 may be performed by the display device 100 (control circuit 105) or by a device external to the display device 100 (for example, an external device that generates image data to be displayed). The above-mentioned gaze detection unit, imaging unit, area designation unit, etc. may be provided in the display device 100 or may be devices external to the display device 100. The method for detecting the gaze is not particularly limited. For example, the gaze may be detected based on the positional relationship between the pupil and the Purkinje image in an image of the user's eye. The method for detecting a predetermined object from a captured image is also not particularly limited. For example, the predetermined object may be detected by template matching, or the predetermined object may be detected by a classifier using a trained model. The classifier, for example, receives image data as input and outputs coordinate data indicating the area of ​​the predetermined object.

[0017] In the first embodiment, each subpixel 107 has one or more light-emitting elements. FIG. 3A is a schematic diagram illustrating an example of an arrangement of light-emitting elements according to the first embodiment. As shown in FIG. 3A, a plurality of light-emitting elements 301 are uniformly arranged in a two-dimensional array (matrix). The light-emitting elements 301 are, for example, organic light-emitting elements. The plurality of light-emitting elements 301 include a light-emitting element emitting red (R), a light-emitting element emitting green (G), and a light-emitting element emitting blue (B). The R subpixel 107A has one or more R light-emitting elements, the G subpixel 107B has one or more G light-emitting elements, and the B subpixel 107C has one or more B light-emitting elements. The sizes of the light-emitting regions of the light-emitting elements 301 for R, G, and B are approximately equal. The sizes of the light-emitting regions of the light-emitting elements 301 for R, G, and B may be equal or different. It is more preferable that the light-emitting regions of each subpixel are congruent. Here, the size of the light-emitting region may be the area of ​​the light-emitting region, which may be, for example, the size of an opening in a pixel separation layer. Furthermore, "approximately equal" includes the possibility of differences within the range of manufacturing tolerances, and also includes being substantially equal.

[0018] FIG. 3B is a schematic diagram showing an example of the arrangement of sub-pixel circuits (circuits of sub-pixels 107) according to embodiment 1. In the high-definition displayable region 201, small sub-pixel circuits 311 are used to enable high-definition display. In the low-definition display region 202, large sub-pixel circuits 312 are used because low-definition display is sufficient. The high-definition displayable region 201, in which the small sub-pixel circuits are arranged, is an area where the density of the sub-pixel circuits is higher than that of the low-definition display region 202, and where the pitch of the write transistors, which will be described later, is smaller than that of the low-definition display region 202. The density of the sub-pixel circuits can be estimated, for example, by the number of transistors per area in a plan view, and may be estimated by the number of write transistors. The pitch of the write transistors can be determined in either the row direction or the column direction in the arrangement direction of the light-emitting elements 301. The low-definition display region 202, in which large sub-pixel circuits are arranged, is a region in which the density of the sub-pixel circuits is lower than that of the high-definition displayable region 201, and the pitch of the writing transistors is larger than that of the high-definition displayable region 201. The number of light-emitting elements 301 included in the sub-pixel circuit 312 in the low-definition display region 202 is greater than the number of light-emitting elements 301 included in the sub-pixel circuit 311 in the high-definition displayable region 201. In other words, when the number of light-emitting elements 301 connected to one sub-pixel circuit in the high-definition display region is one, the number of light-emitting elements 301 connected to one sub-pixel circuit in the low-definition display region is two or more. Note that it is sufficient if there is a region in which the number of light-emitting elements 301 included in the sub-pixel circuit 312 in the low-definition display region 202 is greater than the number of light-emitting elements 301 included in the sub-pixel circuit 311 in the high-definition displayable region 201. There may be an area where the number of light-emitting elements 301 included in the sub-pixel circuit 312 in the low-definition display area 202 is equal to the number of light-emitting elements 301 included in the sub-pixel circuit 311 in the high-definition displayable area 201 .

[0019] 3C is a schematic diagram showing an example of the arrangement of subpixels in a displayed image according to embodiment 1. In the low-definition display region 202, a large subpixel 322 corresponding to a large subpixel circuit 312 is displayed. Under the control of the control circuit 105, signals (horizontal scanning signal, voltage) corresponding to image data are individually supplied to adjacent subpixel circuits 311 in the high-definition display region 203. Therefore, a small subpixel 323 corresponding to the small subpixel circuit 311 is displayed. Under the control of the control circuit 105, the same signals (horizontal scanning signal, voltage) corresponding to image data are supplied to adjacent subpixel circuits 311 in a region other than the high-definition display region 203 (non-high-definition display region 204) in the high-definition displayable region 201. Therefore, multiple subpixels corresponding to multiple subpixel circuits 311 are displayed as if they were a single subpixel. The size of the light-emitting region of the sub-pixel in the low-definition display region 202 may be the same as or different from the size of the light-emitting region of the region displayed as one sub-pixel in the non-high-definition display region 204. The size of the light-emitting region of the sub-pixel in the low-definition display region 202 may be larger than the size of the light-emitting region of the region displayed as one sub-pixel in the non-high-definition display region 204.

[0020] 3A to 3C, the sub-pixels 107 are described as being the focus of the explanation. However, since each pixel 106 has a plurality of sub-pixels 107, the same can be said about the pixels 106 as about the sub-pixels 107.

[0021] In this way, by controlling the signals (horizontal scanning signals, voltages) supplied to the pixels, the display resolution of the non-high-definition display area 204 is made lower than the display resolution of the high-definition display area 203. Then, by the circuit configuration of the pixels, the display resolution of the low-definition display area 202 is made lower than the display resolution of the non-high-definition display area 204. By dividing the display area into three or more areas and determining the display resolution of each area by the circuit configuration and signal control, it is possible to provide a display device with an even smaller amount of display data (data ultimately used for display).

[0022] Fig. 4A is a circuit diagram showing an example of the basic configuration of a subpixel 107 (subpixel circuit) according to embodiment 1. As shown in Fig. 4A, the subpixel 107 has a light-emitting element 301, a driving transistor 401, a writing transistor 402, a light-emitting control transistor 403, a first capacitor 404, and a second capacitor 405. Note that the total number of transistors and capacitors and the combination of transistor conductivity types are merely examples and are not limited to this configuration.

[0023] One of the source and drain (here, the drain) of the driving transistor 401 is connected to the first electrode of the light-emitting element 301. The other of the source and drain (here, the source) of the driving transistor 401 is connected to one of the source and drain (here, the drain) of the light-emitting control transistor 403. The other of the source and drain of the light-emitting control transistor 403 4A, the source of the light-emitting control transistor 403 is connected to a first power supply terminal 406 (hereinafter, Vdd). The light-emitting control transistor 403 can function as a switch that connects the source of the driving transistor 401 to Vdd 406. A second electrode of the light-emitting element 301 is connected to a second power supply terminal 407 (hereinafter, Vss). One of the source and drain of the writing transistor 402 (here, the source) is connected to the gate of the driving transistor 401, and the other of the source and drain of the writing transistor 402 (here, the drain) is connected to the signal line 109. The writing transistor 402 can function as a switch that connects the gate of the driving transistor 401 to the signal line 109.

[0024] The gate of the write transistor 402 is connected to a write control line 408 of the scanning line 108. The gate of the light emission control transistor 403 is connected to a light emission control line 409 of the scanning line 108.

[0025] The first capacitance element 404 is connected between the gate of the driving transistor 401 and one of the source and drain (here, the source) of the driving transistor 401. The second capacitance element 405 is connected between one of the source and drain (here, the source) of the driving transistor 401 and Vdd 406. Both the first capacitance element 404 and the second capacitance element 405 are connected to the source of the driving transistor 401. The first capacitance element 404 and the second capacitance element 405 may be parasitic capacitances or capacitances having an MIM (Metal-Insulator-Metal) structure.

[0026] An outline of the operation during the light emission period when the light emitting element 301 emits light will be described below. The driving transistor 401 supplies a current from Vdd 406 to the light emitting element 301, causing the light emitting element 301 to emit light. For example, the driving transistor 401 supplies a current to the light emitting element 301 according to the voltage (horizontal scanning signal) of the signal line 109. In this way, the light emitting element 301 is current-driven to emit light.

[0027] When the light emitting element 301 emits light, the writing transistor 402 becomes conductive in response to a scanning signal (writing control signal) applied to its gate from the vertical scanning circuit 103 via a writing control line 408. This causes the writing transistor 402 to write a voltage (horizontal scanning signal) supplied from the signal output circuit 104 to the subpixel 107 via a signal line 109. This written voltage is applied to the gate of the driving transistor 401. The voltage (horizontal scanning signal) supplied from the signal output circuit 104 will hereinafter be referred to as Vsig.

[0028] The emission control transistor 403 is turned on in response to a scanning signal (emission control signal) applied to its gate from the vertical scanning circuit 103 via an emission control line 409, thereby allowing current to be supplied from Vdd 406 to the drive transistor 401. This enables the drive transistor 401 to emit light from the light-emitting element 301. That is, the emission control transistor 403 functions as a transistor that controls the emission and non-emission of the light-emitting element 301. In this way, the switching operation of the emission control transistor 403 can control the ratio of the emission period and non-emission period of the light-emitting element 301. This can reduce afterimages caused by the sub-pixel 107 emitting light during the emission period in one frame period, thereby improving image quality, particularly when displaying moving images. The ratio of emission and non-emission during one frame can be controlled as so-called duty control, or the timing of emission can be controlled.

[0029] The luminance of the light emitting element 301 can be changed by changing the amount of current flowing through the driving transistor 401. The capacitance between the first electrode (here, an anode) and the second electrode (here, a cathode) of the light emitting element 301 is charged to a predetermined potential, and a current according to the potential difference is applied to the light emitting element. This causes the light emitting element 301 to emit light at a predetermined brightness.

[0030] Due to variations during manufacturing, the threshold voltage of the driving transistor 401 may differ for each subpixel 107. When the same Vsig is written to multiple subpixels 107 that emit the same light, the amount of current flowing through the driving transistor 401 differs for each subpixel 107, resulting in variations in the amount of light emitted. Therefore, before Vsig is applied to the gate of the driving transistor 401, a so-called threshold correction operation is performed in which the threshold voltage of the driving transistor 401 is held in a first capacitance element 404 between the gate and source of the driving transistor 401. This threshold correction operation reduces variations in the amount of current through the driving transistor 401 in each subpixel 107, thereby achieving uniform light emission.

[0031] The basic configuration of the subpixel 107 may be the configuration shown in FIG. 4B . In FIG. 4B , a reset transistor 410 is added. One of the source and drain of the reset transistor 410 is connected to the first electrode of the light-emitting element 301, and the other of the source and drain of the reset transistor 410 is connected to a third power supply terminal 411. The third power supply terminal 411 may be at the same potential as the second power supply terminal 407 or may be grounded. The gate of the reset transistor 410 is connected to the vertical scanning circuit 103, and the switching operation (on (conducting) / off (non-conducting)) of the reset transistor 410 is controlled by a control signal from the vertical scanning circuit 103. When the reset transistor 410 is in the on state, no current flows through the light-emitting element 301, and the light-emitting element 301 does not emit light. Therefore, by providing the reset transistor 410, unnecessary current is prevented from flowing through the light-emitting element 301, thereby preventing a decrease in the contrast of the displayed image.

[0032] Fig. 5 is a circuit diagram showing an example of the configuration of small sub-pixel circuits 311 in the high-definition displayable area 201. Fig. 5 shows a total of four sub-pixel circuits 311, two in the horizontal direction (row direction) and two in the vertical direction (column direction). Some components of the sub-pixel circuits 311, such as the first capacitance element 404 and the second capacitance element 405, are omitted from Fig. 5.

[0033] The number of light-emitting elements 301 included in the sub-pixel circuit 311 is not particularly limited, but in FIG. 5, one sub-pixel circuit 311 includes one light-emitting element 301. Therefore, signal lines 109a to 109d are (indirectly) connected to the light-emitting elements 301a to 301d that are adjacent to each other. Signal line 109a is connected to the drain of the write transistor 402a corresponding to the light-emitting element 301a, and signal line 109b is connected to the drain of the write transistor 402b corresponding to the light-emitting element 301b. Similarly, signal line 109c is connected to the drain of the write transistor 402c corresponding to the light-emitting element 301c, and signal line 109d is connected to the drain of the write transistor 402d corresponding to the light-emitting element 301d. When signal lines are connected to transistors, they may be connected via other elements as long as they are electrically connected. The same applies to the other connections described below.

[0034] For ease of understanding, all of the signal lines 109a to 109d are shown separately, but since the light-emitting elements 301a and 301c are light-emitting elements 301 in the same column, the signal lines 109a and 109c connected to them are the same signal line 109. Similarly, since the light-emitting elements 301b and 301d are light-emitting elements 301 in the same column, the signal lines 109b and 109d connected to them are the same signal line 109.

[0035] In FIG. 5, two light emission control lines 409ab and 409cd are used. The light emission control line 409ab is (indirectly) connected to the light emitting elements 301a and 301b in the same row, and the light emission control line 409cd is (indirectly) connected to the light emitting elements 301c and 301d in the same row. The light emission control line 409ab is connected to the gates of the light emission control transistors 403a and 403b corresponding to the light emitting elements 301a and 301b, respectively. The light emission control line 409cd is connected to the gates of the light emitting control transistors 403a and 403b corresponding to the light emitting elements 301a and 301b, respectively. The photoelectric elements 301c and 301d are connected to the gates of the light emission control transistors 403c and 403d, respectively.

[0036] 5, two write control lines 408ab and 408cd are used. The write control line 408ab is (indirectly) connected to the light emitting elements 301a and 301b in the same row, and the write control line 408cd is (indirectly) connected to the light emitting elements 301c and 301d in the same row. The write control line 408ab is connected to the gates of the write transistors 402a and 402b corresponding to the light emitting elements 301a and 301b, respectively. The write control line 408cd is connected to the gates of the write transistors 402c and 402d corresponding to the light emitting elements 301c and 301d, respectively.

[0037] The source of the write transistor 402a is connected to the gate of the drive transistor 401a corresponding to the light-emitting element 301a, and the source of the write transistor 402b is connected to the gate of the drive transistor 401b corresponding to the light-emitting element 301b. Similarly, the source of the write transistor 402c is connected to the gate of the drive transistor 401c corresponding to the light-emitting element 301c. And the source of the write transistor 402d is connected to the gate of the drive transistor 401d corresponding to the light-emitting element 301d.

[0038] Fig. 6 is a circuit diagram showing an example of the configuration of a large sub-pixel circuit 312 in the low-definition display region 202. The number of light-emitting elements 301 included in the sub-pixel circuit 312 is not particularly limited, but in Fig. 6, one sub-pixel circuit 312 has four light-emitting elements 301a to 301d that are adjacent to one another. In Fig. 6, one sub-pixel circuit 312 has a size equivalent to that of a total of four sub-pixel circuits 311 in the high-definition displayable region 201, two in the horizontal direction and two in the vertical direction.

[0039] 6, two emission control lines 409ab and 409cd are used, as in FIG. 5. The number of emission control lines 409 included in the subpixel circuit 312 is not particularly limited, and for example, one emission control line 409 connected (indirectly) to the light-emitting elements 301a to 301d may be used. This makes it possible to simultaneously light up the light-emitting elements 301a to 301d. Furthermore, reducing the number of emission control lines 409 can reduce power consumption. Although details will be described later, even when two emission control lines 409ab and 409cd are used, the light-emitting elements 301a to 301d can be simultaneously lighted up by the configuration of the vertical scanning circuit 103 and the switching operation within the vertical scanning circuit 103.

[0040] In FIG. 6, one signal line 109 is (indirectly) connected to the light emitting elements 301a to 301d. In FIG. 6, one write transistor 402 is used. Therefore, the number of write control lines 408 used is also one, and the same write control line 408 is (indirectly) connected to the light emitting elements 301a to 301d. The signal line 109 is connected to the drain of the write transistor 402, and the source of the write transistor 402 is connected to the gates of the drive transistors 401a to 401d corresponding to the light emitting elements 301a to 301d, respectively. By reducing the number of signal lines 109 and write control lines 408, it is possible to reduce power consumption.

[0041] Fig. 7 is a circuit diagram showing a modified example of the configuration of a large sub-pixel circuit 312 in the low-definition display region 202. In Fig. 7, as in Fig. 6, one sub-pixel circuit 312 has the same size as two horizontal and two vertical sub-pixel circuits 311 (total of four) in the high-definition displayable region 201. Also, in Fig. 7, as in Fig. 6, two light-emitting control lines 409ab and 409cd are used.

[0042] In FIG. 7, similarly to FIG. 6, one signal line 109 is connected to the light emitting elements 301a to 301d (indirectly). 6 and 7. However, the destination of the signal line 109 is different between FIG. 6 and FIG. 7. In FIG. 7, two write control lines 408ab and 408cd and four write transistors 402a to 402d are used, as in FIG. 5. The signal line 109 is connected to the drains of the write transistors 402a to 402d.

[0043] 5 and 7 have the same number of write transistors 402, light emission control transistors 403, write control lines 408, and light emission control lines 409. By making the configuration of the large sub-pixel circuits 312 in the low-definition display area 202 closer to the configuration of the small sub-pixel circuits 311 in the high-definition displayable area 201, the characteristics of the sub-pixel circuits 312 can be made closer to the characteristics of the sub-pixel circuits 311. As a result, it is possible to mitigate changes in display characteristics at the boundary between the low-definition display area 202 and the high-definition displayable area 201.

[0044] Among the multiple sub-pixel circuits 312 in the low-definition display region 202, the sub-pixel circuits 312 arranged in the vertical direction (above or below) with respect to the high-definition displayable region 201 can use the signal lines 109 connected to the sub-pixel circuits 311 in the high-definition displayable region 201. The sub-pixel circuits 312 arranged in the vertical direction with respect to the high-definition displayable region 201 may also be interpreted as sub-pixel circuits 312 whose horizontal position is within the range of the high-definition displayable region 201.

[0045] Therefore, the sub-pixel circuits 312 arranged in the vertical direction relative to the high-definition displayable area 201 may have the configuration shown in FIG. 5. In this case, the same signal (Vsig) corresponding to image data is supplied to the light-emitting elements 301a to 301d of the sub-pixel circuits 312. By configuring the sub-pixel circuits 312 arranged in the vertical direction relative to the high-definition displayable area 201 in the configuration shown in FIG. 5, it is possible to reduce variations in the length (load capacitance) of the signal lines 109 within the horizontal range in which the high-definition displayable area 201 exists. This in turn reduces variations in the display characteristics in the high-definition displayable area 201, thereby improving the quality of the displayed image.

[0046] Fig. 8A is a timing chart showing an example of the timing at which a write control signal is supplied and the timing at which a light-emission control signal is supplied. Fig. 8A is a timing chart corresponding to a sub-pixel circuit 311, among the multiple sub-pixel circuits 311 in the non-high-definition display area 204, for which the high-definition display area 203 does not exist in the row direction. Fig. 8A assumes that the same signal (Vsig) corresponding to image data is supplied to the sub-pixel circuit 311 in the kth row and the sub-pixel circuit 311 in the k+1th row. In Fig. 8A, a write control signal is supplied to the sub-pixel circuit 311 in the kth row and the sub-pixel circuit 311 in the k+1th row at the same timing.

[0047] In this way, the write control signals are supplied simultaneously to the light emitting elements 301 in multiple rows where no high-definition display area 203 exists in the row direction. Control may be performed in the same way for areas in the low-definition display area 202 where no high-definition display area 203 exists in the row direction. This makes it possible to speed up the supply of the write control signals, suppress a decrease in frame rate due to an increase in the number of pixels, and enable a higher frame rate.

[0048] Note that light emission control signals for light emitting elements 301 in multiple rows where no high definition display area 203 exists in the row direction may be supplied at the same timing (period), which also makes it possible to achieve a high frame rate.

[0049] 8B is a timing chart showing another example of the timing at which the write control signal is supplied and the timing at which the light emission control signal is supplied. Fig. 8B is a timing chart corresponding to the sub-pixel circuits 311 in the row direction of the high-definition display area 203, among the multiple sub-pixel circuits 311 in the non-high-definition display area 204. In Fig. 8B, the same signal (Vsig) according to image data is supplied to the sub-pixel circuit 311 in the kth row and the sub-pixel circuit 311 in the k+1th row. It is assumed that when a high-definition display area 203 exists in the row direction, the sub-pixel circuits 311 must be selected row by row to perform high-definition display in the high-definition display area 203. For this reason, in FIG. 8B , the write control signal is supplied to the sub-pixel circuit 311 in the kth row and the sub-pixel circuit 311 in the k+1th row at different times. The same applies to the light-emission control signal.

[0050] 9A and 9B are circuit diagrams showing an example of the configuration of the vertical scanning circuit 103. The vertical scanning circuit 103 has a shift register 901 between the write control lines 408 of each row so that the plurality of light emitting elements 301 can be selected row by row. The vertical scanning circuit 103 also has a plurality of switch groups each including switches 902 to 907. Each of the switches 902 to 907 can be implemented by an NMOS transistor, for example.

[0051] 9A, for rows where the high-definition display area 203 is not present, the control circuit 105 turns on (conductive) switches 902 to 904 and turns off (non-conductive) switches 905 to 907. In FIG. 9A, the write control line 408 in the kth row is connected to the write control line 408 in the k+1th row without passing through the shift register 901. Therefore, it is possible to supply a write control signal to the write control line 408 in the kth row and the write control line 408 in the k+1th row at the same time.

[0052] 9B, for the row where the high-definition display area 203 exists, the control circuit 105 turns off (disconnects) the switches 902 to 904 and turns on (connects) the switches 905 to 907. In FIG. 9B, after a write control signal is supplied to the write control line 408 of the kth row, a write control signal is supplied to the write control line 408 of the (k+1)th row at a timing delayed by the shift register 901.

[0053] The control circuit 105 controls the switches 902 to 907 using, for example, a resolution control signal that is turned ON in rows where the high-definition display area 203 exists and turned OFF in rows where the high-definition display area 203 does not exist. As described above, the setting of the high-definition display area 203 may be performed by the display device 100 (the control circuit 105) or by an external device of the display device 100 (for example, an external device that generates image data to be displayed). The control circuit 105 may detect or determine the high-definition display area by analyzing the image data to be displayed, may obtain information about the high-definition display area from metadata of the image data, or may determine the high-definition display area according to information about the user's line of sight.

[0054] 10 is a timing chart showing an example of the waveform of the resolution control signal and the waveform of the scanning control signal. As shown in FIG. 10, in rows where the high-definition display area 203 does not exist, the scanning control signal is supplied sequentially for every several rows, and in rows where the high-definition display area 203 exists, the scanning control signal is supplied sequentially for every row.

[0055] 11, the low-definition display region 202 may be divided into a medium-definition display region 1101 and a low-definition display region 1102 surrounding the medium-definition display region 1101. Depending on the circuit configuration of the pixels, the display resolution of the low-definition display region 1102 is made lower than the display resolution of the medium-definition display region 1101. For example, each sub-pixel of the high-definition displayable region 201 has one light-emitting element 301, and each sub-pixel of the medium-definition display region 1101 has two light-emitting elements 301 in the horizontal direction and two light-emitting elements 301 in the vertical direction, for a total of four light-emitting elements 301. Each sub-pixel of the low-definition display region 1102 has four light-emitting elements 301 in the horizontal direction and four light-emitting elements 301 in the vertical direction, for a total of 16 light-emitting elements 301.

[0056] FIG. 12 is a circuit diagram showing an example of the configuration of a sub-pixel circuit in the low-resolution display region 1102. FIG. 12 is substantially the same as FIG. 6, except that the number of light-emitting elements 301 is different from that in FIG. 6. In FIG. 12, one signal line 109 is (indirectly) connected to 16 light-emitting elements 301. In FIG. 12, one write transistor 402 is used, as in FIG. 6. The line 109 is connected to the drain of the write transistor 402 , and the source of the write transistor 402 is connected to 16 drive transistors 401 corresponding to the 16 light emitting elements 301 respectively.

[0057] 13 is a circuit diagram showing a modified example of the configuration of the sub-pixel circuit in the low-definition display region 1102. In FIG. 13, one signal line 109 is also connected (indirectly) to 16 light-emitting elements 301. In FIG. 13, two write transistors 402 are used. The signal line 109 is connected to the drains of the two write transistors 402. The source of one of the two write transistors 402 is connected to eight drive transistors 401 corresponding to the eight light-emitting elements 301 in the kth and k+1th rows, respectively. The source of the other of the two write transistors 402 is connected to eight drive transistors 401 corresponding to the eight light-emitting elements 301 in the k+2th and k+3th rows, respectively.

[0058] FIG. 14 is a circuit diagram showing a modified example of the configuration of the sub-pixel circuit in the low-definition display region 1102. In FIG. 14 as well, one signal line 109 is (indirectly) connected to 16 light-emitting elements 301. In FIG. 14, four write transistors 402 are used. The signal line 109 is connected to the drains of the four write transistors 402, respectively. Of the four write transistors 402, the source of the first write transistor 402 is connected to four drive transistors 401 corresponding to the four light-emitting elements 301 in the kth row. The source of the second write transistor 402 is connected to four drive transistors 401 corresponding to the four light-emitting elements 301 in the k+1th row. The source of the third write transistor 402 is connected to four drive transistors 401 corresponding to the four light-emitting elements 301 in the k+2th row. The source of the fourth write transistor 402 is connected to four drive transistors 401 corresponding to the four light-emitting elements 301 in the k+3th row.

[0059] 15 is a circuit diagram showing a modified example of the configuration of the sub-pixel circuit in the low-definition display region 1102. In FIG. 15 as well, one signal line 109 is (indirectly) connected to 16 light-emitting elements 301. In FIG. 15, 16 writing transistors 402 corresponding to the 16 light-emitting elements 301 respectively are used. The signal line 109 is connected to the drain of each of the 16 writing transistors 402.

[0060] Fig. 16 is a circuit diagram showing a modified example of the configuration of the sub-pixel circuit in the low-resolution display region 1102. In Fig. 16, two signal lines 109-1 and 109-2 are used for 16 light-emitting elements. In Fig. 16, 16 writing transistors 402 corresponding to the 16 light-emitting elements 301, respectively, are used. The signal line 109-1 is connected to the drains of the eight writing transistors 402 corresponding to the eight light-emitting elements 301 in the jth and j+1th columns, respectively. The signal line 109-2 is connected to the drains of the eight writing transistors 402 corresponding to the eight light-emitting elements 301 in the j+2th and j+3th columns, respectively.

[0061] In another embodiment of the present invention, a display device having a plurality of pixels arranged in row and column directions may have a first group of signal lines and a second group of signal lines spaced apart more than the first group of signal lines, and a first group of control lines and a second group of control lines spaced apart more than the first group of control lines. The display device has a display area, including a first region electrically connected to the first group of signal lines and the first group of control lines, and a second region connected to at least one of the second group of signal lines or the second group of control lines. The first region has a third region that receives data with a high display resolution from a control unit (control circuit) of the display device, and a fourth region that receives data with a lower display resolution than the third region. The third region can be set based on external information, for example, information detected by detecting the user's line of sight, and does not remain in a fixed position. EMBODIMENTS OF THE PRESENT INVENTION A plurality of aspects can be combined without departing from the spirit of the present invention.

[0062] [Organic light-emitting element] Next, an example of an organic light-emitting element that can be used in the display device according to the first embodiment will be described.

[0063] In the display device according to embodiment 1, the organic light-emitting element includes a first electrode, a second electrode, and an organic compound layer disposed between these electrodes. One of the first electrode and the second electrode is an anode, and the other is a cathode. In embodiment 1, the organic compound layer may be a single layer or a laminate consisting of multiple layers, as long as it includes an emitting layer. When the organic compound layer is a laminate consisting of multiple layers, the organic compound layer may include a hole injection layer, a hole transport layer, an electron blocking layer, a hole / exciton blocking layer, an electron transport layer, an electron injection layer, and the like, in addition to the emitting layer. The emitting layer may also be a single layer or a laminate consisting of multiple layers. When the emitting layer includes multiple layers, a charge generation layer may be disposed between the emitting layers. The charge generation layer may be composed of a compound having a lower LUMO than the hole transport layer, and the LUMO of the charge generation layer may be lower than the HOMO of the hole transport layer. Here, the molecular orbital energy of the organic compound layer may be the molecular orbital energy of the organic compound having the largest weight ratio in the organic compound layer.

[0064] In embodiment 1, when an organic compound is contained in the light-emitting layer, the light-emitting layer may be a layer consisting of only the organic compound, or may be a layer consisting of an organometallic complex and other compounds. Here, when the light-emitting layer is a layer consisting of an organometallic complex and other compounds, the organic compound may be used as a host or a guest of the light-emitting layer. It may also be used as an assist material that can be contained in the light-emitting layer. Here, the host is the compound with the largest mass ratio among the compounds constituting the light-emitting layer. The guest is the compound with a smaller mass ratio than the host among the compounds constituting the light-emitting layer, and is responsible for the main emission of light. The assist material is the compound with a smaller mass ratio than the host among the compounds constituting the light-emitting layer, and assists the emission of the guest. The assist material is also called a second host. The host material can also be called the first compound, and the assist material can also be called the second compound.

[0065] Here, the organic compound may be used in combination with conventionally known low-molecular-weight and high-molecular-weight hole-injecting or hole-transporting compounds, host compounds, light-emitting compounds, electron-injecting or electron-transporting compounds, etc., as needed.

[0066] The hole injection / transport material is preferably a material with high hole mobility that facilitates the injection of holes from the anode and transports the injected holes to the light-emitting layer. Furthermore, a material with a high glass transition temperature is preferred to reduce deterioration of film quality, such as crystallization, in the organic light-emitting device.

[0067] The electron transporting material can be arbitrarily selected from those capable of transporting electrons injected from the cathode to the light-emitting layer, and is selected in consideration of the balance with the hole mobility of the hole transporting material, etc. The electron transporting material is also preferably used in the hole blocking layer.

[0068] The electron-injecting material can be arbitrarily selected from those that allow easy injection of electrons from the cathode, and is selected in consideration of the balance with hole-injecting properties, etc. It can also be used in combination with an electron-transporting material.

[0069] [Configuration of organic light-emitting element] An organic light-emitting element is provided by forming an insulating layer, a first electrode, an organic compound layer (sometimes called a functional layer), and a second electrode on a substrate. On the cathode, a protective layer, a color filter, a micro-layer, and a A microlens or the like may be provided. When a color filter is provided, a planarizing layer may be provided between the color filter and the protective layer. The planarizing layer may be made of an acrylic resin or the like. The same applies when a planarizing layer is provided between the color filter and the microlens.

[0070] [substrate] Examples of the substrate include quartz, glass, silicon wafer, resin, and metal. The substrate may also be provided with switching elements such as transistors and wiring, and an insulating layer (sometimes called an insulating film) thereon. When a silicon wafer is used as the substrate, the active layer, source region, and drain region of the transistor are formed within the substrate. This is also preferred because it allows for densely arranged transistors.

[0071] Any material can be used for the insulating layer as long as it allows for the formation of contact holes so that wiring can be formed between the first electrode and the insulating layer, and ensures insulation from wiring that is not connected. For example, resins such as polyimide, silicon oxide, silicon nitride, etc. can be used.

[0072] [electrode] A pair of electrodes can be used. The pair of electrodes may be an anode (sometimes referred to as an anode electrode) and a cathode (sometimes referred to as a cathode electrode). When an electric field is applied in the direction in which the organic light-emitting element emits light, the electrode with a higher potential is the anode, and the other is the cathode. It can also be said that the electrode that supplies holes to the light-emitting layer is the anode, and the electrode that supplies electrons is the cathode.

[0073] The material for the anode should have as high a work function as possible. Examples of suitable materials include simple metals such as gold, platinum, silver, copper, nickel, palladium, cobalt, selenium, vanadium, and tungsten. Mixtures containing these metals, alloys of these metals, and metal oxides such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide can also be used. Conductive polymers such as polyaniline, polypyrrole, and polythiophene can also be used.

[0074] These electrode materials may be used alone or in combination of two or more. The anode may be composed of one layer or multiple layers.

[0075] When used as a reflective electrode, for example, chromium, aluminum, silver, titanium, tungsten, molybdenum, or alloys or laminates thereof can be used. The above materials can also function as a reflective film without functioning as an electrode. When used as a transparent electrode, transparent conductive oxide layers such as indium tin oxide (ITO) and indium zinc oxide can be used, but are not limited to these. Photolithography techniques can be used to form the electrode.

[0076] On the other hand, materials with a low work function are preferable for the cathode. Examples include alkali metals such as lithium, alkaline earth metals such as calcium, and metals such as aluminum, titanium, manganese, silver, lead, and chromium, as well as mixtures containing these metals. Alloys combining these metals can also be used. Examples include magnesium-silver, aluminum-lithium, aluminum-magnesium, silver-copper, and zinc-silver. Metal oxides such as indium tin oxide (ITO) can also be used.

[0077] These electrode materials may be used alone or in combination of two or more. The cathode may have a single layer or a multi-layer structure. Among them, silver is preferably used, and a silver alloy is more preferable in order to reduce the aggregation of silver. The alloy ratio is not important as long as it can reduce the aggregation of silver. For example, the ratio of silver to other metal may be 1:1, 3:1, etc. stomach.

[0078] The cathode may be a top-emission element using an oxide conductive layer such as ITO, or a bottom-emission element using a reflective electrode such as aluminum (Al), and is not particularly limited. The method for forming the cathode is not particularly limited, but DC and AC sputtering methods are more preferred because they provide good film coverage and make it easier to reduce resistance.

[0079] [Pixel isolation layer] The pixel separation layer is formed of a silicon nitride (SiN) film, a silicon oxynitride (SiON) film, or a silicon oxide (SiO) film formed using a chemical vapor deposition (CVD) method. To increase the in-plane resistance of the organic compound layer, it is preferable that the organic compound layer, particularly the hole transport layer, be thinly formed on the sidewalls of the pixel separation layer. Specifically, the thickness of the sidewalls can be made thin by increasing the taper angle of the sidewalls of the pixel separation layer or the thickness of the pixel separation layer, thereby increasing vignetting during deposition.

[0080] On the other hand, it is preferable to adjust the sidewall taper angle and film thickness of the pixel separation layer to such an extent that voids are not formed in the protective layer formed on top of it. Since voids are not formed in the protective layer, the occurrence of defects in the protective layer can be reduced. Since the occurrence of defects in the protective layer is reduced, it is possible to reduce deterioration in reliability, such as the occurrence of dark spots and poor conduction of the second electrode.

[0081] By adjusting the taper angle of the sidewall of the pixel separation layer, it is possible to effectively suppress charge leakage to adjacent pixels. For example, a taper angle between 60 degrees and 90 degrees can sufficiently reduce charge leakage. The thickness of the pixel separation layer is preferably between 10 nm and 150 nm. Similar effects can also be achieved by using only pixel electrodes without a pixel separation layer. However, in this case, it is preferable to make the thickness of the pixel electrode less than half that of the organic layer or to make the edge of the pixel electrode forward tapered by less than 60 degrees, as this reduces short circuits in the organic light-emitting element.

[0082] [Organic compound layer (functional layer)] The organic compound layer may be formed as a single layer or as multiple layers. When multiple layers are included, they may be called hole injection layer, hole transport layer, electron blocking layer, light-emitting layer, hole blocking layer, electron transport layer, or electron injection layer depending on their functions. The organic compound layer is mainly composed of organic compounds but may also contain inorganic atoms or inorganic compounds. For example, the organic compound layer may contain copper, lithium, magnesium, aluminum, iridium, platinum, molybdenum, zinc, or the like. The organic compound layer may be disposed between the first electrode and the second electrode, or may be disposed in contact with the first electrode and the second electrode.

[0083] When the device has multiple light-emitting layers, a charge generation section may be provided between the first and second light-emitting layers. The charge generation section may have an organic compound with a lowest unoccupied molecular orbital energy (LUMO) of -5.0 eV or less. The same applies when the charge generation section is provided between the second and third light-emitting layers.

[0084] [Protective layer] A protective layer such as an insulating film may be provided on the second electrode. For example, by adhering glass provided with a moisture absorbent on the second electrode, it is possible to reduce the intrusion of water and the like into the organic compound layer and reduce the occurrence of display defects. In another embodiment, a passivation film such as silicon nitride may be provided on the cathode to reduce the intrusion of water and the like into the organic compound layer. For example, after forming the cathode, the cathode may be transferred to another chamber without breaking the vacuum, and a silicon nitride film with a thickness of 2 μm may be formed by the CVD method to serve as a protective layer. After forming the film by the CVD method, an atomic deposition method (AL A protective layer may be formed using a method (D) for forming the film by the ALD method. The material of the film formed by the ALD method is not limited, and may be silicon nitride, silicon oxide, aluminum oxide, etc. Silicon nitride may be further formed on the film formed by the ALD method by a CVD method. The film formed by the ALD method may have a smaller thickness than the film formed by the CVD method. Specifically, it may be 50% or less, or even 10% or less.

[0085] [Color Filter] A color filter may be provided on the protective layer. For example, a color filter taking into consideration the size of the organic light-emitting element may be provided on a separate substrate and then bonded to the substrate on which the organic light-emitting element is provided, or a color filter may be patterned on the protective layer described above using photolithography technology. The color filter may be made of a polymer.

[0086] [Planarization layer] A planarization layer may be provided between the color filter and the protective layer. The planarization layer is provided for the purpose of reducing the unevenness of the underlying layer. It may also be called a material resin layer without limiting its purpose. The planarization layer may be composed of an organic compound, and may be either a low molecular weight or a high molecular weight, but a high molecular weight is preferred.

[0087] The planarizing layer may be provided above or below the color filter, and may be made of the same or different materials, such as polyvinyl carbazole resin, polycarbonate resin, polyester resin, ABS resin, acrylic resin, polyimide resin, phenol resin, epoxy resin, silicone resin, and urea resin.

[0088] [Microlens] The display device may have an optical component such as a microlens on its light-emitting side. The microlens may be made of acrylic resin, epoxy resin, or the like. The purpose of the microlens may be to increase the amount of light extracted from the display device and to control the direction of the extracted light. The microlens may have a hemispherical shape. When the microlens has a hemispherical shape, among the tangents to the hemisphere, there is a tangent that is parallel to the insulating layer, and the point of contact between this tangent and the hemisphere is the vertex of the microlens. The vertex of the microlens can be determined in the same way in any cross-sectional view. In other words, among the tangents to the semicircle of the microlens in the cross-sectional view, there is a tangent that is parallel to the insulating layer, and the point of contact between this tangent and the semicircle is the vertex of the microlens.

[0089] It is also possible to define the midpoint of a microlens. In the cross section of the microlens, a line segment is imagined from the point where an arc shape ends to the point where another arc shape ends, and the midpoint of this line segment can be called the midpoint of the microlens. The cross section for determining the vertex and midpoint may be a cross section perpendicular to the insulating layer.

[0090] The microlens has a first surface having a convex portion and a second surface opposite the first surface. The second surface is preferably disposed closer to the functional layer than the first surface. To achieve this configuration, it is necessary to form the microlens on the display device. When the functional layer is an organic layer, it is preferable to avoid processes that result in high temperatures during the manufacturing process. Furthermore, when the second surface is disposed closer to the functional layer than the first surface, it is preferable that the glass transition temperatures of all organic compounds that make up the organic layer are 100°C or higher, and more preferably 130°C or higher.

[0091] [Counter substrate] An opposing substrate may be provided on the planarization layer. The opposing substrate is called the opposing substrate because it is provided at a position corresponding to the aforementioned substrate. The constituent material of the opposing substrate may be the same as that of the aforementioned substrate. When the aforementioned substrate is defined as the first substrate, the opposing substrate may be the second substrate.

[0092] [Organic layer] The organic compound layers (hole injection layer, hole transport layer, electron blocking layer, light emitting layer, hole blocking layer, electron transport layer, electron injection layer, etc.) constituting the organic light emitting device are formed by the following method.

[0093] The organic compound layer constituting the organic light-emitting device can be formed by dry processes such as vacuum deposition, ionization deposition, sputtering, plasma, etc. Alternatively to the dry process, a wet process can be used in which the compound is dissolved in an appropriate solvent and a layer is formed by a known coating method (e.g., spin coating, dipping, casting, LB method, inkjet method, etc.).

[0094] Here, when a layer is formed by a vacuum deposition method, a solution coating method, etc., crystallization is unlikely to occur and the layer has excellent stability over time. When a film is formed by a coating method, the film can also be formed by combining with an appropriate binder resin.

[0095] Examples of the binder resin include, but are not limited to, polyvinylcarbazole resin, polycarbonate resin, polyester resin, ABS resin, acrylic resin, polyimide resin, phenol resin, epoxy resin, silicone resin, and urea resin.

[0096] These binder resins may be used singly or in combination as homopolymers or copolymers, and may further contain known additives such as plasticizers, antioxidants, and ultraviolet absorbers, if necessary.

[0097] [Pixel circuit] The display device has a pixel circuit connected to a light-emitting element. The pixel circuit may be an active matrix type that controls the light emission of a first light-emitting element and a second light-emitting element independently. The active matrix type circuit may be voltage-programmed or current-programmed. The display device has a pixel circuit for each pixel. The pixel circuit may include a light-emitting element, a transistor that controls the light emission brightness of the light-emitting element, a transistor that controls the light emission timing, a capacitor that holds the gate voltage of the transistor that controls the light emission brightness, and a transistor for connecting to GND without going through the light-emitting element.

[0098] The display device has a display area and a peripheral area arranged around the display area. The display area has pixel circuits, and the peripheral area has a display control circuit. The mobility of transistors constituting the pixel circuits may be smaller than the mobility of transistors constituting the display control circuit.

[0099] The slope of the current-voltage characteristics of the transistors that make up the pixel circuit may be smaller than the slope of the current-voltage characteristics of the transistors that make up the display control circuit. The slope of the current-voltage characteristics can be measured using the so-called Vg-Ig characteristics.

[0100] The transistors that make up the pixel circuit are transistors connected to light-emitting elements such as the first light-emitting element.

[0101] [Pixels] The display device has a plurality of pixels, each of which has sub-pixels that emit different colors, and each of which may emit, for example, RGB colors.

[0102] In a pixel, an area called a pixel aperture emits light. This area is the same as the first area. The pixel aperture may be 15 μm or less, or 5 μm or more. More specifically, it may be 11 μm, 9.5 μm, 7.4 μm, 6.4 μm, etc. The distance between sub-pixels (adjacent sub-pixels) The distance (from center to center) may be 10 μm or less, and specifically may be 8 μm, 7.4 μm, 6.4 μm or less.

[0103] The pixels may be arranged in a known manner in a plan view. For example, they may be in a stripe arrangement, a delta arrangement (honeycomb arrangement), a pentile arrangement, or a Bayer arrangement. The shape of the subpixels in a plan view may be any known shape. For example, they may be rectangular, quadrilaterals such as diamonds, or hexagons. Of course, a shape that is close to a rectangle, rather than an exact shape, is included in the rectangle. The shape of the subpixels and the pixel arrangement may be combined.

[0104] [Use of the display device according to embodiment 1] The display device according to the first embodiment can be used as a component of various devices and apparatuses, etc. For example, it can be used as a display device having a white light source and a color filter.

[0105] The device having the display device according to the first embodiment may be an image information processing device having an image input unit that inputs image information from an area CCD, a linear CCD, a memory card, etc., an information processing unit that processes the input information, and displays the input image on a display unit. The display unit may have the display device according to the first embodiment.

[0106] The display unit of an imaging device or an inkjet printer may include the display device of embodiment 1. The display unit may have a touch panel function. The driving method for this touch panel function may be an infrared method, a capacitance method, a resistive film method, or an electromagnetic induction method, and is not particularly limited. The display device may also be used in the display unit of a multifunction printer.

[0107] Next, a cross section of an example of a part of the display device of the first embodiment will be described with reference to Fig. 17. For convenience of explanation, different reference numerals may be used for elements and the like already mentioned above.

[0108] The display device includes a substrate 11, an insulating layer 14, and a light-emitting element 1700. The insulating layer 14 is located on the substrate 11. The light-emitting element 1700 is located on the insulating layer 14. In other words, the insulating layer 14 is located between the substrate 11 and the light-emitting element 1700.

[0109] The substrate 11 has a main surface (the upper surface in FIG. 17) on which a drive transistor 1701, a write transistor 1703, and a light-emitting control transistor 1702 are formed. The substrate 11 may be formed of, for example, a P-type semiconductor. An N-type well region 13 is formed on the main surface side of the substrate 11 (i.e., the upper side of the substrate 11). The substrate 11 other than the well region 13 becomes a P-type semiconductor region 12.

[0110] The substrate 11 has a plurality of impurity regions that function as source regions or drain regions of the transistors in the well region 13. The conductivity type of the impurity regions can be, for example, P type.

[0111] A conductive layer 1765, a conductive layer 1763G, and a conductive layer 1764G are arranged on the main surface (top surface) of the substrate 11. The conductive layer 1763G functions as the gate of the light-emitting control transistor 1763. One of the P-type impurity regions functions as the source 1763S of the light-emitting control transistor 1763, and another of the P-type impurity regions functions as the drain 1763D. The conductive layer 1765 functions as the gate of the driving transistor 1761. The impurity region that functions as the drain 1763D of the light-emitting control transistor 1763 also functions as the source 1768 of the driving transistor 1701. Another one of the P-type impurity regions functions as the drain 1767 of the driving transistor 1701.

[0112] Furthermore, the conductive layer 1764G functions as the gate of the reset transistor 1764. The impurity region that functions as the source 1768 of the drive transistor 1701 also functions as the drain 1764D of the reset transistor 1764. Another one of the P-type impurity regions functions as the source 1764S of the reset transistor 1764.

[0113] The substrate 11 further has an element isolation portion 1730 formed between adjacent pixels. As the element isolation portion 1730, STI (Shallow Trench Isolation), LOCOS (LOCal Oxidation of Silicon) isolation, N-type diffusion layer isolation, or the like may be used.

[0114] The light-emitting element has a cathode 1716, an organic light-emitting layer 1715, and an anode 1714. The cathode 1716 is electrically connected to the power line 1708. The anode 1714 is electrically connected to the main terminal (here, the drain) of the driving transistor 1701. The organic light-emitting layer 1715 is located between the cathode 1716 and the anode 1714. A bank portion 1717 is arranged at the end of the anode 1714. The bank portion 1717 prevents the current flowing between the anode 1714 and the cathode 1716 from leaking to adjacent pixels.

[0115] Conductive patterns, electrodes of capacitor elements, and plugs are embedded in the insulating layer 14. The insulating layer 14 may be, for example, silicon oxide. Each of the conductive patterns may be a wiring layer. For example, as shown in FIG. 17, the conductive pattern may have wiring WR1, wiring WR2, and wiring WR3.

[0116] The capacitor 1705 has electrodes 1705a and 1705b, and the capacitor 1706 has electrodes 1706a and 1706b. In the insulating layer 14, the electrodes 1705a and 1706a may be disposed on the same insulating layer. The electrodes 1705b and 1706b may be disposed on the same insulating layer. The electrodes 1705a and 1705b face each other with the insulating layer sandwiched between them. The electrodes 1706a and 1706b face each other with the insulating layer sandwiched between them. This forms a capacitor with an MIM (Metal-Insulator-Metal) structure.

[0117] The multiple plugs may include, for example, plug PL1, plug PL2, plug PL3, plug PL4, and plug PL5. The multiple plugs may all have the same thickness or may have different thicknesses, or some may have the same thickness and some may have different thicknesses.

[0118] The plug PL1 may connect the wiring WR1 to a terminal (gate, source, or drain) of the transistor. The plug PL2 may connect the wiring WR2 to the wiring WR2. The lower electrode of the capacitor (1705 or 1706) may be connected to the driving transistor 1701 via the plug PL3, the wiring WR2, the plug PL2, the wiring WR1, and the plug PL1. The upper electrode of the capacitor (1705 or 1706) may be connected to the wiring WR3 via the plug PL5.

[0119] The wiring WR3 may be connected to a transistor (in FIG. 17, any one of the drive transistor, current control transistor, and reset transistor) via a plug PL4, a wiring R2, a plug PL2, a wiring WR1, and a plug PL1. The anode 1714 may be connected to the drain 1767 of the drive transistor 1701 via a plug PL6, a wiring WR3, a plug PL4, a wiring WR2, a plug PL2, a wiring WR1, and a plug PL1.

[0120] The plug may be formed in a separate process from the wiring, or may be formed in the same process as the wiring disposed on the plug. For example, the wiring WR2 and the plug PL2 may be formed in the same process. The wiring WR3 and the plug PL4 may be formed in the same process and may be made of the same material. The wiring and the plug may be made of a metal such as copper, tungsten, aluminum, or titanium, or an alloy thereof.

[0121] In this way, by using a semiconductor substrate as the substrate and using MOS transistors as the transistors in each pixel, the transistors can be arranged more densely than when thin film transistors are used. Therefore, by configuring the display device of embodiment 1 to have a semiconductor substrate and MOS transistors as the transistors, the display device can have higher resolution or be made smaller.

[0122] Fig. 18 is a cross-sectional view showing an example of a display device having an organic light-emitting element and a transistor connected to the organic light-emitting element. A transistor is an example of an active element. Here, an example is shown in which the transistor is a thin-film transistor (TFT), but a MOSFET using a semiconductor substrate can also be used. By using a MOSFET, the transistors in each pixel can be arranged in a smaller area.

[0123] 18 shows an example of a pixel that is a component of the display device according to embodiment 1. The pixel has sub-pixels 10. The sub-pixels are divided into 10R, 10G, and 10B based on the light emitted from the sub-pixels. The emitted colors may be distinguished by the wavelength of light emitted from the light-emitting layer, or the light emitted from the sub-pixels may be selectively transmitted or color-converted using a color filter or the like. Each sub-pixel has a reflective electrode 2 serving as a first electrode on an interlayer insulating layer 1, an insulating layer 3 covering the edge of the reflective electrode 2, an organic compound layer 4 covering the second electrode and the insulating layer, a second electrode 5, a protective layer 6, and a color filter 7.

[0124] A transistor and a capacitor may be disposed below or inside the interlayer insulating layer 1. The transistor and the first electrode may be electrically connected via a contact hole or the like (not shown).

[0125] The insulating layer 3 is also called a bank or a pixel separation film. It covers the edges of the first electrode and surrounds the first electrode. The part where the insulating layer is not provided contacts the organic compound layer 4 and becomes the light-emitting region.

[0126] The organic compound layer 4 includes a hole injection layer 41 , a hole transport layer 42 , a first light-emitting layer 43 , a second light-emitting layer 44 , and an electron transport layer 45 .

[0127] The second electrode 5 may be a transparent electrode, a reflective electrode, or a semi-transparent electrode.

[0128] The protective layer 6 reduces the penetration of moisture into the organic compound layer. Although the protective layer is illustrated as a single layer, it may be a multi-layer. Each layer may be an inorganic compound layer and an organic compound layer.

[0129] The color filters 7 are divided into 7R, 7G, and 7B depending on their colors. The color filters may be formed on a planarization film (not shown). A resin protective layer (not shown) may be provided on the color filters. The color filters may be formed on a protective layer 6. Alternatively, the color filters may be provided on an opposing substrate such as a glass substrate and then bonded thereto.

[0130] (Embodiment 2) 19 is a schematic diagram showing an example of a display component according to embodiment 2. A display device 1900 includes an upper cover 1901 and a lower cover 1909, a touch panel 1903, a display It may have a panel 1905, a frame 1906, a circuit board 1907, and a battery 1908. Flexible printed circuits FPCs 1902 and 1904 are connected to the touch panel 1903 and the display panel 1905.

[0131] The display panel 1905 has the display device of embodiment 1. A transistor is printed on a circuit board 1907. The battery 1908 may not be provided if the display component is not used in a portable device, or may be provided in a different location if the display component is used in a portable device.

[0132] The display component according to the second embodiment may have color filters having red, green, and blue colors, which may be arranged in a delta arrangement.

[0133] The display component according to the second embodiment may be used in a display unit of a mobile terminal. In this case, the display unit may have both a display function and an operation function. Examples of the mobile terminal include a mobile phone such as a smartphone, a tablet, and a head-mounted display.

[0134] The display component according to the second embodiment may be used in a display unit of an imaging device having an optical unit with a plurality of lenses and an imaging element that receives light that has passed through the optical unit. The imaging device may have a display unit that displays information acquired by the imaging element. The display unit may be a display unit exposed to the outside of the imaging device or a display unit disposed within a viewfinder. The imaging device may be a digital camera or a digital video camera.

[0135] (Embodiment 3) 20A is a schematic diagram illustrating an example of an imaging device according to embodiment 3. The imaging device 2000 may include a viewfinder 2001, a rear display 2002, an operation unit 2003, and a housing 2004. The viewfinder 2001 may include the display device according to embodiment 1. In this case, the display device may display not only an image to be captured, but also environmental information, imaging instructions, and the like. The environmental information may include the intensity of external light, the direction of external light, the speed at which the subject is moving, the possibility that the subject will be blocked by an obstruction, and the like.

[0136] Since the optimum timing for capturing an image is very short, it is better to display information as quickly as possible. Therefore, it is preferable to use a display device using organic light-emitting elements, because organic light-emitting elements have a fast response speed. When display speed is required, a display device using organic light-emitting elements can be used more preferably than a liquid crystal display device.

[0137] The imaging device 2000 has an optical section (not shown). The optical section has multiple lenses, which form an image on an imaging element housed in a housing 2004. The focus of the multiple lenses can be adjusted by adjusting their relative positions. This operation can also be performed automatically. The imaging device may also be called a photoelectric conversion device. Instead of sequentially capturing images, the photoelectric conversion device may include an imaging method that detects the difference from the previous image, or a method of cutting out an image from a constantly recorded image, etc.

[0138] (Embodiment 4) 20B is a schematic diagram illustrating an example of an electronic device according to embodiment 4. The electronic device 2010 has a display unit 2011, an operation unit 2012, and a housing 2013. The housing 2013 may include a circuit, a printed circuit board having the circuit, a battery, and a communication unit.

[0139] The display unit 2011 may have the display device according to the first embodiment. The operation unit 2012 may be a button or a touch panel type reaction unit. The operation unit may be a biometric recognition unit that recognizes a fingerprint to unlock the device. An electronic device having a communication unit may also be called a communication device. An electronic device may be equipped with a lens and an imaging element to function as a camera. The electronic device may further have a function of displaying an image captured by the camera function on the display unit. Examples of the electronic device include a smartphone and a laptop computer.

[0140] (Embodiment 5) 21A is a schematic diagram illustrating an example of an image display device (monitor) according to embodiment 5. The image display device 2100 in FIG. 21A is a television monitor, a PC monitor, or the like. The image display device 2100 has a frame 2101 and a display unit 2102 surrounded by the frame 2101. The display unit 2102 may have the display device according to embodiment 1.

[0141] The image display device 2100 further includes a frame 2101 and a base 2103 that supports the display unit 2102. The base 2103 is not limited to the form shown in Fig. 21A. For example, the bottom side of the frame 2101 may also serve as the base.

[0142] The frame 2101 and the display unit 2102 may be curved. The radius of curvature may be 5000 mm or more and 6000 mm or less.

[0143] FIG. 21B is a schematic diagram illustrating another example of an image display device according to embodiment 6. The image display device 2110 in FIG. 21B is configured to be foldable, and is a so-called foldable image display device. The image display device 2110 has a first display unit 2111, a second display unit 2112, a housing 2113, and a bending point 2114. The first display unit 2111 and the second display unit 2112 may include the display device according to embodiment 1. The first display unit 2111 and the second display unit 2112 may be a single, seamless image display device. The first display unit 2111 and the second display unit 2112 can be separated by the bending point. The first display unit 2111 and the second display unit 2112 may display different images, or the first and second display units may display a single image.

[0144] (Embodiment 6) 22A and 22B, an application example of the display device of the first embodiment will be described. The display device can be applied to a system that can be attached as a wearable device, such as smart glasses, an HMD, or a smart contact lens. The image capture device and the display device used in such an application example can be an image capture device capable of photoelectrically converting visible light, and a display device capable of emitting visible light.

[0145] 22A illustrates glasses 2200 (smart glasses) according to one application example. An imaging device 2202, such as a CMOS sensor or a SPAD, is provided on the front side of a lens 2201 of the glasses 2200. In addition, a display device 2204 according to the first embodiment is provided on the back side of the lens 2201.

[0146] The glasses 2200 further include a control device 2203. The control device 2203 functions as a power source that supplies power to the image capture device 2202 and the display device 2204. The control device 2203 also controls the operations of the image capture device 2202 and the display device 2204. The lens 2201 has an optical system formed therein for focusing light onto the image capture device 2202.

[0147] 22B illustrates glasses 2210 (smart glasses) according to one application example. The glasses 2210 have a control device 2212. The control device 2212 is equipped with an imaging device corresponding to the imaging device 2202 and a display device 2214 corresponding to the display device 2204. An optical system for projecting light emitted by the display device 2214 in the control device 2212 is formed in the lens 2211, and an image is projected onto the lens 2211. The control device 2212 functions as a power source that supplies power to the imaging device and the display device 2214, and also controls the operations of the imaging device and the display device 2214.

[0148] The control device 2212 may have a gaze detection unit that detects the gaze of the wearer. Infrared rays may be used to detect the gaze. The infrared light emitting unit emits infrared light toward the eyeball of the user who is gazing at the displayed image. An imaging unit with a light receiving element detects the reflected light of the emitted infrared light from the eyeball, thereby obtaining an image of the eyeball. By having a reduction means for reducing light from the infrared light emitting unit to the display unit in a planar view, degradation of image quality is reduced.

[0149] The gaze of the user relative to the displayed image is detected from an image of the eyeball obtained by capturing infrared light. Any known method can be used for gaze detection using an image of the eyeball. One example is a gaze detection method based on the Purkinje image formed by reflection of irradiated light on the cornea.

[0150] More specifically, gaze detection processing is performed based on the pupil-corneal reflex method, which calculates a gaze vector representing the direction (rotation angle) of the eyeball based on the pupil image and Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0151] The glasses 2210 may have an imaging device with a light receiving element, and may control the image displayed on the display device based on information about the user's line of sight from the imaging device.

[0152] Specifically, the display device 2214 determines a first display area on which the user gazes and a second display area other than the first display area based on the line-of-sight information. The first display area and the second display area may be determined by a control device of the glasses 2210, or may be determined by an external control device and received. In the display area of ​​the display device 2214, the display resolution of the first display area may be controlled to be higher than the display resolution of the second display area. In other words, the resolution of the second display area may be lower than that of the first field of view area.

[0153] The display area includes a first display area and a second display area different from the first display area, and a high-priority area is determined from the first display area and the second display area based on line-of-sight information. The first and second view areas may be determined by a control device of the display device, or may be determined by an external control device and received. The resolution of the high-priority area may be controlled to be higher than the resolution of areas other than the high-priority area. In other words, the resolution of an area with a relatively low priority may be lowered.

[0154] Note that AI may be used to determine the first display area and the area with high priority. The AI ​​may be a model configured to estimate the angle of gaze and the distance to an object in the line of sight from the image of the eyeball, using as training data an image of the eyeball and the direction in which the eyeball in the image was actually looking. The AI ​​program may be included in the display device, the imaging device, or an external device. If included in the external device, it is transmitted to the display device via communication.

[0155] When display control is performed based on visual recognition detection, the smart glasses can be preferably applied to smart glasses that further include an imaging device for capturing images of the outside world. The smart glasses can display captured external information in real time.

[0156] (Embodiment 7) FIG. 23A is a diagram showing the configuration of an HMD (head mounted display) 2301 as an image observation device according to the seventh embodiment. The HMD 2301 is worn on the head of the observer. Reference numeral 2302 denotes the right eye of the observer, and reference numeral 2303 denotes the left eye of the observer. Display lenses 2304 and 2305 constitute an eyepiece optical system OR1 for the right eye, and display lenses 2306 and 2307 constitute an eyepiece optical system OL1 for the left eye. Each eyepiece optical system is a coaxial optical system made up of multiple (two) display lenses. The exit pupil ER1 of the eyepiece optical system OR1 for the right eye is illuminated by the right eye 2. 302 is disposed, and the viewer's left eye 2303 is disposed at the exit pupil EL1 of the left eye eyepiece optical system OL1. The exit pupil ER1 is provided at a position away from the right eye eyepiece optical system OR1 by a distance E1. Similarly, the exit pupil EL1 is provided at a position away from the left eye eyepiece optical system OL1 by a distance E1. Optical films 2314 for lens protection, light collection, etc. are provided on the surfaces of the right eye eyepiece optical system OR1 (the surface facing the right eye 2302) and the left eye eyepiece optical system OL1 (the surface facing the left eye 2303).

[0157] Reference numerals 2308 and 2309 denote display devices for the right and left eyes, respectively. These display devices may be the display devices according to embodiment 1. FIG. 23B is a diagram showing the appearance of an HMD 2301 and a personal computer 2350 connected thereto. Each display device displays a display image (original image) corresponding to an image signal output from the personal computer 2350. In this embodiment, the display devices are connected by wire, but they may also be connected wirelessly. Furthermore, the HMD 2301 may be a device that incorporates an image processing device and operates as a stand-alone device.

[0158] The eyepiece optical systems OR1 and OL1 guide light from the display devices 2308 and 2309 to the exit pupils ER1 and EL1, respectively, to project enlarged virtual images of the displayed image onto the observer's right eye 2302 and left eye 2303. This allows the observer to observe the display images (virtual images of the images) displayed on the display devices 2308 and 2309 through the eyepiece optical systems OR1 and OL1.

[0159] Although not shown, the HMD 2301 may have a control device. The control device functions as a power source that supplies power to the display devices 2308 and 2309, and also controls the operations of the display devices 2308 and 2309.

[0160] The control device may have a gaze detection unit that detects the gaze of the wearer. The gaze detection may use infrared rays. The infrared light emitting unit emits infrared light toward the eyeball of the user who is gazing at the displayed image. An imaging unit having a light receiving element detects the reflected light of the emitted infrared light from the eyeball, thereby obtaining an image of the eyeball. By having a reduction means that reduces light from the infrared light emitting unit to the display unit in a planar view, degradation of image quality is reduced.

[0161] The gaze of the user relative to the displayed image is detected from an image of the eyeball obtained by capturing infrared light. Any known method can be used for gaze detection using an image of the eyeball. One example is a gaze detection method based on the Purkinje image formed by reflection of irradiated light on the cornea.

[0162] More specifically, gaze detection processing is performed based on the pupil-corneal reflex method, which calculates a gaze vector representing the direction (rotation angle) of the eyeball based on the pupil image and Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0163] Specifically, the display devices 2308 and 2309 determine a first display area to which the user is gazing and a second display area other than the first display area based on the line-of-sight information. The first and second display areas may be determined by the control device, or may be determined by an external control device and received. In the display areas of the display devices 2308 and 2309, the display resolution of the first display area may be controlled to be higher than the display resolution of the second display area. In other words, the resolution of the second display area may be lower than that of the first field of view area.

[0164] The display area has a first display area and a second display area different from the first display area, and an area with a high priority is determined from the first display area and the second display area based on line-of-sight information. The first field of view area and the second field of view area may be determined by a control device of the display device, or may be determined by an external control device and received. The resolution of the area with a high priority is set to the area with a high priority. In other words, the resolution of an area with a relatively low priority may be controlled to be lower than that of an area other than the area with a high priority.

[0165] Note that AI may be used to determine the first display area and the area with high priority. The AI ​​may be a model configured to estimate the angle of gaze and the distance to an object in the line of sight from the image of the eyeball, using as training data an image of the eyeball and the direction in which the eyeball in the image was actually looking. The AI ​​program may be included in the display device, the imaging device, or an external device. If included in the external device, it is transmitted to the display device via communication.

[0166] In this way, the display device according to the first embodiment can be applied to various display components, imaging devices, electronic devices, and image display devices according to this embodiment.

[0167] The embodiments described above can be modified as appropriate without departing from the spirit and scope of the present invention. The disclosure of this specification includes not only what is described in this specification, but also all matters that can be understood from this specification and the drawings attached hereto.

[0168] The disclosure of this embodiment includes the following configuration. (Configuration 1) A substrate; a plurality of pixels arranged in a display region on the substrate; a control circuit for controlling signals supplied to the pixels; and the display area includes a first area and a second area surrounding the first area, A part of the first area is set as a third area whose position can be changed, By controlling the signals supplied to the pixels, a display resolution of a fourth region in the first region that is not the third region becomes lower than a display resolution of the third region; The display resolution of the second region is equal to or lower than the display resolution of the fourth region due to the circuit configuration of the pixel. A display device characterized by: (Configuration 2) The number of light-emitting elements connected to the pixel circuits in the second region is greater than the number of light-emitting elements connected to the pixel circuits in the fourth region, so that the display resolution in the second region is equal to or lower than the display resolution in the fourth region. 2. The display device according to configuration 1, (Configuration 3) A plurality of light-emitting elements are uniformly arranged in the display area, Each of the plurality of pixels has one or more light-emitting elements. 3. The display device according to configuration 1 or 2. (Configuration 4) The plurality of light-emitting elements are arranged in a matrix including a row direction and a column direction, Each of the plurality of light-emitting elements is connected to a vertical scanning signal line arranged in the row direction and a horizontal scanning signal line arranged in the column direction, In the second region, adjacent light-emitting elements in the row direction are connected to the same horizontal scanning signal line. 4. The display device according to configuration 3. (Configuration 5) Each of the plurality of pixels has a plurality of sub-pixels that emit light of different colors, The two or more light-emitting elements connected to the same horizontal scanning signal line are all light-emitting elements that emit a first color. 5. The display device according to configuration 4. (Configuration 6) a vertical scanning signal line and a horizontal scanning signal line are connected to each of the plurality of light-emitting elements; the vertical scanning signal lines include write control lines and light emission control lines; each of the plurality of pixels includes one or more light-emitting elements, a driving transistor, a writing transistor, and a light-emitting control transistor; the write control line is connected to the gate of the write transistor; the light-emission control line is connected to the gate of the light-emission control transistor, the horizontal scanning signal line is connected to one of the source and the drain of the write transistor; the other of the source and the drain of the write transistor is connected to the gate of the drive transistor; one of the source and the drain of the driving transistor is connected to the light emitting element; the other of the source and the drain of the drive transistor is connected to one of the source and the drain of the light-emitting control transistor; The other of the source and the drain of the light-emitting control transistor is connected to a power supply. 6. The display device according to any one of configurations 3 to 5, wherein: (Configuration 7) In the second region, One write transistor is provided for two or more adjacent light emitting elements, two or more driving transistors are provided corresponding to the two or more light-emitting elements, respectively; The other of the source and drain of the write transistor is connected to the gates of the two or more drive transistors. 7. The display device according to configuration 6. (Configuration 8) In the second region, two or more write transistors are provided corresponding to two or more adjacent light emitting elements, respectively; The same horizontal scanning signal line is connected to either the source or the drain of the two or more write transistors. 7. The display device according to configuration 6. (Configuration 9) a vertical scanning signal line and a horizontal scanning signal line are connected to each of the plurality of light-emitting elements; In the fourth region, the same horizontal scanning signal is supplied to two or more adjacent light emitting elements. 9. The display device according to any one of configurations 3 to 8, wherein: (Configuration 10) The plurality of light-emitting elements are arranged in a matrix including row and column directions, Each of the plurality of light-emitting elements is connected to a vertical scanning signal line arranged in the row direction and a horizontal scanning signal line arranged in the column direction, In an area in which the third area does not exist in the row direction, a vertical scanning signal is sequentially supplied to light emitting elements for each of a plurality of rows; In the region where the third region exists in the row direction, a vertical scanning signal is sequentially supplied to the light emitting elements for each row. 10. The display device according to any one of configurations 3 to 9, wherein: (Configuration 11) the display area further includes a fifth area surrounding the second area, The circuit configuration of the pixel makes it possible to set the display resolution of the fifth region to the display resolution of the third region. lower than 11. The display device according to any one of configurations 1 to 10. (Configuration 12) Further comprising a line of sight detection unit, The control circuit sets the third area based on the detection result of the line of sight detection unit. 12. The display device according to any one of configurations 1 to 11, wherein: (Configuration 13) further comprising an imaging unit; The control circuit sets an area in which a predetermined object is displayed in the image captured by the imaging unit as the third area. 12. The display device according to any one of configurations 1 to 11, wherein: (Configuration 14) The control circuit detects the predetermined object from the image captured by the imaging unit using a classifier that uses a trained model. 14. The display device according to configuration 13. (Configuration 15) A region designation unit is provided, The control circuit sets the third region based on information from the region designation unit. 12. The display device according to any one of configurations 1 to 11, wherein: (Configuration 16) an optical unit; an imaging element that receives light that has passed through the optical unit; a display device that displays an image captured by the imaging element; and The display device is a display device according to any one of configurations 1 to 15. A photoelectric conversion device characterized by: (Configuration 17) A display device according to any one of configurations 1 to 15, a housing in which the display device is provided; a communication unit provided in the housing for communicating with the outside; An electronic device comprising: [Explanation of symbols]

[0169] 100: Display device 101: Substrate 105: Control circuit 106: Pixel 201: High-definition display area 202: Low-definition display area 203: High-definition display area

Claims

1. A substrate; a plurality of pixels arranged in a display region on the substrate; a control circuit for controlling signals supplied to the pixels; and the display area includes a first area and a second area surrounding the first area, a part of the first area is set as a third area whose position can be changed; By controlling the signals supplied to the pixels, a display resolution of a fourth region in the first region that is not the third region becomes lower than a display resolution of the third region, The display resolution of the second region is equal to or lower than the display resolution of the fourth region due to the circuit configuration of the pixel. A display device characterized by:

2. The number of light-emitting elements connected to the pixel circuits in the second region is greater than the number of light-emitting elements connected to the pixel circuits in the fourth region, so that the display resolution in the second region is equal to or lower than the display resolution in the fourth region.

2. The display device according to claim 1.

3. A plurality of light-emitting elements are uniformly arranged in the display area, Each of the plurality of pixels has one or more light-emitting elements.

2. The display device according to claim 1.

4. The plurality of light-emitting elements are arranged in a matrix including a row direction and a column direction, Each of the plurality of light-emitting elements is connected to a vertical scanning signal line arranged in the row direction and a horizontal scanning signal line arranged in the column direction, In the second region, adjacent light-emitting elements in the row direction are connected to the same horizontal scanning signal line.

4. The display device according to claim 3.

5. Each of the plurality of pixels has a plurality of sub-pixels that emit light of different colors, The two or more light-emitting elements connected to the same horizontal scanning signal line are all light-emitting elements that emit a first color.

5. The display device according to claim 4.

6. a vertical scanning signal line and a horizontal scanning signal line are connected to each of the plurality of light-emitting elements; the vertical scanning signal lines include write control lines and light emission control lines; each of the plurality of pixels includes one or more light-emitting elements, a driving transistor, a writing transistor, and a light-emitting control transistor; the write control line is connected to the gate of the write transistor; the light-emission control line is connected to the gate of the light-emission control transistor, the horizontal scanning signal line is connected to one of the source and the drain of the write transistor; the other of the source and the drain of the write transistor is connected to the gate of the drive transistor; one of the source and the drain of the driving transistor is connected to the light emitting element; the other of the source and the drain of the drive transistor is connected to one of the source and the drain of the light-emitting control transistor; The other of the source and the drain of the light-emitting control transistor is connected to a power supply.

4. The display device according to claim 3.

7. In the second region, One write transistor is provided for two or more adjacent light emitting elements, two or more driving transistors are provided corresponding to the two or more light-emitting elements, respectively; The other of the source and drain of the write transistor is connected to the gates of the two or more drive transistors.

7. The display device according to claim 6.

8. In the second region, two or more write transistors are provided corresponding to two or more adjacent light emitting elements, respectively; The same horizontal scanning signal line is connected to either the source or the drain of the two or more write transistors.

7. The display device according to claim 6.

9. a vertical scanning signal line and a horizontal scanning signal line are connected to each of the plurality of light-emitting elements; In the fourth region, the same horizontal scanning signal is supplied to two or more adjacent light emitting elements.

4. The display device according to claim 3.

10. The plurality of light-emitting elements are arranged in a matrix including row and column directions, Each of the plurality of light-emitting elements is connected to a vertical scanning signal line arranged in the row direction and a horizontal scanning signal line arranged in the column direction, In an area in which the third area does not exist in the row direction, a vertical scanning signal is sequentially supplied to light emitting elements for every plurality of rows; In the region where the third region exists in the row direction, a vertical scanning signal is sequentially supplied to the light emitting elements for each row.

4. The display device according to claim 3.

11. the display area further includes a fifth area surrounding the second area, The circuit configuration of the pixel causes the display resolution of the fifth region to be lower than the display resolution of the third region.

2. The display device according to claim 1.

12. Further comprising a line of sight detection unit, The control circuit sets the third area based on the detection result of the line-of-sight detection unit.

2. The display device according to claim 1.

13. further comprising an imaging unit; The control circuit sets an area in which a predetermined object is displayed in the image captured by the imaging unit as the third area.

2. The display device according to claim 1.

14. The control circuit detects the predetermined object from the image captured by the imaging unit using a classifier that uses a trained model.

14. The display device according to claim 13.

15. A region designation unit is provided, The control circuit sets the third region based on information from the region designation unit.

2. The display device according to claim 1.

16. an optical unit; an imaging element that receives light that has passed through the optical unit; a display device that displays an image captured by the imaging element; and The display device is a display device according to any one of claims 1 to 15. A photoelectric conversion device characterized by:

17. A display device according to any one of claims 1 to 15, a housing in which the display device is provided; a communication unit provided in the housing for communicating with the outside; An electronic device comprising:

Images