Semiconductor device, module and phased array antenna device

Abstract

To provide a semiconductor device capable of shortening implementation intervals and stable implementation.SOLUTION: A semiconductor device comprises a semiconductor chip, a housing portion 52 housing the semiconductor chip, and a package having a first flange 50A and a second flange 50B sandwiching the housing portion in a first direction. A bottom surface of a first end portion 51A of the first flange in the first direction is positioned above a mounting surface 54 of the housing portion. A first distance DA between the bottom surface of the first end portion and the mounting surface in a second direction perpendicular to the mounting surface is equal to or more a second distance DB between the top surface of a second end portion 51B of the second flange in the direction opposite to the first direction and the mounting surface in the second direction. The first end portion has a first hole or a first notch that penetrates the first end portion in the second direction, and the second end portion has a second hole or a second notch that penetrates the first end portion in the second direction.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, a module, and a phased array antenna device. [Background technology]

[0002] It is known that a semiconductor device uses a package having a pair of flanges sandwiching a main body in a first direction. The main body is mounted on a substrate by the pair of flanges. It is also known that the positions of the pair of flanges are different from each other in a second direction perpendicular to the first direction (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Utility Model Application Publication No. 5-46043 Summary of the Invention [Problem to be solved by the invention]

[0004] As in Patent Document 1, by making the positions of a pair of flanges different from each other in the second direction, it is possible to shorten the mounting intervals of multiple semiconductor devices in the first direction. However, when the semiconductor device is mounted on a substrate, characteristics such as stress deteriorate, making the semiconductor device unstable.

[0005] An object of the present disclosure is to provide a semiconductor device, a module, and a phased array antenna that can be mounted stably with a short mounting interval. [Means for solving the problem]

[0006] An embodiment of the present disclosure is a semiconductor device comprising: a package including a semiconductor chip; an accommodation section in which the semiconductor chip is accommodated; and a first flange and a second flange sandwiching the accommodation section in a first direction; wherein a lower surface of a first end of the first flange in the first direction is located above a mounting surface of the accommodation section; a first distance in a second direction perpendicular to the mounting surface between the lower surface of the first end and the mounting surface is greater than or equal to a second distance in the second direction between an upper surface of a second end of the second flange in the opposite direction to the first direction and the mounting surface; the first end has a first hole or a first notch penetrating the first end in the second direction; and the second end has a second hole or a second notch penetrating the first end in the second direction. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to provide a semiconductor device that can be mounted stably with a short mounting interval. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a side view of the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along the line AA in FIG. [Figure 4] FIG. 4 is a plan view of the module according to the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view taken along line AA in FIG. [Figure 6] FIG. 6 is a plan view of a module according to a first comparative example. [Figure 7] FIG. 7 is a plan view of a module according to a second comparative example. [Figure 8] FIG. 8 is a side view of a semiconductor device according to a first modification of the first embodiment. [Figure 9] FIG. 9 is a side view of a module according to a first modification of the first embodiment. [Figure 10]FIG. 10 is a plan view of a semiconductor device according to the second modification of the first embodiment. [Figure 11] FIG. 11 is a front view of an antenna in a phased array antenna apparatus according to the second embodiment. [Figure 12] FIG. 12 is a block diagram of a phased array antenna apparatus according to the second embodiment. [Figure 13] FIG. 13 is a perspective view of a portion of the phased array antenna apparatus according to the second embodiment. [Figure 14] FIG. 14 is a plan view of a portion of a phased array antenna apparatus 108 according to the second embodiment. [Figure 15] FIG. 15 is a plan view of a portion of the phased array antenna apparatus according to the second embodiment. [Figure 16] FIG. 16 is a front view of some modules and antennas of the phased array antenna apparatus according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] (1) An embodiment of the present disclosure is a semiconductor device comprising: a package including a semiconductor chip; an accommodation section for accommodating the semiconductor chip; and first and second flanges sandwiching the accommodation section in a first direction, wherein a lower surface of a first end of the first flange in the first direction is positioned above a mounting surface of the accommodation section; a first distance in a second direction perpendicular to the mounting surface between the lower surface of the first end and the mounting surface is equal to or greater than a second distance in the second direction between an upper surface of a second end of the second flange in the opposite direction to the first direction and the mounting surface; the first end has a first hole or a first notch penetrating the first end in the second direction; and the second end has a second hole or a second notch penetrating the first end in the second direction. This allows for shorter mounting intervals of semiconductor devices and stable mounting of semiconductor devices. (2) In the above (1), the first holes or the first cutouts may be arranged in a plurality in a third direction perpendicular to the first direction and the second direction, and the second holes or the second cutouts may be arranged in a plurality in the third direction, thereby enabling stable mounting of the semiconductor device. (3) In the above (2), at least two of the plurality of first holes or the plurality of first notches may be positioned on either side of a center line of the package in the third direction, and at least two of the plurality of second holes or the plurality of second notches may be positioned on either side of a center line of the package in the third direction, thereby enabling stable mounting of the semiconductor device. (4) In any of (1) to (3) above, the position of the first hole or the first cutout in a third direction perpendicular to the first direction and the second direction may coincide with the position of the second hole or the second cutout in the third direction, thereby allowing semiconductor devices to be arranged in the first direction. (5) In any one of the above (1) to (4), the top surface of the first end portion may be located higher from the mounting surface than the top surface of the second end portion, which makes it possible to easily form the first end portion. (6) In any one of (1) to (4) above, the first flange and the second flange may have a first layer and a second layer stacked in the second direction, the first end may have the second layer but not the first layer, and the second end may have the first layer but not the second layer, thereby enabling stable mounting of a semiconductor device. (7) In any of the above (1) to (6), the first hole or first notch and the second hole or second notch may be holes or notches through which a fastener for fixing the semiconductor device to a substrate passes, thereby enabling stable mounting of the semiconductor device. (8) A module may include a first semiconductor device that is any one of the semiconductor devices (1) to (7) above and is mounted on a substrate so that the mounting surface is on the upper surface of the substrate, and a second semiconductor device that is any one of the semiconductor devices (1) to (7) above and is mounted on the substrate so that the mounting surface is on the upper surface of the substrate, wherein the first end of the first semiconductor device is provided between the second end of the second semiconductor device and the substrate, and the first semiconductor device and the second semiconductor device are fixed on the substrate by a common fastener that penetrates the first hole or first notch and the second hole or second notch. This allows for shorter mounting intervals between semiconductor devices and stable mounting of the semiconductor devices. (9) In the above (8), the arrangement direction of the first semiconductor device and the second semiconductor device may coincide with the first direction of the first semiconductor device and the first direction of the second semiconductor device, thereby allowing the semiconductor devices to be arranged in the first direction. (10) A phased array antenna device may include the module of (9) above and first and second antennas arranged in the arrangement direction, wherein a third direction orthogonal to the first and second directions in the first semiconductor device coincides with the third direction in the second semiconductor device, and the first antenna overlaps the first semiconductor device when viewed from the third direction, and the second antenna overlaps the second semiconductor device when viewed from the third direction. This makes it possible to provide a phased array antenna device that can handle higher frequencies. (11) In the above (10), the first semiconductor device may have a first amplifier circuit, the second semiconductor device may have a second amplifier circuit, the first amplifier circuit may output an amplified high-frequency signal to the first antenna, and the second amplifier circuit may output an amplified high-frequency signal to the second antenna, thereby suppressing a rise in temperature of the semiconductor devices.

[0011] [Details of the embodiments of the present disclosure] Specific examples of semiconductor devices, modules, and phased array antenna devices according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0012] (Semiconductor device of the first embodiment) Fig. 1 is a plan view of the semiconductor device according to the first embodiment. In Fig. 1, the lid is shown in a see-through manner. Fig. 2 is a side view of the semiconductor device according to the first embodiment. Fig. 3 is a cross-sectional view taken along line AA in Fig. 1. The direction perpendicular to the mounting surface 54 of the base portion 11 is the Z direction (second direction), the direction in which the flanges 50B and 50A sandwich the housing portion 52 is the X direction (first direction), and the direction perpendicular to the X direction and the Z direction is the Y direction (third direction).

[0013] 1 to 3, semiconductor device 100 includes package 10, amplifiers 28A to 28D, and line chips 30A and 30B. Package 10 includes base 11, frame 12, lid 13, feedthroughs 14A and 14B, and leads 15A and 15B.

[0014] Base portion 11 has a substantially rectangular plate shape in plan view. Base portion 11 has flanges 50A and 50B that sandwich housing portion 52 in the X direction. Housing portion 52 includes a portion of base portion 11 sandwiched between flanges 50A and 50B, frame body 12, and lid body 13. Housing portion 52 houses amplifiers 28A to 28D and line chips 30A and 30B.

[0015] The base portion 11 has a mounting surface 54. The mounting surface 54 is flat and is the surface to be mounted on the substrate 35 described later. The flange 50A has an end portion 51A, and the flange 50B has an end portion 51B. The end portion 51A is a portion of the flange 50A that includes the end in the positive X direction, and the end portion 51B is a portion of the flange 50B that includes the end in the negative X direction. The lower surface of the end portion 51A is located above (in the +Z direction) the mounting surface 54 of the base portion 11. The distance between the mounting surface 54 and the lower surface of the end portion 51A in the Z direction is DA. The lower surface of the end portion 51B is at the same position in the Z direction as the mounting surface 54. The distance between the mounting surface 54 and the upper surface of the end portion 51B in the Z direction is DB.

[0016] Ends 51A and 51B have notches 16A and 16B, respectively. Notch 16A penetrates end 51A in the Z direction and opens to the positive side of flange 50A in the X direction. Notch 16B penetrates end 51B in the Z direction and opens to the negative side of flange 50B in the X direction. Two notches 16A are provided in the Y direction, and two notches 16B are provided in the Y direction.

[0017] The frame 12 is provided on the base 11. The planar shape of the frame 12 is approximately rectangular. The lid 13 is provided on the frame 12. The base 11, frame 12, and lid 13 form a gap 17. The feedthrough 14A penetrates the negative side of the frame 12 in the Y direction, and the feedthrough 14B penetrates the positive side of the frame 12 in the Y direction. The lead 15A penetrates the feedthrough 14A in the Y direction, and the lead 15B penetrates the feedthrough 14B in the Y direction. The base 11, frame 12, and leads 15A and 15B are metal layers such as copper layers. The feedthroughs 14A and 14B are insulating layers such as ceramics or resin. The lid 13 is a metal layer such as copper or an insulating layer such as ceramics.

[0018] Amplifiers 28A to 28D and line tips 30A and 30B are provided on base portion 11 within frame 12. Amplifiers 28A to 28D are arranged in the X direction. Line tips 30A and 30B sandwich amplifiers 28A to 28D in the Y direction.

[0019] Each of the amplifiers 28A to 28D includes a semiconductor chip 20, passive chips 25A and 25B, and bonding wires 29A to 29D. The passive chip 25B, the semiconductor chip 20, and the passive chip 25B are arranged in the Y direction.

[0020] The semiconductor chip 20 includes a substrate 21 and electrodes 22 and 23 provided on the substrate 21. For example, a transistor is provided on the substrate 21. The electrodes 22 and 23 are, for example, an input electrode and an output electrode of the transistor. If the transistor is a FET (Field Effect Transistor), the source, gate, and drain of the transistor are electrically connected to, for example, the base portion 11 and the electrodes 22 and 23, respectively.

[0021] The substrate 21 is a semiconductor substrate, and the electrodes 22 and 23 are metal layers such as gold or copper. When the transistor is a GaN HEMT (High Electron Mobility Transistor), the substrate 21 is, for example, a silicon carbide (SiC) substrate, a sapphire substrate, or a gallium nitride (GaN) substrate.

[0022] Passive chips 25A and 25B each include a substrate 26 and an electrode 27 provided on the substrate 26. The substrate 26 is a dielectric substrate made of, for example, alumina or barium titanate. The substrate 26, the electrode 27, and the base portion 11 sandwiching the substrate 26 form a capacitor.

[0023] Bonding wire 29A electrically connects line 32 of line chip 30A to electrode 27 of passive chip 25A. Bonding wire 29B electrically connects electrode 27 of passive chip 25A to electrode 23. Bonding wire 29C electrically connects electrode 22 to electrode 27 of passive chip 25B. Bonding wire 29D electrically connects electrode 27 of passive chip 25B to line 32 of line chip 30B.

[0024] Bonding wires 29A to 29D form an inductor. Bonding wire 29A, passive chip 25A, and bonding wire 29B function as a matching circuit that matches the impedance seen from electrode 23 at bonding wire 29B with the impedance seen from bonding wire 29A at line chip 30A. Bonding wire 29C, passive chip 25B, and bonding wire 29D function as a matching circuit that matches the impedance seen from line chip 30B at bonding wire 29D with the impedance seen from bonding wire 29C at electrode 22.

[0025] Line chips 30A and 30B each include a substrate 31 and a line 32 provided on substrate 31. In line chip 30A, line 32 forms a combiner that combines four input lines into one output line. Furthermore, first ends of bonding wires 29A of amplifiers 28A to 28D are connected to the four input lines of line 32, respectively. In line chip 30B, line 32 forms a distributor that branches one input line into four output lines. First ends of bonding wires 29D of amplifiers 28A to 28D are connected to the four output lines of line 32, respectively. Bonding wire 29E electrically connects one output line of line chip 30A to lead 15A. Bonding wire 29F electrically connects one input line of line chip 30B to lead 15B.

[0026] A high-frequency signal input from lead 15B is branched into four by line tip 30B. The four branched high-frequency signals are input to amplifiers 28A to 28D, respectively. The high-frequency signals amplified in amplifiers 28A to 28D are combined by line tip 30A. The combined high-frequency signal is output from lead 15A.

[0027] The number of semiconductor chips 20 provided within frame 12 may be one or more. At least one of passive chips 25A, 25B and line chips 30A and 30B may not be provided. Although an example in which transistors that handle high-frequency signals are provided on semiconductor chip 20 has been described, semiconductor chip 20 may also be provided with semiconductor elements used in a power conversion circuit.

[0028] (Module of the first embodiment) Fig. 4 is a plan view of the module according to the first embodiment. Fig. 5 is a cross-sectional view taken along line AA in Fig. 4. Screws are not shown in Fig. 4.

[0029] 4 and 5, a module 102 according to the first embodiment includes a substrate 35 and a plurality of semiconductor devices 100A to 100C. The plurality of semiconductor devices 100A to 100C are arranged in the X direction on the substrate 35. The plurality of semiconductor devices 100A to 100C are mounted on the substrate 35 such that the mounting surfaces 54 of the plurality of semiconductor devices 100A to 100C are provided on the upper surface of the substrate 35.

[0030] In the Z direction, the end portion 51B of the semiconductor device 100B is sandwiched between the end portion 51A of the semiconductor device 100A and the substrate 35. When viewed from the Z direction, the notch 16A of the semiconductor device 100A and the notch 16B of the semiconductor device 100B overlap. The screw 36 passes through the notch 16A of the semiconductor device 100A and the notch 16B of the semiconductor device 100B.

[0031] The end 51B of the semiconductor device 100C is sandwiched between the end 51A of the semiconductor device 100B and the substrate 35 in the Z direction. When viewed from the Z direction, the notch 16A of the semiconductor device 100B and the notch 16B of the semiconductor device 100C overlap. A screw 36 passes through the notch 16A of the semiconductor device 100B and the notch 16B of the semiconductor device 100C. A spacer 34 is provided between the end 51A of the semiconductor device 100C and the substrate 35. When viewed from the Z direction, the notch 16A of the semiconductor device 100C overlaps with the notch 34A provided in the spacer 34. The screw 36 passes through the notch 16A of the semiconductor device 100C and the notch 34A of the spacer 34. The screw 36 passes through the notch 16B of the semiconductor device 100A.

[0032] There is no semiconductor device that overlaps the end portion 51A of the semiconductor device 100C, so the lower surface of the end portion 51A of the semiconductor device 100C may be flush with the mounting surface 54 in the Z direction.

[0033] The screws 36 are inserted into the screw holes 35A of the substrate 35. When the screws 36 are tightened, the heads of the screws 36 are pressed toward the substrate 35. This secures the semiconductor devices 100A to 100C to the substrate 35. The substrate 35 is a heat sink, such as an aluminum or copper plate. By securing the semiconductor devices 100A to 100C to the substrate 35, heat generated in the semiconductor devices 100A to 100C is conducted to the substrate 35. This prevents the temperature of the semiconductor devices 100A to 100C from rising. When the amplifiers 28A to 28D are power amplifiers or when the semiconductor devices 100A to 100C are used in power conversion circuits, the semiconductor devices 100A to 100C generate a large amount of heat. Therefore, it is necessary to fasten the semiconductor devices 100A to 100C to the substrate 35 with screws. Furthermore, by supplying a reference potential, such as a ground potential, to the substrate 35, the reference potential can be stably supplied to the semiconductor devices 100A to 100C. When the semiconductor devices 100A to 100C handle high-frequency signals, their high-frequency characteristics will deteriorate if the reference potentials of the semiconductor devices 100A to 100C are not stable. For these reasons, it is necessary to fasten the semiconductor devices 100A to 100C to the substrate 35 with screws.

[0034] (First Comparative Example) FIG. 6 is a plan view of a module according to a first comparative example. Screws are not shown in FIG. 6. As shown in FIG. 6, in a module 110 according to the first comparative example, multiple semiconductor devices 111A to 111C are arranged in the X direction. In the first comparative example, the flanges 50A and 50B can be screwed to the substrate 35, improving heat dissipation from the semiconductor devices 111A to 111C to the substrate 35. This reduces temperature increases in the semiconductor devices 111A to 111C. Furthermore, a reference potential can be stably supplied to the semiconductor devices 111A to 111C. This reduces degradation of the high-frequency characteristics of the semiconductor devices 111A to 111C. In the semiconductor devices 111A to 111C, the end 51A of the flange 50A and the end 51B of the flange 50B are both flat. Therefore, the ends 51A and 51B cannot overlap when viewed in the Z direction.

[0035] Therefore, the distance D3 between the semiconductor devices 111A and 111B is equal to or greater than the width D4 in the X direction of the semiconductor devices 111A to 111C, which increases the mounting area of ​​the semiconductor devices 111A to 111C.

[0036] It is also possible to fix the semiconductor device to the substrate 35 using a bonding member such as solder without providing the flanges 50A and 50B. However, compared to the first comparative example in which the semiconductor device is directly fixed to the substrate 35, the heat dissipation and electrical contact are inferior because the bonding member is sandwiched between the semiconductor device and the substrate 35. In particular, voids and the like are likely to occur in the bonding member, further deteriorating the heat dissipation and electrical contact.

[0037] (Second Comparative Example) FIG. 7 is a plan view of a module according to a second comparative example. Screws are not shown in FIG. 7. As shown in FIG. 2, in module 112 according to the second comparative example, multiple semiconductor devices 113A to 113C are arranged in the X direction. In semiconductor devices 113A to 113C, end 51A of flange 50A and end 51B of flange 50B are both flat. End 51A of flange 50A is provided on a portion of flange 50A located on the positive side in the Y direction, and is not provided on a portion of flange 50A located on the negative side in the Y direction. End 51B of flange 50B is provided on a portion of flange 50B located on the negative side in the Y direction, and is not provided on a portion of flange 50B located on the positive side in the Y direction.

[0038] When viewed from the Y direction, the end 51A of the semiconductor device 113A and the end 51B of the semiconductor device 113B can overlap. The width in the X direction of the overlap between the end 51A of the semiconductor device 113A and the end 51B of the semiconductor device 113B is defined as D2. In this case, the distance D1 between the semiconductor devices 113A and 113B in the X direction can be made smaller by the distance D2 than the width D4 of the semiconductor devices 113A to 113C in the X direction.

[0039] However, the semiconductor devices 113A to 113C are fixed to the substrate 35 by screwing them into the notch 16A of the end portion 51A and the notch 16B of the end portion 51B. Because the semiconductor devices 113A to 113C are fixed at diagonal corners of the planar shapes of the semiconductor devices 113A to 113C, the fixing of the semiconductor devices 113A to 113C is unstable. This results in poor heat dissipation from the semiconductor devices 113A to 113C to the substrate 35. This causes the temperature of the semiconductor devices 113A to 113C to rise. Furthermore, the supply of the reference potential to the semiconductor devices 113A to 113C becomes unstable. This results in degradation of the high-frequency characteristics of the semiconductor devices 113A to 113C.

[0040] (Description of the First Embodiment) According to the semiconductor device 100 of the first embodiment, the flange 50A (first flange) and the flange 50B (second flange) sandwich the accommodation portion 52 in the X direction, in which the semiconductor chip 20 is accommodated. As shown in FIG. 2 , the lower surface of the end portion (first end portion) of the flange 50A in the positive X direction is positioned above the mounting surface 54 of the accommodation portion 52. The distance DA (first distance) in the Z direction between the lower surface of the end portion 51A and the mounting surface 54 is equal to or greater than the distance DB (second distance) in the Z direction between the upper surface of the end portion 51B (second end portion) of the flange 50B in the negative X direction (opposite the first direction) and the mounting surface 54. The end portion 51A has a notch 16A (first notch), and the end portion 51B has a notch 16B (second notch).

[0041] As a result, as shown in FIGS. 4 and 5 , in the module 102 of the first embodiment, the end 51A of the semiconductor device 100A (first semiconductor device) can be located between the end 51B of the semiconductor device 100B (second semiconductor device) and the substrate 35. Furthermore, the semiconductor devices 100A and 100B can be fixed to the substrate 35 by a common screw 36 (fixing device) that penetrates the notch 16A of the semiconductor device 100A and the notch 16B of the semiconductor device 100B. This allows the distance D1 between the semiconductor devices 100A and 100B in the X direction to be smaller than the width D4 of the semiconductor devices 100A and 100B in the X direction by the overlap width D2 between the end 51A and 51B in the X direction. Therefore, the mounting intervals of the semiconductor devices 100A to 100C can be shorter than those shown in FIG. 6 of the first comparative example. While the screw 36 has been used as an example of a fixing device, fixing devices other than the screw 36 may be used.

[0042] Furthermore, the end 51A of the semiconductor device 100A and the end 51B of the semiconductor device 100B can be fixed to the substrate 35 using a common screw 36. This allows the semiconductor devices 100A to 100C to be fixed to the substrate 35 more stably than in FIG. 7 of the second comparative example. This improves heat dissipation from the semiconductor devices 100A to 100C to the substrate 35. This reduces temperature increases in the semiconductor devices 100A to 100C. Furthermore, a reference potential can be stably supplied to the semiconductor devices 100A to 100C. This improves the high-frequency characteristics of the semiconductor devices 100A to 100C.

[0043] If the difference between the distances DA and DB is large, a space will be created between the end 51A of the semiconductor device 100A and the end 51B of the semiconductor device 100B when they are screwed together. The difference between the distances DA and DB may be set to ½ or ¼ of the distance DB or less. This allows the semiconductor devices 100A to 100C to be more stably fixed to the substrate 35. The distance DB is, for example, 0.5 mm or more and 3 mm or less.

[0044] 1, in the semiconductor device 100, the position of the notch 16A in the Y direction coincides with the position of the notch 16B in the Y direction. This allows the semiconductor devices 100A to 100C to be arranged in the X direction in the module 102, as shown in Fig. 4. The arrangement direction of the semiconductor devices 100A to 100C coincides with the arrangement direction of the flanges 50A and 50B of the semiconductor devices 100A to 100C.

[0045] Note that the term "the position of notch 16A in the Y direction and the position of notch 16B in the Y direction" does not necessarily mean that they are exactly the same. For example, the difference in position between notch 16A and 16B may be ½ or less or ¼ or less of the width of notches 16A and 16B in the Y direction. The positions of notches 16A and 16B in the Y direction are the center positions of the positions of notches 16A and 16B in the Y direction. Furthermore, "the two directions are the same" does not necessarily mean that they are exactly the same. For example, the angle between the two directions may be 10° or less or 5° or less.

[0046] 1, a plurality of notches 16A are arranged in the Y direction, and a plurality of notches 16B are arranged in the Y direction. This allows the semiconductor devices 100A to 100C to be stably fixed to the substrate 35 when they are fixed to the substrate 35 using screws 36, as shown in FIGS. 4 and 5. Note that, although the semiconductor device 100 of the first embodiment has two notches 16A and two notches 16B, the number of notches 16A and three or more notches 16B may be three or more.

[0047] As shown in FIG. 1 , at least two of the multiple notches 16A are positioned on either side of the center line 55 of the package 10 in the Y direction. At least two of the multiple notches 16B are positioned on either side of the center line 55 of the package 10 in the Y direction. This allows the semiconductor devices 100A to 100C to be more stably fixed to the substrate 36. The distance in the Y direction between the centers of the outermost notches 16A among the multiple notches 16A in the Y direction can be set to be at least one-third of the width in the Y direction of the flanges 50A and 50B. This allows the semiconductor devices 100A to 100C to be more stably fixed to the substrate 36. The width in the Y direction of the flanges 50A and 50B is, for example, 1 mm or more and 5 mm or less, and the distance in the Y direction between the centers of the notches 16A in the Y direction is, for example, 0.3 mm or more and 2 mm or less.

[0048] As shown in FIG. 1, the plurality of notches 16A are provided symmetrically with respect to a center line 55 of the package 10 in the Y direction, and the plurality of notches 16B are provided symmetrically with respect to the center line 55 of the package 10 in the Y direction.

[0049] 2 and 3, the upper surface of end 51A is located higher (in the positive Z direction) than the upper surface of end 51B. This allows end 51A to be formed by bending flange 50A. This makes it easy to form end 51A.

[0050] The top surfaces of the ends 51A and 51B are parallel to the mounting surface 54. This allows the semiconductor devices 100A to 100C to be more stably fixed to the substrate 35 when they are fixed to the substrate 35 using screws 36. Note that the two surfaces being parallel do not necessarily have to be parallel in the strict sense. For example, the angle between the two surfaces may be 10° or less or 5° or less.

[0051] From the viewpoint of miniaturizing the module 102, the distance D1 in the X direction between the semiconductor devices 100A and 100B may be set to 0.95 or less times the width D4 in the X direction of the semiconductor devices 100A and 100B, and may be set to 0.9 or less times. From the viewpoint of enlarging the accommodating portion 52, the distance D1 may be set to 0.5 or more times the width D4. The width D1 is, for example, 5 mm or more and 50 mm or less, and the width D4 is, for example, 5 mm or more and 50 mm or less.

[0052] (Modification 1 of the first embodiment) FIG. 8 is a side view of a semiconductor device according to Modification 1 of the first embodiment. As shown in FIG. 8, in a semiconductor device 104 according to Modification 1 of the first embodiment, the base portion 11 includes a first layer 11A, a second layer 11B, and a third layer 11C. The first layer 11A and the third layer 11C sandwich the second layer 11B in the Z direction. The frame body 12 is provided on the third layer 11C. The first layer 11A is not provided at the end portion 51A, but the second layer 11B and the third layer 11C are provided. The second layer 11B and the third layer 11C are not provided at the end portion 51B, but the first layer 11A is provided. The base portion 11 other than the end portions 51A and 51B includes the first layer 11A, the second layer 11B, and the third layer 11C. The first layer 11A, the second layer 11B, and the third layer 11C are metal layers. The first layer 11A and the third layer 11C are, for example, copper layers, and the second layer 11B is, for example, a molybdenum layer.

[0053] Fig. 9 is a side view of a module according to Modification 1 of the first embodiment. As shown in Fig. 9, in a semiconductor device 106 according to Modification 1 of the first embodiment, a first layer 11A of an end portion 51B of a semiconductor device 104B is disposed between a second layer 11B of an end portion 51A of the semiconductor device 104A and the substrate 35. A first layer 11A of an end portion 51B of a semiconductor device 104C is disposed between a second layer 11B of an end portion 51A of the semiconductor device 104B and the substrate 35. The other configurations are the same as those of the first embodiment, and therefore description thereof will be omitted.

[0054] According to the first modification of the first embodiment, the flanges 50A and 50B each have a first layer 11A, a second layer 11B, and a third layer 11C. The first layer 11A, the second layer 11B, and the third layer 11C are stacked in the Z direction. The end 51A has the second layer 11B and the third layer 11C, but does not have the first layer 11A. The end 51B has the first layer 11A, but does not have the second layer 11B or the third layer 11C. As a result, the distance DA in the Z direction between the mounting surface 54 and the lower surface of the end 51A and the distance DB in the Z direction between the mounting surface 54 and the upper surface of the end 51B both correspond to the thickness of the first layer 11A and can be approximately equal to each other. This allows the semiconductor devices 102A to 102C to be more stably fixed to the substrate 35. Although an example in which three layers are laminated on the base portion 11 has been described, the base portion 11 may have two layers or four or more layers laminated on it.

[0055] (Modification 2 of the first embodiment) Fig. 10 is a plan view of a semiconductor device according to Modification 2 of the first embodiment. As shown in Fig. 10, in a semiconductor device 107 according to Modification 2 of the first embodiment, holes 18A (first hole) and 18B (second hole) penetrating the base portion 11 in the Z direction are provided in end portions 51A and 51B. The other configurations are the same as those in the first embodiment, and therefore description thereof will be omitted.

[0056] As in Modification 2 of the first embodiment, holes 18A and 18B may be provided instead of the notches 16A and 16B. The notches 16A and 16B have a planar shape that is surrounded by the base portion 11 on three sides in the XY plane and is open on one side. The holes 18A and 18B are closed surfaces that are surrounded by the base portion 11 on the XY plane.

[0057] (Second embodiment) The second embodiment is an example in which the module of the first embodiment and its modified example are used in a phased array antenna device. Fig. 11 is a front view of an antenna in the phased array antenna device according to the second embodiment. Fig. 11 is a view seen from the Y direction.

[0058] As shown in Fig. 11, in the phased array antenna device 108, antennas 41 are arranged in a matrix in the X and Z directions on a substrate 40. The spacing between the antennas 41 in the X direction is DX, and the spacing between the antennas 41 in the Z direction is DZ. The spacing DX is approximately constant, and the spacing DZ is also approximately constant. The spacings DX and DZ may be approximately equal. The antennas 41 are, for example, patch antennas.

[0059] Fig. 12 is a block diagram of a phased array antenna apparatus according to the second embodiment. As shown in Fig. 12, a phased array antenna apparatus 108 includes a plurality of blocks 45. Each of the plurality of blocks 45 includes an amplifier circuit 43, a phase shifter 42, and an antenna 41.

[0060] When the phased array antenna device 108 transmits radio waves, the radio frequency signal is input to an amplifier circuit 43. The amplifier circuit 43 amplifies the radio frequency signal. The phase shifter 42 shifts the phase of the amplified radio frequency signal. The antenna 41 emits the phase-shifted radio frequency signal into space as radio waves 44. For example, in blocks 45 arranged in the Z direction, the phase shifted by the phase shifter 42 increases as the blocks move toward the Z direction. By setting the amount of phase increase for each block 45, it is possible to impart directivity in any direction tilted from the Y direction to the Z direction. The same is true for blocks 45 arranged in the X direction.

[0061] Fig. 13 is a perspective view of a portion of a phased array antenna apparatus according to the second embodiment. In Fig. 13, three blocks 45 arranged in the X direction are illustrated, and the substrate 40 is not illustrated. Fig. 14 is a plan view of a portion of a phased array antenna apparatus 108 according to the second embodiment. In Fig. 14, three blocks 45 arranged in the X direction are illustrated, and the plan view is seen from the Z direction. Fig. 15 is a plan view of a portion of a phased array antenna apparatus according to the second embodiment. In Fig. 15, two blocks 45 arranged in the Z direction are illustrated, and the side view is seen from the X direction.

[0062] 13 to 15, a plurality of substrates 35 are provided on a substrate 40 on which an antenna 41 is provided, with the substrate 40 sandwiched between the antenna 41 and the substrate 40 in the Y direction. The substrates 35 are arranged in the Z direction. The module 102 of the first embodiment, a phase shifter 42, and line patterns 39A to 39C are provided on one substrate 35. The line patterns 39A to 39C are provided with an insulating layer 37 sandwiched between them and the substrate 35.

[0063] A line 38 is provided that penetrates the substrate 40. The line 38 electrically connects the antenna 41 and a line pattern 39A. The line pattern 39A electrically connects the line 38 and a phase shifter 42. The line pattern 39B electrically connects the phase shifter 42 and a lead 15A. The line pattern 39C is connected to a lead 15B. The semiconductor chip 20 in each of the semiconductor devices 100A to 100C has an amplifier circuit 43.

[0064] The high-frequency signal input to line pattern 39C is input to semiconductor device 100 via lead 15B. The high-frequency signal amplified by amplifier circuit 43 of semiconductor device 100 is input to phase shifter 42 via lead 15A and line pattern 39B. The high-frequency signal whose phase has been shifted by phase shifter 42 is emitted into space from antenna 41 via line pattern 39A and line 38.

[0065] Fig. 16 is a front view of some modules and antennas of the phased array antenna apparatus according to the second embodiment. Fig. 16 is a plan view of antennas 41A to 41C superimposed on module 102 as viewed from the Y direction. Distance D1 between semiconductor devices 100A to 100C and distance DX between antennas 41A to 41C are the same. This is because if distance D1 and distance DX were different, the electrical distance between leads 15A of semiconductor devices 100A to 100C and antennas 41A to 41C would differ depending on block 45, making it difficult to control the phase of high-frequency signals between blocks 45.

[0066] In the phased array antenna device 108, the spacing DX and DZ between the antennas 41A to 41C are ideally λ / 2 to enhance the directivity of the radio waves. Here, λ is the wavelength in a vacuum of the radio waves emitted by the antennas 41A to 41C. DX and DZ are required to be 2×λ / 3 or greater, even if this sacrifices some of the antenna characteristics. When the radio wave frequency is 5 GHz, λ / 2 and 2×λ / 3 are 30 mm and 40 mm, respectively. When the radio wave frequency is 10 GHz, λ / 2 and 2×λ / 3 are 15 mm and 20 mm, respectively. Thus, as the signal frequency increases, the spacing DX between the antennas 41 must be reduced, which in turn requires a reduction in the spacing D1 between the leads 15A of the semiconductor device 100, etc.

[0067] According to the second embodiment, when viewed from the Y direction, the antenna 41A (first antenna) overlaps the semiconductor device 100A (first semiconductor device), and the antenna 41B (second antenna) overlaps the semiconductor device 100B (second semiconductor device). As a result, as in the first embodiment and its modified example, the distance D1 between the semiconductor devices 100A to 100C can be reduced, and therefore the distance DX between the antennas 41A to 41C can be reduced. Therefore, a phased array antenna device that can handle higher frequencies can be provided.

[0068] The amplifier circuit 43 (first amplifier circuit) of the semiconductor device 100A outputs the amplified high-frequency signal to the antenna 41A, and the amplifier circuit 43 (second amplifier circuit) of the semiconductor device 100B outputs the amplified high-frequency signal to the antenna 41B. As such, when the semiconductor devices 100A to 100C include power amplifiers, the semiconductor devices 100A to 100C tend to become hot. Therefore, the flanges 50A and 50B are fastened with screws. This makes it possible to suppress the temperature rise of the semiconductor devices 100A to 100C.

[0069] In the second embodiment, an example has been described in which six antennas 41 are arranged in the X direction and six antennas 41 are arranged in the Z direction, but it is sufficient that two or more antennas 41 are arranged in the X direction. The frequency of the radio waves 44 of the phased array antenna device 108 is, for example, 5 GHz or higher, or 10 GHz or higher.

[0070] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the meaning described above, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0071] 10:Package 11: Base section 11A: 1st layer 11B: 2nd layer 11C: 3rd layer 12:Frame body 13: Lid 14, 14A, 14B: Feedthrough 15A, 15B: Lead 16A (first notch), 16B (second notch): Notch 17:Void 18A (1st hole), 18B (2nd hole): Hole 20: Semiconductor chip 21, 26, 31, 35, 36, 40: Substrate 22, 23, 27: Electrode 25A, 25B: Passive chips 28A, 28B, 28C, 28D: Amplifiers 29A, 29B, 29C, 29D, 29E, 29F: Bonding wire 30A, 30B: Track chip 32:Railway 34: Spacer 35A: Hole 37: Insulating layer 38: Railroad 39A, 39B, 39C: Track pattern 41, 41A (first antenna), 41B (second antenna), 41C: antenna 42: Phase shifter 43: Amplification circuit 44: Radio Waves 45: Block 50A (first flange), 50B (second flange): flange 51A (first end), 51B (second end): End 52: Storage unit 54: Mounting surface 100, 100A (first semiconductor device), 100B (second semiconductor device), 100C, 104A, 104B, 104C, 106, 107, 111A, 111B, 111C, 113, 113A, 113B, 113C: semiconductor devices 102, 110, 112: Modules 108: Phased array antenna device DA (first distance), DB (second distance): distance

Claims

1. A semiconductor chip; a package including a housing portion for housing the semiconductor chip, and a first flange and a second flange provided on either side of the housing portion in a first direction; Equipped with a lower surface of a first end of the first flange in a first direction is located above a mounting surface of the accommodating portion, and a first distance in a second direction orthogonal to the mounting surface between the lower surface of the first end and the mounting surface is equal to or greater than a second distance in the second direction between an upper surface of a second end of the second flange in a direction opposite to the first direction and the mounting surface, The first end has a first hole or a first notch penetrating the first end in the second direction, and the second end has a second hole or a second notch penetrating the first end in the second direction.

2. 2. The semiconductor device according to claim 1, wherein a plurality of the first holes or the first notches are arranged in a third direction perpendicular to the first direction and the second direction, and a plurality of the second holes or the second notches are arranged in the third direction.

3. At least two of the plurality of first holes or the plurality of first notches are positioned on either side of a center line of the package in the third direction, The semiconductor device according to claim 2 , wherein at least two of the plurality of second holes or the plurality of second notches are arranged on either side of a center line of the package in the third direction.

4. 4. The semiconductor device according to claim 1, wherein the position of the first hole or the first notch in a third direction perpendicular to the first direction and the second direction coincides with the position of the second hole or the second notch in the third direction.

5. The semiconductor device according to claim 1 , wherein an upper surface of the first end portion is located higher from the mounting surface than an upper surface of the second end portion.

6. the first flange and the second flange have a first layer and a second layer stacked in the second direction, the first end includes the second layer and does not include the first layer; The semiconductor device according to claim 1 , wherein the second end portion includes the first layer and does not include the second layer.

7. 4. The semiconductor device according to claim 1, wherein the first hole or first notch and the second hole or second notch are holes or notches through which a fastener for fixing the semiconductor device to a substrate passes.

8. A substrate; 4. The semiconductor device according to claim 1, further comprising: a first semiconductor device mounted on the substrate such that the mounting surface is provided on an upper surface of the substrate; and 4. The semiconductor device according to claim 1, further comprising: a second semiconductor device mounted on the substrate such that the mounting surface is provided on an upper surface of the substrate; and Equipped with the first end of the first semiconductor device is provided between the second end of the second semiconductor device and the substrate, A module in which the first semiconductor device and the second semiconductor device are fixed onto the substrate by a common fastener that passes through the first hole or first notch and the second hole or second notch.

9. 9. The module according to claim 8, wherein an arrangement direction of said first semiconductor device and said second semiconductor device coincides with said first direction of said first semiconductor device and said first direction of said second semiconductor device.

10. A module according to claim 9; a first antenna and a second antenna arranged in the arrangement direction; Equipped with a third direction orthogonal to the first direction and the second direction in the first semiconductor device coincides with the third direction in the second semiconductor device; When viewed from the third direction, the first antenna overlaps with the first semiconductor device, The phased array antenna device, wherein the second antenna overlaps with the second semiconductor device when viewed from the third direction.

11. the first semiconductor device has a first amplifier circuit; the second semiconductor device has a second amplifier circuit; the first amplifier circuit outputs the amplified high-frequency signal to the first antenna; the second amplifier circuit outputs the amplified high-frequency signal to the second antenna; The phased array antenna apparatus according to claim 10.

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