Manufacturing method for semiconductor device, and wiring board

Abstract

To provide a manufacturing method for a semiconductor device, capable of attaching a semiconductor member for sure.SOLUTION: An example of a manufacturing method for a semiconductor device using a bridge die is disclosed. Copper posts 22 are provided on a carrier substrate 20, and a semiconductor die 40 to serve as a bridge die is attached between the copper posts 22. The semiconductor die 40 is attached by a resin layer 43 covering a terminal electrode 42 so that the terminal electrode 42 faces (faces down) the carrier substrate 20. The resin layer 43 is cured to form a sealing material layer 23. A wiring layer 24 is formed on one surface of the sealing material layer 23 and a wiring layer 28 is formed on the other surface by separating the carrier substrate 20. Active dies 50, 55 are attached to an interposer P to obtain a semiconductor device 1. By this method, the bridge dies are attached with their faces directed downward; therefore, the attachment can be achieved for sure. Since the active die, which is expensive, is attached finally, the manufacturing cost can be reduced.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a wiring substrate. [Background technology]

[0002] In recent years, with the rapid advancement in functionality of electronic devices, such as AI and HPC, semiconductor packages have become larger and denser. These package structures are not limited to surface mounting with higher density; package structures and mounting processes are becoming more complex and diverse, including inorganic (silicon) or organic interposer (Bridgedie / RDL) technology, 2.xD mounting using these, and 3D mounting (HBM / Chiplet) technology using TSV. For example, Resonac Inc., based at its Packaging Solutions Center, is developing next-generation semiconductor packaging process technology from the perspective of its customers (semiconductor manufacturers), combining mounting processes and materials.

[0003] As a technology in the field of semiconductor packaging, Patent Document 1 discloses a method for manufacturing a semiconductor device in which a semiconductor die is mounted face-up on a carrier and sealed, a wiring layer is formed on the sealing layer, and another semiconductor die is mounted on the wiring layer. Patent Document 2 discloses another method for manufacturing a semiconductor device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0098421 [Patent Document 2] US Patent Application Publication No. 2022 / 0093526 Summary of the Invention [Problem to be solved by the invention]

[0005] In the semiconductor device manufacturing method described in Patent Document 1, a conceivable method for mounting a semiconductor die on a support is to use a collet to suck up the terminal electrode side of the semiconductor die and then mount the semiconductor die face-up on the support. In this case, the collet sucks the outer periphery of the semiconductor die so as to avoid the internal region where the terminal electrodes are provided. However, if the mounting is performed in this suction state, the semiconductor die may not be mounted reliably.

[0006] An object of the present disclosure is to provide a method for manufacturing a semiconductor device that can reliably attach a semiconductor member (semiconductor die). [Means for solving the problem]

[0007] [1] One aspect of the present disclosure relates to a method for manufacturing a semiconductor device, the method comprising the steps of: providing, on a first support, a conductive columnar member having a first end and an opposite second end, the first end being located on the first support side; attaching a semiconductor member including a semiconductor substrate having a first surface and an opposite second surface, a terminal electrode provided on the first surface of the semiconductor substrate, and a resin layer provided on the first surface so as to cover the terminal electrode, to the first support with the first surface facing the first support; forming a first encapsulant layer on the first support to encapsulate the columnar member and the semiconductor member; forming a first wiring layer on the first encapsulant layer, the first wiring layer being electrically connected to at least the columnar member; separating the first support from the first encapsulant layer; grinding at least the resin layer to expose tips of the terminal electrodes; and forming a second wiring layer on the first encapsulant layer, the second wiring layer being electrically connected to at least one of the terminal electrodes and the columnar member, the terminal electrodes being exposed.

[0008] In this method for manufacturing a semiconductor device, the semiconductor member is attached to the first support so that the first surface on which the terminal electrodes are provided faces the first support. That is, the semiconductor member is attached face down. Therefore, when the semiconductor member is sucked with a collet or the like for bonding, the terminal electrode side does not need to be sucked, and the semiconductor member can be reliably attached. Note that when the semiconductor member is picked up before bonding, the terminal electrode side may be sucked with a collet first (and then the semiconductor member is turned over for bonding). In this case, because the terminal electrodes are covered with a resin layer, the outer periphery does not need to be sucked with a collet, and the semiconductor member can be reliably picked up.

[0009] Furthermore, in this semiconductor device manufacturing method, the semiconductor chip connected to the semiconductor member can be attached at the end of the process (for example, after the first and second wiring layers are formed), so if a defect occurs during the manufacturing process, the semiconductor chip, which is an expensive active die, can be avoided from being attached, thereby reducing the overall manufacturing cost.

[0010] [2] Preferably, the method for manufacturing a semiconductor device according to [1] above further comprises a step of curing the resin layer containing the curable resin composition after attaching the semiconductor member to the first support and before forming the first encapsulant layer. In this case, displacement of the semiconductor member can be prevented when forming (encapsulating) the first encapsulant layer.

[0011] [3] In the method for manufacturing a semiconductor device according to [1] or [2] above, the resin layer formed when the semiconductor member is attached to the first support may be a semi-cured or uncured curable resin composition. In this case, the semiconductor member can be reliably attached to the first support at a predetermined position.

[0012] [4] In the method for manufacturing a semiconductor device according to any one of [1] to [3] above, the resin layer preferably has a visible light transmittance of 30% or more. In this case, the positions of the terminal electrodes of the semiconductor member can be confirmed before attachment, and the semiconductor member can be attached to the first support at a predetermined position with high precision.

[0013] [5] In the method for manufacturing a semiconductor device according to any one of [1] to [4] above, in the step of attaching the semiconductor member, it is preferable to determine the positions of the terminal electrodes through the resin layer and attach the semiconductor member to a predetermined position on the first support based on the result of the determination. In this case, the positions of the terminal electrodes of the semiconductor member can be confirmed directly or indirectly, and the semiconductor member can be attached to the predetermined position on the first support with high precision.

[0014] [6] In any of the methods for manufacturing a semiconductor device according to [1] to [5] above, the resin layer may contain an inorganic filler. In this case, the hardness (elastic modulus, etc.) of the resin layer can be improved, and bending or cracking of the semiconductor member can be suppressed. Furthermore, the inclusion of an inorganic filler can also suppress warping of the semiconductor member including the resin layer.

[0015] [7] In the method for manufacturing a semiconductor device according to [6] above, the content of the inorganic filler may be 30% by mass or more based on the total amount of solids contained in the resin layer. In this case, warping of the semiconductor member can be more reliably suppressed.

[0016] [8] In the method for manufacturing a semiconductor device according to [6] or [7] above, the inorganic filler may have an average particle diameter of 20 μm or less. In this case, even if the terminal electrodes and their pitch of the semiconductor member are miniaturized, the resin and filler can be inserted (filled) between the terminal electrodes, ensuring that the terminal electrodes are covered with the resin layer. In addition, warping of the cured resin layer can be suppressed.

[0017] [9] In any of the methods for manufacturing a semiconductor device according to [1] to [8] above, the elastic modulus of the resin layer at room temperature after curing may be 10 MPa or more. In this case, warping and cracking of the semiconductor member can be further suppressed. Furthermore, when the cured resin layer is polished to expose the heads of the terminal electrodes, the polishing operation can be easily performed. The elastic modulus here refers to Young's modulus. Room temperature refers to 25°C. Note that the cured resin layer may not be completely cured, and it is sufficient if it is hard enough to be polished in the polishing operation.

[0018]

[10] In any of the methods for manufacturing a semiconductor device according to the above [1] to [9], the resin layer may be formed by laminating a non-conductive adhesive film (NCF) or a die attach film (DAF). In this case, it is preferable that the resin layer is formed by laminating an NCF.

[0019]

[11] In any of the methods for manufacturing a semiconductor device described above in [1] to

[10] , the thickness of the resin layer may be between 100% and 150% of the height of the terminal electrodes. In this case, the thickness of the resin layer and the height of the terminal electrodes are approximately equal, which makes it possible to more reliably lift and attach the semiconductor member.

[0020]

[12] In any of the methods for manufacturing a semiconductor device described above in [1] to

[11] , the resin layer may be formed by laminating a resin film, and the thickness of the resin film before lamination may be between 75% and 150% of the height of the terminal electrode. In this case, when the resin film is laminated, the thickness of the resin layer and the height of the terminal electrode become approximately equal, making it possible to more reliably lift and attach the semiconductor member.

[0021]

[13] The method for manufacturing a semiconductor device according to any one of [1] to

[12] above may further include a step of grinding the first sealing material layer after forming the first sealing material layer and before forming the first wiring layer so as to expose the second ends of the pillar-shaped members. In this case, the first wiring layer connected to the pillar-shaped members can be formed more reliably.

[0022]

[14] Any of the semiconductor device manufacturing methods [1] to

[13] above may further include a step of providing a second support on the first wiring layer after forming the first wiring layer, and may separate the first support from the first encapsulant layer after providing the second support. In this case, various manufacturing steps can be performed while the first encapsulant layer is supported by either support, making it possible to manufacture a semiconductor device using a thin first encapsulant layer. Furthermore, even if the first encapsulant layer is thin, warping and cracking can be prevented.

[0023]

[15] The semiconductor device manufacturing method described in

[14] above may further include a step of forming connection bumps on the surface of the first wiring layer opposite the first encapsulant layer. The step of forming the connection bumps may be performed before the second support is provided on the first wiring layer or after the second support is separated from the first wiring layer. If the connection bumps are formed before the second support is provided on the first wiring layer, an active die such as a logic die can be attached in the final step. This eliminates the need to attach an expensive active die if the wiring substrate is defective, thereby reducing manufacturing costs. Furthermore, if the connection bumps are formed after the second support is separated from the first wiring layer, many processes can be performed on the wiring substrate without the connection bumps. This makes it easier to perform various processes, such as forming the second wiring layer, and improves manufacturing efficiency.

[0024]

[16] In the method for manufacturing a semiconductor device according to any one of [1] to

[15] above, the semiconductor member may have a fine wiring layer between the first surface of the semiconductor substrate and the terminal electrode, thereby ensuring reliable connection between the fine circuit in the semiconductor substrate and the terminal electrode.

[0025]

[17] In any one of the methods for manufacturing a semiconductor device according to [1] to

[16] above, the semiconductor member may have an internal electrode extending in the thickness direction of the semiconductor substrate, a first end of the internal electrode may be connected to the second wiring layer via a terminal electrode, and a second end of the internal electrode may be connected to the first wiring layer. In this case, a through electrode such as a TSV (Through Silicon Via) can be provided in the semiconductor substrate, improving the degree of freedom in wiring design. Furthermore, miniaturization of wiring can be promoted.

[0026]

[18] Preferably, the method for manufacturing a semiconductor device according to any one of the above [1] to

[17] further comprises the step of attaching at least one semiconductor chip to the surface of the second wiring layer opposite to the first sealing material layer.

[0027]

[19] In the method for manufacturing a semiconductor device according to

[18] above, in the step of attaching the semiconductor chips, it is preferable to attach a first semiconductor chip and a second semiconductor chip as at least one semiconductor chip to the second wiring layer, and it is preferable that the first semiconductor chip and the second semiconductor chip are electrically connected by a semiconductor member. In this case, the semiconductor member can be used as a so-called bridge die.

[0028]

[20] The method for manufacturing a semiconductor device according to

[18] or

[19] above may further include a step of forming a second encapsulant layer that encapsulates at least one semiconductor chip. In this case, the semiconductor chip is reliably protected by the encapsulant layer.

[0029]

[21] In the method for manufacturing a semiconductor device according to any one of the above [1] to

[20] , it is preferable that at least one of the first connection portion between the columnar member and the first wiring layer and the second connection portion between the columnar member and the second wiring layer is connected without solder. In this case, it is not necessary to consider the diffusion of solder, and therefore the design of the semiconductor device can be simplified accordingly.

[0030]

[22] In any of the semiconductor device manufacturing methods [1] to

[21] above, the columnar member may be provided in a substrate having a first surface and an opposite second surface. In the step of providing the columnar member, a connecting member including the columnar member, the substrate, another terminal electrode provided on the first surface side of the substrate, and another resin layer provided on the first surface side of the substrate so as to cover the other terminal electrode may be attached to the first support with the first surface facing the first support, thereby providing the columnar member on the first support. In this case, the step of providing the columnar member can be simplified. Furthermore, the semiconductor member and the connecting member can be attached in parallel, improving manufacturing efficiency.

[0031]

[23] In the method for manufacturing a semiconductor device according to

[22] above, in the step of forming the first encapsulating layer, the connecting member may be encapsulated together with the semiconductor member, in the grinding step, the resin layer and the other resin layer may be ground so as to expose the other terminal electrode together with the terminal electrode, and in the step of forming the second wiring layer, the second wiring layer may be formed so as to be electrically connected to each of the terminal electrode and the other terminal electrode. In this case, even when the connecting member is used, the semiconductor device can be manufactured in the same way as when the columnar member is directly formed.

[0032]

[24] The method for manufacturing a semiconductor device according to

[22] or

[23] above may further include a step of grinding a part of the semiconductor substrate and a part of the substrate together with the first sealing material layer so as to expose the second ends of the columnar members, after forming the first sealing material layer and before forming the first wiring layer. In this case, even when a connecting member is used, the semiconductor device can be manufactured in the same way as when the columnar members are directly formed.

[0033]

[25] Another aspect of the present disclosure relates to a wiring substrate used in manufacturing a semiconductor device. The wiring substrate includes a semiconductor member, a conductive columnar member having a first end and a second end opposite the semiconductor member and disposed adjacent to the semiconductor member, a first encapsulant layer encapsulating the semiconductor member and the columnar member, a first wiring layer disposed on the first encapsulant layer and electrically connected to at least the columnar member, and a second wiring layer disposed on the surface of the first encapsulant layer opposite the first wiring layer and electrically connected to at least one of the terminal electrodes and the columnar member. The semiconductor member of the wiring substrate includes a semiconductor substrate having a first surface and an opposite second surface, terminal electrodes disposed on the first surface of the semiconductor substrate, and a resin layer disposed on the first surface so as to expose the tips of the terminal electrodes and cover the remaining portions of the terminal electrodes. Such a wiring substrate can be used as an interposer for mounting a semiconductor chip to fabricate a semiconductor device.

[0034]

[26] In yet another aspect, the present disclosure relates to a method for manufacturing a semiconductor device. The method includes providing the wiring substrate of

[25] and attaching a first semiconductor chip and a second semiconductor chip onto a second wiring layer of the wiring substrate. In the attaching step, the first semiconductor chip is electrically connected to the second semiconductor chip by a semiconductor member. In this case, a semiconductor device in which the semiconductor member functions as a bridge die can be easily fabricated.

[0035]

[27] In the method for manufacturing a semiconductor device according to

[26] above, the first semiconductor chip may include a logic chip, and the second semiconductor chip may include a memory chip. In this case, the logic chip can be easily connected to the memory chip via a bridge die. [Effects of the Invention]

[0036] According to the present disclosure, it is possible to provide a method for manufacturing a semiconductor device that can reliably attach a semiconductor member. [Brief explanation of the drawings]

[0037] [Figure 1]FIG. 1 is a cross-sectional view showing an example of a cross-sectional configuration of a semiconductor device according to the first embodiment. [Figure 2] 2(a) to 2(d) are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. [Figure 3] 3(a) and 3(b) are enlarged cross-sectional views showing the semiconductor member to be attached in FIG. 2(c). [Figure 4] 4(a) to 4(d) are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 1, illustrating steps performed after the step shown in FIG. 2(d). [Figure 5] 5(a) to 5(c) are cross-sectional views showing the method for manufacturing the semiconductor device shown in FIG. 1, illustrating steps performed after the step shown in FIG. 4(d). [Figure 6] 6(a) to 6(c) are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 1, illustrating steps performed after the step shown in FIG. 5(c). [Figure 7] FIG. 7 is a cross-sectional view showing an example of a cross-sectional configuration of a semiconductor device according to the second embodiment. [Figure 8] 8(a) to 8(d) are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. [Figure 9] 9(a) to 9(c) are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 7, illustrating steps performed after the step shown in FIG. 8(d). [Figure 10] 10(a) to 10(c) are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 7, illustrating steps performed after the step shown in FIG. 9(c). [Figure 11] 11(a) to 11(c) are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 7, illustrating steps performed after the step shown in FIG. 10(c). DETAILED DESCRIPTION OF THE INVENTION

[0038] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same or equivalent parts will be denoted by the same reference numerals, and duplicate explanations will be omitted. Furthermore, unless otherwise specified, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings. Furthermore, the dimensional ratios of the drawings are not limited to those shown in the drawings.

[0039] In this specification, the term "layer" encompasses not only a structure with a shape formed over the entire surface when observed in a plan view, but also a structure with a shape formed on a portion of the surface. In this specification, the term "process" refers not only to an independent process, but also to a process that cannot be clearly distinguished from other processes, as long as the process achieves its intended function. In this specification, "(meth)acrylic" means acrylic or its corresponding methacrylic. Furthermore, when multiple substances corresponding to each component are present in the composition, the content of each component in the composition refers to the total amount of the multiple substances present in the composition, unless otherwise specified.

[0040] In this specification, numerical ranges indicated using "to" indicate ranges that include the numerical values ​​before and after "to" as the minimum and maximum values, respectively. In numerical ranges described in stages in this specification, the upper or lower limit of a numerical range in one stage may be replaced with the upper or lower limit of a numerical range in another stage. In numerical ranges described in this specification, the upper or lower limit of that numerical range may be replaced with a value shown in the examples.

[0041] [First embodiment] FIG. 1 is a diagram illustrating an example of a semiconductor device manufactured by a manufacturing method according to a first embodiment. As illustrated in FIG. 1, the semiconductor device 1 includes semiconductor dies 2 and 3, semiconductor dies 4 and 5, wiring layers 6 and 7, encapsulant layers 8 and 9, connection electrodes 10, connection bumps 11, and underfills 12 and 13. The semiconductor device 1 is mounted on a substrate M. The substrate M may be, for example, a motherboard. A structure S in which the semiconductor device 1 is further mounted on the substrate M may also be referred to as a semiconductor device. In the semiconductor device 1, a wiring layer 6, an encapsulant layer 8 that encapsulates the semiconductor dies 4 and 5 and the connection electrodes 10, a wiring layer 7 electrically connected to the semiconductor dies 4 and 5 and the connection electrodes 10, and an encapsulant layer 9 that encapsulates the semiconductor dies 2 and 3 are stacked in this order on the substrate M.

[0042] The semiconductor dies 2 and 3 (first semiconductor chip and second semiconductor chip) are, for example, semiconductor chips such as LSI chips (logic chips), CMOS sensors, memory chips, etc., and may be so-called active dies. The semiconductor dies 2 and 3 each have terminal electrodes 2a and 3a and fine wiring layers 2b and 3b provided on the terminal electrodes 2a and 3a sides. In the semiconductor device 1, the semiconductor dies 2 and 3 are mounted so that the terminal electrodes 2a and 3a face the semiconductor dies 4 and 5 and the wiring layer 7. An underfill material is introduced into the connection areas of the terminal electrodes 2a and 3a and hardens to form an underfill 13. The semiconductor dies 2 and 3 are encapsulated by an encapsulant constituting the encapsulant layer 9, and each surface is exposed to the outside.

[0043] The semiconductor dies 4 and 5 (semiconductor members) may be, for example, bridge dies or silicon capacitors, and may be so-called passive dies. The semiconductor dies 4 and 5 may also be active dies. The semiconductor dies 4 and 5 are ultra-thin semiconductor dies, for example, having a thickness of 100 μm or less, and may have a thickness of 50 μm or less. Each of the semiconductor dies 4 and 5 has terminal electrodes 4a and 5a and fine wiring layers 4b and 5b provided on the terminal electrodes 4a and 5a sides. The terminal electrodes 4a and 5a of the semiconductor dies 4 and 5 and their pitches are also becoming smaller, with the diameter of each of the terminal electrodes 4a and 5a being, for example, 10 μm to 50 μm, and the height of each of the terminal electrodes 4a and 5a being, for example, 20 μm to 50 μm. The terminal pitch (separation distance) between the terminal electrodes 4a and the terminal pitch (separation distance) between the terminal electrodes 5a being, for example, 5 μm to 20 μm. However, the size and pitch of the terminal electrodes 4a and 5a are not limited to those described above.

[0044] In the semiconductor device 1, the semiconductor dies 4 and 5 are disposed so that the terminal electrodes 4a and 5a face the semiconductor dies 2 and 3. As an example, the semiconductor die 4 is a bridge die, and connects the semiconductor dies 2 and 3 to each other via the wiring portion 7a of the wiring layer 7 (second wiring layer). The semiconductor die 5 is connected to the semiconductor die 3, but not to the semiconductor die 2, via the wiring portion 7a of the wiring layer 7. If the semiconductor dies 4 and 5 further have through electrodes 4c and 5c, the semiconductor dies 4 and 5 may connect the semiconductor dies 2 and 3 to the wiring portion 6a of the wiring layer 6 (first wiring layer) via the through electrodes 4c and 5c.

[0045] The wiring layers 6 and 7 are rewiring layers and have wiring portions 6a and 7a and insulating portions 6b and 7b covering the wiring portions 6a and 7a, respectively. The wiring layers 6 and 7 may have the same wiring pitch and wiring width, but it is preferable that the wiring pitch and wiring width of the wiring layer 7 are narrower than the wiring pitch and wiring width of the wiring layer 6. The wiring portions 6a of the wiring layer 6 are connected to connection bumps 11. The connection bumps 11 are, for example, solder bumps. An underfill material is introduced into the connection areas formed by the connection bumps 11 and hardens to form an underfill 12.

[0046] The encapsulant layers 8 and 9 are layers that encapsulate the semiconductor dies with an encapsulant, such as an encapsulant containing epoxy resin. The encapsulant layer 8 encapsulates the semiconductor dies 4 and 5. The encapsulant layer 9 encapsulates the semiconductor dies 2 and 3.

[0047] The connection electrodes 10 are conductive columnar members that connect the wiring layers 6 and 7 (wiring portions 6a and 7a), and are so-called posts or pillars. The connection electrodes 10 are made of, for example, copper. The connection electrodes 10 are provided adjacent to the semiconductor dies 4 and 5. The height of the connection electrodes 10 is approximately the same as the thickness of the semiconductor dies 4 and 5. The diameter of the connection electrodes 10 is, for example, 10 μm to 50 μm. The connection electrodes 10 are encapsulated together with the semiconductor dies 4 and 5 by an encapsulant and are located within the encapsulant layers 8 and 9. The semiconductor dies 4 and 5 are disposed between the connection electrodes 10.

[0048] In the semiconductor device 1, the semiconductor dies 4 and 5 are disposed face-up within the encapsulant layer 8. The semiconductor dies 4 and 5 are provided with a resin layer (see resin layers 33 and 43 in FIG. 3 ) covering the terminal electrodes 4 a and 5 a. The tips of the terminal electrodes 4 a and 5 a are exposed from the resin layer and connected to the wiring portion 7 a, while the other portions of the terminal electrodes 4 a and 5 a are covered by the resin layer. As will be described in detail later, the resin layer is formed of a resin film containing a thermosetting adhesive, such as a non-conductive film (NCF) or a die attach film (DAF), or a liquid thermosetting adhesive. The resin layer is a cured resin layer formed by curing either of these adhesive layers. That is, the material constituting the resin layer is in a semi-cured (B-stage) state and then cured to a fully cured (C-stage) state by a subsequent curing process. The curing method may be heat or light. However, the resin layer of the semiconductor dies 4 and 5 may be in a cured state that is not fully cured, as long as it does not interfere with the semiconductor device 1. The curable resin composition constituting the resin layers of the semiconductor dies 4 and 5 includes a thermosetting resin, and may further include a curing agent, a curing accelerator, and an inorganic filler.

[0049] Next, an example of a method for manufacturing the semiconductor device 1 will be described with reference to Fig. 2 to Fig. 6. Fig. 2 and Fig. 4 to Fig. 6 are cross-sectional views sequentially illustrating the method for manufacturing the semiconductor device 1. Fig. 3 is an enlarged cross-sectional view showing a semiconductor member.

[0050] In this method for manufacturing a semiconductor device, first, a temporary fixing layer 21 is formed on a carrier substrate 20 (first support), as shown in (a) of Fig. 2. The carrier substrate 20 is, for example, a glass substrate. The temporary fixing layer 21 is, for example, a curable adhesive layer, and is configured to be peeled off together with the carrier substrate 20 by light, heat, or the like in a process described below.

[0051] Next, as shown in FIG. 2(b), a plurality of posts 22 are formed on the temporary fixing layer 21. Each post 22 is a conductive columnar member made of, for example, copper. Each post 22 has a first end 22a and an opposite second end 22b, and is formed so that the first end 22a of each post 22 is located on the carrier substrate 20 side. The posts 22 correspond to the connection electrodes 10 shown in FIG. 1. Since semiconductor dies 30 and 40 will be placed on the carrier substrate 20 (temporary fixing layer 21) in a process described later, the posts 22 are not placed in this region. Such posts 22 can be formed, for example, by a semi-additive method. The height of the posts 22 may be, for example, 50 μm to 200 μm or 75 μm to 180 μm. The diameter of the posts 22 may be, for example, 10 μm to 50 μm.

[0052] Next, as shown in FIGS. 3A and 3B, semiconductor dies 30 and 40 (semiconductor members) are prepared. As shown in FIG. 3A, the semiconductor die 30 includes a semiconductor substrate 31, multiple terminal electrodes 32, a resin layer 33, a fine wiring layer 34, and internal electrodes 35. The semiconductor die 30 corresponds to the semiconductor die 5 shown in FIG. 1. The semiconductor substrate 31 is made of, for example, silicon, and has a first surface 31a and an opposite second surface 31b. Multiple terminal electrodes 32 are provided on the first surface 31a side of the semiconductor substrate 31. The multiple terminal electrodes 32 are, for example, copper pillars provided on the first surface 31a side of the semiconductor substrate 31, and are connected to wiring (not shown) within the semiconductor substrate 31. The diameter of each terminal electrode 32 is, for example, 10 μm to 50 μm, the terminal pitch (separation distance) between the terminal electrodes 32 is, for example, 5 μm to 20 μm, and the height of the terminal electrodes 32 is, for example, 20 μm to 50 μm, however, the sizes of the terminal electrodes 32 are not limited to these.

[0053] The resin layer 33 is a resin member formed from a thermosetting adhesive (curable resin composition) and provided on the first surface 31a side so as to cover the multiple terminal electrodes 32. The resin layer 33 may be formed so as to cover the entire first surface 31a of the semiconductor substrate 31, or so as to expose the tips of the terminal electrodes 32 from the surface of the resin layer 33. The resin layer 33 attaches (bonds) the semiconductor die 30 to (attaches) the temporary fixing layer 21 of the carrier substrate 20. The resin layer 33 can be formed by bonding (bonding) a resin film containing a resin composition, such as a non-conductive adhesive film (NCF) or a die attach film (DAF). The resin film before bonding may have a thickness between 75% and 150% or between 100% and 120% of the height of the multiple terminal electrodes 32, and is preferably a film having a thickness similar to the height of the terminal electrodes 32. The resin layer 33 is a curable resin composition that is semi-cured or uncured when the semiconductor die 30 is attached to the carrier substrate 20. Such a resin layer 33 may have a visible light transmittance of 30% or more, preferably a visible light transmittance of 50% or more, and more preferably a visible light transmittance of 80% or more. In this case, when attaching the semiconductor die 30 to the carrier substrate 20 in a step described below, the positions of the multiple terminal electrodes 32 can be determined through the resin layer 33, and the semiconductor die 30 can be attached to the predetermined positions on the carrier substrate 20 with high accuracy based on the determination results. Note that the resin layer 33 may be formed by applying a liquid adhesive containing a thermosetting adhesive (curable resin composition) similar to the resin film to the first surface 31a of the semiconductor substrate 31.

[0054] The thickness of the resin layer 33 may be, for example, 50 μm or less, 20 μm or less, 10 μm or less, 9 μm or less, 8 μm or less, or 7 μm or less, or 1 μm or more, 2 μm or more, 3 μm or more, 4 μm or more, 5 μm or more, or 10 μm or more. The thickness of the resin layer 33 may be between 100% and 150% of the height of the multiple terminal electrodes 32, or may be between 100% and 120%, and is preferably the same thickness as the height of the terminal electrodes 32. Note that the thickness of the resin layer 33 here refers to the thickness in an uncured or semi-cured state, and the height of the multiple terminal electrodes 32 refers to the average height of the multiple terminal electrodes 32.

[0055] The fine wiring layer 34 is a wiring layer located between the semiconductor substrate 31 and the resin layer 33. The fine wiring layer 34 has a wiring portion 34a and an insulating portion 34b that covers the wiring portion 34a. The wiring portion 34a electrically connects the wiring or internal electrode 35 in the semiconductor substrate 31 to the terminal electrode 32. The semiconductor die 30 does not necessarily have to have the fine wiring layer 34.

[0056] The internal electrode 35 is an electrode that connects the wiring layers provided on both sides of the semiconductor die 30 and is formed to extend in the thickness direction of the semiconductor substrate 31. The internal electrode 35 corresponds to the through electrode 4c shown in FIG. 1. The internal electrode 35 has a first end 35a and a second end 35b on the opposite side. The first end 35a is connected to the corresponding terminal electrode 32 via the fine wiring layer 34. Meanwhile, the second end 35b of the internal electrode 35 is not exposed to the outside and is located within the semiconductor substrate 31 when the semiconductor die 30 is attached to the carrier substrate 20 (stage (c) of FIG. 2). By grinding the second surface 31b of the semiconductor substrate 31 in a process described later (stage (a) of FIG. 4), the second end 35b of the internal electrode 35 is exposed to the outside, and the internal electrode 35 functions as a through electrode. The semiconductor die 30 does not necessarily have an internal electrode 35 that serves as a through electrode.

[0057] The semiconductor die 40 has a similar configuration to the semiconductor die 30 and includes a semiconductor substrate 41, multiple terminal electrodes 42, a resin layer 43, a micro-wiring layer 44, and internal electrodes 45, as shown in FIG. 3B. The semiconductor die 40 corresponds to the semiconductor die 4 shown in FIG. 1. The semiconductor substrate 41 is made of, for example, silicon and has a first surface 41a and an opposite second surface 41b. Multiple terminal electrodes 42 are provided on the first surface 41a of the semiconductor substrate 41. The multiple terminal electrodes 42 are connected to wiring (not shown) within the semiconductor substrate 41. The size, height, etc. of the terminal electrodes 42 are similar to those of the terminal electrodes 32. The resin layer 43 is an adhesive member provided on the first surface 41a so as to cover the multiple terminal electrodes 42. The resin layer 43 allows the semiconductor die 40 to be attached (bonded) to the temporary fixing layer 21 of the carrier substrate 20. The resin layer 43 can be formed by laminating (sticking) a resin film containing a resin composition such as NCF or DAF. The resin film before lamination may have a thickness between 75% and 150%, or between 100% and 120%, of the height of the terminal electrodes 42, and is preferably a film having a thickness similar to the height of the terminal electrodes 42. The resin layer 43 is a curable resin composition that is semi-cured or uncured when the semiconductor die 40 is attached to the carrier substrate 20. The resin composition constituting the resin layer 43 can be the same as that of the resin layer 33.

[0058] The fine wiring layer 44 is a wiring layer located between the semiconductor substrate 41 and the resin layer 43. The fine wiring layer 44 has a wiring portion 44a and an insulating portion 44b covering the wiring portion 44a. The wiring portion 44a electrically connects the wiring or internal electrode 45 in the semiconductor substrate 41 to the terminal electrode 42. The internal electrode 45 is an electrode that connects the wiring layers provided on both sides of the semiconductor die 40 and has a first end 45a and a second end 45b on the opposite side. The first end 45a is connected to the corresponding terminal electrode 42 via the fine wiring layer 44. The second end 45b is not exposed when the semiconductor die 40 is attached to the carrier substrate 20. By grinding the second surface 41b of the semiconductor substrate 41, the second end 45b of the internal electrode 45 is exposed, and the internal electrode 45 functions as a through electrode. The semiconductor die 40 does not necessarily have the fine wiring layer 44 or the internal electrode 45.

[0059] The semiconductor dies 30 and 40 described above can be fabricated by dividing a wafer or panel-shaped semiconductor substrate including a large number of semiconductor dies 30 and 40 having the layer structure described above into individual pieces.

[0060] Here, an example of an adhesive constituting the resin layers 33, 43 will be described. As such an adhesive, an adhesive containing (a) an epoxy resin, (b) a curing agent, (c) a polymer component having a weight-average molecular weight of 10,000 or more, (d) an inorganic filler having an average particle size of 100 nm or less, and (e) a glycidyl-based silane coupling agent can be used. In this adhesive, the content of the inorganic filler (d) may be 20 to 40 mass %. The adhesive constituting the resin layers 33, 43 is not limited to the adhesive described below.

[0061] Examples of the epoxy resin of component (a) include epoxy resins having two or more epoxy groups in the molecule, such as bisphenol A epoxy resins, bisphenol F epoxy resins, naphthalene epoxy resins, phenol novolac epoxy resins, cresol novolac epoxy resins, phenol aralkyl epoxy resins, biphenyl epoxy resins, triphenylmethane epoxy resins, dicyclopentadiene epoxy resins, and various polyfunctional epoxy resins. Component (a) can be used alone or in combination of two or more. The content of component (a) is, for example, 10 to 50 mass% based on the total amount of the thermosetting adhesive.

[0062] Examples of curing agents for component (b) include phenolic resin-based curing agents, acid anhydride-based curing agents, amine-based curing agents, imidazole-based curing agents, and phosphine-based curing agents. When component (b) contains a phenolic hydroxyl group, acid anhydrides, amines, or imidazoles, it tends to exhibit flux activity that suppresses the formation of oxide films at the connection, making it easy to improve connection reliability and insulation reliability. Each curing agent is described below.

[0063] (i) Phenolic resin curing agent Examples of phenolic resin-based curing agents include curing agents having two or more phenolic hydroxyl groups in the molecule, such as phenol novolac, cresol novolac, phenol aralkyl resin, cresol naphthol formaldehyde polycondensate, triphenylmethane-type polyfunctional phenol, various polyfunctional phenolic resins, etc. The phenolic resin-based curing agents can be used alone or in combination of two or more.

[0064] The equivalent ratio (phenolic hydroxyl group / epoxy group, molar ratio) of the phenolic resin curing agent to the component (a) is preferably 0.3 to 1.5, more preferably 0.4 to 1.0, and even more preferably 0.5 to 1.0, from the viewpoint of good curability, excellent adhesion, and storage stability. When the equivalent ratio is 0.3 or more, curability and adhesive strength tend to be improved, while when it is 1.5 or less, no excessive unreacted phenolic hydroxyl groups remain, water absorption is kept low, and insulation reliability tends to be further improved.

[0065] (ii) Acid anhydride curing agent Examples of acid anhydride curing agents that can be used include methylcyclohexanetetracarboxylic dianhydride, trimellitic anhydride, pyromellitic anhydride, benzophenonetetracarboxylic dianhydride, and ethylene glycol bisanhydrotrimellitate. The acid anhydride curing agents can be used alone or in combination of two or more.

[0066] The equivalent ratio (acid anhydride group / epoxy group, molar ratio) of the acid anhydride curing agent to the component (a) is preferably 0.3 to 1.5, more preferably 0.4 to 1.0, and even more preferably 0.5 to 1.0, from the viewpoint of good curability, excellent adhesion, and storage stability. When the equivalent ratio is 0.3 or more, curability and adhesive strength tend to be improved, while when it is 1.5 or less, no excess unreacted acid anhydride remains, water absorption is kept low, and insulation reliability tends to be further improved.

[0067] (iii) Amine-based curing agents As the amine-based curing agent, for example, dicyandiamide can be used.

[0068] The equivalent ratio (amine / epoxy group, molar ratio) of the amine-based curing agent to the component (a) is preferably 0.3 to 1.5, more preferably 0.4 to 1.0, and even more preferably 0.5 to 1.0, from the viewpoint of good curability, excellent adhesion, and storage stability. When the equivalent ratio is 0.3 or more, curability and adhesive strength tend to improve, while when it is 1.5 or less, no excessive unreacted amine remains, and insulation reliability tends to further improve.

[0069] (iv) Imidazole-based curing agents Examples of imidazole curing agents include 2-phenylimidazole, 2-phenyl-4-methylimidazole, 1-benzyl-2-methylimidazole, 1-benzyl-2-phenylimidazole, 1-cyanoethyl-2-undecylimidazole, 1-cyano-2-phenylimidazole, 1-cyanoethyl-2-undecylimidazole trimellitate, 1-cyanoethyl-2-phenylimidazolium trimellitate, 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-s-triazine, and 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-s-triazine. -[2'-undecylimidazolyl-(1')]-ethyl-s-triazine, 2,4-diamino-6-[2'-ethyl-4'-methylimidazolyl-(1')]-ethyl-s-triazine, 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-s-triazine isocyanuric acid adduct, 2-phenylimidazole isocyanuric acid adduct, 2-phenyl-4,5-dihydroxymethylimidazole, 2-phenyl-4-methyl-5-hydroxymethylimidazole, and adducts of epoxy resins and imidazoles. Among these, from the viewpoint of achieving even better curing properties, storage stability, and connection reliability, 1-cyanoethyl-2-undecylimidazole, 1-cyano-2-phenylimidazole, 1-cyanoethyl-2-undecylimidazole trimellitate, 1-cyanoethyl-2-phenylimidazolium trimellitate, 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-s-triazine, 2,4-diamino-6-[2'-ethyl-4'-methylimidazolyl-(1')]-ethyl-s-triazine, 2,4-diamino-6-[2'-methylimidazolyl-(1')]-ethyl-s-triazine isocyanuric acid adduct, 2-phenylimidazole isocyanuric acid adduct, 2-phenyl-4,5-dihydroxymethylimidazole, and 2-phenyl-4-methyl-5-hydroxymethylimidazole are preferred. The imidazole curing agents can be used alone or in combination of two or more. They can also be microencapsulated to form latent curing agents.

[0070] The content of the imidazole curing agent is preferably 0.1 to 20 parts by mass, and more preferably 0.1 to 10 parts by mass, per 100 parts by mass of component (a). When the content of the imidazole curing agent is 0.1 part by mass or more, curability tends to be improved, while when the content is 20 parts by mass or less, the adhesive composition does not cure before a metal bond is formed, and connection defects tend to be less likely to occur.

[0071] (v) Phosphine-based curing agents Examples of phosphine curing agents include triphenylphosphine, tetraphenylphosphonium tetraphenylborate, tetraphenylphosphonium tetra(4-methylphenyl)borate, and tetraphenylphosphonium(4-fluorophenyl)borate.

[0072] The content of the phosphine-based curing agent is preferably 0.1 to 10 parts by mass, and more preferably 0.1 to 5 parts by mass, per 100 parts by mass of component (a). When the content of the phosphine-based curing agent is 0.1 part by mass or more, curability tends to be improved, while when it is 10 parts by mass or less, the adhesive for semiconductors does not harden before a metal bond is formed, and connection defects tend to be less likely to occur.

[0073] The phenolic resin curing agent, the acid anhydride curing agent, and the amine curing agent can each be used alone or in combination of two or more. The imidazole curing agent and the phosphine curing agent can each be used alone, or can be used together with the phenolic resin curing agent, the acid anhydride curing agent, or the amine curing agent.

[0074] As component (b), from the viewpoint of excellent curing properties, a combination of phenol and imidazole, a combination of acid anhydride and imidazole, a combination of amine and imidazole, or imidazole alone is preferred. Since productivity improves when bonding is performed in a short time, the use of imidazole alone, which has excellent fast curing properties, is more preferred. In this case, since curing in a short time can suppress volatile components such as low-molecular-weight components, the occurrence of voids can also be easily suppressed.

[0075] Examples of (c) polymer components having a weight-average molecular weight of 10,000 or more (excluding compounds corresponding to component (a)) include phenoxy resins, polyimide resins, polyamide resins, polycarbodiimide resins, cyanate ester resins, (meth)acrylic resins, polyester resins, polyethylene resins, polyethersulfone resins, polyetherimide resins, polyvinyl acetal resins, urethane resins, and acrylic rubber. Among these, from the viewpoint of excellent heat resistance and film formability, phenoxy resins, polyimide resins, (meth)acrylic resins, acrylic rubber, cyanate ester resins, and polycarbodiimide resins are preferred, and phenoxy resins, polyimide resins, (meth)acrylic resins, and acrylic rubber are more preferred. Component (c) can be used alone or as a mixture or copolymer of two or more types.

[0076] The mass ratio of component (c) to component (a) is not particularly limited, but in order to maintain the film form, the content of component (a) is preferably 0.01 to 5 parts by mass, more preferably 0.05 to 4 parts by mass, and even more preferably 0.1 to 3 parts by mass per part by mass of component (c). If the content is 0.01 part by mass or more, curability and adhesive strength tend to be improved, and if the content is 5 parts by mass or less, film-forming properties and membrane-forming properties tend to be improved.

[0077] The weight-average molecular weight of component (c) is 10,000 or more in polystyrene equivalent, but in order to exhibit good film-forming properties by itself, it is preferably 30,000 or more, more preferably 40,000 or more, and even more preferably 50,000 or more. When the weight-average molecular weight is 10,000 or more, film-forming properties tend to be improved. In this specification, the weight-average molecular weight means the weight-average molecular weight measured in polystyrene equivalent using high-performance liquid chromatography (Shimadzu Corporation C-R4A).

[0078] The (d) component is not particularly limited as long as it is an inorganic filler with an average particle size of 100 nm or less, and examples thereof include insulating inorganic fillers. Examples of insulating inorganic fillers include glass, silica, alumina, titanium oxide, carbon black, mica, and boron nitride. Of these, silica, alumina, titanium oxide, and boron nitride are preferred, with silica, alumina, and boron nitride being more preferred. The insulating inorganic filler may be whiskers, and examples of whiskers include aluminum borate, aluminum titanate, zinc oxide, calcium silicate, magnesium sulfate, and boron nitride. The insulating inorganic fillers can be used alone or in combination of two or more. The shape, particle size, and content of the (d) component are not particularly limited. The (d) component can be used alone or in combination of two or more.

[0079] From the viewpoint of improving visibility, the average particle size of component (d) is 100 nm or less. From the viewpoint of improving visibility, the average particle size of component (d) is preferably 60 nm or less. From the viewpoint of improving adhesive strength, component (d) is preferably an inorganic filler having an average particle size of 60 nm or less and having been surface-treated with a (meth)acrylic silane.

[0080] The content of component (d) is 20 to 40 mass% based on the total amount of the adhesive. When the content of component (d) is 20 mass% or more, adhesive strength is high and reflow resistance tends to be improved. When the content of component (d) is 40 mass% or less, thickening can be prevented and connection reliability can be improved.

[0081] There are no particular restrictions on component (e) as long as it is a glycidyl-based silane coupling agent. If it is a glycidyl-based agent, it will react with the epoxy resin to improve adhesive strength. The content of component (e) is preferably 1 to 5 parts by mass, more preferably 1.5 to 4% by mass, per 100 parts by mass of component (d). If the content is 1 part by mass or more, adhesive strength tends to improve, and if it is 5 parts by mass or less, defects such as the generation of voids can be prevented.

[0082] The adhesive according to the present embodiment may further contain additives such as a fluxing agent, a resin filler, an antioxidant, a silane coupling agent (excluding compounds corresponding to component (e)), a titanium coupling agent, and a leveling agent. These additives may be used alone or in combination of two or more. The content of these additives may be adjusted appropriately so that the effects of each additive are exerted.

[0083] Furthermore, as another type of adhesive constituting the resin layers 33, 43, an adhesive containing a high-molecular-weight resin component and a thermosetting component may be used. The high-molecular-weight resin component may contain, for example, at least one resin selected from the group consisting of acrylic rubber, polyimide, and phenoxy resin. The high-molecular-weight resin component may have a reactive group such as an epoxy group. The weight-average molecular weight (standard polystyrene equivalent value measured by GPC method) of the high-molecular-weight resin component may be 100,000 to 3,000,000. The content of the high-molecular-weight resin component may be 30 to 80 parts by mass relative to 10 parts by mass of the total mass of the resin layer 33.

[0084] The thermosetting component contained in this other type of adhesive is a compound having a reactive group that forms a crosslinked structure by self-polymerization and / or reaction with a curing agent. The thermosetting component may include, for example, at least one selected from the group consisting of epoxy resin, bismaleimide resin, triazine resin, and phenolic resin. The content of the thermosetting component may be 1 to 30 parts by mass per 100 parts by mass of the resin layer 33. This other type of adhesive may contain other components as needed. Examples of the other components include a curing agent that reacts with the thermosetting component, a curing accelerator that promotes the reaction between the thermosetting component and the curing agent, a coupling agent (e.g., a silane coupling agent), and an inorganic filler (e.g., silica).

[0085] Specific examples of inorganic fillers contained in this other type of adhesive include glass, as described above. The average particle size of the inorganic filler may be, for example, 20 μm or less, or may be 10 μm or less, and the maximum particle size of the inorganic filler may be, for example, 30 μm or less. It is preferable that the average particle size of the inorganic filler is 5 μm or less, and the maximum particle size of the inorganic filler is 20 μm or less. By having an average particle size of 10 μm or less and a maximum particle size of 30 μm or less, it is possible to fill gaps between terminals when forming a resin layer on the terminal surface, and to suppress warping after curing the resin layer. There are no particular restrictions on the lower limit of the average particle size or the maximum particle size of the inorganic filler, but both may be 0.001 μm or more.

[0086] The average particle size and maximum particle size of the inorganic filler can be measured, for example, by measuring the particle sizes of approximately 20 inorganic fillers using a scanning electron microscope (SEM). Measurements using an SEM can be performed, for example, by preparing a sample by heat-curing a resin composition containing the inorganic filler (preferably at 150 to 180°C for 1 to 10 hours), cutting the center of the sample, and observing the cross section with an SEM. In this case, the probability of fillers with particle sizes of 3 μm or less in the cross section is preferably 80% or more of the total filler.

[0087] The content of the inorganic filler may be 10% by mass to 95% by mass based on the total solid content of the adhesive before curing. The content of the inorganic filler in the adhesive is preferably 20% by mass or more, more preferably 30% by mass or more, particularly preferably 40% by mass or more, and preferably 40% by mass to 95% by mass based on the total solid content of the adhesive (resin layers 33, 43) before curing. The elastic modulus (Young's modulus, after curing) of such resin layer 33 may be, for example, 10 MPa or more, or 1.0 GPa or more at room temperature (25°C). The linear expansion coefficient of resin layer 33 at temperatures below its glass transition temperature may be, for example, 10 ppm / K to 200 ppm / K.

[0088] Returning to FIG. 2, the explanation continues. Next, after preparation of the semiconductor dies 30, 40 is completed, as shown in FIG. 2C, the semiconductor dies 30, 40 are attached to the carrier substrate 20 so that the bottom surfaces on which the terminal electrodes 32, 42 (see FIGS. 3A and 3B) are provided face the carrier substrate 20. At this time, the entire top surfaces (second surfaces 31b, 41b) of the semiconductor dies 30, 40 are vacuum-sucked by a collet for bonding. The collet is made of an elastic material such as rubber. The semiconductor dies 30, 40 are moved to a predetermined position on the carrier substrate 20 by the vacuum-sucked collet, and are attached to the predetermined position on the carrier substrate 20 by the resin layers 33, 43. During this attachment, the terminal electrodes 32, 42 of the semiconductor dies 30, 40 are protected because they are covered by the resin layers 33, 43. This results in the state shown in FIG. 2C. In this step, the semiconductor dies 30, 40 are placed face down with the terminal electrodes 32, 42 facing downward.

[0089] When attaching the semiconductor dies 30, 40, the positions of the terminal electrodes 32, 42 in the planar direction may be determined through the resin layers 33, 43 of the semiconductor dies 30, 40, and the semiconductor dies 30, 40 may be attached to predetermined positions on the carrier substrate 20 based on the results of this determination. If the resin layers 33, 43 have a transmittance equal to or greater than a predetermined value (e.g., a transmittance of 30% or greater for visible light), this pre-attachment position determination can be performed, thereby enabling the positional relationship between the terminal electrodes 32, 42 and the posts 22 to be determined with high precision. If the carrier substrate 20 is a transparent member such as a glass substrate, the positions of the posts 22 and the terminal electrodes 32, 42 can be determined from below the carrier substrate 20. The positions of the terminal electrodes 32, 42 may be determined directly through the resin layers 33, 43, or indirectly by determining the positions of positioning markings provided on the surfaces of the first surfaces 31a, 41a through the resin layers 33, 43. The positions of the terminal electrodes 32, 42 may be determined by other methods, and are not particularly limited.

[0090] Next, after the attachment of the semiconductor dies 30, 40 is completed, the resin layers 33, 43 containing the curable resin composition are cured before the semiconductor dies 30, 40 are encapsulated. The resin layers 33, 43 are cured using heat and / or light. This fixes the semiconductor dies 30, 40 to the carrier substrate 20. Note that the fixation here is sufficient as long as the semiconductor dies 30, 40 are fixed to a degree that will prevent misalignment during the encapsulation process described below.

[0091] Next, as shown in FIG. 2(d), an encapsulant layer 23 (first encapsulant layer) is formed on the carrier substrate 20. The encapsulant layer 23 encapsulates the posts 22 and the semiconductor dies 30 and 40 with an encapsulant. The encapsulant layer 23 contains a thermosetting resin, such as an epoxy resin, and is cured by heat or other means after encapsulation. The resin layers 33 and 43 of the semiconductor dies 30 and 40 may be further cured by this thermal curing. The encapsulant constituting the encapsulant layer 23 contains a thermosetting resin composition, such as an epoxy resin and a curing agent. The encapsulant constituting the encapsulant layer 23 may further contain an inorganic filler, such as a silica filler. The average particle diameter of the inorganic filler contained in the encapsulant may be, for example, 50 μm or less, 25 μm or less, 10 μm or less, or 0.01 μm or less. The encapsulant constituting the encapsulant layer 23 preferably contains an inorganic filler with a large particle size in order to suppress warping during or after manufacturing of the semiconductor device 1, and preferably contains an inorganic filler with an average particle size larger than the average particle size of the inorganic filler contained in the resin layers 33, 43 of the semiconductor dies 30, 40.

[0092] Next, after the encapsulant layer 23 is formed, the encapsulant layer is ground by CMP or the like to thin it into a ground encapsulant layer 23a as shown in FIG. 4(a). The encapsulant layers 23, 23a may have an elastic modulus (Young's modulus) of, for example, 3.0 GPa or more. The encapsulant layers 23, 23a may have a linear expansion coefficient of 5 ppm / K to 150 ppm / K, and the difference between the linear expansion coefficient of the encapsulant layers 23, 23a and the linear expansion coefficient of the resin layers 33, 43 is 100 ppm / K or less. This grinding process results in the semiconductor dies 30a, 40a having second ends 35b, 45b, which are the tips of the internal electrodes 35, 45, exposed outside the encapsulant layer 23a. This grinding process also exposes the second ends 22b of the multiple posts 22 outside the encapsulant layer 23a. The second ends 22b of the multiple posts 22 may be slightly ground.

[0093] Subsequently, after the encapsulant layer 23a is formed, as shown in FIG. 4B, a wiring layer 24 (first wiring layer) is formed on the encapsulant layer 23a. The wiring layer 24 may be, for example, a redistribution layer (RDL). The wiring layer 24 includes a wiring portion 24a and an insulating portion 24b covering the wiring portion 24a. The wiring portion 24a connects an external device to the semiconductor dies 50 and 55 described below. For example, the wiring portion 24a is connected to the second end 22b of each post 22 and the second end 35b, 45b of the internal electrodes 35, 45 of the semiconductor dies 30a and 40a. The wiring portion 24a may include, for example, a copper pillar. The wiring layer 24 including the wiring portion 24a can be fabricated using a known method. Note that, in this fabrication method, the posts 22 and the semiconductor dies 30 and 40 are aligned with high precision, as described above, so the wiring portion 24a can be formed using mask exposure. In this case, the manufacturing efficiency of the wiring layer 24 can be significantly improved. Furthermore, the terminal on the opposite side (upper side in the figure) of the wiring portion 24a may be formed with a connection bump 25. The connection bump 25 may be, for example, a solder bump.

[0094] Subsequently, after the wiring layer 24 is formed, a carrier substrate 26 (second support) is provided on the wiring layer 24, as shown in FIG. 4(c). As a result, a structure including the sealing material layer 23a and the wiring layer 24 is sandwiched between the carrier substrate 20 and the carrier substrate 26. When providing the carrier substrate 26, a temporary fixing layer 27 may be provided on the wiring layer 24 side. The temporary fixing layer 27 may be the same as the temporary fixing layer 21. When the connection bumps 25 are formed, the temporary fixing layer 27 preferably has a thickness that protects the connection bumps 25.

[0095] Next, after the carrier substrate 26 is provided, the carrier substrate 20 is separated from the sealing material layer 23a as shown in (d) of Fig. 4. In this separation, the temporary fixing layer 21 is irradiated with laser light or subjected to heat treatment to reduce the adhesiveness of the temporary fixing layer 21, and the carrier substrate 20 is separated from the sealing material layer 23a by peeling.

[0096] Next, after the carrier substrate 20 is separated, the encapsulant layer 23a is ground by CMP or the like to further thin the encapsulant layer 23b after grinding, as shown in FIG. 5(a). This grinding is performed until the terminal electrodes 32, 42 provided in the resin layers 33, 43 of the semiconductor dies 30b, 40b are exposed. The thickness of the ground resin layers 33, 43 may be 20 μm or more. When grinding the encapsulant layer 23a including the resin layers 33, 43, the tips of the terminal electrodes 32, 42 and the tips of the posts 22 may also be ground. This grinding may be performed using a grinder or an etching process. A cleaning process is preferably performed after grinding.

[0097] Next, after the grinding of the encapsulant layer is completed and the terminal electrodes 32, 42 are exposed, as shown in FIG. 5B, a wiring layer 28 (second wiring layer) electrically connected to the terminal electrodes 32, 42 and the posts 22 is formed on the encapsulant layer 23b from which the resin layers 33, 43 have been ground. The wiring layer 28 may be, for example, a redistribution layer (RDL). The wiring layer 28 includes a wiring portion 28a and an insulating portion 28b covering the wiring portion 28a. The wiring portion 28a connects the posts 22 and the semiconductor dies 30b, 40b to the semiconductor dies 50, 55 described below. For example, the wiring portion 28a is connected to the first ends 22a of the posts 22 and the first ends 35a, 45a of the terminal electrodes 32, 42 and internal electrodes 35, 45 of the semiconductor dies 30b, 40b. The wiring portion 28a may include, for example, a copper pillar. The wiring layer 28, including the wiring portions 28a, can be fabricated by a known method, similar to the wiring layer 24. In this fabrication method, the posts 22 and the terminal electrodes 32, 42 of the semiconductor dies 30b, 40b are aligned with high precision, as described above, so the wiring layer 28 can be formed using mask exposure. This significantly improves the manufacturing efficiency of the wiring layer 28. The wiring pitch and width of the wiring portions 28a are preferably smaller than those of the wiring portions 24a. This allows for the connection of semiconductor dies 50, 55 with fine structures. The interposer P (wiring substrate) is fabricated in this manner. The connection points (first connection points) between the posts 22 and the wiring layer 24 and the connection points (second connection points) between the posts 22, the terminal electrodes 32, 42, and the wiring layer 28 are connected without soldering.

[0098] Next, after the wiring layer 28 is formed, as shown in FIG. 5C, semiconductor dies 50 and 55 (first and second semiconductor chips) are attached to a surface 28c (the bottom surface in the figure) of the wiring layer 28 opposite the encapsulant layer 23b. At this time, the terminal electrodes of the semiconductor dies 50 and 55 are connected to the tips of the wiring portions 28a of the wiring layer 28. This connection may be made via solder. The semiconductor dies 50 and 55 may be semiconductor chips such as LSI chips (logic chips), CMOS sensors, memory chips, etc., and may also be so-called active dies. The semiconductor dies 50 and 55 correspond to the semiconductor dies 3 and 2 shown in FIG. 1. Here, it is sufficient to attach one or more semiconductor chips, but it is preferable to attach two or more semiconductor chips. In this process, the semiconductor die 50 and the semiconductor die 55 are electrically connected to each other by the built-in semiconductor die 40b. The built-in semiconductor die 30b is connected to the semiconductor die 50. Each post 22 is similarly connected to semiconductor dies 50 and 55 via wiring layer 28 .

[0099] 6A, the semiconductor dies 50 and 55 are encapsulated on the wiring layer 28 with an encapsulant to form an encapsulant layer 29 (second encapsulant layer) on the wiring layer 28. The encapsulant layer 29, like the encapsulant layer 23, is made of a thermosetting resin such as an epoxy resin, and is hardened after encapsulation.

[0100] Next, after the semiconductor dies 50 and 55 are encapsulated with the encapsulant to form the encapsulant layer 29, the encapsulant layer 29 may be ground until the surfaces 50a and 55a of the semiconductor dies 50 and 55 are exposed from the surface of the encapsulant layer, as shown in Fig. 6(b), thereby thinning the encapsulant layer 29 to the encapsulant layer 29a shown in Fig. 6(b).

[0101] Subsequently, after grinding down to the sealing material layer 29a, as shown in FIG. 6(c), the temporary fixing layer 27 is irradiated with laser light or heated to reduce the adhesiveness of the temporary fixing layer 27, thereby peeling and separating the carrier substrate 26 from the wiring layer 24. This exposes the connection bumps 25 to the outside. In the above description, an example is shown in which the connection bumps 25 are fabricated by the process shown in FIG. 4(b), but this is not limiting, and the connection bumps 25 may be provided on the wiring layer 24 after the temporary fixing layer 27 is separated.

[0102] 6(c) and 1 is fabricated. Such a semiconductor device 1 is mounted on a substrate M. At this time, an underfill material is applied between the semiconductor device 1 and the substrate M. Thereafter, the underfill material is cured by thermal curing or the like, thereby fabricating the semiconductor device (structure S) shown in FIG.

[0103] As described above, in the method for manufacturing a semiconductor device according to the first embodiment, the semiconductor dies 30, 40 are attached to the carrier substrate 20 so that the first surfaces 31 a, 41 a on which the terminal electrodes 32, 42 are provided face toward the carrier substrate 20. That is, the semiconductor dies 30, 40 are attached face down. Therefore, when the semiconductor dies 30, 40 are bonded by suction using a collet or the like, it is not necessary to suction the terminal electrode side, and the attachment of the semiconductor dies 30, 40 can be ensured. Note that when picking up the semiconductor dies 30, 40 before bonding, the terminal electrode 32, 42 side may be temporarily sucked with a collet (and then the die is turned over for bonding). In this case, because the terminal electrodes 32, 42 are covered with the resin layers 33, 43, it is not necessary to suction the outer periphery with a collet, and the pickup of the semiconductor dies 30, 40 can be ensured.

[0104] Furthermore, in this semiconductor device manufacturing method, semiconductor dies 50 and 55 connected to semiconductor dies 30 and 40 can be attached at the end of the process (for example, after wiring layer 24 and wiring layer 28 are formed), so if a defect occurs during the manufacturing process, semiconductor dies 50 and 55, which are expensive active dies, can be left unattached, thereby reducing the overall manufacturing cost.

[0105] [Second embodiment] Next, a semiconductor device according to a second embodiment and a method for manufacturing the same will be described with reference to Figures 7 to 11. Explanations of points that overlap with the semiconductor device according to the first embodiment and a method for manufacturing the same will be omitted.

[0106] 7 is a diagram showing an example of a semiconductor device manufactured by the manufacturing method according to the second embodiment. As shown in FIG. 7, the semiconductor device 1A includes semiconductor dies 2 and 3, semiconductor dies 4 and 5, wiring layers 6 and 7, encapsulant layers 8 and 9, connection bumps 11, and underfills 12 and 13. The semiconductor device 1 is mounted on a substrate M. This semiconductor device 1A differs from the semiconductor device 1 according to the first embodiment in that it further includes a connection member 60 including a plurality of connection electrodes 10.

[0107] The connection member 60 includes a plurality of connection electrodes 10, a substrate 61 having the connection electrodes 10 provided therein, terminal electrodes 62 (another terminal electrodes) provided on the first surface side (upper side in the figure) of the substrate 61, and a resin layer 63 (another resin layer) provided on the first surface side (upper side in the figure) of the substrate 61 so as to cover the terminal electrodes 62. The connection member 60 may further include a fine wiring layer 64.

[0108] The substrate 61 is made of silicon or the like, similar to the semiconductor substrates of the semiconductor dies 4 and 5. The substrate 61 may be made of other materials (e.g., resin or the like). The connection electrodes 10 are through electrodes that penetrate the substrate 61, and their functions are similar to those of the first embodiment. In the semiconductor device 1A according to the second embodiment, the connection member 60 has a configuration similar to that of the semiconductor dies 4 and 5, and may have a fine wiring layer 64 between the resin layer 63 and the connection electrodes 10.

[0109] Next, an example of a method for manufacturing the semiconductor device 1A will be described with reference to Figures 8 to 11. Figures 8 to 11 are cross-sectional views sequentially showing a method for manufacturing the semiconductor device 1A described above.

[0110] In this method for manufacturing a semiconductor device, as shown in FIG. 8(a), a temporary fixing layer 21 is formed on a carrier substrate 20 (first support).

[0111] Next, as shown in FIG. 8B, a connection member 60 is prepared, in which multiple posts 22 are provided inside a substrate 61. The connection member 60 includes multiple posts 22, a substrate 61 having a first surface 61a and a second surface 61b opposite the first surface 61a, terminal electrodes 62 provided on the first surface 61a of the substrate 61, and a resin layer 63 provided on the first surface 61a of the substrate 61 so as to cover the terminal electrodes 62. In the connection member 60, the first ends 22a of the posts 22 are connected to the terminal electrodes 62, while the second ends 22b of the posts 22 are located within the substrate 61. The connection member 60 may further include a fine wiring layer 64 between the substrate 61 and the resin layer 63. The fine wiring layer 64 connects the posts 22 and the terminal electrodes 62. The resin layer 63 may be made of the same material as the resin layers 33 and 43 of the semiconductor dies 30 and 40. The fine wiring layer 64 has a configuration corresponding to the fine wiring layers 34 and 44.

[0112] Next, after preparation of the connection member 60 is completed, the connection member 60 is attached to the carrier substrate 20 so that the lower surface on which the terminal electrodes 62 are provided faces the carrier substrate 20. At this time, the entire upper surface (second surface 61b) of the connection member 60 is vacuum-adsorbed and bonded by a collet. The connection member 60 is moved to a predetermined position on the carrier substrate 20 by the vacuum-adsorbed collet and attached to the predetermined position on the carrier substrate 20 by a resin layer 63. During attachment, the terminal electrodes 62 of the connection member 60 are protected because they are covered by the resin layer 63. In addition, simultaneously with, before, or after the installation of the connection member 60, the semiconductor dies 30 and 40 are attached to the carrier substrate 20. The attachment method of the semiconductor dies 30 and 40 is the same as in the first embodiment. As a result, the state shown in FIG. 8(b) is achieved. In this process, the connection member 60 and the semiconductor dies 30 and 40 are arranged face-down, with the terminal electrodes facing downward.

[0113] After the attachment of the semiconductor dies 30, 40 and the connecting members 60 is completed, the resin layers 33, 43, 63 containing the curable resin composition are cured before the semiconductor dies 30, 40 and the connecting members 60 are encapsulated. The resin layers 33, 43, 63 are cured using heat and / or light. This fixes the semiconductor dies 30, 40 and the connecting members 60 to the carrier substrate 20.

[0114] 8(c), an encapsulant layer 23 is formed on the carrier substrate 20 to encapsulate the connecting member 60 including the plurality of posts 22 and the semiconductor dies 30 and 40 with an encapsulant. After encapsulation, the encapsulant layer 23 is cured by heat or the like. The resin layers 33, 43, and 63 may be further cured by this thermal curing.

[0115] Next, after the encapsulant layer 23 is formed, the encapsulant layer is ground by CMP or the like to thin it into the ground encapsulant layer 23a as shown in FIG. 8(d). This grinding process results in the semiconductor dies 30a, 40a having the second ends 35b, 45b of the internal electrodes 35, 45 exposed outside the encapsulant layer 23a. This grinding process also exposes the second ends 22b of the posts 22 outside the encapsulant layer 23a.

[0116] Subsequently, after the encapsulant layer 23a is formed, the wiring layer 24 is formed on the encapsulant layer 23a, as shown in (a) of Fig. 9. The wiring portions 24a of the wiring layer 24 connect an external device to the semiconductor dies 50 and 51, and are connected, for example, to the second ends 22b of the posts 22 and the second ends 35b and 45b, which are the tips of the internal electrodes 35 and 45 of the semiconductor dies 30a and 40a (see also (d) of Fig. 8). In addition, connection bumps 25 may be formed on the terminals on the opposite side (upper side in (a) of Fig. 9) of the wiring portions 24a.

[0117] Subsequently, after the wiring layer 24 is formed, as shown in (b) of Fig. 9, a carrier substrate 26 is provided on the wiring layer 24. When providing the carrier substrate 26, a temporary fixing layer 27 may be provided on the wiring layer 24 side. Thereafter, as shown in (c) of Fig. 9, the carrier substrate 20 is separated from the sealing material layer 23a.

[0118] Next, after the carrier substrate 20 is separated, the encapsulant layer 23a is ground by CMP or the like to further thin the encapsulant layer 23b after grinding, as shown in FIG. 10(a). This grinding is performed until the terminal electrodes 32, 42 provided in the resin layers 33, 43 of the semiconductor dies 30, 40 are exposed to the outside. Furthermore, grinding is performed until the terminal electrode 62 provided in the resin layer 63 of the connection member 60a is exposed to the outside. The thickness of the ground resin layers 33, 43, 63 may be 20 μm or more. When grinding the encapsulant layer 23a, the tips of the terminal electrodes 32, 42 and the tips of the posts 22 may also be ground.

[0119] 10(b), when grinding of the encapsulant layer is completed and the terminal electrodes 32, 42, 62 are exposed, the wiring layer 28 electrically connected to the terminal electrodes 32, 42, 62 is formed on the encapsulant layer 23b from which the resin layers 33, 43, 63 have been ground away. The wiring portions 28a of the wiring layer 28 connect the posts 22 and the semiconductor dies 30, 40 to the semiconductor dies 50, 55, and are connected, for example, to the first ends 22a of the posts 22 and the first ends 35a, 45a of the terminal electrodes 32, 42 and internal electrodes 35, 45 of the semiconductor dies 30, 40.

[0120] Subsequently, after the wiring layer 28 is formed, the semiconductor dies 50 and 55 are attached to a surface 28c (the bottom surface in the figure) of the wiring layer 28 opposite the encapsulant layer 23b, as shown in Figure 10(c). In this process, the semiconductor die 50 and the semiconductor die 55 are electrically connected to each other by the built-in semiconductor die 40b. The built-in semiconductor die 30b is connected to the semiconductor die 50. Each post 22 is similarly connected to the semiconductor dies 50 and 55 via the wiring layer 28.

[0121] Next, after the semiconductor dies 50 and 55 are mounted, as shown in FIG. 11A, the semiconductor dies 50 and 55 are encapsulated on the wiring layer 28 with an encapsulant to form an encapsulant layer 29 on the wiring layer 28. The encapsulant layer 29 is hardened after encapsulation. Thereafter, as shown in FIG. 11B, grinding may be performed until the surfaces of the semiconductor dies 50 and 55 are exposed from the surface of the encapsulant layer. As a result, the encapsulant layer 29 is thinned to an encapsulant layer 29a shown in FIG. 11B.

[0122] Next, after the sealing material layer 29a is ground, as shown in FIG. 11(c), the temporary fixing layer 27 is irradiated with laser light or heated to reduce the adhesiveness of the temporary fixing layer 27, thereby peeling and separating the carrier substrate 26 from the wiring layer 24. This exposes the connection bumps 25 to the outside. In this manner, the semiconductor device 1A shown in FIG. 11(c) and FIG. 7 is fabricated. Such a semiconductor device 1A is mounted on a substrate M. At this time, an underfill material is applied between the semiconductor device 1 and the substrate M. Thereafter, the underfill material is hardened by thermal curing or the like, thereby fabricating the semiconductor device shown in FIG. 7.

[0123] As described above, in the method for manufacturing a semiconductor device according to the second embodiment, similarly to the first embodiment, the semiconductor dies 30, 40 are attached to the carrier substrate 20 so that the first surfaces 31 a, 41 a on which the terminal electrodes 32, 42 are provided face toward the carrier substrate 20. That is, the semiconductor dies 30, 40 are attached face down. This ensures reliable attachment of the semiconductor dies 30, 40. Also, in this method, the connection member 60 is attached to the carrier substrate 20 so that the first surface 61 a on which the terminal electrodes 62 are provided faces toward the carrier substrate 20. That is, the connection member 60 is attached face down. This ensures reliable attachment of the connection member 60.

[0124] Furthermore, in this semiconductor device manufacturing method, similar to the first embodiment, the semiconductor dies 50 and 55 connected to the semiconductor dies 30 and 40 can be attached at the end of the process, so that if a defect occurs during the manufacturing process, the expensive active semiconductor dies 50 and 55 can be left unattached, thereby reducing the overall manufacturing cost.

[0125] Furthermore, in this method of manufacturing a semiconductor device, rather than forming the posts 22 individually on the carrier substrate 20, a connection member 60 including a plurality of posts 22 is formed in advance, and the posts 22 are provided by attaching the connection member 60 to the carrier substrate 20. This simplifies the formation of the posts 22. Furthermore, by forming the connection member 60 with the same structure and material as the semiconductor dies 30, 40 (excluding the circuits within the semiconductor dies), the process of picking up and attaching the semiconductor dies 30, 40 and the connection member 60 can be simplified, significantly improving manufacturing efficiency.

[0126] Although the embodiments of the present disclosure have been described above, the present invention is not limited to the above-described embodiments, and appropriate modifications may be made without departing from the spirit of the present invention. [Explanation of symbols]

[0127] 1, 1A... semiconductor device, 2, 3, 50, 55... semiconductor die (first semiconductor chip, second semiconductor chip), 4, 5, 30, 40... semiconductor die (semiconductor member), 4a, 5a, 32, 42... terminal electrode, 6, 24... wiring layer (first wiring layer), 7, 28... wiring layer (second wiring layer), 8, 23, 23a, 23b... encapsulant layer (first encapsulant layer), 9, 29, 29a... encapsulant layer (second encapsulant layer), 10... connection electrode, 11... connection bump, 20... carrier substrate (first support), 22... post, 22a... first end, 22b... second end, 23, 23a, 23b... encapsulant layer (first encapsulant layer), 24... wiring layer (first wiring layer), 25...connection bump, 26...carrier substrate (second support), 28...wiring layer (second wiring layer), 29, 29a...encapsulant layer (second encapsulant layer), 30, 30a, 30b, 40, 40a, 40b...semiconductor die (semiconductor member), 31, 41...semiconductor substrate, 31a, 41a...first surface, 31b, 41b...second surface, 32, 42...terminal electrode, 33, 43...resin layer, 34, 44...fine wiring layer, 35, 45...internal electrode, 35a, 45a...first end, 35b, 45b...second end, 50, 55...semiconductor die (semiconductor chip), 60, 60a...connection member, 61...substrate, 62...terminal electrode, 63...resin layer, 64...fine wiring layer.

Claims

1. providing a conductive pillar-shaped member on a first support, the pillar-shaped member having a first end and a second end opposite the first end, the first end being located on the first support side; a step of attaching a semiconductor member including a semiconductor substrate having a first surface and an opposite second surface, terminal electrodes provided on the first surface side of the semiconductor substrate, and a resin layer provided on the first surface side so as to cover the terminal electrodes, to the first support so that the first surface faces the first support; forming a first encapsulant layer on the first support body to encapsulate the columnar members and the semiconductor member; forming a first wiring layer electrically connected to at least the pillar-shaped member on the first sealing material layer; separating the first support from the first encapsulant layer; grinding at least the resin layer so that the tip of the terminal electrode is exposed; forming a second wiring layer electrically connected to at least one of the terminal electrodes and the columnar members on the first sealing material layer where the terminal electrodes are exposed; A method for manufacturing a semiconductor device, comprising:

2. The resin layer when the semiconductor member is attached to the first support is a semi-cured or uncured curable resin composition. The method for manufacturing a semiconductor device according to claim 1 .

3. The resin layer has a transmittance of 30% or more for visible light. The method for manufacturing a semiconductor device according to claim 1 or 2.

4. In the step of attaching the semiconductor member, the positions of the terminal electrodes are determined through the resin layer, and the semiconductor member is attached to a predetermined position of the first support based on the result of the determination. The method for manufacturing a semiconductor device according to claim 1 or 2.

5. The resin layer contains an inorganic filler. The method for manufacturing a semiconductor device according to claim 1 or 2.

6. The content of the inorganic filler is 30 mass% or more based on the total amount of solids contained in the resin layer. The method for manufacturing a semiconductor device according to claim 5 .

7. The average particle size of the inorganic filler is 20 μm or less. The method for manufacturing a semiconductor device according to claim 5 .

8. The elastic modulus of the resin layer at 25°C when cured is 10 MPa or more. The method for manufacturing a semiconductor device according to claim 1 or 2.

9. The resin layer is formed by laminating a non-conductive adhesive film (NCF) or a die attach film (DAF). The method for manufacturing a semiconductor device according to claim 1 or 2.

10. the thickness of the resin layer is between 100% and 150% of the height of the terminal electrode; The method for manufacturing a semiconductor device according to claim 1 or 2.

11. The resin layer is formed by laminating a resin film, The thickness of the resin film before bonding is between 75% and 150% of the height of the terminal electrode. The method for manufacturing a semiconductor device according to claim 1 or 2.

12. the method further includes a step of grinding the first sealing material layer after forming the first sealing material layer and before forming the first wiring layer so that the second ends of the columnar members are exposed. The method for manufacturing a semiconductor device according to claim 1 or 2.

13. The method further includes providing a second support on the first wiring layer after forming the first wiring layer, separating the first support from the first encapsulant layer after providing the second support; The method for manufacturing a semiconductor device according to claim 1 or 2.

14. a step of providing a connection bump on a surface of the first wiring layer opposite to the first sealing material layer, the step of providing the connection bumps is performed before providing the second support on the first wiring layer or after separating the second support from the first wiring layer. The method for manufacturing a semiconductor device according to claim 13.

15. The semiconductor member has a fine wiring layer between the first surface of the semiconductor substrate and the terminal electrode. The method for manufacturing a semiconductor device according to claim 1 or 2.

16. The semiconductor member has an internal electrode extending in a thickness direction of the semiconductor substrate, a first end of the internal electrode is connected to the second wiring layer via the terminal electrode; a second end of the internal electrode connected to the first wiring layer; The method for manufacturing a semiconductor device according to claim 1 or 2.

17. further comprising a step of attaching at least one semiconductor chip to a surface of the second wiring layer opposite to the first sealing material layer. The method for manufacturing a semiconductor device according to claim 1 or 2.

18. In the step of attaching the semiconductor chip, a first semiconductor chip and a second semiconductor chip are attached to the second wiring layer as the at least one semiconductor chip; The first semiconductor chip and the second semiconductor chip are electrically connected by the semiconductor member. The method for manufacturing a semiconductor device according to claim 17.

19. 18. The method for manufacturing a semiconductor device according to claim 17, further comprising the step of forming a second encapsulant layer that encapsulates the at least one semiconductor chip.

20. At least one of a first connection point between the columnar member and the first wiring layer and a second connection point between the columnar member and the second wiring layer is connected without solder. The method for manufacturing a semiconductor device according to claim 1 or 2.

21. the columnar member is provided in a substrate having a first surface and an opposite second surface; In the step of providing the columnar member, a connection member including the columnar member, the substrate, another terminal electrode provided on the first surface side of the substrate, and another resin layer provided on the first surface side of the substrate so as to cover the another terminal electrode is attached to the first support so that the first surface faces the first support, thereby providing the columnar member on the first support. The method for manufacturing a semiconductor device according to claim 1 or 2.

22. In the step of forming the first sealing material layer, the connecting member is sealed together with the semiconductor member, In the grinding step, the resin layer and the another resin layer are ground so that the terminal electrode and the another terminal electrode are exposed, In the step of forming the second wiring layer, the second wiring layer is formed so as to be electrically connected to the terminal electrode and the another terminal electrode. The method for manufacturing a semiconductor device according to claim 21.

23. the method further includes a step of grinding a part of the semiconductor substrate and a part of the substrate together with the first sealing material layer after forming the first sealing material layer and before forming the first wiring layer so that the second ends of the columnar members are exposed. The method for manufacturing a semiconductor device according to claim 21.

24. a semiconductor member including a semiconductor substrate having a first surface and an opposite second surface, a terminal electrode provided on the first surface side of the semiconductor substrate, and a resin layer provided on the first surface side so as to expose a tip of the terminal electrode and cover other portions of the terminal electrode; a conductive columnar member having a first end and a second end opposite to the first end, the columnar member being adjacent to the semiconductor member; a first sealing material layer that seals the semiconductor member and the columnar member; a first wiring layer provided on the first sealing material layer and electrically connected to at least the columnar member; a second wiring layer provided on a surface of the first sealing material layer opposite to the first wiring layer and electrically connected to at least one of the terminal electrode and the columnar member; A wiring substrate used in manufacturing a semiconductor device, comprising:

25. Providing a wiring substrate according to claim 24; and attaching a first semiconductor chip and a second semiconductor chip onto the second wiring layer of the wiring substrate, A method for manufacturing a semiconductor device, wherein in the attaching step, the first semiconductor chip is electrically connected to the second semiconductor chip by the semiconductor member.

26. the first semiconductor chip includes a logic chip; the second semiconductor chip includes a memory chip; The method for manufacturing a semiconductor device according to claim 25.

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