Display device

Abstract

To provide a semiconductor device including a circuit that deteriorates less.SOLUTION: A semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch. The first transistor has a first terminal thereof connected to a first wire, and a second terminal thereof connected to a second wire. The second transistor has a gate and a first terminal thereof connected to the first wire, and a second terminal thereof connected to a gate of the first transistor. The first switch is connected between the second wire and a third wire. The second switch is connected between the second wire and the third wire. The third switch is connected between the gate of the first transistor and the third wire.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a driving method thereof. [Background technology]

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as LCD TVs. In particular, transistors made of non-single-crystal semiconductors are used to form a pixel portion. The technology of configuring drive circuits such as gate drivers on the board reduces manufacturing costs and improves reliability. It is being actively developed to make a significant contribution to

[0003] However, transistors using non-single-crystal semiconductors are subject to degradation. In particular, in the gate driver, A transistor ( This degradation is particularly noticeable in the gate signal When the line is not selected, the pull-down transistor turns on, This is because a negative voltage is supplied to the gate signal line. In other words, the gate signal line is not selected. Therefore, the pull-down transistor is on for most of the frame period. do.

[0004] To solve this problem, Patent Document 1 describes a method for suppressing the deterioration of a pull-down transistor. Patent Document 1 discloses a gate driver capable of In order to suppress the deterioration, a circuit capable of outputting a pulse (for example, FIG. 7 of Patent Document 1) A holding control unit 350 is provided for each stage of the gate driver. Thus, the conduction state of the pull-down transistor is controlled using the output signal of the circuit. The circuit outputs a pulse in synchronization with a clock signal, etc. This reduces the time the pull-down transistor is on, thereby suppressing deterioration of the pull-down transistor. However, the circuit that can output the above pulses has a 1-frame This includes transistor Q32, which is on for most of the period. Q32 deteriorates. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-50502 Summary of the Invention [Problem to be solved by the invention]

[0006] One embodiment of the present invention is a semiconductor device including first and second transistors and first, second, and third switches. In a semiconductor device, deterioration of first and second transistors and first to third switches is suppressed. Alternatively, in a semiconductor device having the first to fifth transistors, The semiconductor device further includes a sixth transistor. In this case, the deterioration of the first to sixth transistors is suppressed. In a semiconductor device having a transistor, deterioration of first to seventh transistors is suppressed. [Means for solving the problem]

[0007] One aspect of the present invention is a semiconductor device including a first transistor, a second transistor, a first switch, a second a first terminal of the first transistor is connected to a first wiring; The second terminal is connected to the second wiring, and the gate and the first terminal of the second transistor are connected to the second wiring. The first terminal is connected to the first wiring, the second terminal is connected to the gate of the first transistor, and the first The switch is connected between the second wiring and the third wiring, and the second switch is connected between the second wiring and the The third switch is connected between the gate of the first transistor and the third wiring. It is a semiconductor device connected between the line.

[0008] In the above aspect, the first period and the second period are included, and in the first period, the first switch The switch, the second switch, and the third switch are turned off, and the potential of the first wiring becomes H level. In the second period, the first switch is turned off, and the second switch and the third switch are turned on. The switch may be turned on, and the potential of the first wiring may become L level.

[0009] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, and a third transistor. a fourth transistor and a fifth transistor, and the first terminal of the first transistor is connected to the The first terminal is connected to the first wiring, the second terminal is connected to the second wiring, and the gate of the second transistor The first terminal is connected to the first wiring, and the second terminal is connected to the gate of the first transistor. The gate of the third transistor is connected to the fourth wiring, and the first terminal is connected to the third wiring. The second terminal of the fourth transistor is connected to the second wiring, and the gate of the fourth transistor is connected to the fifth wiring. The first terminal is connected to the third wiring, and the second terminal is connected to the second wiring. The gate of the fifth transistor is connected to the fifth wiring, and the first terminal is connected to the third wiring. The first terminal of the semiconductor device is connected to the gate of the first transistor, and the second terminal of the semiconductor device is connected to the gate of the first transistor.

[0010] In the above embodiment, the channel width of the fifth transistor is equal to the channel width of the second transistor. and the channel width of the second transistor is greater than the channel width of the first transistor. It may also be large.

[0011] In the above embodiment, a sixth transistor is provided, and the gate of the sixth transistor is connected to the second transistor. The first terminal is connected to the third wire, and the second terminal is connected to the sixth wire. It may be possible.

[0012] In the above embodiment, there are periods A and B, and in period A, the potential of the first wiring is set to the H level. The potential of the fifth wiring and the potential of the fourth wiring become L level, and the first transistor The first transistor, the second transistor and the sixth transistor are turned on, and the third transistor, The fourth transistor and the fifth transistor are turned off, and the potential of the sixth wiring is at the L level. During period B, the potential of the first wiring becomes L level, and the potential of the fifth wiring becomes H level. The potential of the fourth wiring becomes L level, and the first transistor, the second transistor, The first, third and sixth transistors are turned off, and the fourth and sixth transistors are turned on. The second and fifth transistors may be turned on, and the potential of the sixth wiring may become L level.

[0013] In the above embodiment, a seventh transistor is provided, and the gate of the seventh transistor is connected to the fourth transistor. The first terminal is connected to the first wiring, and the second terminal is connected to the sixth wiring. That's fine.

[0014] In the above embodiment, there are periods A, B, C, D, and E, and in period A The potential of the first wiring becomes H level, and the potential of the fifth wiring and the potential of the fourth wiring become L level. The first transistor, the second transistor and the sixth transistor are turned on. The third transistor, the fourth transistor, the fifth transistor and the seventh transistor The first line is turned off, the potential of the sixth line is set to L level, and in period B, The potential of the fifth wire becomes L level, the potential of the fourth wire becomes H level, and the potential of the fourth wire becomes L level. The first transistor, the second transistor, the third transistor and the sixth transistor The first transistor is turned off, the fourth transistor and the fifth transistor are turned on, and the third transistor is turned on. The potential of the wiring 6 becomes L level, and in period C, the potential of the first wiring becomes L level. The potential of the fifth wiring and the potential of the fourth wiring become H level, and the first transistor, the second transistor, The first and sixth transistors are turned off, and the third and fourth transistors are turned on. The fifth transistor, the seventh transistor, and the sixth wiring are turned on. becomes L level, and in period D, the potential of the first wiring becomes H level, and the potential of the fifth wiring The potential of the fourth wiring becomes L level, the potential of the first transistor, the second transistor, The first, third and seventh transistors are turned on, and the fourth transistor The fifth transistor, the sixth transistor, and the sixth transistor are turned off, and the potential of the sixth wiring becomes H level, and in period E, the potential of the first wiring becomes L level, and the potential of the fifth wiring The potential of the fourth wiring becomes H level, the potential of the first transistor, the second transistor, The first transistor, the third transistor, the sixth transistor and the seventh transistor are ON. The fourth transistor and the fifth transistor are turned on, and the potential of the sixth wiring may be at L level.

[0015] In each of the above aspects of the present invention, various types of switches can be used. The switch can be an electrical switch or a mechanical switch. In other words, the switch is not limited to any specific type as long as it can control the current. The electrical switch may be a transistor (e.g., bipolar transistor, MOS transistor, transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, -Diode, MIM (Metal Insulator Metal) diode, M IS (Metal Insulator Semiconductor) diode, These include mechanical circuits, which are connected in series with a diode, or logic circuits that combine these. As a switch, MEMS (Micro Electro Mechanical Systems) such as Digital Micromirror Device (DMD) There is a switch that uses Microelectromechanical System (MICS) technology. The switch has a mechanically movable electrode, and the movement of the electrode causes conduction and It operates by controlling conduction and non-conduction.

[0016] When a transistor is used as a switch, the transistor is treated as a simple switch. However, the polarity (conductivity type) of the transistor is not particularly limited. When it is desired to suppress the current, it is desirable to use a transistor having a polarity with a smaller off-state current. The transistor with a low off-state current is a transistor with an LDD region or a multi-gate structure. There are transistors with different structures.

[0017] In each of the above aspects of the present invention, a transistor is used as a switch, and the transistor The transistor operates when the source potential is close to the potential of the low-potential power supply (Vss, GND, 0V, etc.). In this case, it is desirable to use an N-channel transistor as the switch. The transistor operates with the source potential close to the potential of the high-potential power supply (Vdd, etc.). In this case, it is desirable to use a P-channel transistor as the switch. In the case of an N-channel transistor, when the source operates at a potential close to the low-potential power supply, In the case of a P-channel transistor, when the source operates at a potential close to the high-potential power supply, , the absolute value of the voltage between the gate and source can be increased. This is because a more accurate operation can be achieved by using a transistor as a source. Since follower operation is rare, the output voltage is small. This is because there are few.

[0018] In each of the above aspects of the present invention, the switch may be an N-channel transistor and a P A CMOS type switch may be used by using both a CM type transistor and a CM type transistor. When it is made into an OS type switch, the P-channel transistor and the N-channel transistor If either one is conductive, current will flow, making it easier to function as a switch. This allows the switch to output an appropriate voltage regardless of whether the input signal voltage is high or low. Alternatively, the voltage amplitude of the signal for turning the switch on or off can be reduced. Therefore, the power consumption can be reduced.

[0019] When a transistor is used as a switch, the switch is connected to the input terminal (source or One of the drain terminals), the output terminal (the other of the source or drain), and the terminal that controls conduction On the other hand, when a diode is used as a switch, A switch may not have a terminal that controls conduction. However, using a diode as a switch reduces the amount of wiring required to control the terminal. can be done.

[0020] In the invention disclosed in this specification, transistors of various structures are used as transistors. In other words, there is no limitation on the configuration of the transistors used.

[0021] In this specification, a semiconductor device refers to a semiconductor element (transistor, diode, silicon, etc.). However, it refers to a device that has a circuit containing semiconductors. Any device that can be manufactured using semiconductor materials or any device that has semiconductor materials may be called a semiconductor device. In this specification, a display device refers to a device having a display element.

[0022] In this specification, a driving device refers to a device that has semiconductor elements, electric circuits, and electronic circuits. For example, a transistor (selection transistor) that controls the input of a signal from a source signal line to a pixel (sometimes called a driving transistor, switching transistor, etc.) a transistor for supplying a voltage or current to a light-emitting element, etc. is an example of a driving device. Furthermore, a circuit for supplying a signal to the gate signal line (gate driver the source signal line, and the circuit that supplies the signal to the source signal line (sometimes called a gate driver circuit, gate line driver circuit, etc.). A drive device is an example of a drive device.

[0023] Also, the present invention relates to a display device, a semiconductor device, a lighting device, a cooling device, a light-emitting device, a reflecting device, and a driving device. It is possible to combine the above devices with each other, and such devices are also included in the scope of the present invention. For example, a display device may include a semiconductor device and a light-emitting device. The device may have a display device and a driver.

[0024] In each aspect of the present invention, all of the circuits required to realize a predetermined function are a substrate (e.g., a glass substrate, a plastic substrate, a single crystal substrate, an SOI substrate, etc.) This allows for cost reduction by reducing the number of components, or for the circuit section to be formed. This reduces the number of connection points with the product, thereby improving reliability.

[0025] In addition, it is possible to avoid forming all of the circuits required to realize a given function on the same substrate. In other words, part of the circuitry required to achieve a given function is formed on a certain substrate. Another part of the circuitry required to achieve a given function is formed on a different substrate. For example, some of the circuits required to realize a specific function can be made of glass. Another part of the circuitry required to realize a given function is formed on the single crystal substrate. (or SOI substrate). The single crystal substrate (also called IC chip) on which another part of the circuit required for the semiconductor device is formed is called COG ( By using the IC chip on glass, the IC is connected to the glass substrate. It is possible to place the chip on the board. Alternatively, the IC chip can be mounted on the board using TAB (Tape Auto) technology. omated Bonding), COF(Chip On Film), SMT(Su Surface Mount Technology) or a printed circuit board, etc. It is possible to connect to the substrate.

[0026] In this specification, when it is explicitly stated that X and Y are connected, it means that X and Y are When X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are This includes cases where the device is directly connected. , elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Connection relationships, for example, are not limited to those shown in the drawings or text, but include connections shown in the drawings or text. This also includes connections other than those mentioned above.

[0027] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more electrodes (e.g., diodes) can be connected between X and Y.

[0028] An example of a functional connection between X and Y is a function that allows the functional connection between X and Y. Circuits (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (voltage boost circuit, voltage drop circuit, etc.), level shifter circuit that changes the potential level of the signal, voltage source , current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, etc., operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits One or more circuits (e.g., circuits, control circuits) can be connected between X and Y. Even if there is another circuit between X and Y, the signal output from X will be transmitted to Y. If X and Y are functionally connected, then X and Y are functionally connected.

[0029] In this specification, anything explicitly stated as singular is singular. However, even in this case, multiple instances are possible. It is preferable that numbers be plural. But it can also be singular.

[0030] In the figures of the present application, sizes, layer thicknesses, or areas may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The figure is a schematic representation of an ideal example. The figures are only for illustrative purposes and are not limited to the shapes or values ​​shown in the figures. For example, the shapes may vary depending on the manufacturing technology. Variation in shape due to variations, errors, and variations in signal, voltage, or current due to noise or may include variations in signal, voltage, or current due to timing differences. It is possible.

[0031] Note that technical terms are often used to describe specific embodiments or examples. However, one aspect of the present invention should not be construed as being limited by technical terms.

[0032] In addition, undefined terms (including technical terms such as technical or academic terms) are usually It can be used as a meaning equivalent to the general meaning understood by a person skilled in the art. Such defined language shall be construed in a manner consistent with the background of the relevant art. preferable.

[0033] The terms "first," "second," "third," etc. refer to various elements, members, areas, layers, regions, etc. Therefore, the terms "first," "second," "third," etc. are used to distinguish between elements, members, etc. The order and number of regions, layers, areas, etc. are not limited. "The" can be replaced with "the second" or "the third", etc.

[0034] Also, "up," "upward," "downward," "downward," "sideways," "right," "left," Spatial arrangement such as "diagonally," "in the back," "in front," "inside," "outside," or "inside" The phrase "show" simply illustrates the relationship of one element or feature to another element or feature by means of a diagram. However, it is not limited to this usage and is also used to indicate these spatial arrangements. The phrase may include directions in addition to those depicted on the diagram. For example, Y above X is clearly When shown illustratively, Y is not limited to being above X. The configurations shown may be inverted or It is possible to rotate 180 degrees, so that Y is below X. Thus, the phrase "on" includes the direction of "on" as well as the direction of "under." However, the device in the figure can be rotated in various directions. Therefore, the word "on" can be used to refer to the directions "above" and "below," as well as "sideways." "," "to the right," "to the left," "diagonally," "to the back," "to the front," "inside," "outside," or can include other directions such as "inside"; in other words, interpret it appropriately depending on the situation. It is possible.

[0035] Note that we cannot explicitly say that Y is formed on X, or that Y is formed on X. When describing it, it is not limited to forming Y on X in direct contact with it. This also includes cases where X and Y are not connected, that is, where another object is present between X and Y. Here, X and Y represent the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.).

[0036] Therefore, for example, it is explicitly stated that layer Y is formed on (or on) layer X. In the case of a layer mounted on a substrate, there are two cases: one in which layer Y is formed directly on top of layer X, and the other in which layer Y is formed directly on top of layer X. Another layer (such as layer Z) is formed adjacent to it, and layer Y is formed directly on top of it. The other layer (for example, layer Z) may be a single layer or a multiple layer. It may be a layer.

[0037] Furthermore, the same applies when it is explicitly stated that Y is formed above X. It is not limited to Y being directly on top of X, and there may be another object between X and Y. For example, if a layer Y is formed above a layer X, In this case, layer Y is formed directly on layer X, and layer Y is formed directly on layer X. When another layer (such as layer Z) is formed and layer Y is formed directly on top of it, The other layer (for example, layer Z) may be a single layer or a multi-layer. stomach.

[0038] In addition, Y is formed on X, Y is formed on X, or Y is formed above X. When explicitly stating that "Y is formed diagonally above X," this also includes the case where Y is formed diagonally above X. do.

[0039] The same applies to the description of "Y below X" or "Y below X."

[0040] One aspect of the present invention is a semiconductor device including a first transistor, a second transistor, a first switch, a second The first terminal of the first transistor is connected to a first switch and a third switch. The second terminal of the first transistor is connected to the line, and the second terminal of the first transistor is connected to the second wiring. The first terminal of the transistor is connected to the first wiring, and the second terminal of the second transistor is , the gate of the first transistor is connected to the first wiring, and the gate of the second transistor is connected to the first wiring. The first switch is connected between the second wiring and the third wiring. The switch is connected between the second wiring and the third wiring. The third switch is connected to the first It is connected between the gate of the transistor and the third wiring.

[0041] Note that one embodiment of the present invention can have a first period and a second period. During this period, the first to third switches can be turned off. In the second period, the potential of the line can be at the H level. The first wiring is turned off, and the second and third switches are turned on. The potential can be at the L level. [Effects of the Invention]

[0042] One aspect of the present invention is a semiconductor device having first and second transistors and first and third switches. In this device, the time when the first and second transistors and the first and third switches are turned on is shortened. Or, the number of times it is turned on can be reduced, so deterioration can be suppressed. In a semiconductor device having five transistors, the first to fifth transistors are turned on. The time or the number of times it is turned on can be shortened, so deterioration can be suppressed. In a semiconductor device further having a sixth transistor, the first to sixth transistors are Deterioration can be suppressed by shortening the time when the device is turned on or by reducing the number of times it is turned on. Alternatively, in a semiconductor device further having a seventh transistor, the first to seventh transistors The time that the transistor is turned on can be shortened or the number of times that it is turned on can be reduced, thereby suppressing deterioration. It is possible. [Brief explanation of the drawings]

[0043] [Figure 1] 1A and 1B are a circuit diagram of a semiconductor device according to a first embodiment, a logic circuit thereof, a logical expression thereof, and a truth table thereof; [Figure 2] 3A to 3C are schematic diagrams illustrating the operation of the semiconductor device according to the first embodiment. [Figure 3] 3A to 3C are schematic diagrams illustrating the operation of the semiconductor device according to the first embodiment. [Figure 4] 3A to 3C are schematic diagrams illustrating the operation of the semiconductor device according to the first embodiment. [Figure 5] FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Figure 6] FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Figure 7] FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Figure 8] FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Figure 9] FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Figure 10] FIG. 10 is a circuit diagram of a semiconductor device according to a second embodiment. [Figure 11] FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Figure 12] FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Figure 13] 1A and 1B are a circuit diagram of a semiconductor device according to a first embodiment, a logic circuit thereof, a logical expression thereof, and a truth table thereof; [Figure 14] 10A and 10B are circuit diagrams of a semiconductor device according to a second embodiment and schematic diagrams for explaining the operation thereof; [Figure 15] 10 is a timing chart for explaining the operation of the semiconductor device in the second embodiment. [Figure 16] 10A and 10B are circuit diagrams of a semiconductor device according to a second embodiment and schematic diagrams for explaining the operation thereof; [Figure 17] 10A and 10B are a circuit diagram and a timing chart for explaining the operation of a semiconductor device according to a second embodiment of the present invention; [Figure 18] 5A to 5C are schematic diagrams illustrating the operation of the semiconductor device according to the second embodiment. [Figure 19] 5A to 5C are schematic diagrams illustrating the operation of the semiconductor device according to the second embodiment. [Figure 20] 10A and 10B are circuit diagrams of a semiconductor device according to a second embodiment and schematic diagrams for explaining the operation thereof; [Figure 21] 10A and 10B are a circuit diagram and a timing chart for explaining the operation of a semiconductor device according to a second embodiment of the present invention; [Figure 22] 5A to 5C are schematic diagrams illustrating the operation of the semiconductor device according to the second embodiment. [Figure 23] 10A and 10B are circuit diagrams of a semiconductor device according to a second embodiment and schematic diagrams for explaining the operation thereof; [Figure 24] 5A to 5C are schematic diagrams illustrating the operation of the semiconductor device according to the second embodiment. [Figure 25] 10A and 10B are a circuit diagram and a timing chart for explaining the operation of a semiconductor device according to a second embodiment of the present invention; [Figure 26] 5A to 5C are schematic diagrams illustrating the operation of the semiconductor device according to the second embodiment. [Figure 27] FIG. 10 is a circuit diagram of a semiconductor device according to a second embodiment. [Figure 28] FIG. 10 is a circuit diagram of a semiconductor device according to a second embodiment. [Figure 29]FIG. 10 is a circuit diagram of a semiconductor device according to a second embodiment. [Figure 30] FIG. 10 is a circuit diagram of a semiconductor device according to a second embodiment. [Figure 31] 10A and 10B are a circuit diagram and a timing chart for explaining the operation of a semiconductor device according to a second embodiment of the present invention; [Figure 32] 10A and 10B are a circuit diagram and a timing chart for explaining the operation of a semiconductor device according to a second embodiment of the present invention; [Figure 33] 10A and 10B are a block diagram and a circuit diagram of a pixel of a display device according to Embodiment 3. [Figure 34] FIG. 11 is a circuit diagram of a shift register according to a third embodiment. [Figure 35] 10 is a timing chart illustrating the operation of the shift register according to the third embodiment. [Figure 36] 10A and 10B are a circuit diagram of a signal line driver circuit according to a fourth embodiment, a timing chart for explaining the operation of the signal line driver circuit, and a block diagram of a display device. [Figure 37] FIG. 13 is a circuit diagram of a protection circuit according to a fifth embodiment. [Figure 38] FIG. 13 is a circuit diagram of a protection circuit according to a fifth embodiment. [Figure 39] FIG. 20 is a cross-sectional view of a semiconductor device according to a sixth embodiment. [Figure 40] 13A and 13B are a top view and a cross-sectional view of a display device according to Embodiment 7. [Figure 41] 10A to 10C illustrate a manufacturing process of a transistor in Embodiment 8. [Figure 42] FIG. 20 is a layout diagram of a semiconductor device according to a ninth embodiment. [Figure 43] 13A to 13C illustrate electronic devices in Embodiment 10. [Figure 44] 13A to 13C illustrate electronic devices in Embodiment 10. [Figure 45] FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Figure 46] FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Figure 47] FIG. 10 is a circuit diagram of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0044] Hereinafter, embodiments will be described with reference to the drawings. The present invention can be implemented in various forms and in various ways without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications can be made to the embodiments. It should not be construed as being limited to the contents of the description. In the drawings, parts or parts having similar functions are indicated by the same reference numerals, and the same parts or parts having similar functions are indicated by the same reference numerals. A detailed description of parts having similar functions will be omitted.

[0045] (Embodiment 1) The configuration of this embodiment will be described with reference to FIG. 45(A). 1 shows a circuit diagram of a semiconductor device according to an embodiment;

[0046] The circuit 100 includes a transistor 101 (first transistor), a switch 102S (first switch), switch 103S (second switch), transistor 104 (second transistor and switch 105S (third switch).

[0047] The transistor 101 and the transistor 104 are N-channel transistors. In this type of transistor, the potential difference between the gate and source (Vgs) is equal to the threshold voltage (Vth). However, the transistor 101 and the transistor The transistor 104 can be a P-channel type. It turns on when the voltage difference (Vgs) between the terminal and source falls below the threshold voltage (Vth). .

[0048] The first terminal of the transistor 101 is connected to a wiring 112 (first wiring). The second terminal of the switch 101 is connected to the wiring 111 (second wiring). The switch 103S is connected between the wiring 111 and the wiring 115 (third wiring). The first terminal of the transistor 104 is connected between the line 111 and the wiring 115. The second terminal of the transistor 104 is connected to the gate of the transistor 101. The gate of the transistor 104 is connected to the wiring 112. The switch 105S is , is connected between the wiring 115 and the gate of the transistor 101.

[0049] The switches 102S, 103S, and 105S each have a control terminal. In FIG. 45(B), the control terminal of the switch 102S is connected to the wiring 114 (the The control terminal of the switch 103S is connected to the wiring 113 (the fifth wiring). 1 shows a configuration in which the control terminal of switch 105S is connected to wiring 113.

[0050] The switches 102S, 103S, and 105S are transistors. In FIG. 1(A), a transistor is used as a switch. The switches 102S, 103S, and 105S are each a transistor. a transistor 102 (third transistor), a transistor 103 (fourth transistor), An example in which a transistor 105 (fifth transistor) is used is shown. The first terminal of the transistor 102 is connected to the wiring 115, and the second terminal of the transistor 102 is connected to the wiring 11 1, and the gate of the transistor 102 is connected to a wiring 114. A first terminal of the transistor 103 is connected to a wiring 115, and a second terminal of the transistor 103 is connected to a wiring The gate of the transistor 103 is connected to a wiring 113. The first terminal of the transistor 105 is connected to the wiring 115, and the second terminal of the transistor 105 is connected to the wiring 115. is connected to the gate of the transistor 101, and the gate of the transistor 105 is connected to the wiring 11. It is connected to 3.

[0051] The transistors 102, 103, and 105 are transistors. The transistors 102 and 103 are N-channel type, the same as the transistor 101. , and the transistor 105 may be a P-channel type.

[0052] The connection point between the gate of the transistor 101 and the second terminal of the transistor 104, The node between the gate of the transistor 101 and the second terminal of the transistor 105 is called a node Shown as 11.

[0053] Next, examples of signals or voltages input to or output from the wirings 111 to 115 and This section explains the function of the wiring.

[0054] A signal OUT is output from the wiring 111.

[0055] A signal IN1 is input to the wiring 112. A signal IN2 is input to the wiring 113. The wiring 114 receives a signal IN3.

[0056] A voltage V1 is supplied to the wiring 115. The voltage V1 is a power supply voltage, a reference voltage, a ground voltage, and the like. The wiring 115 may be connected to a signal line, such as, but not limited to, a voltage, a ground, or a negative power supply voltage. (For example, a clock signal or an inverted clock signal) may be input.

[0057] When referring to an L-level signal, an L-signal, an L-level potential, or a voltage V1, these The potential is approximately V1. H level signal, H signal, H level potential, or voltage V2 When written as V2, V1, ... The error is caused by noise, process variations, and variations in the manufacturing process of the device. This includes various errors such as errors due to the nature of the measurement and / or measurement errors (the same applies below).

[0058] For example, if the gate of a transistor is connected to a certain node and the potential of that node is at the L level, When this happens, the transistor is turned off (or on). When the potential of the node becomes L level, the potential of the node turns off (or on) the transistor. Or, the potential of the node becomes the L level when The potential of the node is set to a value that allows a circuit including the transistor to perform a predetermined operation. The voltage (Vgs) between the gate and source of the transistor is reduced (or increased) to a certain extent. This means that the value becomes such that it is possible to

[0059] If clock signals are used as the signals IN1 to IN3, the clock signals can be balanced or non-equilibrium (also called disequilibrium) Equilibrium is when the period of H level and the period of L level are roughly equal in one cycle. Non-equilibrium means that the period when the signal is at the H level is different from the period when the signal is at the L level. say.

[0060] For example, a clock signal is used as the signal IN1, and a phase signal is derived from the signal IN1 as the signal IN2. Signals that are approximately 180° out of phase are used, and signals IN1 and IN2 are unbalanced. In this case, the signal IN2 may not be the inverted signal of the signal IN1.

[0061] As shown in FIG. 5A, the wirings 112 to 115 are used to transmit signals from the circuit 150. The circuit 150 generates a signal or a voltage and supplies the signal or voltage to the wirings 112 to 111. 5 to supply a signal or voltage.

[0062] The circuit 150 may include circuits 151 to 154. The circuit 151 receives a signal The circuit 152 has a function of generating a signal or a voltage and supplying the signal or the voltage to the wiring 112. The circuit 153 has a function of generating a signal or a voltage and supplying the signal or the voltage to the wiring 113. The circuit 1 has a function of generating a signal or a voltage and supplying the signal or the voltage to the wiring 114. The element 54 has a function of generating a signal or a voltage and supplying the signal or the voltage to the wiring 115 .

[0063] The circuits 150 to 154 are the amplifier circuit of FIG. 5(B) and the bipolar transistor circuit of FIG. 5(C), respectively. 5(D), the MOS transistor in Fig. 5(E), the capacitor in Fig. 5(F), the inverter in Fig. 5(F). 5(G), the DC voltage source of FIG. 5(H), and / or the DC voltage source of FIG. 5(I). Includes current sources, etc.

[0064] As shown in FIG. 5(A), a protection circuit 160 is connected to the wirings 112 to 114.

[0065] Next, the functions of the circuit 100 and the transistors 101 to 105 will be described.

[0066] The circuit 100 has a function of controlling the potential of the wiring 111. The potential of the wiring 112, the potential of the wiring 113, the potential of the wiring 114, or the potential of the wiring 115 is applied to the wiring 111. Alternatively, the circuit 100 may have a function of controlling the timing at which the signal is supplied to the wiring 111. The circuit 100 has a function of controlling the timing of supplying a signal or voltage. It has a function of controlling the timing of supplying the H signal or voltage V2 to the line 111. The circuit 100 has a function of controlling the timing of supplying the L signal or the voltage V1 to the wiring 111. Alternatively, the circuit 100 has a function of controlling the timing at which the potential of the wiring 111 is increased. Alternatively, the circuit 100 has a function of controlling the timing at which the potential of the wiring 111 is decreased. Alternatively, the circuit 100 has a function of controlling the timing at which the potential of the wiring 111 is maintained. As described above, the circuit 100 functions as a control circuit. It is not necessary for the circuit 100 to have all of the above functions. Controlled according to IN1 to IN3.

[0067] Note that the circuit 100 has a function as a logic circuit including AND as shown in FIG. Specifically, the circuit 100 is a logic circuit that combines a three-input AND and two NOTs. The first input terminal of the AND receives a signal IN1. The second input terminal of the AND receives the signal IN2 inverted by the first NOT. is input, and the third input terminal of the AND receives the signal IN3 inverted by the second NOT. A signal OUT is output from the AND output. , the function to realize the logical formula shown in FIG. 1(C) or the function to realize the truth table shown in FIG. 1(D) Possess the ability.

[0068] The transistor 101 has a function of controlling electrical continuity between the wiring 112 and the wiring 111 . Alternatively, the transistor 101 may be configured to supply the potential of the wiring 112 to the wiring 111 at a timing determined by the timing of the supply of the potential of the wiring 112. Alternatively, when a signal or voltage is input to the wiring 112, the transistor The timing controller 101 controls the timing of supplying the signal or voltage input to the wiring 112 to the wiring 111. Alternatively, the transistor 101 may supply an H signal or a voltage to the wiring 111. The transistor 101 has a function of controlling the timing of supplying V2. It has a function of controlling the timing of supplying the L signal or voltage V1 to the line 111. The transistor 101 has a function of controlling the timing at which the potential of the wiring 111 is increased. Alternatively, the transistor 101 controls the timing at which the potential of the wiring 111 is decreased. Alternatively, the transistor 101 may have a function of performing a bootstrap operation. Alternatively, the transistor 101 may be configured to supply the potential of the node 11 by a bootstrap operation. As described above, the transistor 101 functions as a switch or a barrier. The transistor 101 has all of the above functions. There is no need to.

[0069] The transistor 102 has a function of controlling electrical continuity between the wiring 115 and the wiring 111 . Alternatively, the transistor 102 may be configured to supply the potential of the wiring 115 to the wiring 111 at a timing determined by the timing of the supply of the potential of the wiring 115. Alternatively, when a signal or voltage is input to the wiring 115, the transistor The timing controller 102 controls the timing at which a signal or voltage input to the wiring 115 is supplied to the wiring 111. Alternatively, the transistor 102 may supply an L signal or a voltage to the wiring 111. The transistor 102 has a function of controlling the timing of supplying V1. The transistor 111 has a function of controlling the timing at which the potential of the transistor 111 is decreased. The transistor 102 functions as a switch. The transistor 102 does not need to have all of the functions. It can be controlled by the signal IN3.

[0070] The transistor 103 has a function of controlling electrical continuity between the wiring 115 and the wiring 111 . Alternatively, the transistor 103 may be configured to supply the potential of the wiring 115 to the wiring 111 at a timing determined by the timing of the supply of the potential of the wiring 115. Alternatively, when a signal or voltage is input to the wiring 115, The transistor 103 determines the timing at which a signal or voltage input to the wiring 115 is supplied to the wiring 111. Alternatively, the transistor 103 may be connected to the wiring 111 via an L signal or The transistor 103 has a function of controlling the timing of supplying the voltage V1. has a function of controlling the timing at which the potential of the wiring 111 is decreased. The transistor 103 functions as a switch. The transistor 103 does not necessarily have all of the above functions. It can be controlled by a position (signal IN2).

[0071] The transistor 104 has a function of controlling electrical continuity between the wiring 112 and the node 11 . Alternatively, the transistor 104 may be configured to supply the potential of the wiring 112 to the node 11 at a timing determined by the Alternatively, when a signal or voltage is input to the wiring 112, the transistor The timing controller 104 controls the timing of supplying the signal or voltage input to the wiring 112 to the node 11. Alternatively, the transistor 104 may apply an H signal or a voltage to the node 11. The transistor 104 has a function of controlling the timing of supplying V2. The transistor 11 has a function of controlling the timing at which the potential of the transistor 11 is increased. The transistor 104 has a function of making the node 11 floating. 4 has a function as a switch, a diode, or a diode-connected transistor, etc. It is not necessary for the transistor 104 to have all of the above functions. The transistor 104 receives the potential of the wiring 112 (signal IN1) and / or the potential of the node 11. It is possible to control the

[0072] The transistor 105 has a function of controlling electrical continuity between the wiring 115 and the node 11 . Alternatively, the transistor 105 may be configured to supply the potential of the wiring 115 to the node 11 at a timing determined by the Alternatively, when a signal or voltage is input to the wiring 115, the transistor The timing controller 105 controls the timing of supplying a signal or voltage input to the wiring 115 to the node 11. Alternatively, the transistor 105 may apply an L signal or a voltage to the node 11. The transistor 105 has a function of controlling the timing of supplying V1. The function of this circuit is to control the timing at which the potential of the transistor 11 is decreased. The transistor 105 functions as a switch. The transistor 105 does not need to have all of the functions. It can be controlled by the signal IN2.

[0073] Next, the operation of the circuit 100 will be explained with reference to the truth table (also referred to as an operation table) of FIG. FIG. 1D shows a truth table when the signals IN1 to IN3 are digital signals. Therefore, there are eight combinations of H and L levels of the signals IN1 to IN3. In other words, the circuit 100 can perform at least eight patterns of operation. Here, we will explain each of the eight patterns of operation.

[0074] The circuit 100 does not need to perform all of these eight patterns of operation, but can select some of them. It should be noted that the circuit 100 can perform operations other than these eight patterns. For example, if the signals IN1 to IN3 have three or more values, or When the signals IN1 to IN3 are analog signals, the circuit 100 can output signals in any pattern other than these eight patterns. However, many more actions can be performed.

[0075] First, operation 1 of the circuit 100 will be described with reference to FIG. This turns on the transistor 105, and the wiring 115 and the node 11 Since the potential of the wiring 115 (for example, voltage V1) is supplied to the node 11, At this time, the signal IN1 becomes H level, so the transistor 104 is turned on. Then, the wiring 112 and the node 11 are electrically connected, so that the potential of the wiring 112 (for example, H level) The signal IN1 of the line is supplied to the node 11. That is, the signal IN1 of the line is supplied to the node 11. A potential (for example, voltage V1) of the line 112 and a potential (for example, signal IN1 at H level) of the line 113 are supplied. Here, the channel width of the transistor 105 is larger than that of the transistor 104. Therefore, the potential of the node 11 becomes L level. The potential of Vth101 is greater than V1, and is V1+Vth101 (Vth101 is the potential of transistor 101). As a result, the transistor 101 is turned off, and The wiring 112 and the wiring 111 are brought into a non-conductive state.

[0076] Then, the signal IN2 goes to H level, and the transistor 103 turns on. Since the signal IN3 becomes H level, the transistor 102 is turned on. Since the wiring 115 and the wiring 111 are in a conductive state, the potential of the wiring 115 (for example, voltage V1) Therefore, the potential of the wiring 111 becomes V1, and the signal OUT becomes L level. It becomes a lu.

[0077] Note that "The channel width of transistor A is larger than the channel width of transistor B" is " 1 / W (W is the channel width) of transistor A is smaller than 1 / W of transistor B. "The L (L is the channel length) of transistor A is smaller than the L of transistor B," "1 / L of transistor A is greater than 1 / L of transistor B," "Transistor A The W / L of transistor A is greater than the W / L of transistor B, and the Vgs of transistor A (Vg s is the potential difference between the gate and source of transistor B, is greater than Vgs of transistor B. In other words, the transistor has a multi-gate structure, and the transistor When there are multiple gates, the number of gates of transistor A is equal to the number of gates of transistor B. "The reciprocal of the number of gates of transistor A is less than the number of gates of transistor B." This can be rephrased as "larger than the reciprocal of the number of gates in B."

[0078] Next, operation 2 of the circuit 100 will be described with reference to FIG. Compared to the previous example, the difference is that the signal IN3 becomes L level. However, transistor 102 is turned off. However, the transistor 103 is turned on as in operation 1. The wiring 111 is in a conductive state as in operation 1, so the wiring 111 receives the electric current of the wiring 115. Therefore, the potential of the wiring 111 becomes V1, and the signal OUT becomes L level.

[0079] Next, operation 3 of the circuit 100 will be described with reference to FIG. This turns off the transistor 105, and the wiring 115 and the node 11 At this time, the signal IN1 becomes H level, so the transistor 104 Then, the wiring 112 and the node 11 are brought into electrical continuity, and the A potential (for example, a signal IN1 at a high level) is supplied to the node 11. The potential of the wiring 112 (for example, the H-level signal IN1) is supplied to the node 1. The potential of node 11 begins to rise. Eventually, the potential of node 11 becomes V1+Vth101+Va(Va is a positive number), the transistor 101 is turned on. Since the potential of the wiring 112 (for example, the signal IN1 at the H level) is After that, the potential of node 11 continues to rise. When the potential becomes V2-Vth104 (Vth104 is the threshold voltage of the transistor 104), The transistor 104 is turned off. Then, the wiring 112 and the node 11 are not electrically connected to each other. Therefore, the node 11 is in a floating state while maintaining its potential at V2-Vth104. becomes.

[0080] Then, the signal IN2 goes low, turning off the transistor 103. Since the signal IN3 becomes H level, the transistor 102 is turned on. Since the wiring 115 and the wiring 111 are in a conductive state, the potential of the wiring 115 (for example, voltage V1) That is, the potential of the wiring 111 (for example, voltage V1) and The potential of the wiring 112 (for example, the signal IN1 at H level) is supplied. The channel width of the transistor 102 is larger than the channel width of the transistor 101. At this time, the potential of the wiring 111 is equal to the voltage V1, a value lower than the sum of the threshold voltages of any one of the transistors 101 to 105 In this way, the potential of the wiring 111 becomes L level, and the signal OUT becomes L level. It becomes a lu.

[0081] Next, operation 4 of the circuit 100 will be described with reference to FIG. Compared to the previous example, the difference is that the signal IN3 becomes L level. At this time, transistor 103 is also turned off. Therefore, the wiring 115 and the wiring 111 are in a non-conductive state. The potential of the wiring 112 (for example, the signal IN1 at the H level) is supplied to the wiring 112. The potential of node 11 starts to rise. At this time, node 11 is in a floating state. Due to the parasitic capacitance between the gate and the second terminal of transistor 101, the potential of node 11 is As a result, the potential of the node 11 becomes V2+Vth101+Va. This is a bootstrap operation. In this way, the potential of the wiring 111 becomes V2, and the signal O UT becomes H level.

[0082] Next, operation 5 of the circuit 100 will be described with reference to FIG. This turns on the transistor 105, and the wiring 115 and the node 11 Since the potential of the wiring 115 (for example, voltage V1) is supplied to the node 11, At this time, the signal IN1 becomes L level, so the transistor 104 is turned off. In other words, the node 11 is connected to the wiring 112. Therefore, the potential of node 11 becomes V1. Then, the transistor 101 is turned off, and the wiring 112 and the wiring 111 are not electrically connected. become.

[0083] Then, the signal IN2 goes to H level, and the transistor 103 turns on. Since the signal IN3 becomes H level, the transistor 102 is turned on. Since the wiring 115 and the wiring 111 are in a conductive state, the potential of the wiring 115 (for example, voltage V1) Therefore, the potential of the wiring 111 becomes V1, and the signal OUT becomes L level. It becomes a lu.

[0084] Next, the sixth operation of the circuit 100 will be described with reference to FIG. Compared to the previous example, the difference is that the signal IN3 becomes L level. However, transistor 102 is turned off. However, the transistor 103 is turned on as in operation 5. That is, the wiring 115 and Since the wiring 111 is in a conductive state as in operation 5, the potential of the wiring 115 is applied to the wiring 111. (For example, voltage V1) is supplied. Therefore, the potential of the wiring 111 becomes V1, and the signal O UT will be at L level.

[0085] Next, operation 7 of the circuit 100 will be described with reference to FIG. This turns off the transistor 105, and the wiring 115 and the node 11 At this time, the signal IN1 is at the L level, so the transistor 104 Then, the wiring 112 and the node 11 are not electrically connected. Node 11 is now floating and maintains the potential it had in the previous state. The potential of V1 is lower than V1+Vth101. Therefore, the transistor 101 is turned off. Therefore, the wiring 112 and the wiring 111 are in a non-conductive state.

[0086] Then, the signal IN2 goes low, turning off the transistor 103. When this happens, the signal IN3 goes high, turning on the transistor 102. Since the wiring 115 and the wiring 111 are in a conductive state, the potential of the wiring 115 (for example, voltage V1) Therefore, the potential of the wiring 111 becomes V1, and the signal OUT becomes L level. Become Bell.

[0087] Next, operation 8 of the circuit 100 will be described with reference to FIG. Compared to the previous example, the difference is that the signal IN3 becomes L level. At this time, transistor 103 is also turned off. Therefore, the wiring 115 and the wiring 111 are in a non-conductive state. is in an indeterminate state Z (floating, floating, or high impedance state) Therefore, if there is no fluctuation in potential due to noise or the like, the potential of the wiring 111 will remain in its previous state. Therefore, for example, if the operation immediately before operation 8 is operations 1 to 3 and operation 5, In this case, the signal OUT becomes L level. For example, the operation immediately before operation 8 is operation 4. In this case, the signal OUT is at H level. become.

[0088] As described above, the transistors 101 to 105 are turned on in any of the operations 1 to 8. Therefore, the time that the transistor is on is shortened or This reduces the number of times that this occurs, thereby suppressing the deterioration of the transistor. This results in degradation of transistor characteristics (e.g., an increase in threshold voltage or a decrease in mobility). can be suppressed.

[0089] Alternatively, deterioration of the transistor can be suppressed, or the transistor included in the circuit 100 can be reduced. Since the polarity of all transistors can be N-channel, the semiconductor layer of the transistor As a result, materials that are more susceptible to deterioration than single-crystal semiconductors (for example, amorphous semiconductors or microcrystalline semiconductors) It is now possible to use non-single-crystal semiconductors such as conductors, organic semiconductors, or oxide semiconductors. Therefore, it is possible to reduce the number of steps, increase the yield, and / or shorten the manufacturing time. For example, the semiconductor device of this embodiment can be used for display. In this case, the display device can be made larger.

[0090] Alternatively, in consideration of the case where the transistor deteriorates, the channel width of the transistor is increased. Alternatively, the bootstrap operation can be used to reduce the Vgs of the transistor. can be increased, so that the channel width of the transistor can be reduced. Alternatively, the amplitude of the output signal can be set to the same value as the power supply voltage or the same value as the amplitude of the signal. Therefore, the amplitude of the output signal can be increased. The channel width of the transistor can be reduced. The channel width can be reduced, which reduces the area of ​​the transistor channel. can be done.

[0091] Alternatively, the area of ​​the transistor channel can be reduced, resulting in a reduction in layout area. As a result, for example, the semiconductor device of this embodiment can be used in a display device. In this case, the resolution of the display device can be increased. The frame of the device can be made smaller.

[0092] Alternatively, the area of ​​the transistor channel can be reduced, so that the gate The area where the functional material and the semiconductor layer overlap with each other via the insulating layer can be reduced. As a result, short-circuiting between the material functioning as the gate and the semiconductor layer is reduced. Therefore, it is possible to reduce the variation in the output signal and prevent malfunction. and / or increase the yield.

[0093] Alternatively, all transistors may be N-channel, or all transistors may be It is possible to make it a P-channel type. Therefore, the number of processes is reduced compared to CMOS circuits. It is possible to reduce the number of chips, improve the yield, improve the reliability, or reduce the manufacturing cost. By making all transistors N-channel, the semiconductor layer of the transistor and The semiconductor material may be a non-single-crystal semiconductor such as an amorphous semiconductor or a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor. However, transistors using these semiconductor layers However, the semiconductor device of this embodiment suppresses the deterioration of the transistor. It is possible.

[0094] Next, in addition to operations 1 to 8, operations that the circuit 100 can perform will be described.

[0095] First, in operations 1 and 2, the channel width of the transistor 104 is set to the same as that of the transistor 1 By making the channel width larger than that of transistor 105, transistor 101 will be turned on. Then, the wiring 112 and the wiring 111 are electrically connected, and the wiring 112 A potential (for example, a signal IN1 at an H level) is supplied to the wiring 111. is the potential of the wiring 115 (for example, voltage V1) and the potential of the wiring 112 (for example, a high-level signal I In this case, the current supply capacity of the transistor 101 is reduced. By setting the potential of the wiring 111 to a value slightly higher than V1, the signal OUT is set to the L level. For this reason, the channel width of the transistor 101 can be It is preferable that the channel width of the transistor 102 or the channel width of the transistor 103 be smaller than that of the transistor 103. Alternatively, it is preferable that Vgs of the transistor 101 is smaller than V2-V1. More preferably, it is smaller than (V2-V1) x 1 / 2. By controlling the Vgs of the transistor 101, an analog voltage is output from the wiring 111. That is, the circuit 100 can be used as an analog buffer or amplifier circuit, etc. As another example, the channel width of the transistor 101 can be The channel width of the transistor 102 is set to be larger than the sum of the channel width of the transistor 103. By doing so, it is possible to make the signal OUT high level.

[0096] Next, signal IN1 changes from H level to L level, and signal IN2 changes from L level to H level. As a result, the operation switches from operation 4 to operation 6. In this case, as shown in FIG. Thus, in operation 6, by turning on transistor 101 for a short time, The potential of the signal IN112 (for example, the signal IN1 at the L level) can be supplied to the wiring 111. By doing this, the fall time of the signal OUT can be shortened. To achieve this, the transistor 101 is turned on before the signal IN1 goes low. It is possible to delay the timing of turning off the power supply. Therefore, it is possible to delay the timing at which the signal IN2 becomes high level compared to the timing at which the signal IN2 becomes high. Alternatively, it is possible to make the distortion of signal IN2 larger than that of signal IN1. Alternatively, the channel width of the transistor 105 is smaller than that of the transistor 103. Alternatively, one electrode of the capacitor element may be connected to the node 11. The other electrode of the capacitor element can be connected to a power supply line or a signal line (for example, a wiring 1). 15 or wiring 111). Parasitic effects of transistors (e.g., transistor 101, transistor 104, or transistor 105) Alternatively, the wiring 113 may be formed on the same substrate as the circuit 100. The signal can be provided by a circuit that is connected to the

[0097] Next, in operations 7 and 8, the potential of the node 11 is V1+Vth101+Va. In this case, the transistor 101 is turned on, and the wiring 112 and the wiring The line 111 is electrically connected to the line 112. Then, the potential of the line 112 (for example, the signal IN1 at an L level) ) is supplied to the wiring 111. By doing so, especially in operation 8, the voltage of the wiring 111 Since the potential can be fixed, the circuit can be made resistant to malfunctions.

[0098] As described above, the semiconductor device of this embodiment performs various operations in addition to operations 1 to 8. It is possible.

[0099] Next, the ratio of the channel widths of the transistors 101 to 105 will be described.

[0100] First, the load driven by the transistors 104 and 105 (for example, the gate of the transistor 101) ) is a load driven by the transistors 101 to 103 (for example, a load connected to the wiring 111). (e.g., the gate of a transistor). The channel width is the channel width of the transistor 101, the channel width of the transistor 102, and and / or may be smaller than the channel width of the transistor 103. The channel width of the transistor 105 is the same as that of the transistor 101, and / or the channel width of transistor 103. In this case, the channel width of the transistor 101 is It is preferably 20 times or less the width of the panel, and more preferably 10 times or less. It is more preferable that the difference is 7 times or less. The channel width of the transistor 105 is preferably 10 times or less than the channel width of the transistor 105. Preferably, it is 5 times or less, and more preferably, it is 3 times or less. Desirable.

[0101] Next, when the signal OUT becomes L level, the potential of the wiring 115 (for example, the voltage V1) The signal is supplied to the wiring 111 through two transistors, a transistor 102 and a transistor 103. On the other hand, when the signal OUT becomes an H level, the potential of the wiring 112 (for example, For example, a high-level signal IN1 is transmitted through a single transistor called transistor 101. 111. Therefore, the channel width of transistor 101 is The channel width of the transistor 102 and / or the channel width of the transistor 103 are larger than In such a case, the channel width of the transistor 101 is It is preferable that the channel width of the transistor 102 or the channel width of the transistor 103 is three times or less. It is more preferable that the ratio is 2 times or less.

[0102] Next, assume that the signal IN1 goes to H level and the transistor 101 turns on. When the transistor 102 or the transistor 103 is turned on, In order to make the potential of 111 low, the channel width of the transistor 102 is The channel width of the transistor 103 can be larger than that of the transistor 101. The channel width can be greater than the channel width of transistor 101. In this case, the channel width of the transistor 101 is It is preferable that the width is equal to or less than 1 time the channel width of the transistor 103. More preferably, it is equal to or less than 0.7 It is preferable that the ratio is 1:1 or less.

[0103] It is assumed that the signal IN1 becomes H level and the transistor 101 is turned on. When the transistor 103 is turned on, the transistor 102 is turned on in few cases. Therefore, the channel width of the transistor 103 is larger than that of the transistor 102. It is possible to make the size smaller.

[0104] Next, in operations 1 and 2, the transistors 104 and 105 are turned on. By this, the node 11 receives the potential of the wiring 115 (for example, voltage V1) and the potential of the wiring 112. Therefore, as already mentioned, In order to make the potential of the node 11 low, the channel width of the transistor 105 is It is possible that the channel width of the transistor 104 is larger than that of the transistor 104. The channel width of the transistor 105 is preferably 15 times or less than the channel width of the transistor 104. It is more preferable that the ratio is 10 times or less, and even more preferable that the ratio is 8 times or less. For example, the channel length of the transistor 104 is preferably By increasing the channel length of transistor 105 to be larger than that of transistor 105, the W / L ratio of transistor 105 is increased. In this case, the W / L ratio of the transistor 104 can be larger than that of the transistor 104. The channel length of transistor 104 is preferably 9 times or less than the channel length of transistor 105. It is preferable that the ratio is 6 times or less, and more preferable that the ratio is 3 times or less. It is preferable that

[0105] As described above, it is preferable to set the ratio of the channel widths of the transistors to an appropriate value. , considering the ratio of the sizes of the above transistors, the channel width of transistor 101 is It is preferable that the thickness is 100 μm or more and 1000 μm or less. It is preferable that the thickness is 1 μm or more and 300 μm or less, or 500 μm or more and 800 μm or less. The channel width of the transistor 102 or the channel width of the transistor 103 is 100 μm or more. It is preferable that the thickness is 100 μm or more and 300 μm or less. It is preferable that the thickness of the transistor 10 is 700 μm or less, or 700 μm or more and 1200 μm or less. The channel width of 4 is preferably 10 μm or more and 300 μm or less. The channel of the transistor 105 is preferably 20 μm or more and 100 μm or less. The width of the hole is preferably 30 μm or more and 500 μm or less. It is preferable that the thickness is 100 μm or more and 150 μm or less.

[0106] Next, a semiconductor device having a different structure from that shown in FIG. 1A will be described.

[0107] First, in the configuration described in FIG. 1A, the first terminal of the transistor 105 is connected to the wiring 11. 5 (for example, wiring 112). The gate of the transistor 105 is connected to a wiring other than the wiring 113 (for example, the wiring 111, the wiring 116, or can be connected to nodes (e.g., node 11).

[0108] The wiring 116 can be supplied with a voltage V2. For example, the wiring 116 can function as a power supply line. Therefore, the wiring 116 can function as a signal line. It is Noh.

[0109] In FIG. 6A, in the semiconductor device of FIG. 1A, the first terminal of the transistor 105 is 112. An H signal is supplied to the first terminal of the transistor 105. Therefore, a reverse bias can be applied to the transistor 105. Therefore, deterioration of the transistor 105 can be suppressed.

[0110] In FIG. 6B, in the semiconductor device of FIG. 1A, the first terminal of the transistor 105 is , and the gate of the transistor 105 is connected to the node 11. This allows an H signal to be supplied to the first terminal of the transistor 105. , a reverse bias can be applied to the transistor 105, so that the Deterioration can be suppressed.

[0111] In FIG. 6C, in the semiconductor device of FIG. 1A, the first terminal of the transistor 105 is The gate of the transistor 105 is connected to a wiring 112 and the gate of the transistor 106 is connected to a wiring 116. The signal IN1 at H level is input to the node 101 via the transistor 104 and the transistor 105. Therefore, the channel width of the transistor 104 can be reduced. It can be made easier.

[0112] Next, in the configuration described with reference to FIG. 1(A) and FIGS. 6(A) to 6(C), the transistor 103 The first terminal of the wiring 115 can be connected to a wiring (for example, wiring 112) other than the wiring 115. Alternatively, the gate of the transistor 103 may be connected to a wiring (for example, a wiring 111, wiring 116 or node 11, etc.

[0113] In FIG. 6D, in the semiconductor device of FIG. 1A, the first terminal of the transistor 103 is 112. An H signal is supplied to the first terminal of the transistor 103. Therefore, a reverse bias can be applied to the transistor 103. Therefore, deterioration of the transistor 103 can be suppressed.

[0114] In FIG. 6E, in the semiconductor device of FIG. 1A, the first terminal of the transistor 103 is The gate of the transistor 103 is connected to a wiring 111. Therefore, a reverse bias can be applied to the transistor 103. This can suppress the deterioration of the resistor 103.

[0115] In FIG. 6F, in the semiconductor device of FIG. 1A, the first terminal of the transistor 103 is The gate of the transistor 103 is connected to a wiring 116. The signal IN1 at H level is input via the transistor 103 and the transistor 101. This allows the supply of current to the wiring 111. Therefore, the channel width of the transistor 101 can be reduced. It can be reduced.

[0116] Next, in the configuration described with reference to FIG. 1(A) and FIGS. 6(A) to 6(F), the transistor 104 The first terminal of the wiring 112 may be connected to a wiring (such as the wiring 116) other than the wiring 112. Alternatively, the gate of the transistor 104 may be connected to a wiring (for example, It is possible to connect the wiring 116, etc.

[0117] FIG. 7A shows a semiconductor device in which the first terminal of the transistor 104 is The configuration connected to the wiring 116 is shown.

[0118] FIG. 7B shows a semiconductor device in FIG. 1A in which the gate of the transistor 104 is connected to a wiring. The potential of the wiring 112 (for example, Therefore, the potential of the node 11 can be fixed. Therefore, a semiconductor device that is resistant to noise can be obtained.

[0119] Next, in the configurations described in FIG. 1(A), FIG. 6(A) to FIG. 6(F), and FIG. 7(A) to FIG. 7(B), The first terminal of the transistor 102 is connected to a wiring other than the wiring 115 (for example, the wiring 113, the wiring line 114 or node 11). The first terminal of the transistor 103 and / or the first terminal of the transistor 105 are connected to a wiring 115. It can be connected to other wirings (such as wiring 113, wiring 114, or node 11). be.

[0120] In FIG. 7C, in the semiconductor device of FIG. 1A, the first terminal of the transistor 102 is 113. An H signal is supplied to the first terminal of the transistor 102. Therefore, a reverse bias can be applied to the transistor 102. Therefore, deterioration of the transistor 102 can be suppressed.

[0121] FIG. 7D shows a first terminal of the transistor 103 in the semiconductor device of FIG. and a first terminal of the transistor 105 is connected to a wiring 114. A H signal can be supplied to the first terminal of the transistor 103 or the first terminal of the transistor 105. Therefore, when a reverse bias is applied to the transistor 103 or the transistor 105, Therefore, deterioration of the transistor 103 or the transistor 105 can be suppressed. can be done.

[0122] Next, in the configurations described in FIG. 1(A), FIG. 6(A) to FIG. 6(F), and FIG. 7(A) to FIG. 7(D), Each terminal or electrode of the transistor can be connected to a separate wiring. For example, the first terminal of the transistor 101 and the first terminal of the transistor 104 are connected to separate Alternatively, the gate of the transistor 103 and the The gate of the transistor 105 can be connected to a separate wiring. The first terminal of the transistor 102, the first terminal of the transistor 103, and the first terminal of the transistor 105 The first terminal can be connected to a separate wiring. It is possible to split a line into multiple wires.

[0123] In FIG. 7(E), in the semiconductor device of FIG. 1(A), the wiring 112 is made up of wirings 112A to 112C. 2B, and the wiring 113 is divided into a plurality of wirings 113A to 113B. The wiring 115 is divided into a plurality of wirings 115A to 115C. The first terminal of the transistor 101 is connected to a wiring 112A. The first terminal of the transistor 104 is connected to the wiring 112B. The gate of the transistor 103 is connected to the wiring 112B. A, and the gate of the transistor 105 is connected to the wiring 113B. The first terminal of the transistor 102 is connected to the wiring 115A, and the first terminal of the transistor 103 is connected to the wiring 115B. The first terminal of the transistor 105 is connected to the wiring 115B, and the second terminal of the transistor 105 is connected to the wiring 115C. and is connected.

[0124] The wirings 112A and 112B can have the same function as the wiring 112. Alternatively, the wirings 113A to 113B may have the same function as the wiring 113. Alternatively, the wirings 115A to 115C may have the same function as the wiring 115. Therefore, the signal IN1 can be input to the wirings 112A and 112B. Alternatively, a signal IN2 can be input to the wirings 113A to 113B. In this case, a voltage V1 can be supplied to the wirings 115A to 115C. The lines 112A and 112B can be supplied with different voltages or different signals. Alternatively, different voltages or different signals can be supplied to the wirings 113A and 113B. Alternatively, different voltages or different signals may be supplied to the wirings 115A to 115C. is possible.

[0125] Next, in the configurations described in FIG. 1(A), FIG. 6(A) to FIG. 6(F), and FIG. 7(A) to FIG. 7(E), , transistor 105A and / or transistor 103A can be newly provided. is.

[0126] FIG. 8A shows a configuration in which a transistor 105A is newly provided in the semiconductor device of FIG. Transistor 105A can correspond to transistor 105 and The first terminal of the transistor 105A is connected to the wiring 112. The second terminal of the transistor 105A is connected to the node 11, and the second terminal of the transistor 105B is connected to the node 11. The gate of 105A is connected to the wiring 113. For example, similar to FIGS. 6(B) to 6(C), The gate of the transistor 105A can be connected to the node 11 or the wiring 116. For example, as in FIGS. 6B and 6C, the gate of the transistor 105A is connected to the wiring 1. 13 (for example, node 11, wiring 116, or wiring 111, etc.) It is possible to do this.

[0127] FIG. 8B shows a configuration in which a transistor 103A is newly provided in the semiconductor device of FIG. Transistor 103A can correspond to transistor 103, and The first terminal of the transistor 103A is connected to the wiring 112. The second terminal of the transistor 103A is connected to the wiring 111. The gate of the capacitor 103A is connected to the wiring 113. For example, as in FIGS. 6(E) to 6(F), The gate of the transistor 103A is connected to a wiring other than the wiring 113 (for example, the wiring 111, the wiring 116 or node 11).

[0128] Next, Figs. 1(A), 6(A) to (F), 7(A) to (E), and 8(A) to (B) In the configuration described in the above, a transistor 106 can be newly provided.

[0129] FIG. 8C shows a structure in which a transistor 106 is newly provided in the semiconductor device of FIG. The transistor 106 is an N-channel transistor. However, this embodiment is not limited to this. The transistor 106 may be a P-channel type. A first terminal of the transistor 106 is connected to the wiring 115, and a second terminal of the transistor 106 is connected to the The gate of the transistor 106 is connected to the wiring 114 .

[0130] The function of the transistor 106 will be described. The transistor 106 is connected to the wiring 115 and the node The transistor 106 has a function of controlling electrical continuity between the wiring 11 and the transistor 106. The wiring 11 has a function of controlling the timing at which the potential of the wiring 11 is supplied to the node 11. When a signal or voltage is input to the wiring 115, the transistor 106 The timing at which a signal or voltage is supplied to the node 11 is controlled. The transistor 106 controls the timing of supplying the L signal or voltage V1 to the node 11. Alternatively, the transistor 106 may be configured to decrease the potential of the node 11. As described above, the transistor 106 functions as a switch. It is possible for the transistor 106 to have all of the above functions. Note that the transistor 106 is turned on by the potential of the wiring 114 (signal IN3). It can be controlled by

[0131] The operations of the semiconductor device in FIG. 8C will be described below. At this time, the signal IN3 goes high, turning on the transistor 106. Since the wiring 115 and the node 11 are electrically connected, the potential of the wiring 115 (for example, voltage V1 ) is supplied to node 11. In this way, the potential of node 11 can be fixed. Therefore, a semiconductor device that is resistant to noise can be obtained. This allows the transistor 101 to be easily turned off. Since the channel width of the stator 105 can be reduced, the layout area can be reduced. On the other hand, in operations 2, 4, 6, and 8, the signal IN3 is at the L level. This turns off the transistor 106. Since the time when the transistor 106 is turned on can be shortened, deterioration of the transistor 106 can be suppressed. can.

[0132] Next, Figs. 1(A), 6(A) to (F), 7(A) to (E), and 8(A) to (C) In the configuration described above, the transistor 103 and / or the transistor 105 may be omitted. It is possible to do this.

[0133] FIG. 8D shows a structure in which the transistor 103 is omitted from the semiconductor device of FIG. Even if the transistor 103 is omitted, for example, the transistor 101 may be turned on. The timing when the IN1 signal changes from H level to L level is used to determine the timing when the IN1 signal changes from H level to L level. By delaying the switching of the signal 112, the potential of the wiring 112 (for example, the signal IN1 at the L level) Therefore, the potential of the wiring 111 can be set to V1. Thus, by omitting the transistor 103, the number of transistors can be reduced. It can be done.

[0134] The timing at which the transistor 101 switches from on to off is determined by the signal IN1 being at the H level. In order to delay the timing of the transition from the bell to the L level, the channel of transistor 105 is The width of the transistor 101 can be smaller than the channel width of the transistor 101. The area (for example, L×W) of the channel of the transistor 101 is It is possible to make it the largest of all.

[0135] FIG. 8E shows a structure in which the transistor 105 is omitted from the semiconductor device of FIG. The number of transistors can be reduced by omitting the transistor 105. can be done.

[0136] Next, Figs. 1(A), 6(A) to (F), 7(A) to (E), and 8(A) to (E) In the configuration described in the section 1, a capacitor element 1 is provided between the gate and the second terminal of the transistor 101. For example, a MOS capacitor can be used as the capacitance element. It is possible.

[0137] FIG. 8F shows the gate of the transistor 101 and the second In the illustrated configuration, a capacitor 107 is connected between the terminals. Therefore, increasing the Vgs of the transistor 101 makes it easier for the potential of the node 11 to rise. As a result, the channel width of the transistor 101 can be reduced. Alternatively, the fall time or rise time of the signal OUT can be shortened.

[0138] Note that the material of one electrode of the capacitor 107 is the same as that of the gate of the transistor. Alternatively, the material of the other electrode of the capacitor 107 is preferably the same as that of the source It is preferable that the material is the same as that of the drain. Alternatively, the capacitance value can be increased.

[0139] Note that the area where one electrode and the other electrode of the capacitor 107 overlap is It is preferable that the area is smaller than the area where the material used as the gate and the semiconductor layer overlap. Desirable.

[0140] Next, Figs. 1(A), 6(A) to (F), 7(A) to (E), and 8(A) to (F) In the configuration described above, a circuit 120 can be newly provided in addition to the circuit 100.

[0141] FIG. 9A shows a structure in which a circuit 120 is newly provided in the semiconductor device of FIG. The circuit 120 includes a wiring 113, a gate of the transistor 103, and a gate of the transistor 104. The circuit 120 is connected to the connection point of the gate of the input terminal 113. Therefore, for example, the gate of the transistor 105 The timing at which the potential of this pin rises is the timing at which the signal IN2 changes from L level to H level. That is, the timing at which the transistor 105 turns on or the The timing at which the potential decreases is before the signal IN2 changes from L level to H level. Therefore, for example, the timing at which the transistor 101 switches from on to off is delayed. The timing can be slower than the timing when signal IN1 changes from H level to L level. As a result, the signal IN1 at L level can be supplied to the wiring 111, For example, as shown in FIG. 9(B), The gate of the transistor 103 is connected to the wiring 113 without passing through the circuit 120. The gate of the gate electrode 105 can be connected to the wiring 113 via the circuit 120 . This is because the transistor 103 that is turned on earlier can supply the voltage V1 to the wiring 111 earlier. Therefore, the fall time of the signal OUT can be shortened. As another example, the gate of the transistor 105 is connected to the wiring 1 through the circuit 120. In this case, the gate of transistor 103 can be connected to transistor 11. It can be connected to the gate of the resistor 105 and can be connected to the wiring 113. It is possible.

[0142] The circuit 120 may have at least a capacitance component and a resistance component. For example, the circuit 120 may include resistors, capacitors, transistors, diodes, and the like. It is possible to use a combination of the above elements or various other elements. C) to (D) show a configuration in which the circuit 120 has a resistive element 121 and a capacitive element 122. As another example, the circuit 120 may include a buffer circuit, an inverter circuit, a NAND circuit, an NAND gate ... OR circuits, level shifter circuits, circuits that combine these circuits, or various other circuits In FIG. 9E, the circuit 120 includes a buffer circuit 123. FIG. 9F shows a configuration in which the circuit 120 includes an inverter circuit 124. .

[0143] The capacitance component can be a parasitic capacitance, and the resistance component can be a parasitic resistance. That is, the circuit 120 may include wiring, contacts between materials on one layer and materials on another layer, and the like. It is possible to use a tact, an FPC pad, or the like. It is preferable that the wiring resistance of the wiring 13 is larger than the wiring resistance of the wiring 112. Therefore, the minimum wiring width of the wiring 113 is smaller than the minimum wiring width of the wiring 112. Alternatively, the wiring 113 is preferably made of a conductive material having the lowest resistance value compared to the wiring 112. It may contain a large amount of material (e.g., material that contains the pixel electrode material), or For example, suppose a certain material is used for both the wiring 113 and the wiring 112. In this case, The minimum thickness of the material of the wiring 113 is the minimum thickness of the material of the wiring 112. It is possible to make the thickness thinner than

[0144] Note that the buffer circuit 123 can have the configuration shown in FIG. The buffer circuit includes a transistor 125, a transistor 126, a transistor 127, and The first terminal of the transistor 125 is connected to a wiring 129. The second terminal of the transistor 125 is connected to the gate of the transistor 103. The gate of the transistor 125 is connected to the wiring 113. The second terminal of the transistor 126 is connected to the wiring 130, and the second terminal of the transistor 103 is connected to the wiring 130. The first terminal of the transistor 127 is connected to the wiring 129. The second terminal of the transistor 127 is connected to the gate of the transistor 126. The gate of the transistor 127 is connected to a wiring 129. The first terminal of the transistor 128 is connected to a wiring 130, and the second terminal of transistor 128 is connected to the gate of transistor 126. The gate of the transistor 128 is connected to the wiring 113. In many cases, a high voltage such as voltage V2 is supplied to the wiring 130, and a voltage such as voltage V1 is supplied to the wiring 130. A negative voltage is supplied.

[0145] The inverter circuit 124 may have the configuration shown in FIG. 9(H). The inverter circuit includes a transistor 131, a transistor 132, a transistor 133, A first terminal of the transistor 131 is connected to the wiring 129. The second terminal of the transistor 131 is connected to the gate of the transistor 103. The first terminal of the transistor 132 is connected to the wiring 130. The terminal 2 is connected to the gate of the transistor 103, and the gate of the transistor 132 is connected to A first terminal of the transistor 133 is connected to the wiring 129. The second terminal of the transistor 133 is connected to the gate of the transistor 131. The gate of the transistor 133 is connected to the wiring 129. The first terminal of the transistor 134 is The second terminal of the transistor 134 is connected to the wiring 130 and the gate of the transistor 131. The gate of the transistor 134 is connected to the wiring 113.

[0146] Next, Fig. 1(A), Fig. 6(A)-(F), Fig. 7(A)-(E), Fig. 8(A)-(F), and In the configurations described in Figs. 9(A)-(B), the transistors are replaced with diodes. For example, the transistor can be diode-connected.

[0147] FIG. 11A shows a semiconductor device in which a transistor is replaced with a diode in the semiconductor device in FIG. The transistor 101 has one electrode (for example, an input terminal) connected to a node 11, and the other electrode (for example, an output terminal) of the diode 1 is connected to the wiring 111. Alternatively, the transistor 102 may be replaced by a transistor 01d. (for example, an input terminal) is connected to the wiring 111, and the other electrode (for example, an output terminal) is connected to the wiring 11 4. Alternatively, the transistor 102 may be replaced by a diode 102d connected to the The resistor 103 has one electrode (for example, an input terminal) connected to the wiring 111, and the other electrode ( For example, the output terminal may be replaced with a diode 103d connected to the wiring 113. Alternatively, one electrode (for example, an input terminal) of the transistor 104 may be connected to the wiring 11. 2, and the other electrode (for example, an output terminal) of a diode 10 connected to a node 11. 4d. Alternatively, the transistor 105 can be replaced by For example, an input terminal) is connected to the node 11, and the other electrode (for example, an output terminal) is connected to the wiring 113. This can be replaced by a diode 105d connected to This reduces the number of signals or power supplies, which means the number of wires can be reduced. Therefore, the connection between the substrate on which the circuit 100 is formed and the substrate for supplying signals to the substrate is The number of connections can be reduced, improving reliability, increasing yield, or reducing manufacturing costs. The circuit 100 includes a plurality of transistors (for example, transistors Some of the transistors (101 to 105) can be replaced with diodes. .

[0148] FIG. 11B shows a semiconductor device in which a transistor is diode-connected in the semiconductor device in FIG. 1A. The first terminal of the transistor 101 is connected to a node 11. Alternatively, the first terminal of the transistor 102 is connected to the wiring 114, and the The gate of the transistor 102 can be connected to the wiring 111. A first terminal of the transistor 103 is connected to the wiring 113, and a gate of the transistor 103 is connected to the wiring 113. , can be connected to the wiring 111. Alternatively, the first terminal of the transistor 105 The gate of the transistor 105 is connected to the wiring 113, and the gate of the transistor 106 is connected to the node 11. This allows the number of signals or power supplies to be reduced. Therefore, the number of wirings can be reduced. This reduces the number of connections to the board for supplying signals to the The circuit 100 can be provided with a plurality of Some of the transistors (e.g., transistors 101 to 105) are diodes. It is possible to connect.

[0149] Next, Fig. 1(A), Fig. 6(A)-(F), Fig. 7(A)-(E), Fig. 8(A)-(F), Fig. 9(A)-(B) and 11(A)-(B), the transistor is easily For example, instead of omitting the transistor, the capacitor element can be replaced. It is possible to provide a new quantum element.

[0150] 11C shows a semiconductor device in FIG. 1A in which the transistor 104 is connected to the wiring 11. 2 and node 11. 104A controls the potential of the node 11 in accordance with the potential of the wiring 112 by capacitive coupling. In this way, by replacing the transistor 104 with the capacitor 104A, This reduces the steady-state current, thereby reducing power consumption.

[0151] FIG. 11D shows a semiconductor device in which a capacitor 104A is newly provided in the semiconductor device in FIG. The potential change of the node 11 can be made steep, so that the power consumption can be reduced. It is possible.

[0152] FIG. 11E shows the semiconductor device of FIG. 1A, in which the transistor 102 and the transistor The transistor 103 and the transistor 105 are connected between the wiring 114 and the wiring 111, respectively. a capacitance element 102A connected between the wiring 113 and the wiring 111; a capacitance element 103B connected between the wiring 113 and the wiring 111; 1 shows a configuration in which the capacitance element 105B is replaced by a capacitance element 105B connected between the line 113 and the node 11. .

[0153] Next, Fig. 1(A), Fig. 6(A)-(F), Fig. 7(A)-(E), Fig. 8(A)-(F), Fig. In the configurations described in Figs. 9(A) to (B) and 11(A) to (F), the transistor is replaced with a resistor. It is possible to replace the resistor element.

[0154] FIG. 11F shows a semiconductor device in which the transistor 104 is replaced with a resistor element 1 in the semiconductor device in FIG. The resistor element 104R is replaced with a resistor element 104R between the wiring 112 and the node 11. is connected between them.

[0155] Next, Fig. 1(A), Fig. 6(A)-(F), Fig. 7(A)-(E), Fig. 8(A)-(F), Fig. 9(A) to (B) and 11(A) to (F), the transistor 10 8 can be newly established.

[0156] In FIG. 46A, a transistor 108 is newly provided in the semiconductor device of FIG. The transistor 108 is an N-channel transistor. Without being limited thereto, the transistor 108 can be a P-channel type. A first terminal of the transistor 108 is connected to the wiring 111, and a second terminal of the transistor 108 is connected to the wiring 111. is connected to node 11, and the gate of transistor 108 is connected to wiring 112.

[0157] The operation of the semiconductor device of FIG. 46(A) will be described. In operations 1 to 3, the signal IN1 is Since the potential becomes H level, the transistor 108 is turned on. Then, the wiring 111 and the node 1 Since the potential of the wiring 111 is supplied to the node 11, the potential of the wiring 111 is supplied to the node 11. The potential of the node 11 is supplied to the wiring 111. However, in operation 4, the signal IN3 is at H level. However, the potential of the node 11 and the potential of the wiring 111 become H level, so that the transistor However, the transistor 108 is turned off until the potential of the wiring 111 becomes H level. The transistor 108 is turned on, so the potential at the node 11 decreases. Since the Vgs of 101 becomes small, the breakdown or deterioration of the transistor 101 is prevented. On the other hand, in operations 5 to 8, the signal IN1 is at the L level, so the The resistor 108 is turned off, and therefore the node 11 and the wiring 111 are not electrically connected to each other.

[0158] Next, Fig. 1(A), Fig. 6(A)-(F), Fig. 7(A)-(E), Fig. 8(A)-(F), Fig. 9(A) to (B), 11(A) to (F), and 46(A), the signal O It is possible to generate a signal separate from the UT. A transistor 109 can be newly provided.

[0159] FIG. 46B shows a configuration in which a transistor 109 is newly provided in the semiconductor device of FIG. The transistor 109 has the same polarity as the transistor 101. The transistor 109 can have the same function as the transistor 101. A first terminal of the transistor 109 is connected to the wiring 112, and a second terminal of the transistor 109 is connected to the wiring 112. The gate of the transistor 109 is connected to the wiring 117, and the gate of the transistor 109 is connected to the node 11. It is possible.

[0160] Here, Fig. 1(A), Fig. 6(A)-(F), Fig. 7(A)-(E), Fig. 8(A)-(F), The configurations described in Figures 9(A) to (B), Figures 11(A) to (F), and Figures 46(A) to (B) are used as appropriate. It should be noted that they can be combined.

[0161] FIG. 12(A) shows a combination of the configuration described in FIG. 6(B) and the configuration described in FIG. 6(E). The first terminal of the transistor 103 is connected to the wiring 112. The second terminal of the transistor 103 is connected to the wiring 111. The first terminal of the transistor 105 is connected to the wiring 112. The second terminal of transistor 105 is connected to node 11, and the gate of transistor 105 is connected to node In this way, the signal IN2 and the wiring 113 can be omitted. Therefore, the number of signals or the number of wirings can be reduced. Reducing the number of connections between the substrate and another substrate, improving reliability, reducing manufacturing costs, and / or It is possible to reduce power consumption, etc.

[0162] FIG. 12(B) shows a combination of the configuration described in FIG. 7(A) and the configuration described in FIG. 8(E). The transistor 105 is omitted, and the first terminal of the transistor 104 is connected to the wiring The second terminal of the transistor 104 is connected to node 112, and the second terminal of the transistor 104 is connected to node 11. The gate of the transistor 104 is connected to the wiring 116. In this way, the number of transistors can be reduced. Therefore, the layout area can be reduced. Since the potential can be fixed at the L level, a circuit that is resistant to noise can be obtained.

[0163] FIG. 12(C) shows a combination of the configuration described in FIG. 7(D) and the configuration described in FIG. 11(C). A first terminal of the transistor 103 is connected to a wiring 114. The first terminal of the transistor 105 is connected to the wiring 114, and the second terminal of the transistor 104 is connected to the wiring 112. The node 11 is replaced by a capacitance element 104A connected between the node 11 and the capacitance element 104A.

[0164] As described above, this embodiment is not limited to the configuration shown in FIG. 1A, and various other configurations may be used. The composition can be used.

[0165] Next, Fig. 1(A), Fig. 6(A)-(F), Fig. 7(A)-(E), Fig. 8(A)-(F), Fig. 9(A)-(B), Figs. 11(A)-(F), Figs. 12(A)-(C), and Figs. 46(A)- In the configuration described in (B), a P-channel transistor is used as the transistor. It is possible that only some of the transistors included in the semiconductor device are P-channel type. That is, the semiconductor device of this embodiment can be a CMOS circuit. is possible.

[0166] FIG. 13A shows a semiconductor device in FIG. 1A, in which a P-channel transistor is used as a transistor. The transistors 101p to 105p are transistors It has the same function as the transistors 101 to 105 and is a P-channel type. The wiring 115 is supplied with a voltage V2.

[0167] In the semiconductor device of FIG. 13A, as shown in FIG. 13B, the circuit 100 includes a NAND Specifically, the circuit 100 can function as a logic circuit including three inputs. It can function as a logic circuit that combines two NANDs and two NOTs. A signal IN1 can be input to the first input terminal of the NAND. and the second input terminal of the NAND receives the signal IN2 inverted by the first NOT. A signal IN3 can be input to the third input terminal of the NAND. The signal that is inverted by NOT can be input, and the output of NAND is The circuit 100 can output a signal OUT. It has the function of realizing a logical formula or the function of realizing a truth table obtained by this logical formula. Therefore, the signal IN1 becomes L level, and the signals IN2 and IN3 When the input signal is H level, the signal OUT is L level. It should be noted that OUT is at H level. The truth table for the case where the signal is a digital signal is shown below.

[0168] FIG. 12(D) shows a semiconductor device shown in FIG. 1(A) in which a P-channel transistor is used as a part of the transistor. The gate of the transistor 104p is connected to a node It is connected to port 11.

[0169] (Embodiment 2) In this embodiment, a semiconductor device in which an element or a circuit is newly provided to the semiconductor device of the first embodiment is used. The body device will be described.

[0170] First, a transistor 201 (sixth transistor) is newly added to the semiconductor device of the first embodiment. FIG. 14A shows a structure in which a transistor is provided in the semiconductor device of FIG. The configuration in which a register 201 is newly provided is shown.

[0171] The transistor 201 is an N-channel transistor. However, this embodiment is not limited to this. Transistor 201 can be a P-channel transistor. A first terminal of the transistor 201 is connected to a wiring 115, and a second terminal of the transistor 201 is connected to a wiring 21. 1 (sixth wiring), and the gate of the transistor 201 is connected to the wiring 111. .

[0172] The gate of the transistor 201 is shown as a node 12. Since this corresponds to the wiring 111 described later, when describing the wiring 111, the wiring 111 is referred to as the node 12. Therefore, the potential of the wiring 111 (potential of the signal OUT) is expressed as In this case, the potential of the wiring 111 (the potential of the signal OUT) can be rephrased as the potential of the node 12. It is possible to do this.

[0173] The function of the transistor 201 will be described. The transistor 201 is connected to the wiring 115. The transistor 201 has a function of controlling electrical continuity between the wiring 11 and the transistor 201. The potential of the wiring 11 is supplied to the wiring 211. When a signal or voltage is input to the wiring 115, the transistor 201 The signal or voltage to be supplied to the wiring 211 is controlled by the control circuit 211. The transistor 201 controls the timing of supplying the L signal or the voltage V1 to the wiring 211. Alternatively, the transistor 201 has a function of decreasing the potential of the wiring 211. As described above, the transistor 201 functions as a switch. It is possible for the transistor 201 to have all of the above functions. It is not necessary to control the transistor 201 by the output signal of the circuit 100. It is possible to do this.

[0174] Next, the operation of the semiconductor device of FIG. 14(A) will be described with reference to FIG. 15(A) shows a timing chart that can be used in the semiconductor device of this embodiment. show.

[0175] Note that the timing chart in FIG. 15A includes a period A and a period B. In the timing chart of FIG. 5(A), the periods A and B are alternately arranged. In the timing chart of A), multiple periods A and multiple periods B are alternately arranged. Alternatively, the timing chart in FIG. 15A may be modified in a period other than the period A and the period B. It is possible to have a period between periods A and B, and it is possible to omit one of the periods A and B. be.

[0176] It should be noted that the periods A and B are approximately equal in length. When a clock signal is input to a semiconductor device, the length of period A and the length of period B are determined as follows: The length is approximately equal to half the period of the clock signal of the present embodiment. If the semiconductor device is used in a gate driver, the length of period A and the length of period B are 1 This is roughly equal to the gate selection period.

[0177] First, the operation of the semiconductor device in the period A will be described with reference to a schematic diagram of FIG. During period A, signal IN1 becomes H level, signal IN2 becomes L level, and signal I N3 becomes L level. Therefore, the circuit 100 can perform operation 4 in FIG. As a result, the potential of the node 12 (signal OUT) becomes H level. 1 is turned on, so that the wiring 115 and the wiring 211 are in a conductive state. The potential (for example, voltage V1) of the wiring 211 is supplied to the wiring 211, so that the potential of the wiring 211 (signal G OUT) becomes L level.

[0178] Next, the operation of the semiconductor device in the period B will be described with reference to a schematic diagram of FIG. During period B, signal IN1 becomes L level, signal IN2 becomes H level, and signal I N3 becomes L level. Therefore, the circuit 100 can perform the operation 6 of FIG. Therefore, the potential of the node 12 (signal OUT) becomes L level. Since the signal 01 is turned off, the wiring 115 and the wiring 211 are not electrically connected. Since the potential of the wiring 211 is in a floating state, the potential of the wiring 211 is maintained at approximately V1.

[0179] As described above, the transistor 201 is turned on during the period A and turned off during the period B. Therefore, the time during which the transistor 201 is turned on can be shortened. In addition, during periods A and B, the deterioration of transistor 1 can be suppressed. 01, transistor 102, transistor 103, transistor 104, transistor 1 The transistors 05 and 201 do not remain on, but are turned on for a short period of time or This can reduce the number of times this occurs.

[0180] Next, the functions of the signals IN1 to IN3 and the characteristics of these signals will be described.

[0181] First, the signal IN1 alternates between H level and L level for each period. Alternatively, the wiring 112 may function as a clock signal. It can function as a signal line (clock line or clock supply line).

[0182] Next, the signal IN2 alternates between H level and L level for each period. , is an inverted signal of signal IN1 or a signal whose phase is shifted by 180° from signal IN1. The signal IN2 may function as an inverted clock signal. The line 113 can function as a clock signal line.

[0183] Next, the signals IN1 and IN2 function as clock signals. In this case, the signals IN1 and IN2 can be balanced as shown in FIG. 15(A). Equilibrium means that there is a period in one cycle when the voltage is at the H level and a period when the voltage is at the H level. The period when the signal is at the H level and the period when the signal is at the L level are roughly equal. This means that the period when the voltage is at the L level is different from the period when the voltage is at the L level. It is assumed that the scope of the invention is outside the scope of the invention.

[0184] FIG. 15B shows the timing chart of FIG. 15A, in which the signals IN1 and I 10 shows a timing diagram when N2 is unbalanced.

[0185] Next, n-phase clock signals can be input to the semiconductor device of this embodiment. Alternatively, some of the n-phase clock signals may be input to the semiconductor device of this embodiment. An n-phase clock signal is a clock signal with n phases, each phase having a 1 / n-cycle offset. This refers to the clock signals.

[0186] In FIG. 15(C), one of the three-phase clock signals is used as the signal IN1, and the three-phase clock signals 10 shows a timing chart in the case where another signal is used as the signal IN1.

[0187] As described above, the signals IN1 to IN3 are as shown in the timing chart of FIG. In addition to the waveform, various other waveforms are possible.

[0188] Next, the ratio of the channel width of the transistor 201 will be described. For example, when the wiring 211 is When the wiring 211 has a function as a gate signal line, the wiring 211 is arranged to extend to the pixel portion. In other words, a large load is connected to the wiring 211. The channel width of the transistor 201 is smaller than that of the transistor included in the circuit 100. In this case, the channel width of the transistor 201 is larger than that of the transistor 101. It is preferable that the channel width of the transistor 201 is 10 times or less. The channel width of the transistor 101 is preferably five times or less than the channel width of the transistor 101. More preferably, the channel width of the transistor 201 is equal to or less than the channel width of the transistor 101. It is preferable that the temperature is three times or less.

[0189] As described above, it is preferable to set the ratio of the channel widths of the transistors to an appropriate value. , considering the ratio of the channel widths of the above transistors, the channel of transistor 201 The width is preferably 1000 μm or more and 5000 μm or less. The channel width of the transistor 201 is preferably 1500 μm or more and 4000 μm or less. More preferably, the channel width of the transistor 201 is 2000 μm or more, and 300 It is preferable that the thickness is 0 μm or less.

[0190] Next, a semiconductor device having a different structure from that shown in FIG. 14(A) will be described.

[0191] First, in the configuration described in FIG. 14A, the circuit 100 is not limited to the configuration of FIG. The circuit 100 is not limited to this, and various configurations described in the first embodiment can be used. In this case, a configuration other than that described in the first embodiment may be used as long as it satisfies the predetermined functions. It is possible to do this.

[0192] 10A shows a circuit 100 in the configuration shown in FIG. 14A, in which the The configuration using the above configuration is shown.

[0193] 10B shows a circuit 100 in the configuration shown in FIG. 14A, in which the The configuration shown here is that noise is generated at node 12 via transistor 103. Therefore, malfunction can be prevented.

[0194] 10C shows a circuit 100 in the configuration shown in FIG. 14A, in which the The potential of the node 11 can be made smaller. , it is possible to prevent the transistor 201 from being turned on.

[0195] Next, in the configuration described with reference to FIGS. 10(A) to 10(C) and FIG. 14(A), the transistor 202 It is possible to establish a new

[0196] FIG. 16A shows a structure in which a transistor 202 is newly provided in the semiconductor device of FIG. The transistor 202 is an N-channel transistor. Without being limited thereto, the transistor 202 can be a P-channel type. A first terminal of the transistor 202 is connected to the wiring 115, and a second terminal of the transistor 202 is connected to the wiring 115. The gate of the transistor 202 is connected to a wiring 211, and the gate of the transistor 202 is connected to a wiring 113. The gate of the transistor 202 can be connected to a wiring other than the wiring 113 . Alternatively, the first terminal of the transistor 202 may be connected to a wiring other than the wiring 115. is possible.

[0197] The function of the transistor 202 will be described. The transistor 202 is connected to the wiring 115. The transistor 202 has a function of controlling electrical continuity between the wiring 11 and the transistor 202. The potential of the wiring 11 is supplied to the wiring 211. When a signal or voltage is input to the wiring 115, the transistor 202 The signal or voltage to be supplied to the wiring 211 is controlled by the control circuit 211. The transistor 202 controls the timing of supplying the L signal or the voltage V1 to the wiring 211. Alternatively, the transistor 202 has a function of decreasing the potential of the wiring 211. As described above, the transistor 202 functions as a switch. It is noted that the transistor 202 may have all of the above functions. Note that the transistor 202 does not need to be connected to the potential of the wiring 113 (for example, the signal IN2). It is possible to control the

[0198] The operation of the semiconductor device in FIG. 16A will be described. In period A, the signal IN2 is at the L level. As a result, the transistor 202 is turned off as shown in FIG. In this case, the signal IN2 becomes H level, so that the transistor Therefore, even during the period B, the wiring 115 and the wiring 211 are in a conductive state. Therefore, the potential of the wiring 115 (for example, voltage V1) is supplied to the wiring 211. This can reduce noise in the wiring 211. For example, the semiconductor device shown in FIG. When the wiring 211 is connected to the gate of the selection transistor of the pixel, In this case, noise on the wiring 211 may cause the pixel to receive a bias signal from a pixel in another row. Alternatively, it is possible to prevent a video signal from being written due to noise on the wiring 211. This prevents the video signal held by the pixel from changing. It is possible to improve the quality.

[0199] Next, in the configurations described in FIGS. 10(A) to 10(C), 14(A), and 16(A), A transistor 203 (a seventh transistor) can be newly provided.

[0200] FIG. 17A shows a structure in which a transistor 203 is newly provided in the semiconductor device of FIG. The transistor 203 is an N-channel transistor. The transistor 203 can be, but is not limited to, a P-channel type. A first terminal of the transistor 203 is connected to the wiring 112, and a second terminal of the transistor 203 is connected to the wiring 112. , and is connected to a wiring 211. The gate of the transistor 203 is indicated as a node 13. The gate of the transistor 102 can be connected to the node 13. Therefore, the potential of the node 13 (V13) can be used as the signal IN3.

[0201] The function of the transistor 203 will be described. The transistor 203 is connected to the wiring 112. The transistor 203 has a function of controlling electrical continuity between the wiring 11 and the transistor 203. The potential of the wiring 11 is supplied to the wiring 211. When a signal or voltage is input to the wiring 112, the transistor 203 The signal or voltage to be supplied to the wiring 211 is controlled by the control circuit 211. The transistor 203 controls the timing of supplying the H signal or the voltage V2 to the wiring 211. Alternatively, the transistor 203 may apply an L signal or a voltage V1 to the wiring 211. Alternatively, the transistor 203 may be connected to the wiring 21. The transistor 203 has a function of controlling the timing at which the potential of the transistor 203 is increased. The transistor 211 has a function of controlling the timing at which the potential of the wiring 211 is decreased. The transistor 203 has a function of performing a bootstrap operation. 3 has the function of raising the potential of node 13 by a bootstrap operation. As such, the transistor 203 can function as a switch or a buffer. It is possible. However, the transistor 203 does not need to have all of the above functions. The transistor 203 receives the potential of the node 13, the potential of the wiring 112 (signal IN1), and Alternatively, it can be controlled by the potential of the wiring 211 (signal GOUT).

[0202] The operation of the semiconductor device of FIG. 17(A) will be described with reference to FIG. 17(B). FIG. 1B) shows a timing chart that can be used in the semiconductor device of this embodiment mode.

[0203] The timing chart of FIG. 17B has periods A to E. In the timing chart, periods C, D, and E are arranged in this order. In the other periods, Period A and Period B are alternately arranged. Periods A to E can be arranged in various orders. may be placed in

[0204] The operation of the semiconductor device in the period A will be described with reference to a schematic diagram in FIG. During period A, signal IN1 goes to H level, signal IN2 goes to L level, and the signal at node 13 The potential (signal IN3) becomes L level. Therefore, the circuit 100 performs operation 4 in FIG. 3(A). This allows the potential of node 12 (signal OUT) to become H level. Since the transistor 201 is turned on, the wiring 115 and the wiring 211 are brought into electrical continuity. Therefore, the potential of the wiring 115 (for example, voltage V1) is supplied to the wiring 211. The potential of the node 13 becomes L level, so the transistor 203 is turned off. As a result, the wiring 211 is disconnected from the wiring 115. Since a potential (for example, voltage V1) is supplied, the signal GOUT becomes L level.

[0205] The operation of the semiconductor device in the period B will be described with reference to a schematic diagram in FIG. During period B, signal IN1 goes to L level, signal IN2 goes to H level, and the signal at node 13 The potential (signal IN3) remains at the L level. Therefore, the circuit 100 performs the operation shown in FIG. Since the operation 6 can be performed, the potential of the node 12 (signal OUT) becomes L level. Then, the transistor 201 is turned off, and the wiring 115 and the wiring 211 are not electrically connected to each other. At this time, the potential of the node 13 becomes L level, so that the transistor 203 is turned off. Then, the wiring 112 and the wiring 211 are in a non-conductive state. Since the potential of the wiring 211 is in a floating state, the potential of the wiring 211 is maintained at approximately V1.

[0206] The operation of the semiconductor device in the period C will be described with reference to the schematic diagram in FIG. During period C, signal IN1 goes to L level, signal IN2 goes to H level, and the signal at node 13 The potential (signal IN3) becomes H level. Therefore, the circuit 100 performs operation 5 in FIG. 3B. Therefore, the potential of the node 12 (signal OUT) becomes L level. Since the transistor 201 is turned off, the wiring 115 and the wiring 211 are not electrically connected. At this time, the potential of the node 13 becomes H level, so the transistor 203 is turned on. When this occurs, the wiring 112 and the wiring 211 are brought into a conductive state, and the potential of the wiring 112 (L level The signal IN1 is supplied to the wiring 211. As a result, the wiring 211 is connected to the wiring 112. Since the potential (signal IN1 at L level) is supplied, the signal GOUT becomes L level.

[0207] The operation of the semiconductor device in the period D will be described with reference to the schematic diagram of FIG. During period D, signal IN1 goes to H level, signal IN2 goes to L level, and the signal at node 13 The potential (signal IN3) becomes H level. Therefore, the circuit 100 performs operation 3 in FIG. 2(C). Therefore, the potential of the node 12 (signal OUT) becomes L level. Since the transistor 201 is turned off, the wiring 115 and the wiring 211 are not electrically connected. At this time, the potential of the node 13 becomes H level, so that the transistor 203 is turned on. Then, the wiring 112 and the wiring 211 are brought into a conductive state, and the potential of the wiring 112 (H level The signal IN1) is supplied to the wiring 211. As a result, the wiring 211 receives the signal IN2. Since the potential of the wiring 211 (signal IN1 at the H level) is supplied, the potential of the wiring 211 starts to rise. At this time, node 13 is in a floating state. The potential at node 13 increases due to the parasitic capacitance between the first terminal and the second terminal. The potential of the node 13 is V2 + Vth203 + Va. This is called bootstrap operation. In this way, the potential of the wiring 211 becomes V2, and the signal GOUT becomes H level. .

[0208] The operation of the semiconductor device in the period E will be described with reference to a schematic diagram in FIG. During period E, signal IN1 goes to L level, signal IN2 goes to H level, and the signal at node 13 The potential (signal IN3) becomes L level. Therefore, the circuit 100 performs operation 6 in FIG. 3(C). Therefore, the potential of the node 12 (signal OUT) becomes L level. Since the transistor 201 is turned off, the wiring 115 and the wiring 211 are not electrically connected. At this time, the potential of the node 13 becomes L level, and the transistor 203 is turned off. Therefore, the wiring 112 and the wiring 211 are not electrically connected. The timing when the potential of the node 13 decreases from the H level to the L level is In this case, when transistor 203 is on, That is, when the wiring 112 and the wiring 211 are in a conductive state, the signal IN1 is at the L level. Therefore, since the signal IN1 at L level is supplied to the wiring 211, the signal G OUT becomes L level.

[0209] 10(A) to (C), FIG. 14(A), FIG. 16(A), and FIG. 17(A). In this configuration, the gate of transistor 203 may be connected to node 12. Alternatively, the gate of transistor 201 can be connected to node 13. (Figure 47(A)).

[0210] 10(A) to (C), FIG. 14(A), FIG. 16(A), FIG. 17(A), and FIG. 47 In the configuration described in (A), the circuit 100 and the other transistors are connected to separate wirings. For example, as shown in FIG. 47B, the transistor 203 The first terminal can be connected to a wiring (wiring 112A) other than the wiring 112. Alternatively, the first terminal of the transistor 201 may be connected to a wiring other than the wiring 115 (the wiring 115 A) can be connected to the

[0211] Next, referring to FIGS. 10(A) to (C), 14(A), 16(A), 17(A), and 47 In the configurations described in (A) and (B), a transistor 204 can be newly provided. be.

[0212] FIG. 20A shows a structure in which a transistor 204 is newly provided in the semiconductor device of FIG. 17A. The transistor 204 is an N-channel transistor. Without being limited thereto, the transistor 204 can be a P-channel type. A first terminal of the transistor 204 is connected to the wiring 115, and a second terminal of the transistor 204 is connected to the wiring 115. , and the gate of transistor 204 is connected to node 12.

[0213] The function of the transistor 204 will be described. The transistor 204 is connected to the wiring 115 and the node The transistor 204 has a function of controlling electrical continuity between the wiring 11 and the gate 13. The wiring 11 has a function of controlling the timing at which the potential of the wiring 11 is supplied to the node 13. When a signal or voltage is input to the wiring 115, the transistor 204 The timing at which a signal or voltage is supplied to the node 13 is controlled. The transistor 204 controls the timing of supplying the L signal or voltage V1 to the node 13. Alternatively, the transistor 204 has a function of decreasing the potential of the node 13. As described above, the transistor 204 functions as a switch. It is noted that the transistor 204 can have all of the above functions. It is not necessary to set the potential of the node 12 (for example, the signal OUT) to the transistor 204. It is possible to control the

[0214] The operation of the semiconductor device in FIG. 20A will be described. As shown, the circuit 100 outputs an H signal, which turns on the transistor 204. Then, the wiring 115 and the node 13 are electrically connected, so that the potential of the wiring 115 (for example, the voltage V 1) is supplied to node 13. During periods B to E, circuit 100 outputs an L signal. Therefore, the transistor 204 is turned off. Therefore, the wiring 115 and the node 13 are not electrically connected. 20C shows a schematic diagram of the semiconductor device in FIG. 20A during the period B. The formula is shown below.

[0215] Next, Figs. 10(A) to (C), 14(A), 16(A), 17(A), and 20(A) ), and in the configuration described in Figures 47(A) to (B), a transistor 205 is newly provided. It is possible to do this.

[0216] FIG. 21A shows a structure in which a transistor 205 is newly provided in the semiconductor device of FIG. 17A. The transistor 205 is an N-channel transistor. Without being limited thereto, the transistor 205 can be a P-channel type. A first terminal of the transistor 205 is connected to the wiring 212, and a second terminal of the transistor 205 is connected to the wiring 212. , and the gate of the transistor 205 is connected to the wiring 212.

[0217] The signal input to the wiring 212 and the function of the wiring 212 will be described. The signal IN4 may function as a start pulse. Therefore, the wiring 212 can function as a signal line. A constant voltage can be supplied to the wire 212. Thus, the wire 212 is connected to the power supply. It is possible for it to function as a line.

[0218] If a plurality of semiconductor devices are connected, the wiring 212 may be connected to another semiconductor device (e.g. The wiring 212 is connected to the wiring 211 of the semiconductor device in the previous stage. , and can function as a scanning line, a selection line, a capacitance line, or a power supply line. , signal IN4 can function as a gate signal or a scanning signal.

[0219] The function of the transistor 205 will be described. The transistor 205 is connected to the wiring 212 and the node The transistor 205 has a function of controlling electrical continuity between the wiring 21 and the gate 13. The wiring 21 has a function of controlling the timing at which the potential of the wiring 21 is supplied to the node 13. When a signal or voltage is input to the wiring 212, the transistor 205 The timing at which a signal or voltage is supplied to the node 13 is controlled. The transistor 205 controls the timing of supplying the H signal or voltage V2 to the node 13. Alternatively, the transistor 205 does not supply a signal or voltage to the node 13. Alternatively, the transistor 205 may be configured to increase the potential of the node 13. Alternatively, the transistor 205 may be configured to keep the node 13 in a floating state. As described above, the transistor 205 functions as a switch, a diode, or It is possible to have the function of a diode-connected transistor. The transistor 205 does not need to have all of the above functions. is controlled by the potential of the wiring 212 (signal IN4) and / or the potential of the node 13. It is possible to do this.

[0220] The operation of the semiconductor device of FIG. 21(A) will be described with reference to FIG. 21(B). FIG. 1B) shows a timing chart that can be used in the semiconductor device of this embodiment mode. During period C, as shown in FIG. 22(A), signal IN4 goes to H level. Since the transistor 205 is turned on, electrical continuity is established between the wiring 212 and the node 13. Then, the potential of the wiring 212 (for example, the H-level signal IN4) is supplied to the node 13. As a result, the potential of node 13 starts to rise. After that, the potential of node 13 rises The potential of the gate of the transistor 205 (for example, V2) is converted into the threshold voltage (Vth20 5), the transistor 205 turns off. Therefore, the node 13 is in a floating state, and the potential of the node 13 is V2-Vth2. During periods A to B and D to E, the signal IN4 is kept at the L level. Therefore, the transistor 205 is turned off, and the wiring 212 and the node 13 are not electrically connected. 22B shows the operation of the semiconductor device of FIG. 21A during the period B. A schematic diagram of the above is shown.

[0221] Next, Figs. 10(A) to (C), 14(A), 16(A), 17(A), and 20(A) ), in the configuration described in FIG. 21(A) and FIG. 47(A)-(B), the transistor 20 It is possible to add a new number 6.

[0222] FIG. 23A shows a structure in which a transistor 206 is provided in the semiconductor device of FIG. The transistor 206 is an N-channel type. However, this embodiment is not limited to this. Transistor 206 may be a P-channel type. A first terminal of the transistor 206 is connected to the wiring 212, and a second terminal of the transistor 206 is connected to the The gate of the transistor 206 is connected to the wiring 113 .

[0223] The function of the transistor 206 will be described. The transistor 206 is connected to the wiring 212 and the node The transistor 206 has a function of controlling electrical continuity between the wiring 21 and the gate 13. The wiring 21 has a function of controlling the timing at which the potential of the wiring 21 is supplied to the node 13. When a signal or voltage is input to the wiring 212, the transistor 206 The timing at which a signal or voltage is supplied to the node 13 is controlled. The transistor 206 controls the timing of supplying the L signal or voltage V1 to the node 13. Alternatively, the transistor 206 may apply an H signal or a voltage V2 to the node 13. Alternatively, the transistor 206 has a function of controlling the timing of supplying the voltage to the node 1. The transistor 206 has a function of controlling the timing of decreasing the potential of the transistor 206. has a function of controlling the timing at which the potential of the node 13 is increased. The transistor 206 can function as a switch. The transistor 206 does not need to have all of the above functions. , can be controlled by the potential of the wiring 113 (for example, the signal IN2).

[0224] The operation of the semiconductor device in FIG. 23A will be described. As shown, the signal IN2 goes high, turning on the transistor 206. Since the wiring 212 and the node 13 are electrically connected, the potential of the wiring 212 (for example, H level The signal IN4) is supplied to the node 13. Thus, during the period C, the signal IN4 of the node 13 Since the potential change can be made steeper, the driving frequency of the semiconductor device can be increased. Cut.

[0225] In periods B and E, as in period C, signal IN2 is at H level. The transistor 206 is turned on, and therefore the wiring 212 and the node 13 are brought into electrical continuity. The potential of the wiring 212 (for example, the signal IN4 at the L level) is supplied to the node 13. In this way, during the period B, the potential of the node 13 can be fixed, which makes it resistant to noise. Alternatively, in the period E, the potential of the node 13 is lowered. Therefore, the transistor 203 can be turned off. 23A) shows a schematic diagram of the operation of the semiconductor device in FIG. 23A in the period B.

[0226] During period A, as shown in FIG. 24(B), signal IN2 becomes L level, and the transistor The resistor 206 is turned off, and therefore the wiring 212 and the node 13 are not electrically connected to each other. In this way, the transistor 206 is turned off, which prevents the transistor 206 from deteriorating. This can be done.

[0227] Next, Figs. 10(A) to (C), 14(A), 16(A), 17(A), and 20(A) ), in the configurations described in Figs. 21(A), 23(A), and 47(A)-(B), A transistor 207 can be newly provided.

[0228] FIG. 25A shows a structure in which a transistor 207 is newly provided in the semiconductor device of FIG. 17A. The transistor 207 is an N-channel transistor. Without being limited thereto, the transistor 207 can be a P-channel type. A first terminal of the transistor 207 is connected to the wiring 115, and a second terminal of the transistor 207 is connected to the wiring 115. , and the gate of the transistor 207 is connected to the wiring 213.

[0229] The signal input to the wiring 213 and the function of the wiring 213 will be described. The signal IN5 can function as a reset signal. Therefore, the wiring 213 can function as a signal line. A constant voltage can be supplied to the wiring 213. Therefore, the wiring 213 is a power supply line. It is possible for the device to have the function as a

[0230] If a plurality of semiconductor devices are connected, the wiring 213 may be connected to another semiconductor device (e.g. The wiring 213 is connected to the wiring 211 of the semiconductor device in the next stage. , and can function as a scanning line, a selection line, a capacitance line, or a power supply line. , signal IN5 can function as a gate signal or a scanning signal.

[0231] The function of the transistor 207 will be described. The transistor 207 is connected to the wiring 115 and the node The transistor 207 has a function of controlling electrical continuity between the wiring 11 and the gate 13. The wiring 11 has a function of controlling the timing at which the potential of the wiring 11 is supplied to the node 13. When a signal or voltage is input to the wiring 115, the transistor 207 The timing at which a signal or voltage is supplied to the node 13 is controlled. The transistor 207 controls the timing of supplying the L signal or voltage V1 to the node 13. Alternatively, the transistor 207 may be configured to decrease the potential of the node 13. As described above, the transistor 207 functions as a switch. It is possible for the transistor 207 to have all of the above functions. Note that the transistor 207 does not need to be connected to the potential of the wiring 213 (for example, the signal IN5). Thus, it can be controlled.

[0232] The operation of the semiconductor device of FIG. 25(A) will be described with reference to FIG. 25(B). FIG. 1B) shows a timing chart that can be used in the semiconductor device of this embodiment mode. During period E, as shown in FIG. 26(A), signal IN5 goes to H level. The transistor 207 is turned on, so that the wiring 115 and the node 13 are brought into electrical continuity. Then, the potential of the wiring 115 (for example, voltage V1) is supplied to the node 13. The potential of the node 13 decreases. During periods A to D, the signal IN5 is at the L level. Since the transistor 207 is turned off, the wiring 115 and the node 13 are not electrically connected to each other. 26B is a schematic diagram of the operation of the semiconductor device in FIG. 25A during the period B. show.

[0233] Next, Figs. 10(A) to (C), 14(A), 16(A), 17(A), and 20(A) ), the structure described in Fig. 21(A), Fig. 23(A), Fig. 25(A), and Fig. 47(A)-(B). In this configuration, the gate of the transistor 102 is connected to a wiring other than the node 13 (for example, wiring 21). 1, etc.).

[0234] In FIG. 27B, in the semiconductor device of FIG. 27A, the gate of the transistor 102 is , and is connected to the wiring 211. A large voltage is applied to the gate of the transistor 102. This prevents the transistor 102 from being broken down or degraded. It can be stopped.

[0235] Note that the semiconductor device in FIG. 27A is the semiconductor device in FIG. 14A with a transistor 20 This configuration adds new numbers 1 to 207.

[0236] Next, Figs. 10(A) to (C), 14(A), 16(A), 17(A), and 20(A) ), Fig. 21(A), Fig. 23(A), Fig. 25(A), Fig. 27(A)-(B), and Fig. 47( In the configurations described in A) and (B), the first terminal of the transistor 204 is connected to the wiring 115. is connected to another wire (e.g., wire 113, wire 212, wire 213, node 12, or node 1 3, etc. Alternatively, the gate of transistor 204 can be connected to a node It is possible to connect the signal line 112 to a wiring other than the signal line 12 (for example, the wiring 112).

[0237] FIG. 27C shows the first terminal of the transistor 204 in the semiconductor device of FIG. The gate of the transistor 204 is connected to a wiring 211, and the gate of the transistor 204 is connected to a wiring 112. In this way, the potential of the node 13 can be reduced during the period D. Therefore, the transistors connected to the node 13 (for example, the transistor 102, the transistor 203, transistor 205, or transistor 206, etc.) Alternatively, the deterioration of these transistors can be suppressed.

[0238] Next, Figs. 10(A) to (C), 14(A), 16(A), 17(A), and 20(A) ), Fig. 21(A), Fig. 23(A), Fig. 25(A), Fig. 27(A) to (C), and Fig. 47( In the configurations described in A) and (B), the first terminal of the transistor 205 is connected to the wiring 212. can be connected to other wirings (for example, wiring 113, wiring 116, etc.). Alternatively, the gate of the transistor 205 may be connected to a wiring other than the wiring 212 (for example, the wiring 113, It is possible to connect the wiring 116, etc.

[0239] FIG. 28A shows the first terminal of the transistor 205 in the semiconductor device of FIG. 11 shows a configuration in which the terminal is connected to wiring 116.

[0240] Next, Figs. 10(A) to (C), 14(A), 16(A), 17(A), and 20(A) ), Figure 21(A), Figure 23(A), Figure 25(A), Figure 27(A)-(C), Figure 28(A) , and in the configuration described in FIG. 47(A)-(B), the second terminal of the transistor 207 is , and a wiring other than node 13 (for example, wiring 211, node 11, or node 12, etc.). Alternatively, the first terminal of the transistor 207 can be connected to the wiring 115. and a different wiring (for example, wiring 112, wiring 116, node 11, or node 12). It is possible to connect.

[0241] FIG. 28B shows the second terminal of the transistor 207 in the semiconductor device of FIG. The wiring 115 is connected to the wiring 211. In the period E, the potential of the wiring 115 (for example, Voltage V1) can be supplied to wiring 211 via transistor 207. Therefore, the fall time of the signal GOUT can be shortened.

[0242] Next, Figs. 10(A) to (C), 14(A), 16(A), 17(A), and 20(A) ), Figure 21(A), Figure 23(A), Figure 25(A), Figure 27(A)-(C), Figure 28(A) 47(A)-(B), the first transistor 201 The terminals are connected to wirings other than the wiring 115 (for example, wiring 113, wiring 212, wiring 213, Node 12, or node 13, etc. Alternatively, the transistor The first terminal of 202 is connected to a wiring other than the wiring 115 (for example, the wiring 112 or the node 12). Alternatively, the first terminal of the transistor 204 may be connected to a wiring 115 (for example, the wiring 113, the wiring 212, the wiring 213, the node 12, or Node 13, etc.) of the first transistor 207. The terminal is connected to a wiring other than the wiring 115 (for example, the wiring 112, the wiring 116, the wiring 212, the Each terminal of each transistor can be connected to the corresponding terminal shown in the figure. In addition to the above, it is possible to connect to various wirings.

[0243] FIG. 28C shows the first terminal of the transistor 201 in the semiconductor device of FIG. The first terminal of the transistor 202 is connected to the wiring 113. The first terminal of the transistor 204 is connected to the wiring 113, and the second terminal of the transistor 207 is connected to the wiring 113. The terminal 1 is connected to the wiring 112. 02, an H signal is input to the first terminals of the transistors 204 and 207. This makes it possible to suppress the deterioration of these transistors.

[0244] Next, Figs. 10(A) to (C), 14(A), 16(A), 17(A), and 20(A) ), Figure 21(A), Figure 23(A), Figure 25(A), Figure 27(A)-(C), Figure 28(A) 47(A)-(B), the transistor is replaced with a diode. For example, the transistor can be diode-connected. It is Noh.

[0245] FIG. 29(A) shows the semiconductor device of FIG. 27(A) in which the transistor is replaced with a diode. The transistor 201 has one electrode (for example, an input terminal) connected to a wiring. 211 and the other electrode (for example, an output terminal) of a diode connected to node 12. Alternatively, the transistor 202 can be replaced by one of the One electrode (for example, an input terminal) is connected to the wiring 211, and the other electrode (for example, an output terminal) is connected to the wiring 1 13. Alternatively, the transistor 202d may be replaced by a diode 202d connected to the transistor 13. The transistor 203 has one electrode (for example, an input terminal) connected to the node 13 and the other electrode (for example, output terminal) is replaced with a diode 203d connected to the wiring 211 Alternatively, the transistor 204 may be configured such that one electrode (for example, an input terminal) is connected to a node 13, and the other electrode (for example, an output terminal) of a diode 2 connected to node 12. Alternatively, the transistor 205 may be replaced by a transistor 04d. (for example, an input terminal) is connected to the wiring 212, and the other electrode (for example, an output terminal) is connected to the node 1 3. Alternatively, the transistor 205 may be replaced by a diode 205d connected to the The resistor 207 has one electrode (for example, an input terminal) connected to the node 13 and the other electrode ( For example, the output terminal may be replaced with a diode 207d connected to the wiring 213. This allows the number of signals or power supplies to be reduced. Therefore, the substrate on which the semiconductor device of this embodiment is formed and the The number of connections to the board for supplying signals can be reduced, improving reliability and yield. This can improve the reliability and reduce the manufacturing cost. Some of the transistors can be replaced with diodes.

[0246] FIG. 29B shows a semiconductor device in which the transistor is diode-connected in the semiconductor device in FIG. For example, the first terminal of the transistor 201 is connected to the node 12. The gate of the transistor 201 is connected to a wiring 211. A first terminal of the transistor 202 is connected to the wiring 113, and a gate of the transistor 202 is connected to the wiring 114. Alternatively, for example, the first terminal of transistor 203 is connected to node 1 3, and the gate of transistor 203 is connected to node 13. For example, the first terminal of the transistor 204 is connected to the node 12, and the The gate is connected to node 13, or, for example, the first terminal of transistor 207. is connected to the wiring 213, and the gate of the transistor 207 is connected to the node 13. In this way, the number of signals or power supplies can be reduced, i.e., the number of wirings can be reduced. Therefore, the substrate on which the semiconductor device of this embodiment is formed and the substrate on which signals are supplied are This reduces the number of connections to the board for the purpose of improving reliability and yield. This can reduce manufacturing costs. The transistors may be diode-connected.

[0247] FIG. 29(C) shows the semiconductor device of FIG. 27(A) in which a P-channel transistor is The transistor 201p, the transistor 202p, and the transistor 203p are connected in a diode-connected configuration. Transistor 203p, transistor 204p, transistor 205p, transistor 207 p are transistors 201, 202, 203, and The transistor 204, the transistor 205, and the transistor 207 have the same functions as each other, and are P-channel. The semiconductor device in FIG. 29(C) has the same connection relationship as the semiconductor device in FIG. 29(B). However, in order to connect the transistor in a diode, the semiconductor device shown in FIG. In comparison, the gate of transistor 201p is connected to node 12, and the gate of transistor 201p is connected to node 13. The gate of transistor 202p is connected to wiring 113, and the gate of transistor 203p is connected to wiring 211. The gate of transistor 204p is connected to node 12, and the gate of transistor 205 The gate of transistor 207p is connected to node 13, and the gate of transistor 207p is connected to wiring 213. This allows the number of signals or power supplies to be reduced. Therefore, the number of lines can be reduced. This reduces the number of connections to the board that supply signals to the board, improving reliability. Furthermore, it is possible to improve the yield and reduce the manufacturing cost. Some of the transistors may be diode-connected.

[0248] Next, Figs. 10(A) to (C), 14(A), 16(A), 17(A), and 20(A) ), Figure 21(A), Figure 23(A), Figure 25(A), Figure 27(A)-(C), Figure 28(A) 29(A)-(C), and 47(A)-(B), Each terminal or electrode of the transistor can be connected to a separate wiring. a first terminal of the transistor 101, a first terminal of the transistor 104, and a first terminal of the transistor The first terminal of 203 can be connected to a separate wiring. The gate of the transistor 103, the gate of the transistor 105, and the gate of the transistor 202 The gate can be connected to a separate wiring. a first terminal of transistor 102, a first terminal of transistor 105, and a first terminal of transistor 201; a first terminal of the transistor 202; a first terminal of the transistor 204; The first terminal of the transistor 207 can be connected to a separate wiring. For example, the first terminal of the transistor 205 and the first terminal of the transistor 206 are To achieve this, the wiring can be divided into multiple wirings. It is possible to divide it.

[0249] In FIG. 30(A), in the semiconductor device of FIG. 27(A), the wiring 112 includes wirings 112A to The wiring 113 is divided into a plurality of wirings 113A to 113D. The wiring 115 is divided into a plurality of wirings 115A to 115G. The wiring 212 is divided into a plurality of wirings, ie, wirings 212A to 212B. The first terminal of the transistor 201 is connected to the wiring 115D. The first terminal of the transistor 202 is connected to the wiring 115E. The first terminal of the transistor 203 is connected to the wiring 113C. 2C. Alternatively, the first terminal of the transistor 204 is connected to the wiring 115F. Alternatively, the first terminal and the gate of the transistor 205 are connected to the wiring 212A. Alternatively, the first terminal of the transistor 206 is connected to the wiring 212B. The gate of the transistor 206 is connected to the wiring 113D. The first terminal of the transistor 7 is connected to the wiring 115G.

[0250] The wirings 112A to 112C can have the same function as the wiring 112. Alternatively, the wirings 113A to 113D may have the same function as the wiring 113. Alternatively, the wirings 115A to 115G may have the same function as the wiring 115. Alternatively, the wirings 212A to 212B may have the same function as the wiring 212. Therefore, the signal IN1 can be input to the wirings 112A to 112C. Alternatively, the signal IN2 can be input to the wirings 113A to 113D. Alternatively, the voltage V1 can be supplied to the wirings 115A to 115G. A signal IN4 can be input to the wirings 212A and 212B. 112C may be supplied with separate voltages or separate signals. The lines 113A to 113D can be supplied with different voltages or different signals. Alternatively, different voltages or different signals can be supplied to the wirings 115A to 115G. Alternatively, different voltages or different signals may be supplied to the wirings 212A and 212B. It is possible.

[0251] Next, Figs. 10(A) to (C), 14(A), 16(A), 17(A), and 20(A) ), Figure 21(A), Figure 23(A), Figure 25(A), Figure 27(A)-(C), Figure 28(A) 29(A)-(C), FIG. 30(A), and FIG. 47(A)-(B). In the structure, some transistors can be omitted. It is possible to omit one of the transistors 201 and 204. Alternatively, for example, Assume that the semiconductor device has a transistor 206. In this case, the transistor 205 and the transistor It is possible to omit either or both of the transistor 207. It is possible to omit some of the transistors.

[0252] FIG. 30B shows a semiconductor device in FIG. 27A in which the transistor 201 and the transistor The figure shows a configuration in which the transistor 205 is omitted. Since the number of transistors is reduced, the layout area is reduced. Alternatively, the power consumption can be reduced.

[0253] Next, Figs. 10(A) to (C), 14(A), 16(A), 17(A), and 20(A) ), Figure 21(A), Figure 23(A), Figure 25(A), Figure 27(A)-(C), Figure 28(A) ~(C), Figures 29(A)~(C), Figures 30(A)~(B), and Figures 47(A)~(B). In the configuration to be described, a capacitor 220 connected between the node 13 and the wiring 211 is newly added. It is possible to provide it in.

[0254] 30C shows the semiconductor device of FIG. 17A, in which a connection is made between the node 13 and the wiring 211. This shows a configuration in which a capacitive element 220 is newly provided. During the flip-flop operation, the potential of the node 13 tends to rise. As a result, the channel width of the transistor 203 can be reduced. Alternatively, the fall time or rise time of the signal GOUT can be shortened. For example, a MOS capacitor can be used as the capacitance element.

[0255] Next, Figs. 10(A) to (C), 14(A), 16(A), 17(A), and 20(A) ), Figure 21(A), Figure 23(A), Figure 25(A), Figure 27(A)-(C), Figure 28(A) ~(C), Figures 29(A)~(C), 30(A)~(C), and 47(A)~(B). In the described configuration, it is possible to generate a signal other than the signal GOUT, for example: The semiconductor device of this embodiment generates a signal SOUT in addition to the signal GOUT. For example, if a plurality of semiconductor devices are connected, the signal SOUT is It is possible that the signal is not output to the line 211 but is input as a start pulse to a semiconductor device in another stage. Therefore, the delay or distortion of the signal SOUT is small compared to the signal GOUT. Therefore, it is possible to drive a semiconductor device using a signal with little delay or distortion. Therefore, the delay of the output signal of the semiconductor device can be reduced. 14(A), 16(A), 17(A), 20(A), 21(A), and 23 (A), Figure 25(A), Figure 27(A)~(C), Figure 28(A)~(C), Figure 29(A)~ (C), in the configurations described in Figs. 30(A) to (C) and Figs. 47(A) to (B), A new resistor 208 can be provided.

[0256] FIG. 31A shows a structure in which a transistor 208 is newly provided in the semiconductor device of FIG. 17A. The transistor 208 can have the same function as the transistor 203. The first terminal of the transistor 208 is connected to the wiring 112, and the second terminal of the transistor 208 is connected to the wiring 112. The second terminal of the transistor 208 is connected to the wiring 214, and the gate of the transistor 208 is connected to the wiring 214. The wiring 214 may have a function similar to that of the wiring 211. For example, if a plurality of semiconductor devices are connected, the wiring 211 can be It is possible to connect with the wiring 212 of the semiconductor device (for example, the semiconductor device of the next stage). For example, as shown in FIG. 31(B), a transistor 209 can be newly provided. The transistor 209 can have the same function as the transistor 203. The first terminal of the transistor 209 is connected to the wiring 115. The second terminal of the transistor 209 is connected to the wiring 214, and the second terminal of the transistor 209 is connected to the wiring 214. The gate of O9 is connected to node 12. Note that in FIG. 31(C), the signal GOUT Separately, a timing chart for generating the signal SOUT is shown.

[0257] As described above, this embodiment is not limited to the configuration shown in FIG. 14A, and various other configurations can be used. It is possible to use the configuration.

[0258] Next, Figs. 10(A) to (C), 14(A), 16(A), 17(A), and 20(A) ), Figure 21(A), Figure 23(A), Figure 25(A), Figure 27(A)-(C), Figure 28(A) ~(C), Figures 29(A)~(C), Figures 30(A)~(C), Figures 31(A)~(B), and In the configuration shown in FIGS. 47(A) and 47(B), a P-channel transistor is used. Only some of the transistors included in the semiconductor device can be used. It is possible for the semiconductor device of this embodiment to be of the P-channel type. It can be a circuit.

[0259] FIG. 32(A) shows a semiconductor device in FIG. 27(A) in which a P-channel transistor is used. The transistors 201p to 207p are transistors. It has the same function as the resistors 201 to 207 and is a P-channel type. A voltage V2 is supplied to 115. As shown in the timing chart of FIG. As shown in FIG. 1, the potential of the signal IN1, the signal IN2, the signal IN4, the signal IN5, the potential of the node 11, the potential of the node 1 It should be noted that the potential of node 2, the potential of node 13, and the signal GOUT can be inverted. Write down.

[0260] Next, the ratio of the channel widths of the transistors 201 to 209 and the size of the transistors will be described. and explain.

[0261] First, the transistor 201 supplies a potential to the wiring 211. is greater than the load at node 12. Therefore, the channel width of transistor 201 is The channel width of the transistor 100 is larger than that of the transistor 100. The channel width of 201 is preferably 10 times or less than the channel width of transistor 101. It is more preferable that the ratio is 5 times or less, and even more preferable that the ratio is 3 times or less. It is preferable that there is.

[0262] Next, the potential of the gate of the transistor 202 is lower than the potential of the gate of the transistor 201. Therefore, the channel width of the transistor 202 is changed sharply. In this case, the channel width of the transistor 201 is preferably smaller than the The width is preferably 10 times or less the channel width of the transistor 202. It is preferably 7 times or less, and more preferably 5 times or less. stomach.

[0263] Next, the transistor 203 supplies a potential to the wiring 211. The potential is changed. Then, the wiring 211 has a large load (for example, a gate signal line, a pixel, Therefore, the channel of the transistor 203 is The width of the transistor is the largest among the transistors included in the semiconductor device of this embodiment. The channel width of the transistor 203 is preferably 10 times or less than that of the transistor 201. It is more preferable that the ratio is 5 times or less, and even more preferable that the ratio is 2 times or less. It is preferable that

[0264] Then, the transistor 204 supplies a potential to the node 13. Then, the load of the node 13 is greater than the load at node 12. Therefore, the channel width of transistor 204 is In this case, the channel width of the transistor 201 is Preferably, the channel width of the transistor 204 is five times or less than the channel width of the transistor 204. Preferably, it is 3 times or less, and more preferably, it is 2 times or less. It's nice.

[0265] Next, by increasing the channel width of the transistor 205, Since the change in potential of the node 13 can be made steep, the driving frequency of the semiconductor device can be increased. Therefore, the channel width of the transistor 205 can be set to be equal to that of the transistor 201 or is larger than the channel width of the transistor included in the circuit 100. The channel width of transistor 05 is smaller than the channel width of transistor 203. In this case, The channel width of transistor 203 is 10 times or less than the channel width of transistor 205. It is more preferable that the ratio is 5 times or less. , preferably 2 times or less.

[0266] Next, the transistor 206 supplies a potential to the node 13, Therefore, the channel width of the transistor 206 is In such a case, the channel width of transistor 205 is smaller than the channel width of transistor 205. It is preferable that the width is three times or less the channel width of the star 206. More preferably, it is two times or less. It is more preferable that the ratio is 1.8 times or less.

[0267] Next, the transistor 207 supplies a potential to the node 13, However, by slowing down the decrease in the potential of node 13, Thus, in period E, transistor 203 can be turned on. Since the transistor 203 can supply a potential to the wiring 211, Therefore, the channel width of the transistor 207 is In such a case, the channel width of transistor 205 is preferably smaller than that of transistor 205. The channel width of transistor 05 is preferably 10 times or less than the channel width of transistor 207. More preferably, it is 7 times or less, and even more preferably, it is 5 times or less. It is preferable that

[0268] Next, the transistor 208 supplies a potential to the wiring 214. is smaller than the load of the wiring 211. In this case, the channel width of the transistor 203 is The channel width is preferably 10 times or less than that of transistor 208. More preferably, It is preferably 100 times or less, and more preferably 4 times or less.

[0269] Next, the transistor 209 supplies a potential to the wiring 214. is smaller than the load of the wiring 211. In this case, the channel width of the transistor 203 is The channel width of the transistor 209 is preferably seven times or less than the channel width of the transistor 209. Preferably, it is 4 times or less, and more preferably, it is 2.5 times or less. Desirable.

[0270] In addition, when the ratio of the channel widths of the above transistors is taken into consideration, the channel width of the transistor 201 is The width of the panel is preferably 1000 μm or more and 5000 μm or less. The channel width of the transistor 201 is 1500 μm or more and 4000 μm or less. More preferably, the channel width of the transistor 201 is 2000 μm or more, and Alternatively, the channel width of the transistor 202 is preferably 2000 μm or less. It is preferable that the thickness is 300 μm or more and 3000 μm or less. It is preferable that the thickness is 400 μm or more and 2000 μm or less. Alternatively, the channel width of the transistor 203 is preferably 2000 μm or less. It is preferable that the thickness is 3000 μm or more and 30,000 μm or less. It is preferable that the thickness is 15,000 μm or more and 4,000 μm or less. Preferably, the channel of the transistor 204 is 10,000 μm or less. The width is preferably 200 μm or more and 2500 μm or less. It is preferable that the thickness is 0 μm or more and 2000 μm or less. More preferably, it is 700 μm or less. Preferably, the channel width of the transistor 205 is 1500 μm or less. is preferably 500 μm or more and 3000 μm or less. It is preferable that the thickness is 2500 μm or more and 1500 μm or less. Preferably, the channel width of the transistor 206 is 2000 μm or less. The thickness is preferably 300 μm or more and 2000 μm or less. It is preferable that the thickness is 800 μm or more and 1500 μm or less. The channel width of the transistor 207 is preferably 1.5 μm or less. It is preferable that the thickness is 100 μm or more and 1500 μm or less. More preferably, it is 300 μm or less. It is preferable that the thickness is 400 μm or more and 1000 μm or less. Alternatively, the channel width of the transistor 208 is preferably 300 μm or less. It is preferable that the thickness is 500 μm or more and 5000 μm or less. It is preferably 2000 μm or less, and more preferably 800 μm or more, and 1500 μm or less. Alternatively, the channel width of the transistor 209 is preferably 200 μm or less. It is preferable that the thickness of the transistor 209 is 2000 μm or more. The channel width is preferably 400 μm or more and 1500 μm or less. The channel width of the transistor 209 is 500 μm or more and 1000 μm or less. is preferred.

[0271] (Embodiment 3) In this embodiment, a display device, a pixel included in the display device, and a shift register included in the display device will be described. The shift register circuit will be described. It is possible to have the semiconductor device described in the second embodiment.

[0272] First, the display device will be described with reference to Figures 33(A) to 33(D). 1001, a circuit 1002, a circuit 1003_1, a pixel portion 1004, and a terminal 1005. In the pixel portion 1004, a plurality of wirings are arranged extending from the circuit 1003_1. The plurality of wirings can function as gate signal lines or scanning lines. Alternatively, a plurality of wirings may be arranged in the pixel portion 1004, extending from the circuit 1002. The plurality of wirings can function as video signal lines or data lines. Then, a plurality of wirings extending from the circuit 1003_1 and a plurality of wirings extending from the circuit 1002 are arranged. A plurality of pixels are arranged corresponding to a plurality of wirings extending from the pixel. Various other wirings can be arranged in the section 1004. The wirings are The wiring can function as a signal line, a data line, a power supply line, a capacitance line, or the like.

[0273] Note that the circuit 1001 does not transmit a signal, a voltage, a current, or the like to the circuit 1002 and the circuit 1003. Alternatively, the circuit 1001 may be a circuit 1002 or a circuit 1003. In this way, the circuit 1001 has a function of controlling a controller, a control circuit, a timing It can function as a power generator, power supply circuit, regulator, etc. be.

[0274] The circuit 1002 has a function of supplying a video signal to the pixel portion 1004. The circuit 1002 has a function of controlling the luminance or transmittance of a pixel included in the pixel portion 1004. In this way, the circuit 1002 is a driver circuit, a source driver, a signal line driver circuit, or the like. It has the function of:

[0275] The circuit 1003_1 and the circuit 1003_2 supply a scanning signal or a gate signal to the pixel portion 1 004. Alternatively, the circuit 1003_1 and the circuit 1003_2 may The pixel selector 1004 has a function of selecting a pixel. The circuit 1003_2 has a function as a driver circuit, a gate driver, or a scanning line driver circuit. Note that the circuits 1003_1 and 1003_2 can drive the same wiring. For example, if the circuit 1003_1 is an odd-numbered stage, The first gate signal line is driven by the circuit 1003_1, and the second gate signal line is driven by the circuit 1003_2. is possible.

[0276] Note that the circuit 1001, the circuit 1002, the circuit 1003_1, and the circuit 1003_2 are pixels. It can be formed on the same substrate 1006 as the pixel portion 1004, or it can be formed separately from the pixel portion 1004. The semiconductor device can be formed on a substrate (such as a semiconductor substrate or an SOI substrate).

[0277] In FIG. 33A, a circuit 1003_1 is formed on the same substrate 1006 as a pixel portion 1004. The circuit 1001 and the circuit 1002 are formed on a substrate different from that of the pixel portion 1004 . The driving frequency of the circuit 1003_1 is slower than that of the circuit 1001 or the circuit 1002. As a semiconductor layer of a transistor, a non-single-crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an oxide semiconductor, As a result, it becomes easier to use semiconductors such as carbide and organic semiconductors. The display device can be manufactured at low cost.

[0278] In FIG. 33B, the circuit 1003_1 and the circuit 1003_2 are mounted on the same substrate as the pixel portion 1004. 1006, and the circuit 1001 and the circuit 1002 are formed on a substrate different from the pixel portion 1004. The driving frequencies of the circuit 1003_1 and the circuit 1003_2 are 1001 or the circuit 1002. Therefore, the semiconductor layer of the transistor is Use of crystalline semiconductors, amorphous semiconductors, microcrystalline semiconductors, oxide semiconductors, organic semiconductors, etc. As a result, the display device can be made larger. It is possible.

[0279] In FIG. 33C, the circuit 1002, the circuit 1003_1, and the circuit 1003_2 are included in the pixel portion 1. 1004, and the circuit 1001 is formed on a substrate different from the pixel portion 1004. The resulting configuration is shown below.

[0280] FIG. 33D shows a circuit 1002a, a circuit 1003_1, and a circuit 1003_2 is formed on the same substrate 1006 as the pixel portion 1004, and the circuit 1001 and the circuit 1002 are formed on the same substrate 1006 as the pixel portion 1004. 10 shows a configuration in which a circuit 1002b of another part of the pixel part 1004 is formed on a substrate different from that of the pixel part 1004. In this case, the circuit 1002a may include a switch, a shift register, and / or a selector. It is possible to use a circuit with a low driving frequency such as a diode.

[0281] Next, the pixel included in the pixel portion 1004 will be described with reference to FIG. The pixel 020 includes a transistor 3021 , a liquid crystal element 3022 , and a capacitor 3023 . A first terminal of the transistor 3021 is connected to a wiring 3031. The second terminal of the capacitor 3023 is connected to one electrode of the liquid crystal element 3022 and one electrode of the capacitor 3023. The gate of the transistor 3021 is connected to a wiring 3032. The other electrode of the capacitor 3023 is connected to the electrode 3034. Connected to 033.

[0282] A video signal is input to the wiring 3031 from the circuit 1002 described in FIGS. 33(A) to 33(D). Therefore, the wiring 3031 functions as a signal line, a video signal line, or a source signal line. The wiring 3032 may include the circuit 10 described in FIGS. A scan signal, a selection signal, or a gate signal is input from the circuit 1003_1 and / or the circuit 1003_2. Therefore, the wiring 3032 functions as a signal line, a scanning line, or a gate signal line. The wiring 3033 and the electrode 3034 may have the following configurations as shown in FIGS. A constant voltage can be supplied from the circuit 1001 described later. 3 can function as a power supply line or a capacitance line. 4 can function as a common electrode or a counter electrode. A precharge voltage can be supplied to the 031. The voltage is approximately equal to the voltage supplied to the electrode 3034. Thus, a signal can be input to the liquid crystal element 3022. This makes it possible to control the video signal amplitude and realize inversion driving. As another example, a signal can be input to electrode 3034. In this way, frame inversion driving can be realized.

[0283] The transistor 3021 is electrically connected to the wiring 3031 and one electrode of the liquid crystal element 3022. Or, it has a function to control the timing of writing a video signal to the pixel. In this way, the transistor 3021 functions as a switch. The liquid crystal element 3023 is connected to the potential of one electrode of the liquid crystal element 3022 and the potential of the wiring 3033. Alternatively, the voltage applied to the liquid crystal element 3022 can be kept constant. In this way, the capacitor 3023 functions as a storage capacitor. It has.

[0284] Next, the shift register circuit will be described with reference to FIG. The path may be included in the circuit 1002, the circuit 1003_1, and / or the circuit 1003_2. is possible.

[0285] The shift register circuit 1100 includes flip-flop circuits 1101_1 to 1101_N (N The flip-flop circuit 1 101_1 to 1101_N are the semiconductors described in the first and second embodiments, respectively. The device can be used.

[0286] The shift register circuit 1100 includes wirings 1111_1 to 1111_N, a wiring 1112, and a wiring 1113, wiring 1114, wiring 1115, and wiring 1116. In a flip-flop circuit 1101_i (i is a natural number from 1 to N), 11 is connected to the wiring 1111_i, the wiring 112 is connected to the wiring 1112, and the wiring 1 13 is connected to the wiring 1113, the wiring 212 is connected to the wiring 1111_i-1, and the wiring The line 213 is connected to the line 1111_i+1, and the line 115 is connected to the line 1115. However, odd-numbered flip-flop circuits and even-numbered flip-flop circuits In the flip-flop circuit 110, the wiring 112 and the wiring 113 are connected to the opposite ends of the wiring 112 and the wiring 113. In the flip-flop circuit 1_1, the wiring 212 is connected to the wiring 1114. In the path 1101_N, the wiring 213 is connected to the wiring 1116.

[0287] Next, we will explain examples of signals or voltages input or output to each wiring, and the functions of each wiring. The wirings 1111_1 to 1111_N output signals GOUT_1 to GOUT_N, respectively. The signals GOUT_1 to GOUT_N are output from the flip-flop circuits 110. It is often an output signal of 1_1 to 1101_N and has the same function as the signal GOUT Therefore, the wirings 1111_1 to 1111_N have the same function as the wiring 211. A signal GCK1 is input to the wiring 1112, and a signal GCK2 is input to the wiring 1111. The signal GCK2 is input to the input terminal 3. The signal GCK1 is the same as the signal IN2 or the signal IN3. The signal GCK2 can have the same function as the signal IN2 or the signal IN3. Therefore, the wiring 1112 can have the same function as the wiring 112 or the wiring 113. The wiring 1113 can have the same function as the wiring 112 or the wiring 113. The signal GSP is input to the wiring 1114. GSP can have the same function as signal IN4. Therefore, line 1114 The wiring 1115 can have the same function as the wiring 212. The wiring 1115 is supplied with a voltage V1. Therefore, the wiring 1115 can have the same function as the wiring 115. A signal GRE is input to the wiring 1116. The signal GRE has the same function as the signal IN5. Therefore, the wiring 1116 has the same function as the wiring 213. It is possible.

[0288] Next, the operation of the shift register circuit in FIG. 34 during one frame period will be explained with reference to the timing in FIG. This will be explained with reference to the timing chart.

[0289] For example, if the signal GOUT_i-1 becomes H level, the flip-flop circuit 1101_i starts operation in period C. Then, the signal GCK1 and the signal GC When K2 is inverted, the flip-flop circuit 1101_i starts its operation in the period D. Therefore, the signal GOUT_i becomes H level. The flip-flop circuit 1101_i+1 is , the operation in period C begins. After that, the signals GCK1 and GCK2 are inverted. Then, the flip-flop circuit 1101_i+1 starts operation in the period D. , the signal GOUT_i+1 becomes H level. The signal GOUT_i+1 is The flip-flop circuit 1101_i receives the signal Therefore, the signal GOUT_i becomes L level. Every time the signals CK1 and GCK2 are inverted, the flip-flop circuit 1101_i The operation in period A and the operation in period B are alternately repeated. In FIG. 35, one of the signals GCK1 and GCK2 is maintained at the L level. Marked with K.

[0290] The shift register of this embodiment is the same as the semiconductor device described in the first and second embodiments. Therefore, the H level values ​​of the signals GOUT_1 to GOUT_N can be can be increased to V2, so the time that the transistor in the pixel is turned on As a result, the video signal can be written to the pixel in sufficient time. Therefore, the display quality can be improved. The fall and rise times of the This prevents a video signal for a pixel in a different row from being written to a pixel in the same row. As a result, the display quality can be improved. Since the variation in the fall time of GOUT_N can be suppressed, the pixel Therefore, the influence of feedthrough on the video signal can be reduced. It is possible to suppress display irregularities such as crosstalk. This reduces the load on the shift register (for example, parasitic capacitance). As a result, an external device having a function of supplying a signal or voltage to the shift register can be provided. Since the current supply capacity of the circuit can be reduced, the size of the external circuit or the The size of the display device with external circuitry can be reduced.

[0291] (Fourth embodiment) In this embodiment, a signal line driver circuit will be described. It can be referred to as a device or a signal generating circuit.

[0292] First, the configuration of the signal line driver circuit will be described with reference to FIG. The circuit includes a circuit 2001 and a circuit 2002. The circuit 2002 includes circuits 2002_1 to 2002_2. It has multiple circuits named 2002_N (N is a natural number). Circuits 2002_1 to 2002_ N represents a plurality of transistors 2003_1 to 2003_k (k is a natural number). The transistors 2003_1 to 2003_k are N-channel transistors. However, the present invention is not limited to this, and the transistors 2003_1 to 2003_k may be P-channel type. It is possible to use a CMOS type switch.

[0293] The connection relationship of the signal line driver circuit will be described using the circuit 2002_1 as an example. The first terminals of the terminals 2003_1 to 2003_k are connected to the wirings 2004_1 to 2004_k, respectively. The second terminals of the transistors 2003_1 to 2003_k are connected to the wiring S The gates of the transistors 2003_1 to 2003_k are connected to the wiring 20 Connected to 05_1.

[0294] The circuit 2001 is a timing circuit that outputs H-level signals to the wirings 2005_1 to 2005_N in order. Alternatively, the circuits 2002_1 to 2002_N may be selected in order. In this way, the circuit 2001 has a function as a shift register. The circuit 2001 sends H-level signals to the wirings 2005_1 to 2005_N in various orders. Alternatively, the circuits 2002_1 to 2002_N can be selected in various orders. In this way, the circuit 2001 has a function as a decoder. It is possible.

[0295] The circuit 2002_1 is a timing circuit in which the wirings 2004_1 to 2004_k and the wirings S1 to Sk are electrically connected. The circuit 2002_1 has a function of controlling the timing. The timing at which the potentials of 004_k are supplied to the wirings S1 to Sk is controlled. In this way, the circuit 2002_1 can have a function as a selector. The circuits 2002_2 to 2002_N can have the same function as the circuit 2002_1. is.

[0296] The transistors 2003_1 to 2003_N are connected to the wirings 2004_1 to 2004_k, respectively. The transistor has a function of controlling the timing at which the wirings S1 to Sk are electrically connected to each other. 2003_1 to 2003_N respectively connect the potentials of the wirings 2004_1 to 2004_k to the wirings S 1 to Sk. For example, the transistor 2003 _1 has a function of controlling the timing at which the wiring 2004_1 and the wiring S1 are electrically connected. Alternatively, the transistor 2003_1 may be a transistor for supplying the potential of the wiring 2004_1 to the wiring S1. In this way, the transistors 2003_1 to 2003_ Each of N can function as a switch.

[0297] Signals are input to the wirings 2004_1 to 2004_k. It is an analog signal corresponding to image information or an image signal. Thus, the signal is called a video signal. Therefore, the wirings 2004_1 to 2004_k can have the function of: For example, depending on the pixel configuration, it can function as a digital signal line. It can be a signal, it can be an analog voltage, it can be an analog current It is possible that:

[0298] Next, the operation of the signal line driver circuit of FIG. 36(A) will be explained with reference to the timing chart of FIG. 36(B). 36B shows signals 2015_1 to 2015_N and 2014_1 to 2014_k. Signals 2015_1 to 2015_N are respectively 001, and signals 2014_1 to 2014_k are output from the wiring 2004_1 1 operation period of the signal line driver circuit is One gate selection period corresponds to a period T0 and a period T1. The period T0 is divided into periods T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22, T23, T24, T25, T26, T27, T28, T29, T30, T31, T32, This is the period during which voltage is applied simultaneously, and can function as a precharge period. The periods T1 to TN are periods during which video signals are written to pixels belonging to selected rows. This is a period for writing data, and can function as a writing period.

[0299] First, in the period T0, the circuit 2001 supplies the H level to the wirings 2005_1 to 2005_N. Then, for example, in the circuit 2002_1, the transistor 200 3_1~2003_k will be turned on, so wiring 2004_1~2004_k and wiring S1 At this time, the wirings 2004_1 to 2004_k are in a conductive state. Therefore, the precharge voltage Vp is supplied to the transistor 2003. 1 to 2003_k and output to the wirings S1 to Sk, respectively. The voltage Vp is written to the pixels in the selected row. The element is precharged.

[0300] During the period T1 to the period TN, the circuit 2001 transmits an H-level signal to the wirings 2005_1 and 2005_2. For example, in the period T1, the circuit 2001 outputs a signal of H level. A signal is output to the wiring 2005_1. Then, the transistors 2003_1 to 2003_k is turned on, so that the wiring 2004_1 to 2004_k and the wiring S1 to Sk are in a conductive state. At this time, the wiring 2004_1 to 2004_k are connected to Data(S1) to Data( Data(S1) to Data(Sk) are input to the transistors 20 Among the pixels belonging to the selected row via 03_1 to 2003_k, the pixels in the 1st to kth columns In this way, in the periods T1 to TN, the pixels belonging to the selected row are written , the video signal is written in order for each k columns.

[0301] As described above, the video signal is written to the pixels in multiple columns. Therefore, the number of connections to external circuits can be reduced. This allows for improved yield, improved reliability, reduced component count, and / or reduced costs. Alternatively, the video signal can be written to the pixels in multiple columns at a time. This allows the write time to be extended, preventing insufficient writing of video signals. Therefore, the display quality can be improved.

[0302] By increasing k, the number of connections to external circuits can be reduced. If k is too large, the time required to write to the pixel becomes short. Therefore, it is preferable that k≦6. It is preferable that k≦3. It is further preferable that k=2. It is preferable that:

[0303] In particular, when the number of color elements of a pixel is n (n is a natural number), k=n or k=n×d (d is a natural number). For example, if the color components of a pixel are red (R), green (G), and blue (B), When the pixel is divided into three parts, it is preferable that k=3 or k=3×d. For example, There are m (m is a natural number) sub-pixels (sub-pixels are also called sub-pixels or sub-sub-pixels) When the pixel is divided into two, it is preferable that k=m or k=m×d. If the pixel is divided into n sub-pixels, then k=2. When the number of the elements is m×n, it is preferable that k=m×n×d.

[0304] For example, this embodiment mode is used in a display device. In this case, the signal line driver circuit of this embodiment mode is It can be formed on the same substrate as the pixel section, or on a substrate (e.g., silicon) separate from the pixel section. The signal transistor of this embodiment can be formed on a silicon substrate, an SOI substrate, or the like. A part of the signal line driving circuit (for example, circuit 2002) is formed on the same substrate as the pixel section. Another part of the signal line driver circuit (for example, the circuit 2001) is formed on a substrate separate from the pixel portion. It is possible.

[0305] In FIG. 36(C), a circuit 2001 and a circuit 2002 are formed on the same substrate as the pixel portion 2007. This reduces the number of connections between the substrate on which the pixel section is formed and the external circuit. This allows for improvements in yield, reliability, reduction in the number of parts, and cost reduction. In particular, the scanning line driving circuit 2006A and the scanning line driving circuit 2006B By forming the pixel section 2007 on the same substrate, the number of connections to external circuits can be further reduced. It can be done.

[0306] In FIG. 36(D), a circuit 2002 is formed on the same substrate as the pixel portion 2007. 7 shows a configuration in which a circuit 2001 is formed on a separate substrate. This reduces the number of connections between the board and the external circuit, improving yield and reliability. Furthermore, it is possible to reduce the number of components and reduce costs. Since fewer circuits are formed on the same substrate, the frame can be made smaller.

[0307] Note that the shift register circuit of Embodiment 3 can be used as the circuit 2001. This allows all transistors to be N-channel type. The manufacturing process can be reduced, and deterioration of the transistor can be suppressed. Therefore, the life of the signal line driver circuit can be extended.

[0308] (Embodiment 5) In this embodiment, a protection circuit will be described. The protection circuit is a semiconductor device connected to a certain wiring. Devices (e.g., transistors, capacitors, circuits, etc.) that are susceptible to ESD (electrostatic discharge) Therefore, the protection circuit is provided to prevent the circuit from being destroyed.

[0309] First, the protection circuit will be described with reference to FIG. The transistor 3001 and the transistor 3002 are The transistor 3002 is assumed to be an N-channel type. However, this embodiment is not limited to this. The transistor is not limited to a P-channel type.

[0310] The connection relationship of the protection circuit 3000 will be described. The first terminal of the transistor 3001 is The first terminal of the transistor 3001 is connected to a wiring 3012, and the second terminal of the transistor 3001 is connected to a wiring 3011. The gate of the transistor 3001 is connected to a wiring 3011. A first terminal of the transistor 3002 is connected to a wiring 3013, and a second terminal of the transistor 3002 is connected to a wiring 3014. The gate of the transistor 3002 is connected to a wiring 3011 , and the gate of the transistor 3002 is connected to a wiring 3013 .

[0311] Examples of signals or voltages input to the wirings 3011 to 3013 and the functions of these wirings The wiring 3011 carries signals (for example, scanning signals, video signals, clock signals, etc.). signal, start signal, reset signal, or select signal), or voltage (negative power supply voltage, ground Therefore, the wiring 3011 is a signal line, a power line, etc. The wiring 3012 can have a function as a positive power supply voltage (VDD) Therefore, the wiring 3012 can function as a power supply line. A negative power supply voltage (VSS), a ground voltage, or the like is supplied to the wiring 3013. Therefore, the wiring 3013 can function as a power supply line.

[0312] The operation of the protection circuit 3000 will be described. When the potential of the wiring 3011 is approximately VSS to VD If the value is between D, the transistor 3001 and the transistor 3002 are turned off. Therefore, the voltage or signal supplied to the wiring 3011 is transmitted to the semiconductor device connected to the wiring 3011. However, due to the influence of static electricity or the like, the power supply voltage may be A potential higher than the power supply voltage or a potential lower than the power supply voltage is supplied. The semiconductor device connected to the wiring 3011 is turned on by a potential higher than the power supply voltage or a potential lower than the power supply voltage. To prevent electrostatic damage to semiconductor devices, When the transistor 3001 or the transistor 3002 is turned on, the wiring 30 For example, when a potential higher than the power supply voltage is supplied to the wiring 3011, When the transistor 3001 is turned on, the charge in the wiring 3011 is transferred to the transistor The potential of the wiring 3011 decreases because the charge moves to the wiring 3012 via 3001. Therefore, electrostatic breakdown of the semiconductor device can be prevented. When a potential lower than the power supply voltage is supplied, the transistor 3002 is turned on. The charge in the wiring 3011 moves to the wiring 3013 via the transistor 3002. The potential of the wiring 3011 rises. Electrostatic discharge damage can be prevented.

[0313] In the configuration described in FIG. 37A, the transistor 3001 and the transistor 3 37(A)。 37(B) shows the protection circuit of FIG. 37(C) shows a configuration in which the transistor 3002 is omitted. A) shows a configuration in which the transistor 3001 is omitted from the protection circuit.

[0314] In the configuration described in FIGS. 37(A) to 37(C), between the wiring 3011 and the wiring 3012 Alternatively, a plurality of transistors can be connected in series to the wiring 3011. It is possible to connect multiple transistors in series between the line 3013. In D), a transistor is formed between the wiring 3011 and the wiring 3012 in the protection circuit of FIG. The transistor 3001 and the transistor 3003 are connected in series. Between the wiring 3011 and the wiring 3013, the transistor 3002 and the transistor 3004 are connected. The first terminal of the transistor 3003 is connected to a wiring 3012. The second terminal of the transistor 3003 is connected to the first terminal of the transistor 3001. The gate of the transistor 3003 is connected to the first terminal of the transistor 3001. A first terminal of the transistor 3004 is connected to a wiring 3013. The second terminal of the transistor 3004 is connected to the first terminal of the transistor 3002. The gate of 3004 is connected to the first terminal of transistor 3004. For example, in FIG. As shown in (E), the gate of the transistor 3001 and the gate of the transistor 3003 Alternatively, the gate of the transistor 3002 and the gate of the transistor The gate of the wiring 3011 and the gate of the wiring 301 can be connected. 2 and the wiring 3011 and the wiring 3013, a plurality of transistors are It is possible to connect the capacitors in series.

[0315] In the configuration described in FIGS. 37(A) to 37(E), between the wiring 3011 and the wiring 3012 Alternatively, a plurality of transistors can be connected in parallel to the wiring 3011. A plurality of transistors can be connected in parallel between the wiring 3013 and the transistor. In (F), in the protection circuit of FIG. 37(A), between the wiring 3011 and the wiring 3012, The transistor 3001 and the transistor 3003 are connected in parallel. , the transistor 3002 and the transistor 3004 are connected between the wiring 3011 and the wiring 3013. The first terminal of the transistor 3003 is connected to a wiring 3012. The second terminal of the transistor 3003 is connected to a wiring 3011. The gate of the transistor 3003 is connected to the wiring 3011. The first terminal of the transistor 3004 is connected to a wiring 3013, and the second terminal of the transistor 3004 is connected to a wiring 3011. The gate of the transistor 3004 is connected to a wiring 3013 .

[0316] In the configurations described in FIGS. 37(A) to 37(F), the gate of the transistor and the first terminal A capacitance element and a resistance element can be connected in parallel between the gate of the transistor and the gate of the transistor. Only one of the capacitance element and the resistance element can be connected between the port and the first terminal. FIG. 37(G) shows the gate of the transistor 3001 in the protection circuit of FIG. A capacitance element 3005 and a resistance element 3006 are connected in parallel between the first terminal and the second terminal. A capacitor 3002 is connected between the gate and the first terminal of the transistor 3002. 3007 and a resistor element 3008 are connected in parallel. For example, if a voltage higher than the power supply voltage is applied to the wiring 3011, damage or deterioration of the wiring can be prevented. When a potential is supplied, the Vgs of the transistor 3001 increases. Since the transistor 3001 is turned on, the potential of the wiring 3011 decreases. A large voltage is applied between the gate and the second terminal of 3001, so the transistor To prevent this, the transistor 3001 may be destroyed or deteriorated. The potential of the gate of transistor 3001 is increased to reduce the Vgs of transistor 3001. To achieve this, a capacitive element 3005 is used. When this happens, the potential of the first terminal of the transistor 3001 rises instantaneously. The potential of the gate of the transistor 3001 rises due to the capacitive coupling of the capacitor 3005. Therefore, the Vgs of the transistor 3001 can be reduced. Similarly, a potential lower than the power supply voltage is applied to the wiring 3011. When this voltage is applied, the potential of the first terminal of the transistor 3002 decreases instantaneously. The potential of the gate of the transistor 3002 is reduced by the capacitive coupling of the capacitor 3007. In this way, the Vgs of the transistor 3002 can be reduced. This makes it possible to suppress damage or deterioration of the star 3002.

[0317] The capacitance element is a parasitic capacitance between the gate and the first terminal of the transistor. Therefore, the material used for the gate of the transistor and the The area where the material used as the first terminal of the transistor overlaps with the material used as the gate of the transistor is The area of ​​the material used as the second terminal of the transistor is larger than the area of ​​the material used as the second terminal of the transistor. Larger is preferable.

[0318] The resistor element is made of the material used for the wiring 3011 or the material used for the gate of the transistor. A material with lower conductivity than the material used for the pixel electrode (for example, the same material as the pixel electrode, the transparent electrode, the non-transparent electrode, It is possible to use a semiconductor layer doped with a pure material.

[0319] Here, the protection circuits described in FIGS. 37(A) to 37(G) are for various circuits or wirings (e.g., signal lines Drive circuit, scanning line drive circuit, level shift circuit, gate signal line, source signal line, power supply line, In Figure 38(A), a protection circuit is provided on the gate signal line. In this case, the wiring 3012 and the wiring 3013 are connected to the gate driver. It is possible to connect it to any of the wires connected to the bus 3100. Therefore, the number of power supplies and the number of wirings can be reduced. This shows the configuration in which a protection circuit is provided at a terminal to which a signal or voltage is supplied from the outside. In this case, the wiring 3012 and the wiring 3013 can be connected to any of the external terminals. For example, the wiring 3012 is connected to the terminal 3101a, and the wiring 3013 is connected to the terminal 3101b. In this case, in the protection circuit provided at the terminal 3101a, The transistor 3001 can be omitted. In the protection circuit, the transistor 3002 can be omitted. Therefore, the number of transistors can be reduced, which reduces the layout area. can be done.

[0320] (Embodiment 6) In this embodiment, a transistor will be described with reference to FIGS. explain.

[0321] FIG. 39(A) shows a top-gate transistor and a display element formed thereon. FIG. 39(B) shows a bottom gate type transistor and a surface formed thereon. FIG. 1 is a diagram showing a display element.

[0322] The transistor in FIG. 39(A) is made up of a substrate 5260 and an insulating layer formed on the substrate 5260. 5261, and regions 5262a, 5262b, and 5262c formed on the insulating layer 5261. 262c, a semiconductor layer 5262 having regions 5262d and 5262e, and a semiconductor layer 52 An insulating layer 5263 is formed to cover the semiconductor layer 5262 and the insulating layer 5263. A conductive layer 5264 is formed on the insulating layer 5263 and the conductive layer 5264. An insulating layer 5265 having an opening, and a metal film formed on the insulating layer 5265 and in the opening of the insulating layer 5265. and a conductive layer 5266 formed thereon.

[0323] The transistor in FIG. 39(B) includes a substrate 5300 and a conductive layer formed on the substrate 5300. 5301, an insulating layer 5302 formed to cover the conductive layer 5301, and the conductive layer 5301 A semiconductor layer 5303a formed on the insulating layer 5302 and a semiconductor layer 5303b formed on the semiconductor layer 5303a A semiconductor layer 5303b is formed, and a semiconductor layer 5303b is formed on the semiconductor layer 5303b and on the insulating layer 5302. a conductive layer 5304 formed on the insulating layer 5302 and the conductive layer 5304, and an opening formed on the insulating layer 5302 and the conductive layer 5304; An insulating layer 5305 having an opening, and a metal film formed on the insulating layer 5305 and in the opening of the insulating layer 5305 and a conductive layer 5306 .

[0324] The transistor of FIG. 39(C) is a semiconductor substrate 53 having a region 5353 and a region 5355. 52, an insulating layer 5356 formed on the semiconductor substrate 5352, and an insulating layer 5354 formed thereon, a conductive layer 5357 formed on the insulating layer 5356; A conductive layer 5357 is formed on the insulating layer 5354, the insulating layer 5356, and the conductive layer 5357, and has an opening. An insulating layer 5358 and a conductive layer formed on the insulating layer 5358 and in the opening of the insulating layer 5358. Thus, the region 5350 and the region 5351 each have a transistor is produced.

[0325] In the transistors described in FIGS. 39(A) to 39(C), as shown in FIG. , an opening formed on the transistor, on the conductive layer 5266 and on the insulating layer 5265; an insulating layer 5267 having a first insulating layer 5268 and a second insulating layer 5269 formed on the insulating layer 5267 and in the opening of the insulating layer 5267; a conductive layer 5268 having an opening formed on the insulating layer 5267 and the conductive layer 5268; and an insulating layer 5269 having a conductive film formed on the insulating layer 5269 and in the opening of the insulating layer 5269. A light-emitting layer 5270 and a conductive layer 52 formed on the insulating layer 5269 and on the light-emitting layer 5270. 71 and can be formed.

[0326] In the transistors described in FIGS. 39(A) to 39(C), as shown in FIG. 39(B), A liquid crystal layer disposed on the transistor, on the insulating layer 5305, and on the conductive layer 5306 5307 and a conductive layer 5308 formed on the liquid crystal layer 5307. is.

[0327] The insulating layer 5261 can function as a base film. The insulating layer 5263, the insulating layer 5302, and the insulating layer 5303 function as an isolation layer (for example, a field oxide film). The insulating layer 5356 can function as a gate insulating film. The insulating layer 5301 and the conductive layer 5357 can function as gate electrodes. The insulating layer 5265, the insulating layer 5267, the insulating layer 5305, and the insulating layer 5358 are interlayer films or flat films. The conductive layer 5266, the conductive layer 5304, and the conductive layer 5305 can function as a conductive film. 359 can function as a wiring, an electrode of a transistor, an electrode of a capacitor, or the like. The conductive layer 5268 and the conductive layer 5306 can be used as a pixel electrode, a reflective electrode, or the like. The insulating layer 5269 can function as a partition wall. The conductive layer 5271 and the conductive layer 5308 can function as a counter electrode, a common electrode, or the like. It is possible to do this.

[0328] The substrate 5260 and the substrate 5300 may be a glass substrate, a quartz substrate, a semiconductor substrate (e.g., silicon substrate), or the like. silicon substrate, or single crystal substrate), SOI substrate, plastic substrate, metal substrate, stainless steel substrate , Stainless steel foil substrate, Tungsten substrate, Tungsten foil Examples of the glass substrate include a substrate having a thickness of 100 nm or a flexible substrate. Examples of flexible substrates include polyethylene terephthalate (PET) and aluminoborosilicate glass. Polyethylene naphthalate (PET), Polyethersulfone (P ES) or flexible synthetic resins such as acrylic. Other examples include laminated films (polypropylene, polyester, vinyl, polyvinyl fluoride, etc.) vinyl, vinyl chloride, etc.), paper containing fibrous materials, base film (polyester, polyamide, etc.) (e.g., inorganic film, polyimide, inorganic vapor deposition film, paper, etc.)

[0329] The semiconductor substrate 5352 may be a single crystal Si substrate having n-type or p-type conductivity. However, the present invention is not limited to this, and the semiconductor substrate 5352 can be used in various ways. The substrate may be used in part or in whole as a semiconductor substrate 5352. The region 5353 is , which is a region where impurities are added to the semiconductor substrate 5352 and functions as a well. When the semiconductor substrate 5352 has a p-type conductivity, the region 5353 has an n-type conductivity. On the other hand, when the semiconductor substrate 5352 has n-type conductivity, The region 5353 has p-type conductivity and functions as a p-well. The region 5355 is an impurity-containing region. A region where a material is added to the semiconductor substrate 5352 and functions as a source region or a drain region. It is possible to form an LDD region in the semiconductor substrate 5352.

[0330] The insulating layer 5261 is made of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y )(x>y>0), silicon oxynitride (SiN x O y )(x>y>0) The insulating layer 5261 is a two-layer structure. When it is installed in this structure, a silicon nitride film is installed as the first insulating layer, and a silicon nitride film is installed as the second insulating layer. When the insulating layer 5261 has a three-layer structure, A silicon oxide film is provided as the first insulating layer, a silicon nitride film is provided as the second insulating layer, and a silicon nitride film is provided as the third insulating layer. A silicon oxide film can be provided as the insulating layer.

[0331] The semiconductor layer 5262, the semiconductor layer 5303a, and the semiconductor layer 5303b are made of a non-single-crystal semiconductor. Conductors (e.g., amorphous silicon, polycrystalline silicon, microcrystalline silicon, etc.) ), single crystal semiconductor, compound semiconductor or oxide semiconductor (e.g., ZnO, InGaZn O, SiGe, GaAs, IZO (indium zinc oxide), ITO (indium tin oxide) compounds), SnO, TiO, AlZnSnO(AZTO), organic semiconductors, or carbon nanotubes Tubes and the like.

[0332] For example, the region 5262a is an intrinsic semiconductor layer 5262 to which no impurities are added. However, when impurities are added to the region 5262a, the region 5262a functions as a channel region. The impurity added to the region 5262a can be added to the region 5262b, the region 5262c, and the region 5262d. 2c, region 5262d, or region 5262e. It is preferable that the region 5262b and the region 5262d are not included in the region 5262c or the region 5262e. It is a region where impurities are added at a lower concentration than that of the LDD (Lightly Doped Diode). However, the area 5262b and the area 5262d are omitted. The regions 5262c and 5262e are semiconductor regions containing high concentrations of impurities. The doped region is a region in the body layer 5262, and functions as a source region or a drain region.

[0333] The semiconductor layer 5303b is a semiconductor layer to which phosphorus or the like is added as an impurity element. It has n-type conductivity.

[0334] When an oxide semiconductor or a compound semiconductor is used for the semiconductor layer 5303a, The semiconductor layer 5303b can be omitted.

[0335] The insulating layer 5263, the insulating layer 5302, and the insulating layer 5356 are made of silicon oxide (SiO x ) , silicon nitride (SiN x ), silicon oxynitride (SiO x N y )(x>y>0), silicon oxynitride (SiN x O y ) (x>y>0) or a laminate thereof There are structures, etc.

[0336] Conductive layer 5264, conductive layer 5266, conductive layer 5268, conductive layer 5271, conductive layer 5301, A conductive layer 5304, a conductive layer 5306, a conductive layer 5308, a conductive layer 5357, and a conductive layer 535 The conductive film 9 may be a single-layer conductive film or a laminated structure thereof. , aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), W, Neodymium (Nd), Chromium (Cr), Nickel (Ni), Platinum (Pt ), gold (Au), silver (Ag), copper (Cu), manganese (Mn), cobalt (Co), Niobium (Nb), silicon (Si), iron (Fe), palladium (Pd), carbon (C), scandium (Sb) Sodium (Sc), zinc (Zn), gallium (Ga), indium (In), tin (Sn), A group consisting of zirconium (Zr) and cerium (Ce), one selected from this group A film of one element alone, or a compound containing one or more elements selected from this group The single film or compound may contain phosphorus (P), boron (B), arsenic ( It is possible for the fluorine atom to contain fluorine (As), and / or oxygen (O).

[0337] The compound contains one or more elements selected from the above-mentioned elements. Compounds (e.g., alloys) containing one or more elements selected from the above-mentioned elements Compounds of elements and nitrogen (for example, nitride film), or a single element selected from the above-mentioned multiple elements. or compounds of silicon with multiple elements (e.g., silicide films), or nanotube materials As alloys, indium tin oxide (ITO), indium zinc oxide (I ZO), indium tin oxide with silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO), Cadmium Tin Oxide (CTO), Aluminum Neodymium (Al-Nd), Al Aluminum tungsten (Al-W), aluminum zirconium (Al-Zr), aluminum Aluminum-titanium (Al-Ti), aluminum-cerium (Al-Ce), magnesium-silver ( Mg-Ag), Molybdenum Niobium (Mo-Nb), Molybdenum Tungsten (Mo-W) As for nitride films, titanium nitride, tantalum nitride, etc. Examples of silicide films include tungsten silicide, molybdenum nitride, etc. Titanium silicide, nickel silicide, aluminum silicon, molybdenum silicon, etc. Nanotube materials include carbon nanotubes, organic nanotubes, and inorganic nanotubes. nanotubes, or metallic nanotubes.

[0338] Insulating layer 5265, insulating layer 5267, insulating layer 5269, insulating layer 5305, and insulating layer 535 The insulating layer 8 may be a single layer or a laminated layer of these. , silicon oxide (SiO x), silicon nitride (SiN x ), or silicon oxynitride (SiO x N y )(x>y>0), silicon oxynitride (SiN x O y ) (x>y>0) etc. oxygen or nitrogen a film containing carbon such as DLC (diamond-like carbon), or a film containing siloxane Resin, epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene , or organic materials such as acrylic.

[0339] The light-emitting layer 5270 may be an organic EL element or an inorganic EL element. The hole injection layer is made of a hole injection material, the hole transport layer is made of a hole transport material, and the light emitting material an electron transport layer made of an electron transport material; an electron injection layer made of an electron injection material; or a single layer structure of a layer made of a mixture of multiple materials from among these materials, or There are laminated structures.

[0340] Note that an insulating layer functioning as an alignment film is provided over the insulating layer 5305 and the conductive layer 5306. It is possible to form an insulating layer or the like that functions as a protrusion.

[0341] Note that a color filter, a black matrix, or a protrusion may be formed on the conductive layer 5308. An insulating layer or the like that functions as an alignment film can be formed under the conductive layer 5308. It is possible to form an insulating layer that acts as a barrier.

[0342] The transistor of this embodiment is used in the semiconductor device described in the first and second embodiments. In particular, in FIG. 39(B), a non-single crystal semiconductor, When an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used, However, the semiconductor devices according to the first to sixth embodiments and the shift register are In a display device or a transistor, the deterioration of the transistor can be suppressed. .

[0343] (Embodiment 7) In this embodiment, the cross-sectional structure of the display device will be described with reference to FIGS. 40(A), 40(B), and 40(C). Please refer to the following for explanation.

[0344] 40(A) is a top view of a display device. A driver circuit 5392 and a pixel portion are disposed on a substrate 5391. The driver circuit 5392 is a scanning line driver circuit or a signal line driver circuit. There are drive circuits, etc.

[0345] FIG. 40(B) shows the AB cross section of FIG. 40(A). 5400, a conductive layer 5401 formed on the substrate 5400, and a conductive layer 5402 formed on the conductive layer 5401. The insulating layer 5402 is formed as shown in FIG. 5, and the conductive layer 5401 and the insulating layer 5402 are formed on the insulating layer 5402. A semiconductor layer 5403a, a semiconductor layer 5403b formed on the semiconductor layer 5403a, and a semiconductor A conductive layer 5404 formed on the conductor layer 5403b and on the insulating layer 5402, and an insulating layer 5403b are formed on the insulating layer 5402. An insulating layer 5405 having an opening formed on the insulating layer 402 and on the conductive layer 5404; A conductive layer 5406 formed on the insulating layer 5405 and in the opening of the insulating layer 5405; an insulating layer 5408 disposed on the insulating layer 5405 and on the conductive layer 5406; A liquid crystal layer 5407 is formed, and a liquid crystal layer 5408 is formed on the liquid crystal layer 5407 and on the insulating layer 5408. A conductive layer 5409 and a substrate 5410 formed over the conductive layer 5409 are shown.

[0346] The conductive layer 5401 can function as a gate electrode. The conductive layer 5404 can function as a gate insulating film. The insulating layer 5405 can function as an electrode, an electrode of a capacitor, or the like. The conductive layer 5406 can function as a wiring, a pixel electrode, or a planarization film. The insulating layer 5408 can function as a polarizer or a reflective electrode. The conductive layer 5409 can function as a counter electrode or a common electrode. It is possible.

[0347] Here, a parasitic capacitance may occur between the driver circuit 5392 and the conductive layer 5409. As a result, the output signal of the driver circuit 5392 or the potential of each node may be rounded or delayed. Or, the power consumption will increase. However, as shown in Figure 40(B), As shown in FIG. 5B, an insulating layer 5408 that can function as a sealant is formed on the driver circuit 5392. By forming the conductive layer 5409, the parasitic capacitance generated between the driver circuit 5392 and the conductive layer 5409 is reduced. This is because the dielectric constant of the sealing material is lower than that of the liquid crystal layer. Therefore, the output signal of the driver circuit 5392 or the potential of each node may be rounded or delayed. Alternatively, the power consumption of the driver circuit 5392 can be reduced. .

[0348] As shown in FIG. 40C, a film that functions as a sealant is provided on a part of the driver circuit 5392. In this case, an insulating layer 5408 can be formed. The parasitic capacitance generated between the driver circuit 5392 and the conductive layer 5409 can be reduced. Therefore, it is possible to reduce the distortion or delay of the output signal of the driver circuit 5392 or the potential of each node. However, it is not limited to this, and a film that functions as a sealant can be provided on the driver circuit 5392. It is possible that the insulating layer 5408 is not formed.

[0349] The display element is not limited to a liquid crystal element, and may be any of various display elements such as an EL element or an electrophoretic element. It is possible to use a display element.

[0350] In the above, the cross-sectional structure of the display device has been described in the present embodiment. It is possible to combine the semiconductor device according to the first and second embodiments. The semiconductor layer of the transistor is made of a non-single-crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide. When a semiconductor or the like is used, the channel width of the transistor becomes large. If the parasitic capacitance of the driver circuit can be reduced, the channel width of the transistor can be reduced. Therefore, the layout area can be reduced, and the display device can be This allows for a narrower frame, or allows for a higher resolution display device.

[0351] (Embodiment 8) In this embodiment, a manufacturing process of a semiconductor device will be described. In particular, a method for manufacturing a capacitor using an oxide semiconductor as a semiconductor layer will be described. The manufacturing process for this case will be described below.

[0352] The manufacturing steps of a transistor and a capacitor will be described with reference to FIGS. 41A to 41C show a process for fabricating a transistor 5441 and a capacitor 5442. The transistor 5441 is an inverted staggered thin film transistor and is made of an oxide semiconductor. A transistor in which wiring is provided on the semiconductor layer via a source electrode or a drain electrode. do.

[0353] First, a first conductive layer is formed on the entire surface of the substrate 5420 by sputtering. A resist mask formed by a photolithography process using a first photomask is used. Then, the first conductive layer is selectively etched to form a conductive layer 5421 and a conductive layer 5422. The conductive layer 5421 can function as a gate electrode, and the conductive layer 542 2 can function as one electrode of a capacitor element. The conductive layers 5421 and 5422 are used as wirings, gate electrodes, or electrodes of a capacitor. After this, the resist mask is removed.

[0354] Next, an insulating layer 5423 is formed on the entire surface by plasma CVD or sputtering. The insulating layer 5423 can function as a gate insulating layer, and the conductive layer 5421 The insulating layer 5423 is formed to cover the insulating layer 5424 and the conductive layer 5422. The diameter is greater than or equal to 250 nm and less than or equal to 250 nm.

[0355] Next, a resist mask formed by a photolithography process using a second photomask 5423 to selectively etch the insulating layer 5423 to form a contact that reaches the conductive layer 5421. A hole 5424 is formed. After this, the resist mask is removed. However, the present invention is not limited to this. Therefore, the contact hole 5424 can be omitted. After forming the contact hole 5424, the contact hole 5424 can be formed. The cross section of this corresponds to FIG. 41(A).

[0356] Next, an oxide semiconductor layer is formed on the entire surface by sputtering. The oxide semiconductor layer is formed by sputtering, and a buffer layer (e.g., For example + The oxide semiconductor layer can be formed to a thickness of 5 nm or more. , 200 nm or less.

[0357] Next, a resist mask formed by a photolithography process using a third photomask The oxide semiconductor layer is selectively etched using the resist mask. do.

[0358] Next, a second conductive layer is formed on the entire surface by sputtering. The second conductive layer is selectively formed using a resist mask formed by a photolithography process. The conductive layer 5429, the conductive layer 5430, and the conductive layer 5431 are formed by etching the conductive layer 5429, the conductive layer 5430, and the conductive layer 5431. The conductive layer 5429 is connected to the conductive layer 5421 through a contact hole 5424. The conductive layer 5429 and the conductive layer 5430 function as a source electrode and a drain electrode. The conductive layer 5431 can function as the other electrode of the capacitor. However, the conductive layer 5429, the conductive layer 5430, and the conductive layer 54 31 is a part that functions as a wiring, a source or drain electrode, or an electrode of a capacitor element. The cross section at this stage corresponds to Figure 41(B).

[0359] Next, a heat treatment is performed at 200°C to 600°C in an air atmosphere or a nitrogen atmosphere. The treatment causes rearrangement at the atomic level in the In-Ga-Zn-O non-single crystal layer. As shown above, the distortion that inhibits carrier movement is released by heat treatment (including optical annealing). The timing of this heat treatment is not limited, and various methods can be used after the formation of the oxide semiconductor. It can be done at the right time.

[0360] Next, an insulating layer 5432 is formed over the entire surface. The insulating layer 5432 has a single-layer structure. For example, the insulating layer 5432 may be an organic thin film. When an insulating layer is used, a composition that is a material for the organic insulating layer is applied, and the applied composition is heated under an air atmosphere or nitrogen. Heat treatment is carried out at 200°C to 600°C in an atmosphere to form an organic insulating layer. By forming an organic insulating layer in contact with the oxide semiconductor layer, a thin film with high reliability in electrical properties can be obtained. A thin film transistor can be manufactured. Note that an organic insulating layer is used as the insulating layer 5432. In this case, a silicon nitride film or a silicon oxide film can be provided under the organic insulating layer.

[0361] Next, a third conductive layer is formed on the entire surface. Next, a photolithography process is performed using a fifth photomask. The third conductive layer is selectively etched using the resist mask formed by the etching process. A conductive layer 5433 and a conductive layer 5434 are formed. A cross-sectional view of the process up to this stage is shown in FIG. The conductive layer 5433 and the conductive layer 5434 correspond to a wiring, a pixel electrode, a reflective electrode, a transparent electrode, and the like. The conductive layer 5434 can function as a photo-transistor or an electrode of a capacitor. Since the conductive layer 5422 is connected to the conductive layer 5422, the conductive layer 5422 can function as an electrode of the capacitor 5442. However, it is not limited to this, and any other material having the function of connecting the first conductive layer and the second conductive layer may be used. For example, by connecting the conductive layer 5433 and the conductive layer 5434, The conductive layer 5422 and the conductive layer 5430 are connected to a third conductive layer (conductive layer 5433 and conductive layer 543 4) can be connected via

[0362] Through the above steps, the transistor 5441 and the capacitor 5442 can be manufactured. .

[0363] As shown in FIG. 41D, an insulating layer 5435 is formed over the oxide semiconductor layer 5425. In FIG. 41(D), reference numeral 5437 denotes a conductive layer, and 5436 denotes a The semiconductor layer is shown.

[0364] As shown in FIG. 41(E), after the second conductive layer is patterned, the oxide semiconductor layer 5425. In FIG. 41(E), reference numerals 5438 and 54 39 indicates a conductive layer.

[0365] The substrate, insulating layer, conductive layer, and semiconductor layer of this embodiment may be the same as those of other embodiments. Materials described or similar to those described herein can be used.

[0366] (Embodiment 9) In this embodiment mode, a layout diagram (also referred to as a top view) of a semiconductor device will be described. In this embodiment, a layout diagram of a semiconductor device shown in FIG. The content described in the embodiment can be appropriately combined with the content described in other embodiments. Note that the layout diagram of this embodiment is an example, and the layout diagram of the semiconductor device It should be noted that the present invention is not limited to this.

[0367] The layout diagram of this embodiment will be described with reference to FIG. 42. In FIG. 42, A) is a layout diagram of the semiconductor device.

[0368] The transistor or wiring shown in FIG. 42 includes a conductive layer 901, a semiconductor layer 902, a conductive layer 903, and a 903, a conductive layer 904, and a contact hole 905. However, it is not limited to this, and another conductive layer, an insulating film, or another contact hole can be newly formed. For example, a contact hole for connecting the conductive layer 901 and the conductive layer 903 can be formed. New ones can be added.

[0369] The conductive layer 901 can include a portion that functions as a gate electrode or a wiring. The conductor layer 902 may include a portion that functions as a semiconductor layer of a transistor. The conductive layer 903 may include a portion that functions as a wiring, a source, or a drain. The conductive layer 904 may include a portion that functions as a light-transmitting electrode, a pixel electrode, or a wiring. The contact hole 905 has a function of connecting the conductive layer 901 and the conductive layer 904. Alternatively, the conductive layer 903 and the conductive layer 904 are connected to each other.

[0370] Note that a semiconductor layer 902 is formed in the area where the conductive layer 901 and the conductive layer 903 overlap. By doing so, the parasitic capacitance between the conductive layer 901 and the conductive layer 903 can be reduced. For the same reason, the conductive layer A semiconductor layer 902 or a conductive layer 903 is formed in the area where the conductive layer 904 overlaps with the semiconductor layer 901. It is possible.

[0371] A conductive layer 904 is formed on a part of the conductive layer 901. It is possible to connect with the conductive layer 904 through the hole 905. By doing so, the wiring resistance can be reduced. and a conductive layer 904 are formed, and the conductive layer 901 is connected to the corresponding substrate through a contact hole 905. The conductive layer 903 is connected to the conductive layer 904 through another contact hole 905. It is possible to connect with the conductive layer 904. By doing so, the wiring resistance can be further reduced. can be further reduced.

[0372] A conductive layer 904 is formed on a part of the conductive layer 903. It is possible to connect with the conductive layer 904 through the hole 905. This can reduce the wiring resistance.

[0373] Note that the conductive layer 901 or the conductive layer 903 is formed under a part of the conductive layer 904. 904 is connected to the conductive layer 901 or the conductive layer 903 through a contact hole 905. By doing so, the wiring resistance can be reduced. .

[0374] As already mentioned, in the transistor 101, The parasitic capacitance between the gate and the second terminal can be made larger than the parasitic capacitance. For this reason, in the transistor 101, the conductive layer 90 The area where the conductive layer 901 having the function as the first terminal overlaps with the conductive layer 901 having the function as the gate is The area where the conductive layer 903 having the function of a gate and the conductive layer 901 having the function of a gate overlap is It is also preferable that the value is large.

[0375] (Embodiment 10) In this embodiment, an example of an electronic device will be described.

[0376] 43(A) to (H) and 44(A) to (D) are diagrams showing electronic devices. The child device includes a housing 5000, a display unit 5001, a speaker 5003, an LED lamp 5004, Operation keys 5005 (including a power switch or an operation switch), a connection terminal 5006, a sensor Sa 5007 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature Degree, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient , vibration, smell or infrared measuring function), microphone 5008, etc. It can have.

[0377] FIG. 43(A) shows a mobile computer, which includes, in addition to the above, a switch 5009, It may have an infrared port 5010, etc. FIG. 43(B) shows a portable device equipped with a recording medium. A type of image reproducing device (for example, a DVD reproducing device), which, in addition to the above, also has a second display 43(C) shows a GOG In addition to the above, the display includes a second display unit 5002, a support unit 5012, The game machine may have earphones 5013, etc. Figure 43(D) shows a portable game machine. In addition to the above, it can have a recording medium reading unit 5011, etc. In addition to the components described above, the projector includes a light source 5033, a projection lens 5034, etc. FIG. 43(F) shows a portable gaming machine, which, in addition to the above, has a second display unit 43(G) shows a television receiver. In addition to the components described above, the image sensor may also include a tuner, an image processor, etc. 43(H) is a portable television receiver, which, in addition to the above, is capable of transmitting and receiving signals. 44(A) is a display, and the above-mentioned In addition to the above, it may have a support stand 5018, etc. Figure 44(B) shows a camera. In addition to the above, an external connection port 5019, a shutter button 5015, an image receiving unit 5016, etc. FIG. 44(C) is a computer, and In addition, there are a pointing device 5020, an external connection port 5019, a reader / writer 5 021, etc. Fig. 44(D) shows a mobile phone, which can have the above-mentioned Antennas, tuners for one-segment partial reception services for mobile phones and mobile terminals, etc. It can have:

[0378] The electronic devices shown in FIGS. 43(A) to 43(H) and 44(A) to 44(D) have various functions. For example, various information (still images, videos, text images, etc.) can be displayed on the display. Functions such as touch panel, calendar, date or time display, and various software Functions that control processing by software (programs), wireless communication functions, and It has the ability to connect to various computer networks and wireless communication functions to store various data. Functions for transmitting or receiving data, reading programs or data recorded on recording media, Furthermore, a display device having a plurality of display units can be used. In the child device, one display unit is used as the main display unit for displaying image information, and another display unit is used as the main display unit for displaying image information. It is also possible to display text information on multiple displays, or to display images that take parallax into account on multiple displays. Furthermore, it can have a function of displaying a stereoscopic image by using a receiver. The child device has the functions of taking still images, taking videos, and automatically saving the captured images. or manual correction function, and the captured images are saved to a recording medium (external or built-in to the camera). The camera can have functions such as a camera function, a function to display the captured image on the display unit, etc. The functions that the electronic devices shown in Figures 44(A) to (H) and 44(A) to (D) can have are as follows: The function is not limited to the above, and may have various functions.

[0379] The electronic device described in this embodiment has a display unit for displaying some information. The electronic device of this embodiment and the semiconductor device of any one of the first to fifth embodiments are characterized in that: By combining it with a device, a shift register, or a display device, the reliability and yield can be improved. This allows for improved resolution, cost reduction, larger display area, and higher resolution display area. .

[0380] Next, application examples of the semiconductor device will be described.

[0381] FIG. 44(E) shows an example in which a semiconductor device is integrated with a building. ) includes a housing 5022, a display unit 5023, a remote control device 5024 as an operation unit, and a speaker 5025. 025, etc. The semiconductor device is a wall-mounted type that is integrated with the building, and the installation space is limited. It can be installed without requiring a large space.

[0382] FIG. 44(F) shows another example in which a semiconductor device is provided inside a building as an integral part of the building. The display panel 5026 is attached to the unit bath 5027 as a unit. The display panel 5026 becomes viewable.

[0383] In this embodiment, a wall and a unit bath are used as examples of buildings. The manner in which the semiconductor device is installed is not limited to this, and the semiconductor device can be installed in various buildings.

[0384] Next, an example in which the semiconductor device is integrated with a moving object will be described.

[0385] FIG. 44G shows an example in which the semiconductor device is provided in an automobile. 5028 is attached to the body 5029 of the automobile, and is The information entered can be displayed on demand. It may be possible.

[0386] FIG. 44(H) is a diagram showing an example in which a semiconductor device is integrated with a passenger airplane. FIG. 44(H) shows a passenger plane with a display panel 5031 mounted on a ceiling 5030 above the seats. The display panel 5031 is attached to the ceiling 50. 30 and the hinge part 5032 are attached together, and the extension and contraction of the hinge part 5032 This allows passengers to view the display panel 5031. The display panel 5031 is operated by passengers. It has the function of displaying information by

[0387] In this embodiment, an automobile body and an airplane body are exemplified as moving bodies. However, this is not limited to motorcycles, four-wheeled vehicles (including cars, buses, etc.), trains (monorails, etc.), It can be installed on a variety of things, including buildings, railways, ships, etc. [Explanation of symbols]

[0388] 11 nodes 12 nodes 13 nodes 100 circuits 101 Transistor 101d Diode 101p transistor 102 transistor 102A Capacitive Element 102d Diode 102S Switch 103 Transistor 103A transistor 103B Capacitor element 103d Diode 103S Switch 104 transistors 104A Capacitive Element 104d Diode 104p transistor 104R resistor element 105 transistors 105A transistor 105B Capacitive element 105D Capacitive element 105S Switch 106 transistors 107 Capacitor element 108 transistors 109 Transistor 111 Wiring 112 Wiring 112A wiring 112B wiring 112C wiring 113 Wiring 113A wiring 113B wiring 113C wiring 113D Wiring 114 Wiring 115 Wiring 115A wiring 115B wiring 115C wiring 115D Wiring 115E wiring 115F wiring 115G wiring 116 Wiring 117 Wiring 120 circuits 121 Resistor element 122 Capacitor element 123 Buffer Circuit 124 Inverter Circuit 125 transistors 126 transistors 127 transistors 128 transistors 129 Wiring 130 Wiring 131 Transistor 132 transistors 133 Transistor 134 transistors 150 circuits 151 circuits 152 circuits 153 circuits 154 circuits 160 Protection circuit 201 Transistor 201d diode 201p transistor 202 Transistor 202d Diode 202p transistor 203 Transistor 203d Diode 203p transistor 204 Transistor 204d Diode 204p transistor 205 Transistor 205d diode 205p transistor 206 Transistor 207 Transistor 207d Diode 207p transistor 208 Transistor 209 Transistor 211 Wiring 212 Wiring 212A wiring 212B wiring 213 Wiring 214 Wiring 220 Capacitive element 350 Holding control section 901 Conductive layer 902 Semiconductor layer 903 Conductive layer 904 Conductive layer 905 Contact Hole 1001 circuits 1002 circuits 1002a circuit 1002b circuit 1003 Circuit 1004 Pixel section 1005 terminal 1006 board 1100 Shift register circuit 1101 Flip-Flop Circuit 1111 Wiring 1112 Wiring 1113 Wiring 1114 Wiring 1115 Wiring 1116 Wiring 2000 circuits 2001 Circuit 2002 Circuit 2003 Transistor 2004 Wiring 2005 Wiring 2006A Scanning Line Driver Circuit 2006B Scanning line driver circuit 2007 Pixel section 2014 signal 2015 signal 2206 Transistor 3000 protection circuit 3001 Transistor 3002 transistor 3003 Transistor 3004 Transistor 3005 Capacitor 3006 Resistor element 3007 Capacitor element 3008 Resistor element 3011 Wiring 3012 Wiring 3013 Wiring 3020 pixels 3021 Transistor 3022 Liquid crystal element 3023 Capacitor element 3031 Wiring 3032 Wiring 3033 Wiring 3034 Electrode 3100 Gate Driver 3101a terminal 3101b terminal 5000 cabinets 5001 Display section 5002 Display section 5003 Speaker 5004 LED lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 pointing device 5021 Reader / Writer 5022 Housing 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Panel 5027 Unit bath 5028 Display Panel 5029 Car Body 5030 Ceiling 5031 Display Panel 5032 Hinge part 5033 Light source 5034 Projection lens 5260 board 5261 Insulation layer 5262 Semiconductor layer 5262a area 5262b area 5262c area 5262d area 5262e area 5263 Insulation layer 5264 Conductive layer 5265 Insulation layer 5266 Conductive layer 5267 Insulation layer 5268 Conductive layer 5269 Insulation layer 5270 luminous layer 5271 Conductive layer 5273 Insulation layer 5300 board 5301 Conductive layer 5302 Insulation layer 5303a Semiconductor layer 5303b Semiconductor layer 5304 Conductive layer 5305 Insulation layer 5306 Conductive layer 5307 Liquid crystal layer 5308 Conductive layer 5350 area 5351 area 5352 Semiconductor substrate 5353 area 5354 Insulation layer 5355 area 5356 Insulation layer 5357 Conductive layer 5358 Insulation layer 5359 Conductive layer 5391 Circuit Board 5392 drive circuit 5393 Pixel section 5400 board 5401 Conductive layer 5402 Insulation layer 5403a Semiconductor layer 5403b Semiconductor layer 5404 Conductive layer 5405 Insulation layer 5406 Conductive layer 5407 Liquid crystal layer 5408 Insulation layer 5409 Conductive layer 5410 PCB 5420 PCB 5421 Conductive layer 5422 Conductive layer 5423 Insulation layer 5424 Contact Hole 5425 Oxide semiconductor layer 5429 Conductive layer 5430 Conductive layer 5431 Conductive layer 5432 Insulation layer 5433 Conductive layer 5434 Conductive layer 5435 Insulation layer 5441 Transistor 5442 Capacitor element

Claims

[Claim 1] a first substrate; a first conductive layer disposed on the first substrate; a first insulating layer disposed on the first conductive layer; a first semiconductor layer disposed on the first conductive layer and the first insulating layer; a second semiconductor layer disposed on the first semiconductor layer; a second conductive layer disposed on the second semiconductor layer and the first insulating layer; a second insulating layer disposed on the first insulating layer and the second conductive layer, the second insulating layer having an opening; a third conductive layer disposed on the second insulating layer and in the opening in the second insulating layer; a third insulating layer disposed on the second insulating layer and the third conductive layer; a liquid crystal layer disposed on the second insulating layer; a fourth conductive layer disposed on the liquid crystal layer and the third insulating layer; a second substrate disposed on the fourth conductive layer; A display device having:

Images