Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing the warpage of a substrate.SOLUTION: A semiconductor device comprises a substrate 8 including first and second main surfaces, first and second non-volatile semiconductor memories mounted on the first main surface, and an adhesive part. The substrate 8 includes a first wiring layer provided on the first main surface, a second wiring layer provided on the second main surface as a mesh-like wiring layer, a plurality of wiring layers formed as inner layers, and a plurality of insulating layers provided between the wiring layers. Third and fourth wiring layers of the inner layers are plane layers. The third wiring layer is formed closer to the first main surface side than the centerline of the layer structure of the substrate 8. The fourth wiring layer is formed closer to the second main surface side than the centerline of the layer structure of the substrate 8. In the fourth wiring layer, a slit 32 is formed in a part of the portion facing the gap between the first and second non-volatile semiconductor memories. The slit 32 extends from a first side along a longitudinal direction of the substrate in a shorter direction and does not reach another second side along the longitudinal direction.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, semiconductor devices have been used in which nonvolatile semiconductor memory elements such as NAND flash memories are mounted on a substrate on which a connector is formed. In addition to the nonvolatile semiconductor memory elements, the semiconductor devices also have volatile semiconductor memory elements and a controller that controls the nonvolatile semiconductor memory elements and the volatile semiconductor memory elements.

[0003] In such semiconductor devices, the shape and size of the substrate may be restricted depending on the environment in which the semiconductor device is used, standards, etc. For example, a substrate having a rectangular shape in a plan view may be used. In addition, due to the recent demand for miniaturization of semiconductor devices, there is a trend toward thinner substrates. When such a thin rectangular substrate is used, it is necessary to suppress warpage of the substrate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-79445 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device capable of suppressing warpage of the substrate. [Means for solving the problem]

[0006] The semiconductor device according to the embodiment includes a substrate, first and second nonvolatile semiconductor memories, and an adhesive. The substrate has a first main surface and a second main surface facing the opposite side of the first main surface. The first and second nonvolatile semiconductor memories are mounted on the first main surface of the substrate. The adhesive fills the gap between the first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory while exposing the surfaces of the first and second nonvolatile semiconductor memories. The substrate includes a first wiring layer provided on the first main surface, a second wiring layer as a mesh wiring layer provided on the second main surface, multiple wiring layers formed as inner layers, and multiple insulating layers provided between these wiring layers. Of the multiple wiring layers formed as the inner layers, third and fourth wiring layers are plane layers. The third wiring layer is formed closer to the first main surface than the center line of the layer structure of the substrate. The fourth wiring layer is formed closer to the second main surface than a center line of the layer structure of the substrate. The fourth wiring layer faces the second wiring layer across an insulating layer. A slit is formed in a portion of the fourth wiring layer facing the gap between the first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory. The substrate has a substantially rectangular shape in a plan view, and the slit extends from a first side along the longitudinal direction of the substrate along the lateral direction of the substrate, but does not reach a second side along the longitudinal direction of the substrate that is different from the first side. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a plan view showing a schematic configuration of the semiconductor device. [Figure 3] FIG. 3 is a side view of the semiconductor device. [Figure 4] FIG. 4 is a diagram showing the layer structure of the substrate. [Figure 5] FIG. 5 is a diagram showing the wiring density of each layer of the substrate. [Figure 6]FIG. 6 is a diagram showing a wiring pattern formed on the back surface layer (eighth layer) of the substrate. [Figure 7] FIG. 7 is a diagram showing the wiring density of each layer of a substrate as a comparative example. [Figure 8] FIG. 8 is a diagram for explaining the line width and spacing of the wiring pattern formed on the back surface layer (eighth layer) of the substrate. [Figure 9] FIG. 9 is a diagram showing adhesive portions filled in gaps in a NAND memory. [Figure 10] FIG. 10 is a diagram showing a slit formed in the seventh layer of the substrate. [Figure 11] FIG. 11 is a diagram showing a layer structure of a substrate included in a semiconductor device according to the second embodiment. [Figure 12] FIG. 12 is an external perspective view of a holding member used in the semiconductor device transport method according to the third embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing a state in which the holding member shown in FIG. 12 is housed in a box. [Figure 14] FIG. 14 is a front view of a holding member according to a modified example of the third embodiment. [Figure 15] FIG. 15 is a diagram showing a state in which the movable portion of the holding member shown in FIG. 14 is opened. DETAILED DESCRIPTION OF THE INVENTION

[0008] Semiconductor devices according to embodiments of the present invention will be described in detail below with reference to the accompanying drawings, although the present invention is not limited to these embodiments.

[0009] (First embodiment) 1 is a block diagram showing an example of the configuration of a semiconductor device according to a first embodiment. The semiconductor device 100 is connected to a host device (hereinafter abbreviated as host) 1, such as a personal computer or a CPU core, via a memory connection interface such as a SATA interface (ATA I / F) 2, and functions as an external memory for the host 1. Examples of the host 1 include the CPU of a personal computer, and the CPU of an imaging device such as a still camera or video camera. The semiconductor device 100 can also send and receive data to and from a debugging device 200 via a communication interface 3, such as an RS232C interface (RS232C I / F).

[0010] The semiconductor device 100 includes a NAND flash memory (hereinafter abbreviated as NAND memory) 10 as a nonvolatile semiconductor memory element, a drive control circuit 4 as a controller, a DRAM 20 as a volatile semiconductor memory element capable of faster storage operations than the NAND memory 10, a power supply circuit 5, an LED 6 for displaying status, and a temperature sensor 7 for detecting the temperature inside the drive. The temperature sensor 7 measures the temperature of the NAND memory 10 directly or indirectly, for example. If the measurement result by the temperature sensor 7 exceeds a certain temperature, the drive control circuit 4 restricts writing of information to the NAND memory 10, thereby preventing further temperature rise.

[0011] The power supply circuit 5 generates a plurality of different internal DC power supply voltages from an external DC power supply supplied from the power supply circuit on the host 1 side, and supplies these internal DC power supply voltages to each circuit in the semiconductor device 100. The power supply circuit 5 also detects the rise of the external power supply, generates a power-on reset signal, and supplies it to the drive control circuit 4.

[0012] FIG. 2 is a plan view showing a schematic configuration of the semiconductor device 100. FIG. 3 is a side view of the semiconductor device 100. The power supply circuit 5, DRAM 20, drive control circuit 4, and NAND memory 10 are mounted on a substrate 8 on which a wiring pattern is formed. The substrate 8 has a generally rectangular shape in a plan view. A connector 9 is provided on one short side of the generally rectangular substrate 8. The connector 9 is connected to the host 1 and functions as the SATA interface 2 and the communication interface 3 described above. The connector 9 functions as a power input unit that supplies power input from the host 1 to the power supply circuit 5. The connector 9 is, for example, an LIF connector. The connector 9 has a slit 9a formed in the connector 9 at a position offset from the center along the short side of the substrate 8, and is adapted to fit with a protrusion (not shown) provided on the host 1. This prevents the semiconductor device 100 from being installed upside down.

[0013] The substrate 8 has a multi-layer structure formed by stacking layers of synthetic resin, for example, an eight-layer structure. The number of layers of the substrate 8 is not limited to eight. FIG. 4 is a diagram showing the layer configuration of the substrate 8. On the substrate 8, wiring patterns are formed as wiring layers 8b in various shapes on the surface or inner layer of each layer (insulating film 8a) made of synthetic resin. The wiring patterns are made of, for example, copper. The power supply circuit 5, DRAM 20, drive control circuit 4, and NAND memory 10 mounted on the substrate 8 are electrically connected to each other via the wiring patterns formed on the substrate 8. In addition, the surface (first layer side) and back surface (eighth layer side) of the substrate are covered with solder resist 8c as a protective film.

[0014] 5 is a diagram showing the wiring density of each layer of the substrate 8. Here, the first to fourth layers formed on the surface layer side of the center line 30 (see also FIG. 4) of the layer structure of the substrate 8 are referred to as upper layers, and the fifth to eighth layers formed on the back layer side of the center line 30 are referred to as lower layers.

[0015] The wiring layers 8b formed on each layer of the substrate 8 function as signal layers for transmitting and receiving signals and plane layers serving as ground and power lines, as shown in Fig. 5. The wiring density of the wiring patterns formed on each layer, i.e., the proportion of the surface area of ​​the substrate 8 that is occupied by the wiring layers, is configured as shown in Fig. 5.

[0016] In this embodiment, the eighth layer, which functions as ground, is a mesh wiring layer rather than a plain layer, thereby suppressing its wiring density to 30-60%. Here, the wiring density of the entire upper layer of the substrate 8 is approximately 60%. Therefore, by forming a wiring pattern with a wiring density of approximately 30% on the eighth layer, the wiring density of the entire lower layer can be approximately 60%, making the wiring density of the entire upper layer and the wiring density of the entire lower layer approximately equal. Note that the wiring density of the eighth layer can be adjusted within a range of approximately 30-60% so that it is approximately equal to the wiring density of the entire upper layer.

[0017] Fig. 6 is a diagram showing a wiring pattern formed on the back surface layer (eighth layer) of substrate 8. As shown in Fig. 6, a wiring pattern is formed in a mesh-like pattern on the back surface layer (eighth layer) of substrate 8. By making the eighth layer of substrate 8 a mesh-like wiring layer in this way, the wiring density is kept lower than if it were formed as a plain layer.

[0018] The wiring layer formed on the back surface layer is also required to function as a shielding layer to reduce the impact of noise leaking from the semiconductor device 100 on other devices. Figure 8 is a diagram for explaining the line width and spacing of the wiring pattern formed on the back surface layer (eighth layer) of the substrate. As shown in Figure 8, a mesh wiring with a line width L of 0.3 mm and a line spacing S of 0.9 mm is formed on the eighth layer of the substrate 8. The mesh wiring formed in this manner has an opening width W of 0.9 × √2 = 1.27 mm.

[0019] For example, the shielding effect against high frequency noise such as the 3GHz SATA fundamental wave is calculated as follows: First, calculate the half wavelength (λ / 2) of the second harmonic of the SATA fundamental wave from C=f×λ×√ε. Here, C is the speed of light, which is 3.0×10 8m / s. f is the frequency of the second harmonic, 6.0×10 9 Hz. ε is the relative permittivity, which is 4.6.

[0020] According to the above conditions, λ is 23.3 mm and 1 / 2 wavelength (λ / 2) is 11.7 mm. In other words, 1 / 2 wavelength (λ / 2) is about 10 times the aperture width W (1.27 mm). Also, since λ / 20 = 1.2 mm, which is approximately equal to the aperture width W, the shielding effectiveness is about -20 dB.

[0021] FIG. 9 is a diagram showing adhesive portions filled in the gaps between the NAND memories 10. As shown in FIG. 9, adhesive portions 31 made of a synthetic resin material are filled in the gaps between the NAND memories 10 and the substrate 8, bonding the NAND memories 10 to the substrate 8. A portion of the adhesive portion 31 protrudes from the gap between the NAND memories 10 and the substrate 8. The protruding portion fills the gaps between the NAND memories 10 arranged along the longitudinal direction of the substrate 8. Therefore, the adhesive portion 31 bonds the sides of the NAND memories 10 to each other. The adhesive portion 31 protrudes to a degree that does not exceed the height of the NAND memories 10, leaving the surfaces of the NAND memories 10 exposed. While FIG. 9 shows the adhesive portion 31 filling the gaps between the NAND memories 10 up to about the middle of their height, it may be lower, as long as the adhesive portion 31 contacts adjacent NAND memories 10. Of course, the adhesive portion 31 may be filled between the NAND memories 10 to a height greater than that shown in FIG. 9.

[0022] FIG. 10 is a diagram showing slits formed in the seventh layer of the substrate 8. FIG. 10 shows the substrate 8 as viewed from the back layer side, with the eighth layer omitted. The NAND memory 10 mounted on the front layer side is indicated by a dashed line. A plane layer is formed as a wiring layer in the seventh layer of the substrate 8. As shown in FIG. 10, a wiring pattern is formed as a plane layer in the seventh layer of the substrate 8 over substantially the entire area of ​​the seventh layer, and a slit 32 (a portion where no wiring layer is formed) is provided in a part of the wiring pattern formed over substantially the entire area of ​​the seventh layer. The slit 32 is provided in a portion of the wiring pattern formed over substantially the entire area of ​​the seventh layer that faces the gap of the NAND memory 10.

[0023] FIG. 7 is a diagram showing the wiring density of each layer of a substrate as a comparative example. As shown in the comparative example of FIG. 7, in a conventional substrate, the wiring density was approximately 90% by using the eighth layer as a plain layer. Therefore, the wiring density of the lower layer was approximately 75%, which was significantly different from the wiring density of the upper layer (approximately 60%). The difference in wiring density results in a difference in the ratio of insulating film 8a (synthetic resin) to wiring portion (copper) in the entire upper layer of substrate 8 from the ratio of synthetic resin to copper in the entire lower layer of substrate 8. This results in a difference in thermal expansion coefficient between the upper and lower layers of substrate 8. Due to this difference in thermal expansion coefficient, warpage that forms a convex shape (an upward convex shape in FIG. 3 ) on the surface layer side along the longitudinal direction of substrate 8 is likely to occur as the temperature of substrate 8 changes. Such temperature changes are likely to occur during the manufacturing process of semiconductor device 100. Furthermore, due to recent demands for miniaturization of semiconductor devices, substrates 8 also tend to become thinner, making such warpage more likely to occur.

[0024] On the other hand, in this embodiment, the wiring density of the eighth layer is adjusted within a range of approximately 30 to 60%, and the wiring density of the entire upper layer is made approximately equal to the wiring density of the entire lower layer, so that the thermal expansion coefficients are also approximately equal. This makes it possible to suppress the occurrence of warping in the substrate 8. Furthermore, because the wiring density is adjusted in the eighth layer, which is the farthest from the center line 30 (see also FIG. 4), it is possible to generate a larger moment to suppress warping.

[0025] Furthermore, since the wiring density is adjusted on the eighth layer of the substrate 8, the wiring design is easier and costs can be reduced compared to adjusting the wiring density on a layer with wiring layout restrictions, such as a signal layer.

[0026] Furthermore, because the adhesive 31 fills the gaps between adjacent NAND memories 10, the bonding strength of the adhesive 31 generates a force that attracts the NAND memories 10 together, as indicated by the arrow X. This force that attracts the NAND memories 10 together counteracts the force that warps the substrate 8 to form a convex shape, and therefore warping of the substrate 8 can be suppressed.

[0027] Furthermore, among the wiring patterns formed over substantially the entire seventh layer of the substrate 8, the slits 32 are provided in the portions facing the gaps between the NAND memories 10, and therefore the bonding strength of the wiring patterns is weakened at the slits 32. As a result, the force that resists the force (see also arrow X in FIG. 9 ) that occurs when the adhesive portions 31 fill the gaps between the NAND memories 10 is weakened, and warping of the substrate 8 can be suppressed even more effectively.

[0028] In this embodiment, the eighth wiring layer is a mesh wiring layer in order to adjust the wiring density of the entire lower layer of the substrate 8, but this is not limiting and, for example, the wiring layer may be formed in lines. Also, the wiring density of the lower layers other than the eighth layer, i.e., the wiring layers from the fifth to the seventh layers, may be adjusted to adjust the wiring density of the entire lower layers. Of course, the wiring density of all layers from the fifth to the eighth layers may be adjusted to adjust the wiring density of the entire lower layers.

[0029] Furthermore, the layer in which the slits 32 are formed is not limited to the seventh layer. Slits may be formed in the lower layers other than the seventh layer, that is, the fifth to sixth and eighth layers.

[0030] (Second embodiment) 11 is a diagram showing the layer structure of a substrate provided in a semiconductor device according to a second embodiment. In this embodiment, an outermost layer is provided as a ninth layer outside the eighth layer of substrate 8. The entire outermost layer is covered with copper foil to serve as a shielding layer. By covering the entire outermost layer with copper foil in this manner, noise leakage from the semiconductor device can be more reliably prevented. Note that the entire layers inside the ninth layer may also be covered with copper foil to serve as shielding layers.

[0031] (Third embodiment) Fig. 12 is an external perspective view of a holding member used in a semiconductor device transport method according to a third embodiment. Fig. 13 is a cross-sectional view showing a state in which the holding member shown in Fig. 12 is stored in a box. In this embodiment, semiconductor devices 100 are packed in holding members 50 and transported. Holding members 50 suppress warping of substrates 8 due to changes over time.

[0032] The holding member 50 includes a clamping portion 51 and a connecting portion 52. Two clamping portions 51 are provided for one holding member 50. The clamping portions 51 hold the substrate 8 by clamping the portion along the longitudinal direction. In order to hold the substrate 8 from both sides, two clamping portions 51 are provided for one holding member 50. The clamping portions 51 are formed with a U-shaped cross section, and clamp the portion along the longitudinal direction of the substrate 8 in the gap between them. The clamping portions 51 suppress warping of the substrate 8 by resisting forces that cause warping along the longitudinal direction of the substrate 8 over time. Therefore, the clamping portions 51 are formed with a strength that can resist forces that tend to warp the substrate 8.

[0033] Furthermore, in order to prevent warping of the substrate 8, it is preferable that the clamping portion 51 be in close contact with the substrate 8 while holding the substrate 8. The gap formed in the clamping portion 51 may be formed, for example, to be slightly narrower than the thickness of the substrate 8, so that the substrate 8 is inserted into the clamping portion 51 while the gap is being expanded. Alternatively, the clamping portion 51 may be formed to have a width substantially equal to or slightly wider than the substrate 8, so that the substrate 8 can be easily inserted into the gap.

[0034] The connecting portion 52 connects the two clamping portions 51, thereby integrating the holding member 50. As shown in Fig. 13, the connecting portion 52 maintains the spacing between the semiconductor devices 100 when multiple semiconductor devices 100 are stored in a box, and also functions as a buffer material that absorbs shocks applied to the semiconductor devices 100 during transportation.

[0035] Each of the clamping portions 51 is formed with a spacing portion 53. The spacing portion 53 is formed to extend on the side opposite to the side where the connecting portion 52 is provided with respect to the clamping portion 51. As shown in Fig. 13, the spacing portion 53 maintains the spacing between the semiconductor devices 100 when multiple semiconductor devices 100 are stored in a box, and functions as a buffer material that absorbs shocks applied to the semiconductor devices 100 during transportation.

[0036] In the present embodiment, the clamping portion 51 is described as clamping the substrate 8, but electronic components (not shown) such as resistors and capacitors, NAND memory 10, etc. are mounted on the substrate 8. Therefore, when electronic components, etc. are mounted on the periphery of the substrate 8, the clamping portion 51 should be formed with a width that can clamp the substrate 8 and the electronic components, etc. together.

[0037] 14 is a front view of holding member 50 according to a modified example of the third embodiment. In this modified example, clamping section 51 is configured to have fixed section 51a and movable section 51b. Fixed section 51a and movable section 51b are rotatably connected at the bottom of a gap formed in clamping section 51, allowing movable section 51b to be opened and closed.

[0038] Each of the movable parts 51b is formed with a closing part 55. As shown in Fig. 14, the closing parts 55 hook together when the movable parts 51b are closed, thereby maintaining the closed state of the movable parts 51b. Furthermore, by keeping the movable parts 51b in the closed state, the width of the gap formed in the clamping part 51 is maintained constant.

[0039] Fig. 15 is a diagram showing a state in which movable portion 51b of holding member 50 shown in Fig. 14 is opened. As shown in Fig. 15, by opening movable portion 51b, the gap of clamping portion 51 can be widened. With the gap of clamping portion 51 widened, semiconductor device 100 is placed on fixed portion 51a and movable portion 51b is closed, whereby semiconductor device 100 can be held by holding member 50 more easily than in the case where semiconductor device 100 is inserted into clamping portion 51 while pushing the gap wide. [Explanation of symbols]

[0040] 1 host, 2 SATA interface (ATA / IF), 3 communication interface, 4 drive control circuit (controller), 5 power supply circuit, 7 temperature sensor, 8 substrate, 8a insulating film, 8b wiring layer, 9 connector, 9a slit, 10 NAND memory (NAND type flash memory, non-volatile semiconductor memory element), 20 DRAM (volatile semiconductor memory element), 30 center line, 31 adhesive portion, 32 slit, 50 holding member, 51 clamping portion, 52 connecting portion, 53 spacing holding portion, 55 closing portion, 100 semiconductor device, 200 debugging equipment.

Claims

1. a substrate having a first main surface and a second main surface facing opposite to the first main surface; first and second nonvolatile semiconductor memories mounted on the first main surface of the substrate; an adhesive portion that fills a gap between the first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory while exposing surfaces of the first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory; the substrate includes a first wiring layer provided on the first main surface, a second wiring layer as a mesh wiring layer provided on the second main surface, a plurality of wiring layers formed as inner layers, and a plurality of insulating layers respectively provided between the wiring layers; a third wiring layer and a fourth wiring layer among the plurality of wiring layers formed as the inner layers are plane layers; the third wiring layer is formed on the first main surface side of the center line of the layer structure of the substrate, the fourth wiring layer is formed on the second main surface side of the center line of the layer structure of the substrate, the fourth wiring layer faces the second wiring layer across an insulating layer; a slit is formed in a part of the fourth wiring layer facing the gap between the first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory; The substrate has an approximately rectangular shape when viewed in a plane, and the slit extends from a first side along the longitudinal direction of the substrate along the short direction of the substrate, and does not reach a second side along the longitudinal direction of the substrate that is different from the first side.

2. a fifth wiring layer facing the third wiring layer across an insulating layer and the first wiring layer among the plurality of wiring layers formed as the inner layers are signal layers for transmitting and receiving signals; 2. The semiconductor device according to claim 1, wherein a surface of the first wiring layer is covered with a solder resist.

3. 3. The semiconductor device according to claim 2, wherein, among the plurality of wiring layers formed as the inner layers, a sixth wiring layer that faces the fifth wiring layer across an insulating layer is a signal layer for transmitting and receiving signals, and at least one of the third and fourth wiring layers is a wiring layer that has a ground.

4. 2. The semiconductor device according to claim 1, wherein a sixth wiring layer, which is a signal layer for transmitting and receiving signals among the plurality of wiring layers formed as the inner layers, faces the fourth wiring layer across an insulating layer.

5. The substrate has a substantially rectangular shape in a plan view, a connector provided on a side along a short-side direction of the substrate for connecting to an external device; and a controller electrically connected to the connector, controlling the first and second nonvolatile semiconductor memories, and mounted on the first main surface of the substrate, the first and second nonvolatile semiconductor memories are provided on an opposite side of the connector from the position of the controller in a plan view, 5. The semiconductor device according to claim 1, wherein the second nonvolatile semiconductor memory is provided on an opposite side of the controller from the position of the first nonvolatile semiconductor memory in a plan view.

6. a volatile semiconductor memory mounted on the first main surface of the substrate; the controller controls the volatile semiconductor memory; The semiconductor device according to claim 5 , wherein the volatile semiconductor memory is provided on the same side as the connector when viewed from above with respect to the position of the controller.

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