NAND flash memory and manufacturing method thereof

Abstract

To provide a NAND flash memory capable of reducing capacitive coupling between adjacent memory cells, and a manufacturing method thereof.SOLUTION: A NAND flash memory of the present invention includes: an active region 30 formed within a silicon substrate 20 to extend along a bit line direction; a trench isolation region 40 defining the active region 30; a charge storage layer 110 formed on the active region corresponding to each memory cell and including a stacked SiN layer sandwiched between insulation layers; a first control gate 120 formed on the charge storage layer 110 corresponding to each memory cell; and a second control gate 130 formed on the first control gate 120 to extend in a word line direction. The second control gate 130 is electrically connected to a plurality of the first control gates 120 in a corresponding row direction. The trench isolation region 40 aligns with side walls of the first control gate 120 and the charge storage layer 110.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a two-dimensional (2D) NAND flash memory. [Background technology]

[0002] The cell structure of NAND flash memory employs a floating gate (FG) structure. The floating gate is made of, for example, polysilicon and has excellent charge retention characteristics. Highly reliable NAND flash memory that suppresses the effects of floating gate coupling between memory cells has also been disclosed (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Non-Patent Document 1] Japanese Patent Application Publication No. 2017-097927 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional FG-type two-dimensional NAND flash memory, as miniaturization progresses, the coupling effect of parasitic capacitance between the floating gates of adjacent memory cells or between the floating gate and control gate increases, and for example, the charge on the floating gate of an adjacent memory cell can change the threshold voltage (Vth) of the programmed memory cell. As a result, the threshold voltage distribution of memory cells becomes larger, posing a problem of reduced reliability of the NAND flash memory.

[0005] SUMMARY OF THE INVENTION An object of the present invention is to provide a NAND flash memory capable of solving the above-mentioned conventional problems and reducing the capacitive coupling between adjacent memory cells, and a method for manufacturing the same. [Means for solving the problem]

[0006] The NAND flash memory according to the present invention includes an active region formed in a semiconductor substrate and extending in a bit line direction, trench isolation regions defined in the active region, a charge storage layer formed on the active region for each memory cell and including a nitride layer sandwiched between insulating layers, a first conductive layer formed on the charge storage layer for each memory cell, and a second conductive layer formed on the first conductive layer and extending in a word line direction, the second conductive layer being electrically connected to a corresponding plurality of first conductive layers in the row direction, and the trench isolation regions being aligned with sidewalls of the first conductive layer and the charge storage layer.

[0007] In one embodiment, the charge storage layer has an oxide / nitride / oxide ONO structure, or a structure including a stack of multiple types of insulating films other than oxide between a silicon substrate and the nitride layer, or a structure including a stack of multiple types of insulating films other than oxide between the nitride and the first conductive layer. In one embodiment, the first conductive layer includes a polysilicon layer, the semiconductor substrate includes a silicon region, and the charge storage layer has a SONOS structure. In one embodiment, the trench isolation region is formed in a self-aligned manner when etching the first conductive layer, the charge storage layer, and the semiconductor substrate. In one embodiment, the peripheral region of the NAND flash memory includes a gate insulating film and a gate material separated from the charge storage layer and the first conductive layer.

[0008] A method for manufacturing a NAND flash memory according to the present invention includes the steps of: forming a stack of a charge storage layer including a nitride layer sandwiched between insulating layers and a first conductive layer on a semiconductor substrate; simultaneously etching the first conductive layer, the charge storage layer, and the semiconductor substrate to pattern the first conductive layer and the charge storage layer in the bit line direction, and forming trenches in the semiconductor substrate to define active regions; filling the trenches with an insulating material; forming a second conductive layer over the entire surface of the semiconductor substrate including the first conductive layer; simultaneously etching the second conductive layer, the first conductive layer, and the charge storage layer to pattern the second conductive layer, the first conductive layer, and the charge storage layer in the word line direction; and forming impurity regions for source / drain in the active regions from which the second conductive layer, the first conductive layer, and the charge storage layer have been removed.

[0009] In one aspect, the manufacturing method further includes forming a mask pattern covering the cell array region, removing the charge storage layer and the first conductive layer on the peripheral region, and forming the gate insulating film and the gate material on the peripheral region, the gate insulating film and the gate material being separated from the charge storage layer and the first conductive layer. In one aspect, the manufacturing method further includes forming a gate insulating film and a gate material on the entire surface of the semiconductor substrate, and planarizing the gate insulating film and the gate material until the first conductive layer on the cell array region is exposed. [Effects of the Invention]

[0010] According to the present invention, a charge storage layer including a nitride layer is formed for each memory cell, thereby reducing the capacitive coupling between adjacent memory cells compared to FG-type memory cells and narrowing the threshold distribution of the memory cells. Furthermore, by aligning the trench isolation region that defines the active region with the charge storage layer and the first conductive layer, it is possible to reduce the capacitive coupling between adjacent memory cells while achieving high integration of the cell array. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a schematic diagram of a cross section of a cell array region of a conventional two-dimensional NAND flash memory in a direction perpendicular to the bit lines. [Figure 2] 2A and 2B are diagrams showing a two-dimensional NAND flash memory according to an embodiment of the present invention, in which FIG. 2A is a plan view of a portion of a cell array, and FIG. 2B is a schematic cross-sectional view taken along line AA in FIG. 2A. [Figure 3] 1A to 1C are diagrams illustrating a manufacturing process of a cell array portion of a NAND flash memory according to an embodiment of the present invention. [Figure 4] 1A to 1C are diagrams illustrating a manufacturing process of a cell array portion of a NAND flash memory according to an embodiment of the present invention. [Figure 5] Figure 5(A) is a plan view of the substrate when the first control gate, charge storage layer, and substrate are etched through a mask pattern, and Figure 5(B) is a plan view of the substrate when the heights of the first control gate and trench insulator are made approximately the same. [Figure 6] 1A to 1C are diagrams illustrating manufacturing processes for a cell array region and a peripheral region of a NAND flash memory according to an embodiment of the present invention. [Figure 6A] 10A to 10C are diagrams illustrating another manufacturing process for the cell array region and the peripheral region of the NAND flash memory of the present embodiment. [Figure 7] 1A to 1C are diagrams illustrating manufacturing processes for a cell array region and a peripheral region of a NAND flash memory according to an embodiment of the present invention. [Figure 8] 2 is a schematic diagram of a cross section in the bit line direction of a cell array region of the NAND flash memory of the present embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] The two-dimensional NAND flash memory according to the present invention uses silicon nitride (SiN) as a charge storage layer, for example, a SONOS type (Si / oxide / nitride / oxide) charge storage layer to narrow the threshold voltage distribution (Vth) of memory cells. The NAND flash memory according to the present invention is used as a storage medium in various semiconductor devices (e.g., microcontrollers, microprocessors, logic devices, etc. that incorporate such flash memories). [Example]

[0013] Next, an embodiment of the present invention will be described with reference to the drawings. It should be noted that the scale of the drawings is exaggerated to facilitate understanding of the invention and does not necessarily represent the scale of an actual product.

[0014] 1 is a schematic diagram showing a cross section of a cell array of a conventional two-dimensional NAND flash memory in a direction intersecting the NAND strings, i.e., in the word line direction. As shown in the figure, a conventional NAND flash memory 10 has active regions 30 extending in the bit line direction formed in a P-type semiconductor substrate or P-type well 20, and each active region 30 in the bit line direction is isolated by a trench 40.

[0015] The active region 30 provides a channel region and an N-type source / drain diffusion region for the memory cell. A floating gate 60 is formed on the active region 30 via a gate oxide film (or tunnel oxide film) 50, and is patterned for each memory cell. A control gate 70 extending in the word line direction is formed on the floating gate 60. The floating gate 60 is made of, for example, conductive polysilicon doped with impurities, and the control gate 70 is made of, for example, a conductive polysilicon layer and a metal material such as tungsten. The floating gate 60 is capacitively coupled to the control gate 70 via an upper dielectric layer.

[0016] When data is programmed into a memory cell, charges tunneled from the channel region of the active region 30 through the gate oxide film 50 are stored in the floating gate 60. When data is erased from the memory cell, charges stored in the floating gate 60 tunnel through the gate oxide film 50 and are released to the channel region.

[0017] As the process becomes more miniaturized, the distance between the floating gates 60 of adjacent memory cells becomes smaller, and the capacitive coupling between the adjacent floating gates 60 becomes larger. For example, the charge stored in the floating gate 60 of a programmed memory cell affects the threshold of the adjacent memory cell.

[0018] 2A and 2B are diagrams showing a two-dimensional NAND flash memory according to an embodiment of the present invention, in which FIG. 2A is a plan view of a portion of a cell array, and FIG. 2B is a schematic diagram of a cross section taken along line AA in FIG. 2A.

[0019] In the NAND flash memory 100 of this embodiment, a charge storage layer 110 consisting of multiple stacked insulating layers sandwiching SiN layers is formed on the active region 30 instead of the floating gate 60. The charge storage layer 110 is patterned on the active region 30 for each memory cell. The charge storage layer 110 may have, for example, an oxide / nitride / oxide ONO structure, or multiple types of insulating films may be stacked between the silicon substrate and the nitride layer rather than a single layer of oxide. Furthermore, multiple types of insulating films may be stacked between the nitride and the gate rather than a single layer of oxide. A first control gate (CG1) 120 is formed on the charge storage layer 110 and patterned to match the charge storage layer 110. The first control gate 120 may be made of, for example, impurity-doped conductive polysilicon, or may be made of multiple low-resistance materials, such as TaN, and / or another metal layer. A second control gate (CG2) 130 is formed on the first control gate 120 and patterned to extend in the word line direction (row direction). The second control gate 130 is electrically connected to the first control gate 120. The second control gate 130 is preferably low-resistance and is made of a metal material such as Al or Cu. The first control gate 120 may be made of the same material as the second control gate 130, or may be made of a different material.

[0020] As described above, the charge storage layer 110 has, for example, an oxide / nitride / oxide ONO structure, which provides a SONOS structure formed between a silicon substrate (or silicon well) and a first control gate made of polysilicon. During a program operation, the charge storage layer 110 stores charges that have tunneled from the channel region through the oxide by FN tunneling at the interface with the nitride layer, and during an erase operation, the charges stored in the charge storage layer are released to the channel region by FN tunneling through the oxide layer.

[0021] In this embodiment, the thickness of the nitride layer (SiN layer) of the charge storage layer is sufficiently smaller than the thickness of the floating gate of the FG structure, and the nitride layer is an insulating film, so that the capacitive coupling between adjacent memory cells can be reduced compared to the FG structure, and as a result, it is possible to narrow the threshold distribution of the memory cells. Furthermore, if the nitride layer of the charge storage layer is formed continuously in the word line direction (if it is not separated for each memory cell), there is a problem that the threshold of the memory cell fluctuates when electrons held in the nitride layer are attracted to holes and move, or when holes are attracted to electrons and move. However, by separating the charge storage layer for each memory cell as in this embodiment, the above problem can be solved.

[0022] Next, the manufacturing process of the cell array portion of the NAND flash memory of this embodiment will be described with reference to Figures 3 to 5. As shown in Figure 3(A), a charge storage layer 210 having a three-layer structure of, for example, an oxide film such as SiO2, a SiN film such as Si3N4, and an oxide film such as SiO2 is formed on the surface of a P-type silicon substrate or P-type well 200 (hereinafter referred to as "substrate" for convenience) by CVD or the like. In addition, a first control gate 220 made of, for example, polysilicon is formed on the charge storage layer 210.

[0023] Next, as shown in Fig. 3(B), a mask material 230 such as a resist is formed. Next, the mask material 230 is patterned by a photolithography process to form mask patterns M1 that are spaced apart at regular intervals and extend in the bit line direction, as shown in Fig. 3(C).

[0024] Next, as shown in Fig. 4(D), the exposed first control gate 220, charge storage layer 210, and substrate 200 are simultaneously anisotropically etched using a mask pattern M1 to form a stack of patterned charge storage layer 210 and first control gate 220 on the substrate 200, and at the same time, trenches 240 that define active regions 202 are formed in the substrate 200. Fig. 5(A) is a plan view of the substrate when the first control gate 220, charge storage layer 210, and substrate 200 have been etched using the mask pattern M1, and Fig. 4(D) corresponds to the cross section taken along line BB in Fig. 5(A).

[0025] The stack of the charge storage layer 210 and the first control gate 220 extends in the bit line direction, and the trench 240 is formed to be self-aligned to the sidewall of the stack of the charge storage layer 210 and the first control gate 220. Therefore, the trench 240 is formed with high precision without causing any positional error between the stack of the charge storage layer 210 and the first control gate 220. In addition, the charge storage layer 210 is protected from etching because it is covered by the first control gate 220.

[0026] 4(E), an insulating film 250 is formed on the entire surface of the substrate 200 including the trench 240, and then the insulating film 250 is etched to the vicinity of the surface of the substrate 200 so that a trench insulator 250A remains in the trench 240. At this time, the mask pattern M1 protects the first control gate 220 from etching.

[0027] Next, as shown in FIG. 4(F), the trench insulator 250A is etched by surface polishing to expose the surface of the mask pattern M1. Next, as shown in FIG. 4(G), the mask pattern M1 is removed, and the trench insulator 250A is surface polished to make the height of the trench insulator 250A approximately the same as that of the first control gate 220. In this way, the active region 202 extending in the bit line direction is isolated by the trench isolation region 250A, and a stack of the charge storage layer 210 and the first control gate 220 is formed on the active region 202. FIG. 5(B) is a plan view of the substrate when the heights of the first control gate 220 and the trench insulator 250A are made approximately the same, and FIG. 4(G) corresponds to the cross section taken along line CC in FIG. 5(B). Note that the process shown in FIG. 4(G) is not necessarily required.

[0028] Next, the manufacturing process for the cell array region and peripheral region of the flash memory of this embodiment will be described with reference to Figures 6 and 7. As shown in Figure 6(A), a charge storage layer 310 and a first control gate (CG1) 320 are formed on the entire surface of a P-type silicon substrate 300, and then a mask pattern M2 is formed to cover the cell array region. Next, as shown in Figure 6(B), the mask pattern M2 is used as an etching mask to remove the charge storage layer 310 and the first control gate 320 on the peripheral region by etching.

[0029] Next, after removing the mask pattern M2, as shown in FIG. 6C, a gate insulating film 330 is formed on the entire surface of the substrate 200, including the peripheral region. The gate insulating film 330 is, for example, a silicon oxide film. The peripheral region includes a page buffer / sense amplifier, a decoder, and other circuits, and these circuits include transistors driven at high voltages and transistors driven at low voltages. Therefore, the gate insulating film 330 is formed with multiple thicknesses, including thick and thin films suitable for high and low voltages. After the gate insulating film 330 is formed, a gate material 340 for the transistors in the peripheral region is formed on the entire surface of the substrate 200. The gate material 340 is, for example, polysilicon.

[0030] Next, the gate insulating film 330 and the gate material 340 are etched back or planarized to expose the first control gate 320 in the cell array region and the gate material 340 in the peripheral region, as shown in FIG. 6(D). Through these processes, the charge storage layer 310 and the first control gate 320 in the cell array region can be formed separately from the gate insulating film 330 and the gate material 340 in the peripheral region. It should be noted that in conventional FG-type flash memories, the floating gate in the cell array region is connected to the floating gate in the peripheral region (the floating gate is electrically connected to the control gate and functions as the gate of the transistor).

[0031] In the above process, the gate insulating film 330 and gate material 340 are formed after removing the mask pattern M2, but this is just an example, and the mask pattern M2 may be left. As shown in FIG. 6A(E), the gate insulating film 330 and gate material 340 are formed over the entire surface of the substrate, including the mask pattern M2. In this case, the height of the mask pattern M2 in the cell array region is set to be approximately the same as the height of the gate material 340 when the gate insulating film 330 in the peripheral region is a thick insulating film with a high breakdown voltage. Furthermore, the gate insulating film 330 around the boundary between the cell array region and the peripheral region is a thick insulating film with a high breakdown voltage.

[0032] 6A(F), a planarization process is performed to expose the mask pattern M2 in the cell array region and the gate material 340 in the peripheral region, and then the mask pattern M2 is removed. Through these processes, the charge storage layer 310 and the first control gate 320 in the cell array region and the gate insulating film 330 and the gate material 340 in the peripheral region can be formed separately.

[0033] After the first control gate 320 in the cell array region and the gate material 340 in the peripheral region are formed separately, a mask pattern M3 is formed as shown in Figure 7(E) and the gate materials, gate insulating film, and silicon in the cell array region and the peripheral region are simultaneously etched to form trenches 350 and 352 in the substrate 200. The trench 350 formed in the cell array region may have a different size and / or depth than the trench 352 formed in the peripheral region.

[0034] After removing the mask pattern M3, an insulating material 360 is formed to fill the trenches 350 and 352, as shown in FIG. 7(F). The insulating material 360 is, for example, a silicon oxide film. Next, the insulating material 360 is planarized to expose the surfaces of the first control gate 320 and the gate material 340.

[0035] Next, as shown in FIG. 7(F), a conductive material 370, which is a precursor of the second control gate, is formed on the entire surface of the substrate 300, including the first control gate 320 and the gate material 340. The conductive material 370 is not particularly limited, but may be a metal material such as Al or Cu. The conductive material 370 is electrically connected to the first control gate 320 and the gate material 340. Alternatively, a metal silicide may be formed between the conductive material 370 and the first control gate 320 and the gate material 340.

[0036] Next, as shown in FIG. 7(G), the conductive material 370 in the region of the cell array where the charge storage layer 310 and first control gate 320 are to be formed is patterned to extend in the word line direction, forming a second control gate 370A. The second control gate 370A is electrically connected to a corresponding plurality of first control gates 320 in the row direction, providing a word line. Furthermore, by patterning the conductive material 370, the underlying first control gates 320 and charge storage layer 310 are simultaneously etched, exposing the active region. Meanwhile, in the peripheral region, the conductive material 370 is patterned to form a wiring layer 370B electrically connected to the gate material 340 and the like.

[0037] After patterning the second control gate 370A, ion implantation is performed to form N-type impurity diffusion for source / drain in the exposed active region 202. Then, bit lines BL and source lines SL are formed in the cell array region, similar to a conventional NAND flash memory.

[0038] 8 is a cross section of the cell array region in the bit line direction, i.e., a cross section perpendicular to line AA in FIG. 2A. As shown in the figure, an N-well 410 is formed on a P-type silicon substrate 400, and a P-well 420 is formed within the N-well 410. An N-type diffusion region 430 is formed on the surface of the P-well 420 for the source / drain of the memory cells, bit line side select transistors, and source line side select transistors that constitute the NAND string. A charge storage layer 440 is formed on the P-well 420, and a first control gate 450 and a second control gate 460 are formed on the charge storage layer 440. A diffusion region 430A of the bit line side select transistor is electrically connected to a bit line BL via a contact CT1, and a diffusion region 430B of the source line side select transistor is electrically connected to a source line SL via a contact CT2.

[0039] The 2D-NAND flash memory of this embodiment has an insulator stack (charge storage layer) between silicon and a control gate, including an insulating layer that stores charges, such as a SiN layer. The control gate is composed of two layers: a first control gate CG1 formed on the insulator stack and a second control gate CG2 formed on the first control gate CG1. The insulator stack and the first control gate CG1 are successively deposited on silicon (Si). The first control gate CG1, the insulator stack, and the silicon are simultaneously etched, and the trench is filled with an insulating material, thereby forming a self-aligned shallow trench isolation region. After planarizing the insulating material filling the trench, a second control gate CG2 is deposited on the first control gate CG1, electrically connecting the first control gate CG1 and the second control gate CG2 to each other.

[0040] The second control gate, the first control gate, and the charge storage layer are simultaneously etched to form a plurality of rectangular word lines WL, which isolate the charge storage layer from adjacent cells. The ends of the word lines in the cell array region are connected to a row decoder, which applies biases to the word lines WL for read, write (program), and erase operations.

[0041] In this embodiment, an example of a charge storage layer having a three-layer structure of oxide / nitride / oxide is shown, but the present invention is not limited to this, and a charge storage layer having four or more layers including nitride may also be used. Also, the memory cell may be an SLC type that stores one bit (binary data) or a type that stores multiple bits.

[0042] Although the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the specific embodiment, and various modifications and variations are possible within the scope of the gist of the invention described in the claims. [Explanation of symbols]

[0043] 20: Silicon substrate 30:Active area 40: Trench isolation region 100: NAND flash memory 110:SiN layer 120: First Control Gate 130, 290: Second control gate 200: Substrate 210: Charge storage layer 220: First Control Gate 240: Trench 250: Interlayer insulating film 260: Gate insulating film 270: Gate material 280: Insulating materials

Claims

1. A NAND flash memory, an active region formed in a semiconductor substrate so as to extend in a bit line direction; a trench isolation region defined in the active region; a charge storage layer formed on the active region for each memory cell, the charge storage layer including a nitride layer sandwiched between insulating layers; a first conductive layer formed on the charge storage layer for each memory cell; a second conductive layer formed on the first conductive layer so as to extend in a word line direction; the second conductive layer is electrically connected to a plurality of first conductive layers in a corresponding row direction; The trench isolation region is aligned with sidewalls of the first conductive layer and the charge storage layer.

2. 2. The NAND flash memory of claim 1, wherein the charge storage layer comprises an ONO structure of oxide / nitride / oxide, or a structure including a stack of multiple types of insulating films other than oxide between a silicon substrate and the nitride layer, or a structure including a stack of multiple types of insulating films other than oxide between the nitride and the first conductive layer.

3. 3. The NAND flash memory of claim 2, wherein the first conductive layer comprises a polysilicon layer, the semiconductor substrate comprises a silicon region, and the charge storage layer comprises a SONOS structure.

4. 2. The NAND flash memory according to claim 1, wherein the trench isolation region is formed in a self-aligned manner when etching the first conductive layer, the charge storage layer, and the semiconductor substrate.

5. 2. The NAND flash memory according to claim 1, wherein the peripheral region of the NAND flash memory includes a gate insulating film and a gate material separated from the charge storage layer and the first conductive layer.

6. A method for manufacturing a NAND flash memory, comprising: forming a stack of a charge storage layer and a first conductive layer on a semiconductor substrate, the charge storage layer including a nitride layer sandwiched between insulating layers; simultaneously etching the first conductive layer, the charge storage layer, and the semiconductor substrate to pattern the first conductive layer and the charge storage layer in a bit line direction and to form trenches in the semiconductor substrate that define active regions; filling the trench with an insulating material; forming a second conductive layer on the entire surface of the semiconductor substrate including the first conductive layer; simultaneously etching the second conductive layer, the first conductive layer, and the charge storage layer to pattern the second conductive layer, the first conductive layer, and the charge storage layer in a word line direction; forming impurity regions for source / drain in the active region from which the second conductive layer, the first conductive layer, and the charge storage layer have been removed; A manufacturing method comprising the steps of:

7. The manufacturing method further comprises: forming a mask pattern covering a cell array region, and removing the charge storage layer and the first conductive layer on a peripheral region; forming the gate insulating film and the gate material on a peripheral region, the gate insulating film and the gate material being separated from the charge storage layer and the first conductive layer; The method of claim 6, comprising:

8. The manufacturing method further comprises: forming a gate insulating film and a gate material on the entire surface of a semiconductor substrate; planarizing the gate insulating film and the gate material until the first conductive layer on the cell array region is exposed; The method of claim 6, comprising:

9. 7. The manufacturing method according to claim 6, wherein the charge storage layer comprises an ONO structure of oxide / nitride / oxide, or a structure including a stack of multiple types of insulating films other than oxide between a silicon substrate and the nitride layer, or a structure including a stack of multiple types of insulating films other than oxide between the nitride and the first conductive layer.

10. 10. The method of claim 9, wherein the first conductive layer comprises a polysilicon layer, the semiconductor substrate comprises a silicon region, and the charge storage layer comprises a SONOS structure.

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