Output circuit

Abstract

To realize a highly reliable output circuit preferable for a high-speed operation using a low tolerant voltage transistor.SOLUTION: An output circuit 1 outputs an output signal Z having an amplitude VCCH corresponding to an input signal IN having an amplitude VCCL. The output circuit 1 includes: transistors P11, P12 connected between VCCH and an output terminal Z in series; a transistor N21 whose source is grounded, and which receives a first signal NL at the gate; a transistor P21 whose source is connected to VCCH, whose drain is connected to the gate of the transistor P11, and which receives a second signal NH at the gate; and a diode D11 connected between the drains of the transistors N21 and P21.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a high-voltage output circuit using low-voltage transistors. [Background technology]

[0002] Recent advances in semiconductor process miniaturization have led to lower internal power supply voltages for semiconductor integrated circuits and faster operation speeds. Transistor breakdown voltages are also becoming increasingly lower. Meanwhile, some interfaces require high voltages due to their specifications. This has created a need for high-voltage output circuits using low-voltage transistors.

[0003] In order to form a high-voltage output circuit using low-voltage transistors, it has been common to distribute the voltage applied to each transistor by connecting the low-voltage transistors in a cascode configuration or by inserting multiple diodes.

[0004] Patent Document 1 discloses an example of an output circuit that uses low-voltage transistors to output a high-voltage signal. This output circuit is configured so that a high voltage is not directly applied between the gate and source / drain or between the source and drain of the low-voltage transistor. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-90278 Summary of the Invention [Problem to be solved by the invention]

[0006] However, the output circuit disclosed in Patent Document 1 has problems such as low reliability due to an increase in the low level of the output signal and the generation of unnecessary current between the power supply and ground, and an insufficient driving capability of the low-voltage transistor, making it unsuitable for high-speed operation.

[0007] The present disclosure uses low-voltage transistors to realize an output circuit that is highly reliable and suitable for high-speed operation. [Means for solving the problem]

[0008] In an aspect of the present disclosure, an output circuit outputs from an output terminal an output signal having an amplitude corresponding to a second power supply voltage greater than a first power supply voltage in response to an input signal having an amplitude corresponding to the first power supply voltage, the output circuit including: first and second P-type transistors connected in series between a second power supply that supplies the second power supply voltage and the output terminal; first and second N-type transistors connected in series between a ground terminal and the output terminal; a third N-type transistor having a source grounded and a gate receiving a first signal having an amplitude between a ground voltage and a first predetermined voltage in response to the input signal; and a third N-type transistor having a source connected to the second power supply and a drain connected to a gate of the first P-type transistor and a gate receiving the first signal. a third P-type transistor receiving a second signal having an amplitude between the first predetermined voltage and the second power supply voltage in accordance with the first predetermined voltage; one or a plurality of first diodes connected in series between the drain of the third P-type transistor and the drain of the third N-type transistor; a fourth N-type transistor having a source grounded and a drain connected to the gate of the first N-type transistor and receiving the first signal at its gate; a fourth P-type transistor having a source connected to the second power supply and receiving the second signal at its gate; and one or a plurality of second diodes connected in series between the drain of the fourth P-type transistor and the drain of the fourth N-type transistor.

[0009] According to this embodiment, when the input signal is at a low level, the second signal corresponding to the input signal becomes a first predetermined voltage. The third P-type transistor has its source connected to the second power supply and receives the first predetermined voltage at its gate, so it turns on under the condition that (second power supply voltage - first predetermined voltage) is greater than the threshold voltage, and its drain becomes the second power supply voltage. The first P-type transistor has its gate connected to the drain of the third P-type transistor, so the second power supply voltage is applied to its gate, and it is sufficiently turned off. This makes it possible to avoid an increase in the low level of the output signal and the generation of unnecessary current between the power supply and ground, thereby achieving a highly reliable output circuit.

[0010] Furthermore, the fourth P-type transistor has its source connected to the second power supply and receives the first predetermined voltage at its gate, so it turns on when (second power supply voltage - first predetermined voltage) is greater than the threshold voltage, and its drain becomes the second power supply voltage. The first N-type transistor has its gate connected to the drain of the fourth N-type transistor, so a voltage that is the second power supply voltage minus the forward voltage of the first diode is applied to its gate. This allows the gate-source voltage of the first N-type transistor to be sufficiently high, thereby fully utilizing its driving capability. Therefore, an output circuit suitable for high-speed operation can be realized. [Effects of the Invention]

[0011] According to the present disclosure, it is possible to realize an output circuit that is highly reliable and suitable for high-speed operation using low-voltage transistors. [Brief explanation of the drawings]

[0012] [Figure 1] Circuit configuration of the output circuit according to the first embodiment [Figure 2] Circuit configuration of the signal conversion circuit in the output circuit of Figure 1 [Figure 3] The circuit configuration of the level shifter in the signal conversion circuit in Figure 2 [Figure 4] A diagram showing the operation of the output circuit of Figure 1. [Figure 5] A diagram showing the operation of the output circuit of Figure 1. [Figure 6] Circuit configuration of the output circuit according to the second embodiment [Figure 7] (a) is the circuit configuration of the pulse generation circuit in the output circuit of Figure 6, and (b) is the waveform diagram of the pulse signal. [Figure 8] (a) is the circuit configuration of the pulse generation circuit in the output circuit of Figure 6, and (b) is the waveform diagram of the pulse signal. [Figure 9] 6A is a circuit configuration of the circuit 11A in the output circuit of FIG. 6, and FIG. 6B is a waveform diagram of the signal PG. [Figure 10] Circuit configuration of the output circuit according to the third embodiment [Figure 11] 1A is a waveform diagram showing the operation of the circuit 11 in the first embodiment, and FIG. 1B is a waveform diagram showing a steady state. [Figure 12] 10A is a waveform diagram showing the operation of the circuit 11B in the third embodiment, and FIG. 10B is a waveform diagram showing the steady state. [Figure 13] Configuration example in which a diode is added to the circuit 11B in the third embodiment [Figure 14] (a) to (d) are circuit configurations in which diodes are realized using transistors with self-bias configurations. [Figure 15] (a) to (d) are circuit configurations in which diodes are realized using transistors with self-bias configurations. [Figure 16] Circuit configuration of the output circuit related to the comparative example DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments will be described with reference to the drawings. In the following description, "VCCL" and "VCCH" represent power supply voltages or the power supply itself, and "GND" represents ground voltages or a ground terminal. The power supply voltage VCCH is higher than the power supply voltage VCCL. Furthermore, "H" and "L" represent the logic levels of signals, with "H" representing a high level and "L" representing a low level. Furthermore, "Z" represents the output terminal or output signal of an output circuit.

[0014] In the following description, a MOS transistor is used as an example of a transistor. For a P-type MOS transistor (abbreviated as PMOS where appropriate), the threshold voltage is represented as Vthp and the gate-source voltage is represented as Vgsp. For an N-type MOS transistor (abbreviated as NMOS where appropriate), the threshold voltage is represented as Vthn and the gate-source voltage is represented as Vgsn. For a diode, the forward voltage is represented as Vf.

[0015] Furthermore, the symbol for PMOS is "P**," the symbol for NMOS is "N**," and the symbol for diode is "D**" (where * is a number). To avoid cumbersome descriptions of PMOS, NMOS, and diodes, for example, "PMOS P**" is sometimes abbreviated to simply "P**."

[0016] (Embodiment 1) Fig. 1 is a circuit diagram showing the circuit configuration of an output circuit according to embodiment 1. The output circuit 1 shown in Fig. 1 outputs an output signal Z of amplitude VCCH in accordance with an input signal IN of amplitude VCCL. The input signal IN of amplitude VCCL is a signal that is GND when L and VCCL when H. The output signal Z of amplitude VCCH is a signal that is GND when L and VCCH when H.

[0017] As shown in FIG. 1, output circuit 1 includes PMOS transistors P11 and P12 connected in series between power supply VCCH and output terminal Z, and NMOS transistors N11 and N12 connected in series between ground terminal GND and output terminal Z. Output circuit 1 also includes circuit 11 for outputting signal PG to the gate of P11, circuit 12 for outputting signal BP to the gate of P12, circuit 13 for outputting signal NG to the gate of N11, and circuit 14 for outputting signal BN to the gate of N12. Output circuit 1 also includes signal conversion circuit 10 for converting input signal IN into signals NH and NL that correspond to input signal IN. Signal NH has an amplitude between VCCL and VCCH, i.e., VCCL when low and VCCH when high. Signal NL has an amplitude between GND and VCCL, i.e., GND when low and VCCL when high.

[0018] The voltage when the signal NH is L and the voltage when the signal NL is H do not necessarily have to be the same as VCCL. However, it is preferable that the voltage when the signal NH is L and the voltage when the signal NL is H are the same.

[0019] The circuit 11 includes a PMOS P21, a diode D11, and an NMOS N21, which are connected in series between a power supply VCCH and a ground terminal GND. The source of P21 is connected to VCCH, the gate receives a signal NH, and the drain is connected to the anode of D11. The source of N21 is connected to GND, the gate receives a signal NL, and the drain is connected to the cathode of D11. The drain of P21 is connected to the gate of P11 and provides a signal PG.

[0020] The circuit 12 includes a PMOS P22, a diode D21, and an NMOS N22, which are connected in series between a power supply VCCL and a ground terminal GND. The source of P22 is connected to VCCL, the gate receives a signal NL, and the drain is connected to the anode of D21. The source of N22 is connected to GND, the gate receives a signal NL, and the drain is connected to the cathode of D21. The drain of P22 is connected to the gate of P12 and provides a signal BP.

[0021] Circuit 13 includes a PMOS P23, a diode D31, and an NMOS N23, which are connected in series between a power supply VCCH and a ground terminal GND. P23 ​​has a source connected to VCCH, a gate receiving a signal NH, and a drain connected to the anode of D31. N23 has a source connected to GND, a gate receiving a signal NL, and a drain connected to the cathode of D31. The drain of N23 is connected to the gate of N11 and provides a signal NG.

[0022] Circuit 14 includes a PMOS P24, a diode D41, and an NMOS N24, which are connected in series between a power supply VCCH and a power supply VCCL. P24 has a source connected to VCCH, a gate receiving a signal NH, and a drain connected to the anode of D41. N24 has a source connected to VCCL, a gate receiving a signal NH, and a drain connected to the cathode of D41. The drain of N24 is connected to the gate of N12 and provides a signal BN.

[0023] Although each of the diodes D11 to D41 is illustrated as a single diode element, it is not limited to a single diode element and may be a plurality of diode elements connected in series. The number of stages of the series-connected diode elements may be determined appropriately depending on the value of the power supply voltage and the withstand voltage value of the transistors.

[0024] Furthermore, instead of diode elements, the diodes D11 to D41 may be transistors with a self-bias configuration in which the gate is connected to the drain. In this case, the transistors may be either P-type or N-type.

[0025] FIG. 2 shows the circuit configuration of the signal conversion circuit 10. As shown in FIG. 2, the signal conversion circuit 10 includes four inverters IV10, IV11, IV12, and IV13 connected in series, and a level shifter 100. The inverters IV10, IV11, IV12, and IV13 are configured with low-voltage transistors. An input signal IN is applied to the input of the inverter IV10, and a signal NL is output from the output of the inverter IV13. When the input signal IN is L (GND), the signal NL is L (GND), and when the input signal IN is H (VCCL), the signal NL is H (VCCL). The level shifter 100 receives the output IN1 of the inverter IV10 and the output IN2 of the inverter IV11 as inputs, and outputs a signal NH. When the input signal IN is L (GND), the signal NH is L (VCCL), and when the input signal IN is H (VCCL), the signal NH is H (VCCH).

[0026] 3 shows the circuit configuration of the level shifter 100. As shown in FIG. 3, the level shifter 100 includes four PMOS transistors PM1, PM2, PM3, and PM4. The sources of PM1 and PM2 are connected to a power supply VCCL, and the sources of PM3 and PM4 are connected to a power supply VCCH. The output IN2 of the inverter IV11 is applied to the gate of PM1, and the output IN1 of the inverter IV10 is applied to the gate of PM2. The gate of PM3 is connected to the drains of PM2 and PM4. The gate of PM4 is connected to the drains of PM1 and PM3, and serves as the output node for the signal NH.

[0027] 2 and 3. In other words, any circuit configuration may be used as long as, when the input signal IN is L (GND), the signal NL is L (GND) and the signal NH is L (VCCL), and when the input signal IN is H (VCCL), the signal NL is H (VCCL) and the signal NH is H (VCCH).

[0028] <Comparative> Fig. 16 shows, for comparison, the circuit configuration of an output circuit disclosed in Patent Document 1. Like the output circuit 1 described above, the output circuit shown in Fig. 16 outputs an output signal Z of amplitude VCCH in accordance with an input signal IN of amplitude VCCL.

[0029] The output circuit according to the comparative example of FIG. 16 has the following problem.

[0030] (1) When the input signal IN=L, the output signal Z is expected to be L (GND). However, in the output circuit of Figure 16, when IN=L, PG=VCCH-|Vthp|, so P11 cannot be turned off completely. This causes the output signal Z to rise to a low level, and if this rise exceeds the input level specification of the circuit receiving the output signal Z, it will cause a communication error. Furthermore, because P11 does not turn off completely, unnecessary current flows through the path VCCH → P11 → P12 → N12 → N11 → GND. This accelerates the deterioration of transistors and wiring, resulting in reduced reliability.

[0031] (2) In the output circuit of Figure 16, the same signal VG is applied to the gates of P12 and N12. Therefore, the combination of the breakdown voltage of the low-voltage transistor and the voltage value of VCCH makes it impossible to obtain sufficient driving capability, making it unsuitable for high-speed operation.

[0032] For example, let VCCH=1.8V and the breakdown voltage of the transistor be 1.5V. If the gate-source voltages of P12 and N12 are Vgsp12 and Vgsn12, respectively, then When IN=H and Z=H output, P11 turns on and node a becomes VCCH, so |Vgsp12|=1.8-VG When IN=L and Z=L output, N11 turns on and node b becomes GND, so |Vgsn12|=VG-0 Generally, the higher the gate-source voltage, the higher the current capability of the transistor. Therefore, it is preferable to set the voltage of the signal VG to a voltage at which both |Vgsp12| and |Vgsn12| are maximized. Therefore, it is preferable to set the signal VG to 0.9V. In this case, |Vgsp12|=|Vgsn12|=0.9V This becomes:

[0033] As a result, the transistors P12 and N12, which can be applied with 1.5V as a gate-source voltage, are driven by applying 0.9V, and sufficient driving capability cannot be obtained for P12 and N12.

[0034] (3) In the output circuit of Fig. 16, the output of inverter IV1, which operates on VCCL, is given as signal NG to the gate of N11. For this reason, depending on the value of VCCL, it may not be possible to obtain sufficient driving capability for N11.

[0035] For example, let VCCL=0.8V, VCCH=1.8V, and the transistor's breakdown voltage be 1.5V. If the gate-source voltage of N11 is Vgsn11, then When IN=L and Z=L output, the output of inverter IV1, i.e., signal NG, becomes VCCL (0.8V), |Vgsn11|=0.8V This becomes:

[0036] As a result, transistor N11, which can be applied with 1.5V as a gate-source voltage, is driven by applying 0.8V, and sufficient driving capability cannot be obtained for N11.

[0037] <Operation of the Output Circuit According to the Present Embodiment> The operation of the output circuit 1 according to the first embodiment will be described. Here, as an example, VCCL=0.8V VCCH=1.8V Transistor breakdown voltage = 1.5V Transistor threshold voltage |Vthp|=|Vthn|=0.5V Diode forward voltage Vf=0.4V Let's say.

[0038] (1) When IN=L Fig. 4 shows the potentials of each node when IN=L (GND=0V) in the output circuit 1 of Fig. 1. The signal conversion circuit 10 outputs L (0.8V) as the signal NH and L (0V) as the signal NL.

[0039] At this time, P21, P22, P23, and P24 are all |Vgsp|>|Vthp|=0.5V And N21, N22, N23, and N24 are all |Vgsn|<|Vthn|=0.5V and turns off.

[0040] The signal PG output from circuit 11 becomes VCCH (1.8V) because P21 is turned on. As a result, the gate-source voltage |Vgsp11| of P11 becomes 0V, which allows P11 to be completely turned off. At this time, the potential of cathode 11b of D11 in circuit 11 becomes 1.4V, which is lower than the potential of signal PG by Vf (0.4V) of D11.

[0041] A signal BP is output from circuit 12, and a signal BN is output from circuit 14. That is, signals BP and BN can be controlled independently. Because P22 is turned on, signal BP output from circuit 12 becomes VCCL (0.8V). At this time, in circuit 12, the potential of cathode 21b of D21 becomes 0.4V, which is lower than the potential of signal BP by Vf (0.4V) of D21. Because P24 is turned on, signal BN output from circuit 14 becomes 1.4V, which is lower than VCCH (1.8V) by Vf (0.4V) of D41. Therefore, the gate-source voltage |Vgsn12| of N12 can be made higher than in the comparative example, which is suitable for high-speed operation.

[0042] Because P23 is turned on, the signal NG output from circuit 13 becomes 1.4 V, which is lower than VCCH (1.8 V) by Vf (0.4 V) of D31. Therefore, the gate-source voltage |Vgsn11| of N11 can be made higher than in the comparative example, which is suitable for high-speed operation.

[0043] Then, N11 turns on, and the potential of node b becomes 0 V. N12 turns on, and Z becomes L (0 V). The potential of node a becomes the sum of the potential of signal BP (0.8 V) and |Vthp| (0.5 V), that is, 1.3 V.

[0044] As a result of the above operation, the gate-source / drain voltage and the source-drain voltage for all transistors are kept within the breakdown voltage value (1.5V).

[0045] (2) When IN=H Fig. 5 shows the potentials of each node when IN=H (VCCL=0.8V) in the output circuit 1 of Fig. 1. The signal conversion circuit 10 outputs H (1.8V) as the signal NH and H (0.8V) as the signal NL.

[0046] At this time, P21, P22, P23, and P24 are all |Vgsp|<|Vthp|=0.5V And N21, N22, N23, and N24 are all |Vgsn|>|Vthn|=0.5V and turns on.

[0047] Since N21 is turned on, the signal PG output from the circuit 11 becomes 0.4V, which is increased from GND (0V) by Vf (0.4V) of D11.

[0048] Because N22 is turned on, the signal BP output from circuit 12 becomes 0.4V, which is increased from GND (0V) by the Vf (0.4V) of D21. Therefore, the gate-source voltage |Vgsp12| of P12 can be made higher than in the comparative example, which is suitable for high-speed operation. Because N24 is turned on, the signal BN output from circuit 14 becomes VCCL (0.8V). At this time, in circuit 14, the potential of the anode 41a of D41 becomes 1.2V, which is increased from the potential of signal BN by the Vf (0.4V) of D41.

[0049] The signal NG output from the circuit 13 becomes GND (0 V) because N23 is turned on. Therefore, N11 is turned off because |Vgsn11| = 0 V. Also, at this time, in the circuit 13, the potential of the anode 31a of D31 becomes 0.4 V, which is increased from the potential of the signal NG by Vf (0.4 V) of D31.

[0050] Then, P11 turns on, and the potential at node a becomes VCCH (1.8V). P12 turns on, and Z becomes H (1.8V). The potential at node b becomes the value obtained by subtracting |Vthn| (0.5V) from the potential of signal BN (0.8V), that is, 0.3V.

[0051] As a result of the above operation, the gate-source / drain voltage and the source-drain voltage for all transistors are kept within the breakdown voltage value (1.5V).

[0052] According to this embodiment, the problems in the comparative example described above can be solved.

[0053] That is, in the output circuit 1, by applying the signal NH to the gate of P21 in the circuit 11, P21 can be turned on sufficiently. This allows the H level of the signal PG to be raised sufficiently to VCCH, so that P11 can be turned off completely. Therefore, it is possible to avoid the rise in the L level of the output signal Z and the generation of unnecessary current between VCCH and GND in the comparative example (solution of problem (1)).

[0054] In addition, in output circuit 1, a signal BP output by circuit 12 is applied to the gate of P12, while a signal BN output by circuit 14 is applied to the gate of N12. This makes it possible to adjust the signals BP and BN so that the operations of P12 and N12 are optimized. Therefore, sufficient driving capability can be obtained for P12 and N12, making them suitable for high-speed operation (solving problem (2)).

[0055] Furthermore, in the output circuit 1, the signal NG output by the circuit 13 is given to the gate of N11, and the signal NG is generated in the circuit 13 without depending on VCCL. This allows the gate-source voltage of N11 to be increased when the input signal IN is L, which is suitable for high-speed operation (solution of problem (3)).

[0056] Therefore, according to this embodiment, an output circuit 1 can be realized that is highly reliable because the output signal Z does not rise to the L level or an unnecessary current flows between the power supply and the ground by using low-voltage transistors, and that is suitable for high-speed operation because sufficient driving capability can be obtained for the low-voltage transistors.

[0057] (Embodiment 2) Fig. 6 is a circuit diagram showing the circuit configuration of an output circuit according to embodiment 2. Like the output circuit 1 according to embodiment 1, the output circuit 2 shown in Fig. 6 outputs an output signal Z of amplitude VCCH in response to an input signal IN of amplitude VCCL. The basic configuration of the output circuit 2 is the same as that of the output circuit 1. In the output circuit 2, circuits 11A, 12A, 13A, and 14A having additional components are provided instead of circuits 11, 12, 13, and 14. Pulse generating circuits 21 and 22 are also added.

[0058] In the circuit 11A, D11 in the circuit 11 is replaced with multiple stages (four stages in the figure) of diodes D11a, D11b, D11c, and D11d connected in series, and an NMOS N41 is added. The source and drain of N41 are connected to a node 11b between D11b and D11c and a node 11d between D11d and N21.

[0059] In the circuit 12A, D21 in the circuit 12 is replaced with multiple stages (four stages in the figure) of diodes D21a, D21b, D21c, and D21d connected in series, and an NMOS N42 is added. The source and drain of N42 are connected to a node 21b between D21b and D21c and a node 21d between D21d and N22.

[0060] In the circuit 13A, D31 in the circuit 13 is replaced with multiple stages (four stages in the figure) of diodes D31a, D31b, D31c, and D31d connected in series, and a PMOS P41 is added. The source and drain of P41 are connected to a node 31a between P23 and D31a and a node 31c between D31b and D31c.

[0061] In the circuit 14A, D41 in the circuit 14 is replaced with multiple stages (four stages in the figure) of diodes D41a, D41b, D41c, and D41d connected in series, and a PMOS P42 is added. The source and drain of P42 are connected to a node 41a between P24 and D41a and a node 41c between D41b and D41c.

[0062] The pulse generating circuit 21 generates a pulse signal PP from the signal NL, which is applied to the gates of N41 and N42. The pulse generating circuit 22 generates a pulse signal PN from the signal NH, which is applied to the gates of P41 and P42.

[0063] Fig. 7(a) is an example of the circuit configuration of the pulse generating circuit 21, and Fig. 7(b) is a waveform diagram of the pulse signal PP. The amplitude of the pulse signal PP is the same as that of the signal NL, and is between GND and VCCL. As shown in Fig. 7(b), when the signal NL makes a rising transition from L to H, the pulse signal PP generates a pulse, remains H for a predetermined period, and then makes a transition to L. When the signal NL makes a falling transition from H to L, the pulse signal PP remains L and does not change.

[0064] Fig. 8(a) is an example of the circuit configuration of the pulse generating circuit 22, and Fig. 8(b) is a waveform diagram of the pulse signal PN. The amplitude of the pulse signal PN is the same as that of the signal NH, and is VCCL to VCCH. As shown in Fig. 8(b), when the signal NH makes a falling transition from H to L, the pulse signal PN generates a pulse and remains L for a predetermined period, after which it transitions to H. When the signal NH makes a rising transition from L to H, the pulse signal PN remains H and does not change.

[0065] The characteristics of the output circuit 2 will be described using the operation of the circuit 11A as an example. FIG. 9(a) shows the circuit configuration of the circuit 11A, and (b) is a waveform diagram of the signal PG output from the circuit 11A. VCCL=0.8V VCCH=1.8V Let's say.

[0066] When the input signal IN transitions to H, the signals NH and NL transition to H accordingly. When the signal NL transitions to H (0.8V), N21 turns on. When the signal NL transitions to H, the pulse signal PP generates a pulse and remains H for a predetermined period. While the pulse signal PP is H, N41 turns on, shorting nodes 11b and 11d and making them equal in potential. At this time, the number of diodes between P21 and N21 is effectively two, and the potential difference across each diode for D11a and D11b increases. Due to the static characteristics of a diode, the greater the potential difference between the anode and cathode, the greater the current that flows. Therefore, while N41 is on, the transition of the signal PG from H to L becomes faster.

[0067] In the waveform diagram of signal PG shown in FIG. 9(b), dashed line A shows the change when N41 is always off (four-stage diodes), and dashed line B shows the change when N41 is always on (two-stage diodes). Because dashed line B has a larger potential difference per diode, signal PG falls faster. Signal PG changes in the same way as dashed line B during the period when pulse signal PP is H (period (1)), and changes in the same way as dashed line A during the period when pulse signal PP returns to L (period (2)). As a result, signal PG changes as shown by the solid line, and the transition from H to L becomes faster.

[0068] In this way, in circuit 11A, by providing transistor N41 and shorting both ends of D11c and D11d, among the multiple diodes connected in series, when the input signal IN makes a rising transition, the response of the falling edge of signal PG can be accelerated.

[0069] In the circuit configuration of FIG. 9(a), both ends of D11c and D11d among the multiple diodes connected in series are short-circuited via N41, but the number of short-circuited diodes is not limited to two. For example, both ends of one diode may be short-circuited, or both ends of three or more diodes may be short-circuited. Furthermore, the positions of the short-circuited diodes may be different from those shown in FIG. 9(a). For example, in the circuit configuration of FIG. 9(a), both ends of D11a and D11b may be short-circuited, or both ends of D11b and D11c may be short-circuited.

[0070] Circuits 12A, 13A, and 14A operate in the same manner as circuit 11A. That is, in circuit 12A, when signal NL goes high, N22 turns on. While pulse signal PP is high, N42 turns on, so nodes 21b and 21d are shorted and at the same potential, and signal BP transitions from high to low more quickly. In circuit 13A, when signal NH goes low, P23 turns on. While pulse signal PN is low, P41 turns on, so nodes 31a and 31c are shorted and at the same potential, and signal NG transitions from low to high more quickly. In circuit 14A, when signal NH goes low, P24 turns on. While pulse signal PN is low, P42 turns on, so nodes 41a and 41c are shorted and at the same potential, and signal BN transitions from low to high more quickly.

[0071] As described above, according to this embodiment, the response of the signals PG and BP given to the gates of P11 and P12 to the falling edge can be accelerated, and the response of the signals NG and BN given to the gates of N11 and N12 to the rising edge can be accelerated, thereby realizing high-speed operation of the output circuit.

[0072] Note that N41 in circuit 11A and N42 in circuit 12A may be replaced by PMOS transistors. In this case, an inverted signal of pulse signal PP may be applied to the gates of the PMOS transistors. Also, P41 in circuit 13A and P42 in circuit 14A may be replaced by NMOS transistors. In this case, an inverted signal of pulse signal PN may be applied to the gates of the NMOS transistors.

[0073] (Embodiment 3) Fig. 10 is a circuit diagram showing the circuit configuration of an output circuit according to embodiment 3. Like the output circuit 1 according to embodiment 1, the output circuit 3 shown in Fig. 10 outputs an output signal Z of amplitude VCCH in response to an input signal IN of amplitude VCCL. The basic configuration of the output circuit 3 is the same as that of the output circuit 1. In the output circuit 3, circuits 11B, 12B, 13B, and 14B having additional components are provided instead of circuits 11, 12, 13, and 14.

[0074] In circuit 11B, diodes D12 and D13 connected in series are added between the power supply VCCH and the drain of P21. Also, an NMOS N31 is added between P21 and D11. A signal NH is applied to the gate of N31.

[0075] In the circuit 12B, a diode D22 is added between the power supply VCCL and the drain of P22.

[0076] In circuit 13B, serially connected diodes D32 and D33 are added between the ground terminal GND and the drain of N23. A PMOS P31 is also added between D31 and N23. A signal NL is applied to the gate of P31.

[0077] In the circuit 14B, a diode D42 is added between the power supply VCCL and the drain of N24.

[0078] The features of the output circuit 3 will be described in comparison with the output circuit 1 according to the first embodiment. Here, as in the description of the first embodiment, VCCL=0.8V VCCH=1.8V Transistor breakdown voltage = 1.5V |Vthp|=|Vthn|=0.5V Vf=0.4V Let's say.

[0079] First, the operation of the circuit 11 in the output circuit 1 of the first embodiment will be described with reference to FIG. 11. As shown in FIG. 11(a), in the circuit 11, the signal PG and the potential of the node 11a have the same waveform. During the period (period (1)) when the input signal IN is H, N21 is on, so the potential of the signal PG is GND+Vf (0.4V). During the period (period (2)) when the input signal IN is L, P21 is on, so the potential of the signal PG is VCCH (1.8V), and the potential of the node 11b is VCCH-Vf (1.4V). Therefore, the breakdown voltage of each transistor does not exceed 1.5V.

[0080] However, in actual operation, there are cases where the signal is fixed at H or L for a long period of time (steady state). Figure 11(b) shows the waveform in the steady state, assuming that periods (1) and (2) are sufficiently long. During the period (period (1)) when the input signal IN is H, N21 is on, so the potential of the signal PG is initially GND + Vf (0.4 V). However, because a diode current corresponding to the potential difference between nodes 11a and 11b continues to flow through D11, the potential of the signal PG gradually decreases over time. As a result, there is a possibility that the withstand voltage values ​​of P11 and P21 may be exceeded.

[0081] Furthermore, during the period (period (2)) when the input signal IN is low, P21 is on, and the potential at node 11b is initially VCCH-Vf (1.4V). However, a diode current corresponding to the potential difference between nodes 11a and 11b continues to flow through D11, and the potential at node 11b gradually rises over time. As a result, there is a possibility that the withstand voltage of N21 may be exceeded.

[0082] In contrast, in this embodiment, circuit 11B operates as follows. As shown in FIG. 12(a), in circuit 11B, N21 and N31 are turned on during the period (period (1)) when input signal IN is H. Therefore, the potential of signal PG becomes a value obtained by dividing VCCH (1.8V) by three diodes D11, D12, and D13, and in this case, PG=0.6V. Therefore, the withstand voltage values ​​of P11 and P21 are not exceeded.

[0083] During the period (period (2)) when the input signal IN is L, P21 is turned on, so PG=VCCH (1.8V), but N31 is turned off, so the potential of the node 11a is VCCL-|Vthn31|=0.8-0.5=0.3V Therefore, the potential of node 11b is determined to be 0.3V or less, and the withstand voltage of N21 is not exceeded.

[0084] In addition, in the steady state, circuit 11B operates as shown in Figure 12(b). During the period when input signal IN is H (period (1)), N21 and N31 are on, and the potential of signal PG becomes PG = 0.6V. At this time, because steady current is generated in D11, D12, and D13, PG remains constant at PG = 0.6V even after a sufficiently long time has passed. Therefore, the withstand voltage value of P11 and P21 is not exceeded.

[0085] During the period (period (2)) when the input signal IN is L, P21 is turned on and PG=VCCH (1.8V), but N31 is turned off, so the potential of the node 11a is VCCL-|Vthn31|=0.8-0.5=0.3V Therefore, even after a sufficiently long time has passed, the potential of node 11b is determined to be 0.3V or less, and N21 will not exceed its withstand voltage value.

[0086] As described above, by providing N31 in circuit 11B, the withstand voltage of N21 is guaranteed regardless of the number of stages of D11. This makes it possible to minimize the number of stages of D11. Furthermore, since the potential of signal PG when input signal IN is H is determined by voltage division by D11 to D13, reducing the number of stages of D11 also makes it possible to reduce the number of stages of D12 and D13. This allows the circuit to be implemented in a smaller area.

[0087] Furthermore, in circuit 11B, the potential of signal PG can be fixed to any value by adjusting the number of diodes provided between VCCH and the drain of P21. For example, as shown in FIG. 13, suppose diodes D14, D15, and D16 are further added between D13 and VCCH. In this case, there are five diodes between the power supply VCCH and the signal line of signal PG, so the potential of signal PG is PG=VCCH×(1 / 6)=1.8 / 6=0.3V As a result, the gate-source voltage |Vgsp11| of P11 becomes 1.5 (= 1.8 - 0.3) V, which can be set to the maximum value for a transistor with a breakdown voltage of 1.5 V. This voltage value remains constant even in steady state. Therefore, P11 can be used with optimal driving capability.

[0088] Circuits 12B, 13B, and 14B also operate in the same manner as circuit 11B. That is, in circuit 12B, when input signal IN goes high and signal NL goes high, N22 turns on. At this time, the potential of signal BP becomes a value obtained by dividing VCCL by two diodes D21 and D22, and is constant even in the steady state.

[0089] In the circuit 13B, P23 and P31 are on while the input signal IN is at L. Therefore, the potential of the signal NG(H) is a value obtained by dividing VCCH by three diodes D31, D32, and D33, and is constant even in a steady state. Also, while the input signal IN is at H, N23 is on, so the potential of the signal NG(L) becomes GND, but P31 is off, so the potential of the node 31b becomes VCCL+|Vthp31|=0.8+0.5=1.3V Therefore, the potential of node 31a is determined to be 1.3V or higher, and P23 will not exceed its withstand voltage even in a steady state.

[0090] In circuit 14B, when input signal IN goes low and signal NH goes low, P24 turns on. At this time, the potential of signal BN is a value obtained by dividing (VCCH-VCCL) by two diodes D41 and D42, and is constant even in the steady state.

[0091] As described above, according to this embodiment, the signals PG, BP, BN, and NG can be stabilized even in a steady state where the signals are fixed at H or L for a long period of time. Furthermore, the driving capability of the transistors can be increased within a range that does not exceed the breakdown voltage.

[0092] The second and third embodiments may be combined.

[0093] In each of the above-described embodiments, each diode may be replaced with a self-biased transistor in which the gate is connected to the drain. In this case, the transistor may be either a P-type or an N-type.

[0094] 14 shows an example of a circuit configuration in which diodes are realized by NMOSs with a self-bias configuration, and (a) to (d) respectively correspond to circuits 11B, 12B, 13B, and 14B in the output circuit 3 of embodiment 3. In FIG. 14, diodes D11 and the like are replaced with NMOSs N101 and the like.

[0095] 15 shows an example of a circuit configuration in which diodes are realized by PMOSs with a self-bias configuration, and (a) to (d) respectively correspond to circuits 11B, 12B, 13B, and 14B in the output circuit 3 of embodiment 3. In FIG. 15, diodes D11 and the like are replaced with PMOSs P101 and the like.

[0096] The voltage values ​​of VCCL, VCCH, withstand voltages and threshold voltages of transistors used in the above-described embodiments are merely examples, and the present disclosure is not limited to these values. [Industrial Applicability]

[0097] According to the present disclosure, a highly reliable output circuit suitable for high-speed operation can be realized using low-voltage transistors, which is useful for realizing, for example, a high-performance, low-power-consumption semiconductor chip for communications. [Explanation of symbols]

[0098] 1, 2, 3 output circuit 10 Signal conversion circuit 11, 12, 13, 14 circuits 21,22 Pulse generation circuit IN Input signal NL 1st signal NH 2nd signal Z output signal, output terminal VCCL First power supply, first power supply voltage VCCH Second power supply, second power supply voltage GND Ground terminal, ground voltage P** (* is a number) PMOS (P-type transistor) N** (* is a number) NMOS (N-type transistor) D**(*number) Diode

Claims

1. 1. An output circuit that outputs, from an output terminal, an output signal having an amplitude corresponding to a second power supply voltage that is higher than a first power supply voltage in response to an input signal having an amplitude corresponding to the first power supply voltage, first and second P-type transistors connected in series between a second power supply that supplies the second power supply voltage and the output terminal; first and second N-type transistors connected in series between a ground terminal and the output terminal; a third N-type transistor having a grounded source and receiving at its gate a first signal having an amplitude between the ground voltage and a first predetermined voltage according to the input signal; a third P-type transistor having a source connected to the second power supply and a drain connected to the gate of the first P-type transistor, and receiving at its gate a second signal having an amplitude between the first predetermined voltage and the second power supply voltage in accordance with the input signal; one or more first diodes connected in series between the drain of the third P-type transistor and the drain of the third N-type transistor; a fourth N-type transistor having a source grounded, a drain connected to the gate of the first N-type transistor, and a gate receiving the first signal; a fourth P-type transistor having a source connected to the second power supply and a gate receiving the second signal; one or a plurality of second diodes connected in series, connected between the drain of the fourth P-type transistor and the drain of the fourth N-type transistor; Output circuit.

2. 2. The output circuit according to claim 1, a plurality of the first diodes connected in series; and a pulse generating circuit that generates a pulse signal that generates a pulse for a predetermined period when the first signal transitions to a rising edge; a transistor having a source and a drain connected to both ends of a part of the first diode, a gate receiving the pulse signal, and being turned on during the predetermined period during which the pulse is generated; Output circuit.

3. 2. The output circuit according to claim 1, a plurality of the second diodes connected in series; and a pulse generating circuit that generates a pulse signal that generates a pulse for a predetermined period when the second signal transitions to a falling edge; a transistor having a source and a drain connected to both ends of a part of the second diode, a gate receiving the pulse signal, and being turned on during the predetermined period during which the pulse is generated; Output circuit.

4. 2. The output circuit according to claim 1, a third diode, which may be one or more diodes connected in series, connected between the second power supply and the drain of the third P-type transistor; Output circuit.

5. 2. The output circuit according to claim 1, a fourth diode or a plurality of fourth diodes connected in series between the ground terminal and the drain of the fourth N-type transistor; Output circuit.

6. 2. The output circuit according to claim 1, a fifth N-type transistor provided between the drain of the third P-type transistor and the first diode, the fifth N-type transistor receiving the second signal at its gate; Output circuit.

7. 2. The output circuit according to claim 1, a fifth P-type transistor provided between the drain of the fourth N-type transistor and the second diode, the fifth P-type transistor receiving the first signal at its gate; Output circuit.

8. 2. The output circuit according to claim 1, a first circuit that receives the first signal and applies a signal to a gate of the second P-type transistor; The first circuit is a sixth P-type transistor having a source connected to a first power supply that supplies the first power supply voltage, a drain connected to the gate of the second P-type transistor, and a gate receiving the first signal; a sixth N-type transistor having a grounded source and receiving the first signal at its gate; one or a plurality of fifth diodes connected in series, connected between the drain of the sixth P-type transistor and the drain of the sixth N-type transistor; Output circuit.

9. 9. The output circuit according to claim 8, a pulse generating circuit that generates a pulse signal that generates a pulse for a predetermined period when the first signal transitions to a rising edge; The first circuit is a plurality of the fifth diodes connected in series; and a transistor having a source and a drain connected to both ends of a part of the fifth diode, a gate of which receives the pulse signal, and which is turned on during the predetermined period when the pulse is generated; Output circuit.

10. 9. The output circuit according to claim 8, The first circuit is a sixth diode, which may be one or more sixth diodes connected in series, connected between the first power supply and the drain of the sixth P-type transistor; Output circuit.

11. 2. The output circuit according to claim 1, a second circuit that receives the second signal and applies a signal to a gate of the second N-type transistor; The second circuit is a seventh P-type transistor having a source connected to the second power supply and a gate receiving the second signal; a seventh N-type transistor having a source connected to a first power supply that supplies the first power supply voltage, a drain connected to the gate of the second N-type transistor, and a gate receiving the second signal; one or more seventh diodes connected in series between the drain of the seventh P-type transistor and the drain of the seventh N-type transistor; Output circuit.

12. 12. The output circuit of claim 11, a pulse generating circuit that generates a pulse signal that generates a pulse for a predetermined period when the second signal transitions to a falling edge; The second circuit is a plurality of the seventh diodes connected in series; and a transistor having a source and a drain connected to both ends of a part of the seventh diode, a gate of which receives the pulse signal, and which is turned on during the predetermined period when the pulse is generated; Output circuit.

13. 12. The output circuit of claim 11, The second circuit is an eighth diode or a plurality of eighth diodes connected in series between the first power supply and the drain of the seventh N-type transistor; Output circuit.

14. 2. The output circuit according to claim 1, The first predetermined voltage is the same as the first power supply voltage. Output circuit.

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