Semiconductor device having asymmetric integrated lumped gate resistor for balanced turn-on / turn-off behavior and / or multiple spaced lumped gate resistors for improved power handling

Abstract

To provide a semiconductor device that includes a gate pad, a gate bus, and a gate resistor structure electrically interposed between the gate pad and the gate bus.SOLUTION: In a semiconductor device, a gate resistor structure has a first resistance value with respect to a current flowing from a gate pad to a gate bus and a second resistance value with respect to a current flowing from the gate bus to the gate pad, the first resistance value is different from the second resistance value, and the first and second resistance values is set to improve balance of turn-on and turn-off switching behavior of the semiconductor device.SELECTED DRAWING: Figure 2B

Description

[Technical Field]

[0001] This application claims priority to U.S. Patent Application Serial No. 17 / 382,407, filed July 22, 2021, and U.S. Patent Application Serial No. 17 / 843,010, filed June 17, 2022, the entire contents of each of which are incorporated herein by reference as if set forth in their entirety.

[0002] The present invention relates to semiconductor devices, and more particularly to semiconductor devices having lumped gate resistors. [Background technology]

[0003] A wide variety of power semiconductor devices are known in the art, including, for example, power metal oxide semiconductor field effect transistors ("MOSFETs"), insulated gate bipolar transistors ("IGBTs"), and various other devices. These power semiconductor devices are often fabricated from wide bandgap semiconductor materials, such as silicon carbide or gallium nitride based materials. As used herein, the term "wide bandgap semiconductor" includes any semiconductor with a bandgap of at least 1.4 eV. Power semiconductor devices are designed to selectively block or pass high voltages and / or large currents. For example, in the blocking state, power semiconductor devices may be designed to withstand potentials of hundreds or thousands of volts.

[0004] Power semiconductor devices, such as power MOSFETs, can have a lateral or vertical structure. A power MOSFET with a lateral structure has both the source and drain regions of the MOSFET on the same major surface (i.e., the top or bottom) of the device's semiconductor layer structure. In contrast, a power MOSFET with a vertical structure has its source region on one major surface of the semiconductor layer structure and its drain region on the other (opposite) major surface. Vertical device structures are typically used in very high power applications because vertical structures enable a thick semiconductor drift layer that can withstand high current densities and block high voltages. As used herein, the term "semiconductor layer structure" refers to a structure including one or more semiconductor layers in which a p-n junction is formed. A semiconductor layer structure typically includes a semiconductor substrate on which multiple semiconductor epitaxial layers are formed. A wide-bandgap semiconductor layer structure refers to a semiconductor layer structure in which a p-n junction is formed in one or more wide-bandgap semiconductor materials.

[0005] A conventional silicon carbide vertical power MOSFET includes a silicon carbide drift region formed on a silicon carbide substrate, such as a silicon carbide wafer. A so-called "well" region, having the opposite conductivity type to the drift region, is formed in the upper portion of the drift region, and a silicon carbide source region, having the same conductivity type as the drift region, is formed within the well region. The silicon carbide substrate, silicon carbide drift region, silicon carbide well region, and silicon carbide source region form the semiconductor layer structure of the power MOSFET. Gate fingers are formed in or on the semiconductor layer structure to form individual unit cell transistors.

[0006] The unit cell transistors are formed within the so-called "active area" of a MOSFET. MOSFETs further include one or more inactive areas, such as termination regions, which may surround the active area and / or gate bond pad area. The active area serves as the main junction, blocking voltage during reverse-bias operation and providing current flow during forward-bias operation. Power MOSFETs typically have a unit cell structure, meaning that the active area contains many individual "unit cell" MOSFETs electrically connected in parallel to function as a single power MOSFET. In high-power applications, such devices may contain thousands or tens of thousands of unit cells.

[0007] Many power semiconductor devices, such as power MOSFETs and IGBTs, have a gate structure. These devices can be turned on and off by applying various bias voltages to the gate structure. The gate structure has a distributed gate resistance that depends on the length of the electrical path from the gate bond pad (or other gate terminal) to the gate fingers of each individual unit cell and the sheet resistance of the material forming the gate structure. The gate structure may include, for example, a gate bond pad, multiple gate fingers within the active area of ​​the device, a gate pad, and one or more gate buses extending between the gate pad and the gate fingers. In many applications, it may be desirable to increase the amount of gate resistance, for example, by adding one or more discrete or “lumped” gate resistors within the gate structure. Increasing the gate resistance may be used, for example, to limit the switching speed of the device or to reduce electrical ringing and / or noise that could cause oscillations that could result in device failure. Summary of the Invention [Means for solving the problem]

[0008] According to an embodiment of the present invention, there is provided a semiconductor device including a gate pad, a plurality of gate fingers, and a first gate resistor and a first switch coupled between the gate pad and the gate fingers.

[0009] In some embodiments, the first switch may be a diode. In some embodiments, the diode may be implemented within the first gate resistor.

[0010] In some embodiments, the semiconductor device further includes a second gate resistor and a second switch, such as a diode, coupled between the gate pad and the gate finger, the first diode allowing current to flow from the gate pad to the gate finger when forward biased, and the second diode allowing current to flow from the gate finger to the gate pad when forward biased.

[0011] The semiconductor device may have a first total gate resistance value for gate current flowing from the gate pad to the gate fingers, and may have a second total gate resistance value for gate current flowing from the gate fingers to the gate pad, the second total gate resistance value being different from the first total gate resistance value.

[0012] The first gate resistor may include a first section and a second section forming a first diode, the first section including an n-type semiconductor material and the second section including a p-type semiconductor material. In some embodiments, the first gate resistor further includes a third section including a p-type semiconductor material, the first section being between the second and third sections. In some embodiments, the second gate resistor includes a fourth section, a fifth section, and a sixth section, the fourth section including an n-type semiconductor material, the fifth and sixth sections including a p-type semiconductor material, the fourth section being between the fifth and sixth sections, and the fourth and sixth sections forming a second diode. In some embodiments, the second section is closer to the gate pad than the third section, and the fifth section is closer to the gate pad than the sixth section. In some embodiments, the semiconductor device further includes a first metal connector that shorts the first section to the third section and a second metal connector that shorts the fourth section to the fifth section.

[0013] In some embodiments, the first gate resistor includes a first section of n-type semiconductor material and a second section of p-type semiconductor material, where the first section may be in direct contact with the second section. The first gate resistor may also include a third section of p-type semiconductor material, where the first section is between the second and third sections. The n-type semiconductor material may be n-type polysilicon, and the p-type semiconductor material may be p-type polysilicon. The semiconductor device also includes a metal connector that shorts the first section to the third section. The metal connector may include metallization in a via extending through a dielectric layer formed on the top surface of the first gate resistor.

[0014] According to a further embodiment of the present invention, there is provided a semiconductor device including a gate pad, a plurality of gate fingers, and a gate resistor electrically interposed between the gate pad and the gate fingers, wherein the gate resistor includes a first section of n-type semiconductor material and a second section of p-type semiconductor material.

[0015] In some embodiments, the first section may directly contact the second section.

[0016] In some embodiments, the n-type semiconductor material comprises n-type polysilicon and the p-type semiconductor material comprises p-type polysilicon.

[0017] In some embodiments, the gate resistor further includes a third section of p-type semiconductor material, and the first section is between the second section and the third section.

[0018] In some embodiments, the semiconductor device further includes a metal connector that shorts the first section to the second section. The metal connector may include metallization in a via that extends through a dielectric layer formed on top of the gate resistor.

[0019] In some embodiments, the n-type and p-type semiconductor materials form a diode within the gate resistor.

[0020] In some embodiments, the gate resistor is a first gate resistor, and a junction between the first section and the second section forms a first diode, and the semiconductor device further includes a second gate resistor and a second diode electrically coupled in parallel with the first gate resistor and the first diode.

[0021] In some embodiments, the first diode is configured to allow current to flow from the gate pad to the gate finger when forward biased, and the second diode is configured to allow current to flow from the gate finger to the gate pad when forward biased.

[0022] According to a further embodiment of the present invention, there is provided a semiconductor device including a gate pad, a plurality of gate fingers, a first gate resistor and a first circuit element electrically interposed between the gate pad and the gate fingers, the first circuit element being configured to conduct current between the gate pad and the gate fingers in only a first direction.

[0023] In some embodiments, the first circuit element includes a first diode. In some embodiments, the first diode is implemented within the first gate resistor.

[0024] In some embodiments, the semiconductor device further includes a second gate resistor and a second diode electrically interposed between the gate pad and the gate finger, the second diode configured to conduct current between the gate pad and the gate finger only in a second direction opposite the first direction, hi some embodiments, the second diode is implemented within the second gate resistor.

[0025] In some embodiments, the first gate resistor includes a first section of n-type semiconductor material and a second section of p-type semiconductor material.

[0026] In some embodiments, the semiconductor device further includes a first metal connector that shorts the first section of the first gate resistor to the second section of the first gate resistor, hi some embodiments, the metal connector includes metallization in a via extending through a dielectric layer formed on a top surface of the first gate resistor.

[0027] In some embodiments, the first section of the first gate resistor directly contacts the second section of the first gate resistor, the n-type semiconductor material comprises n-type polysilicon, and the p-type semiconductor material comprises p-type polysilicon.

[0028] In some embodiments, the semiconductor device further includes a wide bandgap semiconductor layer structure, and the first gate resistor is on an upper surface of the wide bandgap semiconductor layer structure.

[0029] In some embodiments, the semiconductor device further includes an inner dielectric pattern directly on an upper surface of the first gate resistor.

[0030] According to a further embodiment of the present invention, there is provided a semiconductor device including a gate pad, a gate bus, and a gate resistor structure electrically interposed between the gate pad and the gate bus, the gate resistor structure having a first resistance with respect to a current flowing from the gate pad to the gate bus and a second resistance with respect to a current flowing from the gate bus to the gate pad, the first resistance being different from the second resistance.

[0031] In some embodiments, the semiconductor device further includes a wide bandgap semiconductor layer structure including an active area having a plurality of unit cell transistors, and the gate resistor structure is on an upper surface of the wide bandgap semiconductor layer structure.

[0032] In some embodiments, the semiconductor device further includes an inner dielectric pattern directly on an upper surface of the gate resistor.

[0033] In some embodiments, the gate resistor structure includes a plurality of first gate resistors, a plurality of first switches, a plurality of second gate resistors, and a plurality of second switches.

[0034] In some embodiments, each first gate resistor and each first switch of the first switches is coupled between the gate pad and a gate finger, and each second gate resistor and each second switch of the second switches is coupled between the gate pad and a gate finger.

[0035] In some embodiments, each first switch includes a first diode and each second switch includes a second diode.

[0036] In some embodiments, each first diode is implemented within a respective one of the first gate resistors, and each second diode is implemented within a respective one of the second gate resistors.

[0037] In some embodiments, the first diode is configured to allow current to flow from the gate pad to the gate bus when forward biased, and the second diode is configured to allow current to flow from the gate bus to the gate pad when forward biased.

[0038] In some embodiments, the number of first gate resistors is different from the number of second gate resistors.

[0039] In some embodiments, each first gate resistor is immediately adjacent to at least one second resistor.

[0040] In some embodiments, each first gate resistor and each second gate resistor includes a first section of n-type semiconductor material, a second section of p-type semiconductor material, and a third section of p-type semiconductor material that form an npn junction.

[0041] In some embodiments, the semiconductor device further includes a plurality of first metal connectors that respectively short-circuit a first section of each of the first gate resistors to a third section of each of the first gate resistors, and a plurality of second metal connectors that respectively short-circuit a first section of each of the second gate resistors to a second section of each of the second gate resistors.

[0042] According to a further embodiment of the present invention, there is provided a semiconductor device including a gate pad, a plurality of gate fingers, and a gate resistor structure electrically interposed between the gate pad and the gate fingers, the gate resistor structure having a first resistance when the device is turned on and a second resistance when the device is turned off, the first resistance being different from the second resistance.

[0043] In some embodiments, the semiconductor device further comprises a wide bandgap semiconductor layer structure including an active area, and the gate resistor structure is on an upper surface of the wide bandgap semiconductor layer structure.

[0044] In some embodiments, the semiconductor device further includes an internal metal-dielectric pattern directly on the upper surface of the gate resistor structure.

[0045] In some embodiments, the gate resistor structure includes a first gate resistor and a first switch forming a first circuit coupled between the gate pad and the gate finger, and a second gate resistor and a second switch forming a second circuit coupled between the gate pad and the gate finger.

[0046] In some embodiments, the first switch includes a first diode that, when forward biased, allows current to flow from the gate pad to the gate finger, and the second switch includes a second diode that, when forward biased, allows current to flow from the gate finger to the gate pad.

[0047] In some embodiments, the gate resistor structure includes a plurality of first gate resistor circuits, each including a first gate resistor and a first switch coupled between the gate pad and the gate finger, and a plurality of second gate resistor circuits, each including a second gate resistor and a second switch coupled between the gate pad and the gate finger, wherein all of the first gate resistor circuits and all of the second gate resistor circuits are arranged electrically in parallel with each other.

[0048] In some embodiments, the combined resistance of all of the first gate resistors is different from the combined resistance of all of the second gate resistors.

[0049] In some embodiments, the number of first gate resistors is different from the number of second gate resistors.

[0050] In some embodiments, each first gate resistor is immediately adjacent to at least one second gate resistor.

[0051] According to a further embodiment of the present invention, there is provided a semiconductor device including a gate pad, a plurality of gate fingers, a plurality of first gate resistors electrically interposed between the gate pad and the gate fingers, and a plurality of second gate resistors electrically interposed between the gate pad and the gate fingers, wherein a gate current flowing between the gate pad and the gate fingers flows at least primarily through the first gate resistor when the device is turned on, and the gate current flows at least primarily through the second gate resistor when the device is turned off.

[0052] In some embodiments, the semiconductor device further includes a plurality of first diodes configured to control current flow through the first gate resistor, the plurality of first diodes being configured to exclusively conduct current from the gate pad to the gate fingers. The semiconductor device may also include a plurality of second diodes configured to control current flow through the second gate resistor, the plurality of second diodes being configured to exclusively conduct current from the gate fingers to the gate pad.

[0053] In some embodiments, the total resistance of the second gate resistor differs from the total resistance of the first gate resistor by at least 10%.

[0054] In some embodiments, each first diode is part of a respective one of the first gate resistors.

[0055] In some embodiments, the number of first gate resistors is different from the number of second gate resistors.

[0056] In some embodiments, a first resistance of a first one of the first gate resistors is different from a second resistance of a first one of the second gate resistors.

[0057] In some embodiments, each first gate resistor is immediately adjacent to at least one second gate resistor.

[0058] According to a further embodiment of the present invention, there is provided a semiconductor device including a gate pad, a gate bus, a first gate resistor having a first end directly connected to the metal gate pad and a second end directly connected to the gate bus, and a metal connector electrically connecting a first internal portion of the first gate resistor to a second internal portion of the gate resistor.

[0059] In some embodiments, the semiconductor device further includes a first diode embedded within the first gate resistor.

[0060] In some embodiments, the semiconductor device further includes a second gate resistor and a second diode coupled between the metal gate pad and the gate bus.

[0061] In some embodiments, the first diode is configured to allow current to flow from the metal gate pad to the gate bus when forward biased, and the second diode is configured to allow current to flow from the gate bus to the metal gate pad when forward biased.

[0062] In some embodiments, the semiconductor device has a first resistance between the metal gate pad and the gate bus for signals traveling from the metal gate pad to the gate bus, and a second resistance between the metal gate pad and the gate bus for signals traveling from the gate bus to the metal gate pad, the second resistance being different from the first resistance.

[0063] In some embodiments, the first gate resistor and the second gate resistor each include a first section of n-type semiconductor material and a second section of p-type semiconductor material.

[0064] In some embodiments, the metal connector comprises metallization in a via extending through a dielectric layer formed on top of the first gate resistor.

[0065] According to a further embodiment of the present invention, there is provided a semiconductor device including a gate pad, a plurality of gate fingers, a first conductive path between the gate pad and the gate fingers that conducts current when the device is turned on but does not conduct current when the device is turned off, and a second conductive path between the gate pad and the gate fingers that conducts current when the device is turned off but does not conduct current when the device is turned on.

[0066] In some embodiments, the first conduction path includes a plurality of first gate resistor circuits arranged electrically in parallel with one another, and the second conduction path includes a plurality of second gate resistor circuits arranged electrically in parallel with one another.

[0067] In some embodiments, each first gate resistor circuit includes a first gate resistor and a first diode, and each second gate resistor circuit includes a second gate resistor and a second diode.

[0068] In some embodiments, the number of first gate resistors is different from the number of second gate resistors.

[0069] In some embodiments, a first resistance of at least one of the first gate resistors is different from a second resistance of at least one of the second gate resistors.

[0070] In some embodiments, each first gate resistor is immediately adjacent to at least one second gate resistor.

[0071] According to a further embodiment of the present invention, there is provided a semiconductor device including a wide bandgap semiconductor layer structure, a gate pad on the wide bandgap semiconductor layer structure, a plurality of gate fingers on the wide bandgap semiconductor layer structure, and a plurality of lumped gate resistors electrically coupled between the gate pad and the gate fingers.

[0072] In some embodiments, the semiconductor device may further include a gate bus, and each lumped gate resistor may be connected between the gate pad and the gate bus.

[0073] In some embodiments, at least two of the lumped gate resistors extend outward from side edges of the gate pad to contact portions of the gate bus that extend along a first outer edge of the semiconductor device.

[0074] In some embodiments, a first subset of the lumped gate resistors extends outward from a first side of the gate pad, and a second subset of the plurality of lumped gate resistors extends outward from a second side of the gate pad, in some embodiments, a third subset of the plurality of lumped gate resistors extends outward from a third side of the gate pad opposite the first side, and in some embodiments, a fourth subset of the plurality of lumped gate resistors extends outward from a fourth side of the gate pad opposite the second side.

[0075] In some embodiments, at least each lumped gate resistor of the plurality of lumped gate resistors extends outwardly from each and every side of the gate pad when the semiconductor device is viewed in plan view, hi some embodiments, the lumped gate resistor extends outwardly from the gate pad and substantially surrounds the gate pad when the semiconductor device is viewed in plan view.

[0076] In some embodiments, the plurality of lumped gate resistors may include a first lumped gate resistor, a second lumped gate resistor, and a third lumped gate resistor, each extending from the gate pad, the second lumped gate resistor being directly adjacent to the first and third lumped gate resistors and being between the first and third lumped gate resistors, the width of the second lumped gate resistor being smaller than a first distance between the first and second lumped gate resistors, and the width of the second lumped gate resistor being also smaller than a second distance between the second and third lumped gate resistors.

[0077] In some embodiments, the first distance may be greater than twice the width of the second lumped gate resistor, and the second distance may be greater than twice the width of the second lumped gate resistor, while in other embodiments, the first distance may be greater than three times the width of the second lumped gate resistor, and the second distance may be greater than three times the width of the second lumped gate resistor.

[0078] In some embodiments, the length of the second lumped gate resistor may be at least twice the width of the second lumped gate resistor. In some embodiments, the length of the second lumped gate resistor is less than five times the width of the second lumped gate resistor. In some embodiments, the length of the second lumped gate resistor is less than the width of the second lumped gate resistor. In some embodiments, each lumped gate resistor in the plurality of lumped gate resistors has a respective length that is less than three times the width of the respective lumped gate resistor.

[0079] In some embodiments, the lumped gate resistors may be spaced apart from one another such that heat generated in adjacent pairs of lumped gate resistors during normal operation of the semiconductor device is substantially dissipated from the semiconductor device through various portions of the semiconductor layer structure.

[0080] In some embodiments, the semiconductor layer structure has a thickness D and a heat spreading angle α, and the facing sides of adjacent lumped gate resistors are at least 2 * D * They are spaced apart by tan(α).

[0081] In some embodiments, the semiconductor device further includes a first switch coupled in series with a first lumped gate resistor of the lumped gate resistors between the gate pad and the gate finger, and a second switch coupled in series with a second lumped gate resistor of the lumped gate resistors between the gate pad and the gate finger. In some embodiments, the first switch can be a diode implemented within the first gate resistor. In some embodiments, the first switch includes a first diode that, when forward biased, allows current to flow from the gate pad to the gate finger, and the second switch includes a second diode that, when forward biased, allows current to flow from the gate finger to the gate pad. In some embodiments, the semiconductor device has a first total gate resistance for gate current flowing from the gate pad to the gate finger and a second total gate resistance for gate current flowing from the gate finger to the gate pad, the second total gate resistance being different from the first total gate resistance.

[0082] In some embodiments, the gate pad has an inverted L-shape or an L-shape when viewed in plan.

[0083] According to yet a further embodiment of the present invention, there is provided a semiconductor device including a wide bandgap semiconductor layer structure, a gate pad on the wide bandgap semiconductor layer structure, a gate bus on the wide bandgap semiconductor layer structure, and a lumped gate resistor extending between the gate pad and a portion of the gate bus that extends adjacent to a first outer edge of the semiconductor device.

[0084] According to yet a further embodiment of the present invention, there is provided a semiconductor device including a wide bandgap semiconductor layer structure, a gate pad on the wide bandgap semiconductor layer structure, and a plurality of lumped gate resistors each electrically coupled to the gate pad, wherein at least each pair of lumped gate resistors in the plurality of lumped gate resistors extends outward from each of at least three sides of the gate pad when the semiconductor device is viewed in a plan view. [Brief explanation of the drawings]

[0085] [Figure 1] 1 is a graph of drain current as a function of drain voltage for a conventional silicon carbide power MOSFET. [Figure 2A] FIG. 1 is a circuit diagram of a conventional power MOSFET. [Figure 2B] FIG. 2 is a circuit diagram of a power MOSFET in accordance with a specific embodiment of the present invention. [Figure 3A] 1 is a schematic plan view of a power MOSFET according to a specific embodiment of the present invention; [Figure 3B] FIG. 3B is a schematic plan view of the power MOSFET of FIG. 3A with the top layer removed. [Figure 3C] 3C is a schematic longitudinal cross-section taken along line 3C-3C of FIG. 3A. [Figure 4A] 3C, the cross section of the gate pad region of the power MOSFET of FIGS. 3A-3C, the cross section being taken through an upper portion of the gate pad. [Figure 4B] 4B is a schematic longitudinal cross-sectional view of the power MOSFET of FIGS. 3A-3C taken along line 4B-4B of FIG. 4A. [Figure 4C] FIG. 4 is a schematic cross-sectional view of the gate pad region of the power MOSFET of FIGS. 3A-3C, the cross-section being taken through an underside of the gate pad. [Figure 4D] 4D is a schematic longitudinal cross-sectional view of the power MOSFET of FIGS. 3A-3C taken along line 4D-4D of FIG. 4C. [Figure 4E]3D is a schematic cross-section of the gate pad region of the power MOSFET of FIGS. 3A-3C, the cross-section being taken through a semiconductor layer including a gate resistor. [Figure 4F] 4F is a schematic longitudinal cross-sectional view of the power MOSFET of FIGS. 3A-3C taken along line 4F-4F of FIG. 4E. [Figure 4G] 4G is a schematic longitudinal cross-section taken along line 4G-4G of FIG. 4E. [Figure 4H] 4H is a schematic longitudinal cross-section taken along line 4H-4H of FIG. 4E. [Figure 5A] FIG. 4B is a circuit diagram showing the electrical connections between the gate pads and gate buses of the power MOSFETs of FIGS. 3A-4H. [Figure 5B] FIG. 5B is a schematic diagram illustrating one embodiment of the first gate resistor circuit and the second gate resistor circuit of FIG. 5A. [Figure 5C] FIG. 1 is a schematic perspective view showing a via formed through a dielectric layer that includes a metal connector that shorts a pn junction in an underlying semiconductor layer. [Figure 6] 10A-10C are two schematic plan views of gate resistor circuits included in a power MOSFET according to further embodiments of the present invention. [Figure 7] FIG. 10 is a circuit diagram of a power MOSFET according to a still further embodiment of the present invention. [Figure 8] 1 is a schematic cross-sectional view of a gate trench MOSFET that can include a lumped gate resistor structure according to an embodiment of the present invention. [Figure 9] FIG. 1 is a schematic diagram showing how heat generated in a single large lumped gate resistor is dissipated through a semiconductor layer structure. [Figure 10A] FIG. 1 is a schematic diagram illustrating how heat generated in multiple smaller lumped gate resistors is dissipated through a semiconductor layer structure. [Figure 10B] FIG. 10 is a schematic diagram illustrating how heat generated in multiple smaller lumped gate resistors can be dissipated through substantially different regions of the bottom surface of a semiconductor layer structure. [Figure 11A]FIG. 1 is a schematic plan view of a conventional power semiconductor device. [Figure 11B] FIG. 11B is an enlarged view of the gate pad region of the conventional power semiconductor device of FIG. 11A. [Figure 12A] 3 is a schematic plan view of a power semiconductor device according to a further embodiment of the present invention; [Figure 12B] FIG. 12B is an enlarged view of the gate pad region of the power semiconductor device of FIG. 12A. [Figure 13A] FIG. 1 is a schematic plan view of another conventional power semiconductor device. [Figure 13B] FIG. 13B is an enlarged view of the gate pad region of the conventional power semiconductor device of FIG. 13A. [Figure 13C] FIG. 13B is an enlarged view of a portion of a single large lumped gate resistor included in the conventional power semiconductor device of FIG. 13A. [Figure 14A] 10 is a schematic plan view of a power semiconductor device according to a still further embodiment of the present invention; [Figure 14B] FIG. 14B is an enlarged view of the gate pad region of the power semiconductor device of FIG. 14A. [Figure 14C] FIG. 14B is an enlarged view of a plurality of smaller lumped gate resistors included in the power semiconductor device of FIG. 14A. [Figure 15A] FIG. 10 is a schematic diagram illustrating how the aspect ratio of the lumped gate resistors can be varied to change the spacing between adjacent lumped gate resistors. [Figure 15B] FIG. 10 is a schematic diagram illustrating how the aspect ratio of the lumped gate resistors can be varied to change the spacing between adjacent lumped gate resistors. DETAILED DESCRIPTION OF THE INVENTION

[0086] High-speed, high-power semiconductor switching devices such as silicon carbide-based MOSFETs, IGBTs, and gate-controlled thyristors exhibit high dV during both device turn-on and device turn-off. ds / dt (i.e., source-drain voltage per unit time, V ds(large change in dI) and high dI ds / dt (i.e., source-drain current per unit time I ds When the device turns on, the transconductance (g m ) is the V ds vs. I ds On the other hand, when the device turns off, the discharge of the capacitance in the device ds vs. I ds This is shown in Figure 1, which shows the V of a conventional high switching speed, high power silicon carbide MOSFET. ds vs. I ds In FIG. 1, curves 1-1 to 1-N are graphs of the response of various gate voltages (V gs ) levels, while curves 2-1 through 2-N represent the device response during device turn-on at the same set of gate voltage levels.

[0087] Many applications require relatively balanced switching behavior (i.e., power switching devices need to turn on and off at approximately the same rate). Asymmetries in device turn-on and turn-off response (see Figure 1) result in unbalanced switching behavior. To attempt to compensate for this unbalanced behavior, customers may employ asymmetric gate control schemes that drive the switching devices differently during device turn-on and turn-off to reduce the difference in turn-on and turn-off behavior. For example, circuitry external to the power semiconductor device may be provided that uses off-chip resistors and diodes to couple different amounts of resistance to the gate bond pad during device turn-on and device turn-off.

[0088] As mentioned above, many power semiconductor devices, such as MOSFETs, IGBTs, and gate-controlled thyristors, include one or more lumped gate resistors designed to increase the gate resistance to a desired value. A "lumped" gate resistor refers to a discrete resistor added to a gate structure to increase its resistance. The total resistance of a gate structure is the combination of the lumped gate resistance provided by one or more lumped gate resistors and the distributed gate resistance of the gate pad, gate bus, and gate fingers, which receive the gate signal from an external source and distribute the gate signal to the device's individual unit cell transistors. These lumped gate resistors may, for example, improve the device's electromagnetic interference ("EMI") performance. Furthermore, as the length of the gate fingers of a power switching device increases, long feedback loops are formed, which can result in high levels of instability within the device. Gate resistors make these feedback loops more lossy, thereby improving stability. Therefore, by including additional lumped gate resistors in series with the distributed gate resistors, it may be possible to increase device yield and / or reduce the device's field failure rate.

[0089] As mentioned above, lumped gate resistors may be implemented "off-die," meaning that the lumped gate resistor and the power semiconductor device are separately mounted on a mounting substrate (e.g., a motherboard). In such implementations, the lumped gate resistor may be implemented using a surface-mount resistor. However, this approach takes up valuable space on the mounting substrate, increases cost, and reduces device reliability (because off-die lumped gate resistors are not as effective as on-die lumped gate resistors). Therefore, lumped gate resistors are often implemented "on-die," as part of the power semiconductor die.

[0090] Traditionally, on-die lumped gate resistors are implemented by routing the current path for the gate signal through a high-resistivity material, such as a semiconductor layer (because the semiconductor material has a higher sheet resistance than the metal used to form the gate pad and possibly other parts of the gate structure, such as the gate bus). These gate resistors are typically incorporated into power switching devices between the gate pad and the gate bus / gate fingers. For example, the electrical path connecting the gate pad to the gate fingers may be routed through a portion of the semiconductor layer (typically through a narrow portion to increase its resistance), with this portion of the electrical path acting as a lumped gate resistor that increases the overall gate resistance. The semiconductor layer may include, for example, a polysilicon layer.

[0091] FIG. 2A is a circuit diagram of a conventional power MOSFET 10 including a gate resistor. As shown in FIG. 2A, the conventional power MOSFET 10 includes, among other things, a gate terminal 12 (e.g., a gate bond pad), a source terminal 14 (e.g., a source bond pad), and a drain terminal 16 (e.g., a drain bond pad). The gate terminal 12 is part of a gate structure 20, which further includes a gate pad 22 and a plurality of gate fingers 26 that form the gates of respective unit cell transistors. The gate pad 22 is electrically connected to the gate fingers 26 by a gate bus 24 (also part of the gate structure 20). A gate resistor circuit 30, which includes a gate resistor 32, is electrically disposed in series between the gate pad 22 and the gate bus 24. As mentioned above, the gate resistor 32 is typically implemented by forcing the gate current to flow through a section of semiconductor material that may have a higher resistance than at least some portions of the gate current path through the MOSFET 10. Conventionally, gate resistor 32 is a single relatively large lumped gate resistor used to connect gate pad 22 to gate bus 24 .

[0092] In a conventional power MOSFET, the semiconductor material used to implement resistor 32 may include, for example, polysilicon doped with a first conductivity type dopant. Most commonly, the first conductivity type dopant is a p-type dopant, although an n-type dopant may alternatively be used. Thus, gate resistor 32 in a conventional power MOSFET 10 conducts gate current flowing in a first direction from gate pad 22 to gate fingers 26 (i.e., gate current flowing during device turn-on and on-state operation) and gate current flowing in a second direction from gate fingers 26 to gate pad 22 (i.e., gate current flowing during device turn-off as a capacitance in the device discharges). Thus, the total resistance of lumped gate resistor 32 has a constant value (i.e., the lumped gate resistance value is the same during device turn-on and device turn-off).

[0093] Some embodiments of the present invention provide a power semiconductor device having asymmetric gate resistance. In particular, a power semiconductor device according to embodiments of the present invention may have a first gate resistance for gate current flowing into the semiconductor device and a second gate resistance for gate current flowing out of the semiconductor device, the first gate resistance being different from the second gate resistance by at least 5%, at least 10%, at least 20%, at least 30%, or at least 50%. The first gate resistance may be implemented using one or more first gate resistors inserted in series within the gate structure during device turn-on, and the second gate resistance may be implemented using one or more second gate resistors inserted in series within the gate structure during device turn-off. The values ​​of the first and second gate resistors may be selected to improve device performance parameters, such as a balance between turn-on and turn-off switching behavior.

[0094] FIG. 2B is a circuit diagram of a power MOSFET 50 according to an embodiment of the present invention, including such an asymmetric gate resistor. As shown in FIG. 2B, the power MOSFET 50 includes, among other things, a gate terminal 52 (e.g., a gate bond pad), a source terminal 54 (e.g., a source bond pad), and a drain terminal 56 (e.g., a drain bond pad). The gate terminal 52 is part of a gate structure 60, which further includes a gate pad 62, a gate bus 64, and a plurality of gate fingers 66 that form the gates of respective unit cell transistors. The gate pad 62 is electrically connected to the gate fingers 66 by the gate bus 64. A first gate resistor circuit 70 is electrically disposed in series between the gate pad 62 and the gate bus 64. The first gate resistor circuit 70 includes a first gate resistor 72 and a first switch 74. A second gate resistor circuit 80 is electrically disposed in series between the gate pad 62 and the gate bus 64. The second gate resistor circuit 80 includes a second gate resistor 82 and a second switch 84. The first gate resistor circuit 70 and the second gate resistor circuit 80 are electrically arranged in parallel with each other. The first gate circuit 70 and the second gate circuit 80 are also part of the gate structure 60.

[0095] The power MOSFET 50 is configured so that gate current flowing in a first direction (e.g., from the gate pad 62 to the gate bus 64) flows through the first gate resistor 72 but not through the second gate resistor 82, and so that gate current flowing in a second direction opposite the first direction (e.g., from the gate bus 64 to the gate pad 62) flows through the second gate resistor 82 but not through the first gate resistor 72. As a result, current can flow only through the first gate resistor 72 during device turn-on and only through the second gate resistor 82 during device turn-off. Thus, the first gate resistor 72 can be designed to have a resistance value selected to optimize performance during device turn-on and on-state operation, while the second gate resistor 82 can be designed to have a resistance value selected to optimize performance during device turn-off.

[0096] In some embodiments, the first switch 74 and the second switch 84 may be implemented as diodes electrically in series with the respective first gate resistor 72 and second gate resistor 82 and / or may be implemented within the respective first gate resistor 72 and second gate resistor 82. In some embodiments, the first gate resistor 72 and the second gate resistor 82 may be implemented as semiconductor patterns, and thus the diodes 74, 84 may be implemented as p-n junctions within the semiconductor patterns forming the first gate resistor 72 and second gate resistor 82. In one illustrative embodiment, the first gate resistor 72 and the second gate resistor 82 may each be implemented as a semiconductor pattern having a first n-type region between a second p-type region and a third p-type region such that each semiconductor pattern has a pair of p-n junctions. A metal connector may be used to short one of the p-n junctions of each semiconductor pattern. The other (unshorted) p-n junction forms a diode. The semiconductor pattern used to form the first gate resistor 72 may have a short across a p-n junction formed between a first n-type region and a second p-type region (the second p-type region being a p-type region adjacent to the gate pad 62). Thus, the non-shorting p-n junction in the semiconductor pattern used to form the first gate resistor 72 forms a diode 74 that passes current from the gate pad 62 to the gate bus 64 when forward biased. The semiconductor pattern used to form the second gate resistor 82 may have a short across a p-n junction formed between a first n-type region and a third p-type region (the third p-type region being a p-type region spaced apart from the gate pad 62). Thus, the non-shorting p-n junction in the semiconductor pattern used to form the second gate resistor 82 forms a diode 84 that passes current from the gate bus 64 to the gate pad 62 when forward biased.

[0097] In some embodiments, there may be provided a plurality of first gate resistor circuits 70 and a plurality of second gate resistor circuits 80. This may further improve the balance of the switching operation.

[0098] According to some embodiments, a semiconductor device is provided that includes a gate pad, a plurality of gate fingers, and a first gate resistor and a first switch coupled between the gate pad and the gate fingers. The first switch can be a diode. The devices may further include a second gate resistor and a second diode coupled between the gate pad and the gate fingers. The first diode is configured to allow current to flow from the gate pad to the gate fingers when forward biased, and the second diode is configured to allow current to flow from the gate fingers to the gate pad when forward biased. The semiconductor device may have a first total gate resistance for gate current flowing from the gate pad to the gate fingers and a second total gate resistance for gate current flowing from the gate fingers to the gate pad, the second total gate resistance being different from the first total gate resistance.

[0099] According to a further embodiment of the present invention, there is provided a semiconductor device including a gate pad, a plurality of gate fingers, and a gate resistor electrically interposed between the gate pad and the gate fingers. The gate resistor includes a first section including an n-type semiconductor material (e.g., n-type polysilicon), a second section including a p-type semiconductor material (e.g., p-type polysilicon), and optionally a third section of p-type semiconductor material. A metal connector may be provided to short the first section to the second section.

[0100] According to a further embodiment of the present invention, there is provided a semiconductor device including a gate pad, a plurality of gate fingers, and a first gate resistor and a first circuit element (e.g., a diode) electrically interposed between the gate pad and the gate fingers. The first circuit element is configured to conduct current between the gate pad and the gate fingers in only a first direction. The semiconductor device may further include a second gate resistor and a second circuit element electrically interposed between the gate pad and the gate fingers, the second circuit element being configured to conduct current between the gate pad and the gate fingers in only a second direction opposite the first direction.

[0101] According to yet further embodiments of the present invention, there is provided a semiconductor device including a gate pad, a gate bus, and a gate resistor structure electrically interposed between the gate pad and the gate bus. The gate resistor structure has a first resistance to current flowing from the gate pad to the gate bus and a second resistance to current flowing from the gate bus to the gate pad. The first resistance is different from the second resistance. In some embodiments, the gate resistor structure may include a plurality of first gate resistors, a plurality of first switches, a plurality of second gate resistors, and a plurality of second switches.

[0102] As described above, conventionally, a single large lumped gate resistor is used to connect the gate pad of a power semiconductor device to the gate bus of the power semiconductor device. According to embodiments of the present invention, this single large lumped gate resistor can be broken down into multiple smaller lumped gate resistors that are spaced apart from one another. As described above, this allows at least some of the gate resistors to be designed to allow current flow in only one direction, thereby allowing the total amount of gate resistance to be set to an optimal value for both device turn-on and device turn-off. Another advantage of this approach (regardless of whether some or all of the lumped gate resistors are designed to conduct current in only one direction) is that it can be used to improve the heat dissipation characteristics of a power semiconductor device. Improving heat dissipation can result in increased device robustness, meaning that the device can operate at higher currents / voltages and / or for longer periods of time without device failure.

[0103] When current flows through a gate resistor, energy is dissipated in the resistor and converted to heat. Therefore, whenever a gated power semiconductor device is turned on or off, heat is generated in the gate resistor, and the amount of heat generated depends, among other things, on the switching speed of the device. If a single, large lumped gate resistor is used, the generated heat is concentrated in a small area and can therefore significantly increase the temperature of the portion of the semiconductor layer structure below the gate resistor. Using multiple, smaller, spaced-apart lumped gate resistors instead of the single, large lumped gate resistor used in conventional power semiconductor devices can reduce the amount of temperature increase that occurs in any given portion of the semiconductor layer structure by spreading the generated heat throughout the majority of the semiconductor layer structure. Test results suggest that this approach can increase the robustness of power semiconductor devices by more than four times. Smaller lumped gate resistors can be spread separately such that the heat dissipated by any pair of adjacent lumped gate resistors is substantially spread through various portions of the semiconductor layer structure to enhance and / or optimize heat dissipation.

[0104] Thus, according to a further embodiment of the present invention, there is provided a semiconductor device including a wide bandgap semiconductor layer structure, a gate pad on the wide bandgap semiconductor layer structure, a plurality of gate fingers on the wide bandgap semiconductor layer structure, and a plurality of lumped gate resistors electrically coupled between the gate pad and the gate fingers.

[0105] In another embodiment, a semiconductor device is provided that includes a wide bandgap semiconductor layer structure, a gate pad on the wide bandgap semiconductor layer structure, a gate bus on the wide bandgap semiconductor layer structure, and a lumped gate resistor extending between the gate pad and a portion of the gate bus that extends adjacent to a first outer edge of the semiconductor device.

[0106] In yet another embodiment, a semiconductor device is provided that includes a wide bandgap semiconductor layer structure, a gate pad on the wide bandgap semiconductor layer structure, and a plurality of lumped gate resistors, each electrically coupled to the gate pad, wherein at least each pair of the lumped gate resistors extends outwardly from each of at least three sides of the gate pad when the semiconductor device is viewed in a plan view.

[0107] Power semiconductor devices according to embodiments of the present invention will now be described in more detail with reference to Figures 3A to 14C.

[0108] FIG. 3A is a schematic plan view of a power MOSFET 100 according to an embodiment of the present invention. FIG. 3B is a schematic plan view of the power MOSFET 100, omitting the passivation layer, the top source metallization structure, the gate bond pad, and the intermetal dielectric pattern. FIG. 3C is a schematic cross-sectional view taken along line 3C-3C in FIG. 3A, showing one entire unit cell and portions of two additional unit cells within the active area of ​​the power MOSFET 100. It will be understood that thicknesses of various layers, patterns, and elements in FIGS. 3A-3C and other figures herein are not drawn to scale, and the figures are schematic in nature.

[0109] Power MOSFET 100 includes a wide-bandgap semiconductor layer structure 120 (FIG. 3C) and multiple semiconductor, dielectric, and / or metal layers formed on either side of semiconductor layer structure 120. Referring back to FIG. 3A, gate bond pad 110 and one or more source bond pads 112-1, 112-2 are formed on the upper side of semiconductor layer structure 120 (FIG. 3C), and drain pad 114 (FIG. 3C) is provided on the lower side of MOSFET 100. Each of gate pad 110 and source pad 112 may be formed from a metal, such as aluminum, to which bond wires can be readily attached by conventional techniques, such as thermocompression or soldering. Drain pad 114 may be formed from a metal that can be connected to an underlying submount, such as a lead frame, heat sink, power substrate, etc., by soldering, brazing, direct compression, etc.

[0110] The MOSFET 100 includes a source metallization structure 160 that electrically connects the source region 128 in the semiconductor layer structure 120 of the MOSFET 100 to an external device or voltage source that is electrically connected to the source bond pads 112-1, 112-2. The source metallization structure 160 is illustrated in FIG. 3A by a dashed box because a significant portion of the upper metallization structure 160 is covered by a protective layer 116, such as a polyimide layer. The source bond pads 112-1, 112-2 may, in some embodiments, be portions of the source metallization structure 160 exposed through openings in the protective layer 116. Bond wires 118 are shown in FIG. 3A that may be used to connect the gate bond pad 110 and the source bond pads 112-1, 112-2 to external circuitry, etc. The drain pad 114 may be connected to external circuitry via an underlying submount (not shown) on which the MOSFET 100 is mounted.

[0111] 3B-3C, a gate structure 130 is formed on the semiconductor layer structure 120. The gate structure 130 includes a plurality of gate insulating fingers 132 (FIG. 3C), a plurality of gate fingers 134 (FIGS. 3B-3C), a gate pad 136 (FIG. 3B), and a gate bus structure 138 (FIG. 3B) electrically connecting the gate fingers 134 to the gate pad 136. The gate bus 138 may be implemented as a multi-tiered structure in some embodiments. The electrical connection between the gate fingers 134 and the gate bus 138 is conventional and therefore not described herein. The gate insulating fingers 132 may comprise, for example, silicon oxide, and may insulate the gate fingers 134 from the underlying semiconductor layer structure 120. The gate fingers 134 may comprise, for example, a polysilicon pattern in some embodiments, although other conductive patterns may alternatively be used. The gate fingers 134 may extend laterally across the device (as shown in FIG. 3B ), or alternatively, may comprise a planar layer extending across the top surface of the semiconductor layer structure 120, with openings connecting upper source metallization structures 160 (discussed below) to source regions 128 in the semiconductor layer structure 120. Other structures may be used (e.g., the unit cells may have a hexagonal configuration, the gate fingers 134 may extend vertically rather than horizontally, both vertically and horizontally, etc.). In some embodiments, the gate fingers 134 may be formed in trenches in the top surface of the semiconductor layer structure 120, since forming the gate fingers 134 in such trenches can, for example, improve carrier mobility in the MOSFET 100 (see FIG. 8 ). The gate pad 136 may be directly and electrically connected below the gate bond pad 110. In some embodiments, the gate pad 136 and the gate bond pad 110 may comprise a single monolithic structure. Gate pad 136 and gate bus 138 may comprise metal structures in an illustrative embodiment.

[0112] Referring to FIG. 3C, the semiconductor layer structure is doped with, for example, n-type impurities (e.g., 1×10 18 atoms / cm3 ~1×10 21 atoms / cm 3 The semiconductor device includes an n-type silicon carbide semiconductor substrate 122, such as a heavily doped 4H (or n-type) single crystal silicon carbide semiconductor substrate. The substrate 122 can have any suitable thickness (e.g., 100-500 microns thick) in some embodiments and can be partially or completely removed. It will be understood that the thickness of the substrate 122 and the thicknesses of the other layers are not drawn to scale in the figures.

[0113] A drain pad 114 may be formed on the underside of the semiconductor substrate 122. The drain pad 114 may serve as an ohmic contact to the semiconductor substrate 122 and as a pad that provides an electrical connection between the drain terminal of the MOSFET 100 and an external device. The drain pad 114 may include, for example, a metal such as nickel, titanium, tungsten, and / or aluminum, and / or alloys and / or thin layer stacks of these and / or similar metals.

[0114] The semiconductor layer structure includes a lightly doped n-type (n - ) silicon carbide drift region 124. The n-type silicon carbide drift region 124 may be formed, for example, by epitaxial growth on the silicon carbide substrate 122. The n-type silicon carbide drift region 124 may be, for example, 1×10 14 ~5×10 16 dopant / cm 3 The n-type silicon carbide drift region 124 may have a doping concentration of 1×10 or more. The n-type silicon carbide drift region 124 may be a thick region having a vertical height above the substrate 122, for example, of 3 to 100 microns. It will be understood that the thickness of the drift region 124 is not drawn to scale in FIG. 3C. Although not shown in FIG. 3C, in some embodiments, the upper portion of the n-type silicon carbide drift region 124 may have a higher doping concentration (e.g., 1×10 or more) than the lower portion to provide a current spreading layer for the upper portion of the n-type silicon carbide drift region 124. 16 ~1×10 17 dopant / cm 3The doping concentration of the doped silicon is 0.015 to 0.015.

[0115] A p-type well region 126 is formed in the upper portion of the n-type drift region 124, for example, by ion implantation. Then, a heavily doped (n + ) An n-type silicon carbide source region 128 may be formed, for example, by ion implantation. A channel region 127 is defined laterally of the well region 126. The substrate 122, drift region 124, well region 126, and source region 128 together may comprise the semiconductor layer structure 120 of the MOSFET 100. The semiconductor layer structure 120 may be a wide bandgap semiconductor layer structure 120 (i.e., a semiconductor layer structure 120 formed from a wide bandgap semiconductor material).

[0116] After the n-type source regions 128 are formed, a plurality of gate insulating fingers 132 (collectively comprising a gate insulating pattern) may be formed on the top surface of the semiconductor layer structure 120. Each gate insulating finger 132 may comprise, for example, an elongated strip of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or the like. A gate finger 134, such as a doped polysilicon gate finger 134, is formed on each gate insulating finger 132. The gate fingers 134 and gate insulating fingers 132, along with the gate bond pad 110, gate pad 136, gate bus 138, and gate resistor (discussed below), may collectively comprise the gate structure 130. As mentioned above, the vertically extending portion of the well region 126 between the source regions 128 and the portion of the drift region 124 directly below each gate finger 134 comprises the channel region 127. Channel region 127 electrically connects n-type source region 128 to drift region 124 when a sufficient bias voltage is applied to gate fingers 134. When a bias voltage is applied to gate fingers 134, current can flow from n-type source region 128 through channel region 127 to drift region 124 and then to drain pad 114.

[0117] As shown in FIG. 3C , an intermetal dielectric pattern 150 is formed over the top and side surfaces of the gate insulation fingers 132 and gate fingers 134 to electrically isolate the gate fingers 134 from the source metallization structures 160. Although not shown in FIG. 3C , the intermetal dielectric pattern 150 can also electrically isolate the gate pad 136 and / or gate bus 138 from the source metallization structures 160. The intermetal dielectric pattern 150 can include multiple individual dielectric fingers overlying each gate finger 134 and additional dielectric structures in the gate pad region of the device. The intermetal dielectric pattern 150 can include, for example, one or more of a silicon oxide pattern, a silicon nitride pattern, aluminum oxide, magnesium oxide, or a mixture of these or other oxides and nitrides with silicon dioxide to form a silicate or oxynitride mixed dielectric.

[0118] A source metallization structure 160 may be formed on the intermetal dielectric pattern 150. The source metallization structure 160 may include one or more layers, such as, for example, a diffusion barrier layer (e.g., one or more titanium and / or tungsten-containing layers) and a bulk metal layer (e.g., an aluminum layer).

[0119] FIGS. 4A-4F are horizontal and vertical cross-sectional views of the gate pad region of power MOSFET 100 of FIGS. 3A-3C, illustrating the design of the gate resistor structure of power MOSFET 100. The cross-section of FIG. 4A corresponds to gate pad region "A" shown in FIG. 3A, with passivation layer 116 and gate bond pad 110 removed. FIG. 4B is a schematic vertical cross-section taken along line 4B-4B in FIG. 4A. Gate bond pad 110 and passivation layer 116, omitted in FIG. 4A, are shown in FIG. 4B for completeness. The dotted line between FIGS. 4A and 4B indicates the correspondence between the structures in the two figures. Line 4A-4A in FIG. 4B indicates the vertical "step" of MOSFET 100 from which the cross-section of FIG. 4A was taken.

[0120] As shown in FIGS. 4A-4B, a gate pad 136 is formed below the gate bond pad 110. An intermetal dielectric layer 150 electrically insulates the gate pad 136 from the source metallization 160. A field oxide layer 140 (e.g., a thick silicon oxide layer) is formed on the semiconductor layer structure 120 below the gate pad 136. A polysilicon layer 170 is formed on top of the field oxide layer 140. The polysilicon layer 170 may be a continuous layer below the gate pad 136. The polysilicon layer 170 may also extend into the active region of the device (as shown at the side edges in FIG. 4B) and may be patterned to form gate fingers 134 on top of each gate insulation finger 132. The gate pad 136 is formed on top of the polysilicon layer 170, and the gate bond pad 110 is formed on top of the gate pad 136. The gate pad 136 and the gate bond pad 110 may be monolithic structures or may comprise two or more separate layers. A gate bus 138 is formed on top of an inter-metal dielectric layer 150 and a polysilicon layer 170. Because the gate bus 138 does not extend as far above the semiconductor layer structure 120 as the gate pad 136, the inter-metal dielectric layer 150 covers the top surface of the gate bus 138. The inter-metal dielectric layer 150 electrically insulates the gate pad 136 and the gate bus 138 from the source metallization structure 160.

[0121] Polysilicon layer 170 may be a doped polysilicon layer and may be formed in any suitable manner. For example, in some embodiments, doped polysilicon layer 170 may be formed by deposition (e.g., in a low-pressure chemical vapor deposition reactor with dopant species introduced during growth). In other embodiments, doped polysilicon layer 170 may be deposited as an undoped polysilicon layer 170 and then doped by ion implantation. In yet other embodiments, polysilicon layer 170 may be deposited as an undoped polysilicon layer 170 and then doped by diffusion.

[0122] FIG. 4C is a schematic cross-sectional view of region "A" of power MOSFET 100, taken at a step in the device structure of gate bus 138. As shown in FIG. 4C, an inner portion 152 of inter-metal dielectric pattern 150 separates gate pad 136 from gate bus 138. Gate bus 138 may surround gate pad 136 and may extend throughout MOSFET 100 to carry gate signals applied to gate bond pad 110 to gate fingers 134, as shown in FIG. 3B. An outer portion 154 of inter-metal dielectric pattern 150 separates gate bus 138 from source metallization 160. Inner portion 152 and outer portion 154 of inter-metal dielectric layer 150 may be monolithic in some embodiments (see FIG. 4D).

[0123] Figure 4D is a schematic cross-section taken along line 4D-4D in Figure 4C. The cross-section in Figure 4D is similar to that in Figure 4B, except that the cross-section in Figure 4D is taken at a different location in Figure 4D (i.e., through a long cross-section of inter-metal dielectric pattern 150 rather than through gate pad 136). Figures 4A-4D together show how inter-metal dielectric pattern 150 electrically insulates gate pad 136 from gate bus 138 so that gate current cannot flow directly from gate pad 136 to gate bus 138. Line 4C-4C in Figure 4D indicates the stage of MOSFET 100 from which the cross-section in Figure 4C was taken.

[0124] Figure 4E is a schematic cross-sectional view of region "A" of power MOSFET 100, taken at a stage in the device structure of the portion of polysilicon semiconductor layer 170 underlying gate pad 136. Figure 4F is a schematic longitudinal cross-section taken along line 4F-4F in Figure 4E. Line 4E-4E in Figure 4F indicates the stage of MOSFET 100 from which the cross-section of Figure 4E is taken.

[0125] As shown in Figures 4E-4F, the inter-metal dielectric pattern 150 includes downward protrusions 156 that extend into the polysilicon layer 170 underlying the gate pad 136 and gate bus 138 to form dielectric islands. These dielectric islands 156 separate the polysilicon layer 170 into inner and outer regions 172 and 174. The polysilicon patterns 176 reside in the openings 158 between adjacent dielectric islands 156, allowing current to flow between the inner and outer portions 172 and 174 of the polysilicon layer 170 through the polysilicon patterns 176. The polysilicon patterns 176 in each opening 158 thus provide a respective current path that allows gate current applied to the gate bond pad 110 to flow through the gate pad 136, then through the polysilicon patterns 176 in the openings 158 to the outer portions 174 of the polysilicon layer 170, and then onto the gate bus 138. The polysilicon pattern 176 in the opening 158 (i.e., the polysilicon region between the inner portion 172 and the outer portion 174) acts as a lumped gate resistor 176 that can be used to increase the resistance of the gate structure 130.

[0126] 4G and 4H are cross-sections taken through MOSFET 100 at lines 4G-4G and 4H-4H, respectively, of FIG. 4E.

[0127] 4G, when a bias voltage is applied to the gate bond pad 110, gate current flows downward into the gate pad 136 and into the inner portion 172 of the polysilicon layer 170. The gate current flows through the gate resistor 176 and then follows at least a resistive path into the gate bus 138. The gate current flows primarily at or near the top surface of the portion of the polysilicon layer 170 connecting the inner portion 172 to the outer portion 174, and exits the polysilicon layer 170 as soon as it can flow into the gate bus 138. The polysilicon layer 170 has a substantially higher resistance than the metals used to form the gate bond pad 110, the gate pad 136, and the gate bus 138, so that the portion of the gate current path that flows through the polysilicon layer 170 can act as a lumped gate resistor 176 inserted in the gate current path between the gate pad 136 and the gate bus 138.

[0128] Referring to FIG. 4H, it can be seen that in some locations, the intermetal dielectric layer 150 extends through the entire polysilicon pattern 170 to the underlying field oxide layer 140. As a result, current cannot flow from the inner portion 172 to the outer portion 174 of the polysilicon layer 170 in the portion of the device shown in cross section in FIG. 4H. In other words, gate current can only flow from the inner portion 172 to the outer portion 174 of the polysilicon layer 170 through the openings 158 between the dielectric islands 156 shown in FIG. 4E. Thus, multiple lumped gate resistors 176 are formed in the polysilicon layer 170. The resistance of each lumped gate resistor 176 depends on the dimensions of the opening 158 (i.e., its length and width) and the sheet resistance of the polysilicon material (or other material of the gate resistor layer). The number of openings and / or the dimensions of the openings 158 can be varied so that the total lumped resistance of the lumped gate resistors 176 has a desired resistance value.

[0129] Referring again to FIG. 2A , the conventional power MOSFET 10 includes a lumped gate resistor 32. The lumped gate resistor 32 is typically implemented as a polysilicon pattern disposed electrically in series along the gate current path between the gate pad 22 and the gate bus 24. The polysilicon pattern is doped with a first conductivity type dopant (e.g., a p-type dopant). The lumped gate resistor 32 conducts gate current flowing in both directions (i.e., from the gate pad 22 to the gate bus 24 and from the gate bus 24 to the gate pad 22). Therefore, the lumped gate resistance provided by the lumped gate resistor 32 in the conventional power MOSFET 10 of FIG. 2A has a constant value (i.e., the lumped gate resistance value is the same during device turn-on and device turn-off).

[0130] As discussed above with reference to Figure 2B, a power MOSFET according to an embodiment of the present invention may include both one or more first gate resistor circuits and one or more second gate resistor circuits, each disposed electrically in series between the gate pad and the gate bus. Figure 5A is a circuit diagram illustrating the electrical connections between the gate pad 136 and the gate bus 138 of the power MOSFET 100 of Figures 3A-4H.

[0131] As shown in FIG. 5A , the gate pad 136 is coupled to the gate bus 138 via a plurality of first gate resistor circuits 180 and a plurality of second gate resistor circuits 190. Each first gate resistor circuit 180 and each second gate resistor circuit 190 is electrically arranged in series between the gate pad 136 and the gate bus 138. The first gate resistor circuit 180 and the second gate resistor circuit 190 are electrically arranged in parallel with each other. Each first gate resistor circuit 180 includes a first gate resistor 182 and a first diode 184. Each second gate resistor circuit 190 includes a second gate resistor 192 and a second diode 194. In the depicted embodiment, as shown in FIG. 5A , the first diode 184 is implemented within the first gate resistor 182, and the second diode 194 is implemented within the second gate resistor 192. It will be understood that in other embodiments, the first diode 184 and / or the second diode 194 may be implemented separately from the first gate resistor 182 / second gate resistor 192 and may be disposed electrically in series with the respective first gate resistor 182 and / or second gate resistor 192. It will be understood that the first diode 184 and the second diode 194 may be on either or both sides of the respective first gate resistor 182 and second gate resistor 184.

[0132] FIG. 5B is a schematic diagram illustrating one embodiment of the first gate resistor circuit 180 and the second gate resistor circuit 190 of FIG. 5A. As shown in FIG. 5B, each first gate resistor circuit 180 may include a first section 185 of n-type semiconductor material disposed between a second section 186 of p-type semiconductor material and a third section 187 of p-type semiconductor material. The first section 185 of n-type semiconductor material may be in direct contact with both the second section 186 of p-type semiconductor material and the third section 187 of p-type semiconductor material. The first through third sections 185-187 of semiconductor material may form a first gate resistor 182. A pn ​​junction between the first section 185 of n-type semiconductor material and the second section 186 of p-type semiconductor material may form a first diode 184. When forward biased, the first diode 184 conducts current from left to right (i.e., from the gate pad 136 to the gate bus 138). The first diode 184 blocks current flow from right to left (ie, from the gate bus 138 to the gate pad 136).

[0133] A first metal connector 188 is provided that shorts the first section 185 of n-type semiconductor material to the third section 187 of p-type semiconductor material. Current traveling between the first section 185 of n-type semiconductor material and the third section 187 of p-type semiconductor material flows through the first metal connector 188, thus effectively bypassing the p-n junction formed at the intersection of the first section 185 of n-type semiconductor material and the third section 187 of p-type semiconductor material. The first metal connector 188 may be formed, for example, by forming a dielectric layer (e.g., the inter-metal dielectric layer 150 described above) over the first gate resistor circuit 180, then forming a via 159 through the inter-metal dielectric layer 150 and depositing metal that forms the first metal connector 188 at the bottom of the via 159. This is shown schematically in FIG. 5C . The metal connector 188 electrically connects a first internal portion of the first gate resistor 182 to a second internal portion of the gate resistor 182.

[0134] Referring again to FIG. 5B , each second gate resistor circuit 190 may include a first section 195 of n-type semiconductor material disposed between a second section 196 of p-type semiconductor material and a third section 197 of p-type semiconductor material. The pn junction between the first section 195 of n-type semiconductor material and the third section 197 of p-type semiconductor material may form a second diode 194. When forward biased, the second diode 194 conducts current from right to left (i.e., from the gate bus 138 to the gate pad 136). The second diode 194 blocks current flow from left to right (i.e., from the gate pad 136 to the gate bus 138). A second metal connector 198 is provided that shorts the first section 195 of n-type semiconductor material to the second section 196 of p-type semiconductor material. Current traveling between the first section of n-type semiconductor material 195 and the second section of p-type semiconductor material 196 flows through the second metal connector 198, thus effectively bypassing the p-n junction formed at the intersection of the first section of n-type semiconductor material 195 and the second section of p-type semiconductor material 196. The second metal connector 198 may be formed in the same manner as the first metal connector 188.

[0135] In an example embodiment, the semiconductor material used to form sections 185-187 and 195-197 may be polysilicon. It will also be understood that the conductivity types of each section 185-187 and 195-197 may be reversed in other embodiments.

[0136] As the above discussion makes clear, during device turn-on and device operation, gate current flows only through the first gate resistor circuit 180 and does not flow through the second gate resistor circuit 190. During device turn-off, gate current flows only through the second gate resistor circuit 190 and does not flow through the first gate resistor circuit 180. Referring again to FIG. 4E , multiple gate resistor circuits 176 are formed below the gate pad 136 in the MOSFET 100. Some of the gate resistor circuits 176 may include the first gate resistor circuit 180, while others of the gate resistor circuits 176 may include the second gate resistor circuit 190. In some embodiments, to configure MOSFET 100 to have different lumped gate resistance values ​​during turn-on versus turn-off operations, each of first gate resistor circuits 180 and second gate resistor circuits 190 may have the same shape / size, and the number of first gate resistor circuits 180 may be different from the number of second gate resistor circuits 190. In other embodiments, MOSFET 100 may have the same number of first gate resistor circuits 180 and second gate resistor circuits 190, but at least some of the first gate resistor circuits 180 and second gate resistor circuits 190 may have different sizes / shapes to have different resistance values ​​during turn-on versus turn-off operations. In still further embodiments, the number of first gate resistor circuits may be different from the number of second gate resistor circuits, and the sizes / shapes of the first gate resistor circuits 180 and second gate resistor circuits 190 may vary. It will also be appreciated that further or other parameters may be varied to configure MOSFET 100 to have different lumped gate resistance values ​​during turn-on versus turn-off operations, such as semiconductor materials, doping levels, etc. Some lumped gate resistors without associated switches may be provided so that gate current flows through these gate resistors during both device turn-on and device turn-off.In some embodiments, the gate resistance when the device is turned on may differ from the gate resistance when the device is turned off by at least 5%, at least 10%, at least 20%, at least 30%, or at least 50%.

[0137] In some embodiments, the first gate resistor circuits 180 and the second gate resistor circuits 190 may be “interdigitated,” meaning that each first gate resistor circuit 180 (except for any first gate resistor circuits 180 directly adjacent to an edge of the device) may be directly adjacent to two second gate resistor circuits 190 (i.e., a second gate resistor circuit 190 is on either side of each first gate resistor circuit 180), and similarly, each second gate resistor circuit 190 (except for any second gate resistor circuits 190 directly adjacent to an edge of the device) may be directly adjacent to two first gate resistor circuits 180 (i.e., a first gate resistor circuit 180 is on either side of each second gate resistor circuit 190). This may help to further improve the balance of the device. It will be understood that other combination designs may be used (e.g., multiple pairs of first gate resistor circuits 180 are interposed between two pairs of second gate resistor circuits 190, or vice versa). In some embodiments, each first gate resistor circuit 180 may be directly adjacent to at least one second gate resistor circuit 190.

[0138] Figure 6 is a schematic diagram illustrating another possible implementation of the first gate resistor circuit 180 and the second gate resistor circuit 190 of Figure 5A. As shown in Figure 6, each first gate resistor circuit 180 may include only a first section 185 of n-type semiconductor material and a second section 186 of p-type semiconductor material, and each second gate resistor circuit 190 may include only a first section 195 of n-type semiconductor material and a third section 197 of p-type semiconductor material. 6 may be used, for example, when the portions of polysilicon layer 170 underlying gate pad 136 and gate bus 138 (see FIGS. 4A-4H ) are removed, and gate pad 136 and gate bus 138 are extended to replace the respective omitted portions of polysilicon layer 170 (i.e., gate pad 136 and gate bus 138 are extended to directly contact the top surface of field oxide layer 140). In this design, first gate resistor circuit 180 and second gate resistor circuit 190 directly contact metal gate pad 136 on one side and metal gate bus 138 on the other side, so that a single pn junction may be provided for each first gate resistor circuit 180 and second resistor circuit 190. This design eliminates any need for first metal connector 188 and second metal connector 198 since there is no second pn junction that needs to be shorted.

[0139] 7 is a circuit diagram showing a power MOSFET 200 according to a further embodiment of the present invention, having a different design for the first and second gate resistor circuits. The power MOSFET 200 may be identical to the power MOSFET 100 described above, except that a first gate resistor circuit 280 and a second gate resistor circuit 290 are used in the power MOSFET 200 instead of the first gate resistor circuit 180 and the second gate resistor circuit 190 of the power MOSFET 100. As can be seen by comparing FIGS. 2B and 7, in the power MOSFET 200, the first gate resistor circuit 280 and the second gate resistor circuit 290 include a first gate resistor 282 and a second gate resistor 292, respectively, and a first transistor 284 and a second transistor 294, respectively, which replace the first diode 184 and the second diode 194 included in the power MOSFET 100. 5B , the gates of transistors 284, 294 may be formed on first sections 185, 195 of n-type semiconductor material (and may extend over the edges of second sections 186-187 of p-type semiconductor material and third sections 196-197 of p-type semiconductor material) with a gate insulating layer (not shown) disposed therebetween. A signal may be applied to the gates of transistors 284, 294 to allow gate current to flow exclusively through first gate resistor circuit 280 during device turn-on and device operation, and to allow gate current to flow exclusively through second gate resistor circuit 290 during device turn-off.

[0140] While the above-described examples of the present invention all involve power MOSFET designs, it will be understood that embodiments of the present invention are not limited thereto. In particular, it will be understood that the integrated asymmetric gate resistor designs disclosed herein may be used in any gate-controlled device, including MOSFETs, IGBTs, JFETs, thyristors, GTOs, or any other gate-controlled device.

[0141] While the above discussion has focused primarily on planar MOSFETs, it will be understood that all of the disclosed embodiments can similarly be used in MOSFETs (or other gate-controlled power semiconductor devices) in which gate fingers are formed in trenches in a semiconductor layer structure. For example, FIG. 8 is a schematic cross-sectional view of MOSFET 300, a modification of MOSFET 100. MOSFET 300 of FIG. 8 includes gate fingers 334 formed in trenches 321 in semiconductor layer structure 320, as opposed to having planar gate fingers formed in the semiconductor layer structure. As shown in FIG. 8, MOSFET 300 can be very similar to MOSFET 100 of FIG. 3C, except that trenches 321 are etched (or otherwise formed) in semiconductor layer structure 320, and gate insulation fingers 332 and gate fingers 334 are then formed in their respective trenches 321. Additionally, p-type shield regions 329 may be formed under all or a portion of each trench 321 to protect the gate insulation fingers 332 during reverse bias operation, and p-shield connection regions 331 may be provided to electrically connect the p-type shield regions 329 to the source metallization 160. It will therefore be appreciated that gate resistors according to embodiments of the present invention may be implemented in gate-controlled devices having gate trenches, such as the device of FIG. 8, as well as in devices having planar gate fingers.

[0142] As described above, various gate-controlled power semiconductor devices may exhibit unbalanced switching behavior due to asymmetric device behavior during device turn-on and device turn-off. According to embodiments of the present invention, a power semiconductor device is provided that includes an integrated gate resistor circuit that exhibits different resistance values ​​during device turn-on and turn-off. By applying such different resistance values, switching balance may be improved.

[0143] As described above, the use of asymmetric gate resistors can advantageously improve the balance of power semiconductor device turn-on and turn-off switching behavior. Asymmetric gate resistance can be achieved by implementing the lumped gate resistor of a power semiconductor device as multiple individual lumped gate resistors with relatively small resistances, rather than using a single lumped gate resistor with a relatively large resistance. Each of the relatively small lumped gate resistors can be coupled in series with a diode-like switch, where some of the diodes are configured to allow current to flow from the gate pad to the gate fingers in a first direction, while others of the diodes are configured to allow current to flow from the gate fingers to the gate pad in a second (opposite) direction. In this way, current flowing from the gate pad to the gate fingers flows through a first subset of the lumped gate resistors, thereby resulting in a first gate resistance value for current flowing into the power semiconductor device, and current flowing from the gate fingers to the gate pad flows through a second (different) subset of the lumped gate resistors, thereby resulting in a second gate resistance value for current flowing out of the power semiconductor device. The first gate resistor and the second gate resistor may be set to various values ​​to optimize performance parameters of the power semiconductor device.

[0144] An additional advantage of using multiple discrete lumped gate resistors with relatively small resistances instead of a single lumped gate resistor with a relatively large resistance is that this technique allows the gate resistors to be spaced apart from one another. Whenever a gate-controlled power semiconductor device, such as a MOSFET or IGBT, transitions from its OFF state to its ON state, or vice versa, a certain amount of gate current must flow into the device's gate structure. This gate current is designed to flow through the lumped gate resistor to control the device's switching speed and / or to reduce electrical ringing and noise that can result from undesirable loop behavior if sufficient gate resistance is not present. The total gate resistance includes the resistance of the lumped gate resistor and the distributed gate resistance, which is set by the sheet resistance of the gate fingers (typically polysilicon) and the gate bus (the gate bus is typically metal, but may alternatively be polysilicon or other materials) that electrically connects the gate fingers to the gate pad. It can be shown that the energy loss due to the total gate resistance when altering the gate of a power semiconductor device, such as a MOSFET, is equal to the energy required to alter the MOSFET: Energy loss = 0.5 * Q g_total * ΔV gs where Q g_total is the total gate charge, and ΔV gs is the change in gate-to-source voltage caused by changing the gate.

[0145] Whenever the gate of a power semiconductor device is discharged to transition the device from an ON state to an OFF state, the same amount of energy is lost. Therefore, for one complete switching cycle, the energy lost is Q g_total * ΔV gs This energy loss is equal to the switching frequency (F SW) and therefore the average power dissipation in the total series gate resistance is given by: Average power dissipation = Q g_total * ΔV gs * F SW It can be calculated as:

[0146] Typically, the lumped gate resistor represents a significant portion of the total series gate resistance, and therefore a significant portion of the power dissipation can occur in the lumped gate resistor. Power is dissipated as heat, which must then be removed from the power semiconductor device to ensure that the temperature of the semiconductor device is maintained within the desired operating temperature range for the device.

[0147] As discussed above, lumped gate resistors can be formed on power semiconductor dies to reduce component count and increase device performance. Power semiconductor devices can be designed to operate at high temperatures, such as temperatures of 200° C. or higher. Device performance can degrade at higher temperatures, and operation at sufficiently high temperatures can, on average, result in performance failure of the power semiconductor device.

[0148] In conventional power semiconductor devices, lumped gate resistance is typically implemented as a single lumped gate resistor formed by forcing the gate current through a sheet of polysilicon material with a length and width selected to achieve the desired lumped gate resistance value. * L / (W *t), where ρ is the resistivity of the material (here, polysilicon), W is the width, L is the length, and t is the thickness. As mentioned above, a significant portion of the power loss that occurs during gate charging and discharging is dissipated in the lumped gate resistor, which converts power to heat that must then be removed from the device. This is typically accomplished by providing a heat dissipation path through the device to a cooling medium, such as a heat sink. Typically, the heat sink is attached to the "bottom" or "back" side of the semiconductor layer structure, while the lumped gate resistor is formed on the top side of the semiconductor layer structure. Therefore, heat generated in the lumped gate resistor is primarily dissipated from the device by conduction through the semiconductor layer structure to the heat sink.

[0149] As heat from the lumped gate resistor travels through the semiconductor layer structure, it increases the temperature of the semiconductor layer structure. Using the law of heat conduction, the increase in temperature can be calculated as follows: ΔT=P g * R th where P g is the heat flow and R th is the thermal resistance of the semiconductor layer structure.

[0150] The thermal resistance of a medium, such as a semiconductor layer structure in a power semiconductor device, can be determined based on the cross-sectional area of ​​the medium (i.e., for a medium with a rectangular cross-section, the length of the medium multiplied by the width of the medium), the thickness of the medium, and the thermal conductivity of the medium. However, in the case of a lumped gate resistor, the surface area of ​​the lumped gate resistor in contact with the heat dissipation medium (here, the semiconductor layer structure) is much smaller than the surface area of ​​the heat dissipation medium. Therefore, heat enters the semiconductor layer structure through a portion of its first surface with a small surface area and exits the semiconductor layer structure through a portion of its second surface with a much larger surface area. Therefore, heat not only moves through the semiconductor layer structure in its thickness direction, but also diffuses laterally. Lateral heat diffusion acts to increase the heat flow area. The increased heat flow area reduces the effective thermal resistance of the heat dissipation medium, resulting in improved heat dissipation. The net effect of increasing the heat flow area is to remove more heat while keeping the temperature increase of the semiconductor layer structure constant, or alternatively, to reduce the net increase in the temperature of the semiconductor layer structure while keeping the amount of heat removal constant.

[0151] Figure 9 shows the lumped gate resistor R L 9 is a schematic diagram showing how heat generated in the semiconductor layer structure SLS is dissipated through the semiconductor layer structure SLS. L and length L L A single lumped gate resistor R L is formed on the top surface of the semiconductor layer structure SLS. As shown in FIG. 9, a lumped gate resistor R L The heat introduced into the semiconductor layer structure SLS from the semiconductor layer structure SLS is diffused in the semiconductor layer structure SLS according to a heat diffusion angle α associated with the material used to form the semiconductor layer structure SLS, and the heat is diffused in the semiconductor layer structure SLS according to a heat diffusion angle α associated with the material used to form the semiconductor layer structure SLS. E and length L E Therefore, the heat leaves the area with surface area A out =W E * L E As can be seen from FIG. 9, the single lumped gate resistor R LThe surface area A of the bottom surface of the semiconductor layer structure SLS through which the heat generated by the out is determined by the heat diffusion angle α and the thickness T of the semiconductor layer structure SLS, and the lumped gate resistor R L The surface area of ​​the base (A in =W L * L L ) can be much larger than

[0152] According to an embodiment of the present invention, the above-mentioned single lumped gate resistor R provided in a conventional power semiconductor device L is a multiple smaller lumped gate resistor R spaced apart from one another to improve the heat dissipation characteristics of the power semiconductor device. g As mentioned above, the conventional single lumped gate resistor R L Considering that only the gate resistor R occupies a small area on the top surface of the semiconductor layer structure SLS, the gate resistor R L The heat generated by the single large lumped gate resistor R used in conventional power semiconductor devices can only diffuse laterally through the semiconductor layer structure SLS as much as it can dissipate through the semiconductor layer structure SLS, and therefore all of the heat ends up dissipating through a relatively small area of ​​the semiconductor layer structure SLS, significantly increasing the temperature of this portion of the semiconductor layer structure SLS. L Instead of multiple smaller spaced apart lumped gate resistors R g By using this method, heat dissipation in power semiconductor devices can be significantly improved. Initial test results suggest that this technique can increase the "ruggedness" of power semiconductor devices by about four times, where ruggedness refers to the device's ability to operate at higher power levels.

[0153] In some embodiments, a smaller lumped gate resistor R g is the value of any pair of adjacent lumped gate resistors R g10A, which shows a semiconductor layer structure SLS having multiple smaller lumped gate resistors R. g1 ~R g3 10A is a schematic diagram showing how heat generated in the semiconductor layer structure SLS is dissipated through three relatively small lumped gate resistors R g1 ~R g3 is formed on the top surface of a semiconductor layer structure having a thickness T. A smaller lumped gate resistor R g Each of these is connected to a single larger lumped gate resistor R shown in Figure 9. L Preferably, the smaller lumped gate resistor R g Each of these has its respective heat output area A out As is readily apparent from a comparison of FIG. 9 and FIG. 10A, the three regions A out The area occupied by a single lumped gate resistor R L 10A. The area Aout in FIG. 10A may be significantly larger than the corresponding area Aout in FIG.

[0154] In other embodiments, a smaller lumped gate resistor R g is the value of any pair of adjacent lumped gate resistors R g 10B shows an example of such an embodiment. In FIG. 10B, two smaller lumped gate resistors R g1 and R g2 is shown. The lumped gate resistor R g1 The heat generated by the g2 The heat generated by the first area A1 exits the bottom surface of the semiconductor layer structure SLS through the second area A2. The first area A1 and the second area A2 partially overlap, and this overlap region is called the overlap area A O As mentioned above, in some embodiments, a lumped gate resistor Rg1 , R g2 The two resistors may be separately diffused in such an amount that the heat dissipated by the two resistors substantially passes through various portions of the semiconductor layer structure SLS. In this context, "substantially" means that the sum of the first area A1 and the second area A2 shown in FIG. 10B is the overlapping area A O At least 10 times (i.e., A1 + A2 ≥ 10 * A O ) In other words, both lumped gate resistors R g1 , R g2 The heat from the first gate resistor and the second gate resistor of the pair exits the semiconductor layer structure for only 10% of the area where the heat from the first gate resistor and the second gate resistor of the pair exits the semiconductor layer structure. For example, the first area A1 is A1=W E * L E =(2 * T * tan(α)+W L ) * (2 * T * tan(α)+L L ) can be calculated as

[0155] It will be appreciated that while having little or no overlap between the first area A1 and the second area A2 may provide the greatest improvement in heat dissipation, improved performance may still be achieved with a greater amount of overlap. Thus, in other embodiments, the sum of the first area A1 and the second area A2 shown in FIG. 10B may be less than the overlap area A O At least 8 times (i.e., A1 + A2 ≥ 8 * A O ), overlap area A O At least 5 times (i.e., A1 + A2 ≥ 5 * A O ), overlap area A O At least twice (i.e., A1 + A2 ≥ 2 * A O ), or overlap area A O At least 1.5 times (i.e., A1 + A2 ≥ 1.5 * A O ) can be.

[0156] The number of smaller lumped gate resistors used in place of a single lumped gate resistor in a conventional device can be selected based on various considerations. Generally speaking, increasing the number of smaller lumped gate resistors (while keeping the overall value of the lumped gate resistor constant) reduces the effective thermal resistance (and thus improves heat dissipation) until the available area at the bottom of the semiconductor layer structure for heat dissipation is fully utilized. At that point, further subdividing the lumped gate resistors has no effect on the effective thermal resistance. As shown in FIGS. 10A-10B, to prevent heat generated by a first one of the lumped gate resistors from exiting through the same region of the semiconductor layer structure SLS as heat generated by an adjacent second one of the lumped gate resistors, the facing side edges of the first and second lumped gate resistors are spaced at least two apart. * T * They should be separated by a distance of tan(α).

[0157] Fig. 11A is a schematic plan (top) view of a conventional power semiconductor device 400. Fig. 11B is an enlarged view of the gate pad region of the conventional power semiconductor device 400 of Fig. 11A.

[0158] As shown in FIG. 11A , power semiconductor device 400 includes gate pad 410, gate bus 420, lumped gate resistor 430, measurement pad 440, and source metallization 450. Measurement pad 440 is not actually part of a conventional power semiconductor device 400, but represents an additional feature included to enable accurate measurement of gate resistance. In this particular device, gate pad 410 is located in the upper left corner of device 400. Gate bus 420 includes multiple gate bus segments 422-1 through 422-7 that are interconnected to form a continuous gate bus 420 that extends around approximately most of the periphery of power semiconductor device 400 and also extends into the device's interior. First and second segments 422-1 and 422-2 of gate bus 420 are spaced from gate pad 410 by respective first and second gaps 424-1 and 424-2. A gate resistor 430 is inserted into a portion of the first gap 424-1 between the gate pad 410 and the first gate bus segment 422-1 to electrically connect the gate pad 410 to the first gate bus segment 422-1. The gate resistor 430 represents the only electrical connection between the gate pad 410 and the gate bus 420. Thus, when gate current is applied to the gate pad 410 from an external source, the entire gate current flows through the gate resistor 430, then to the gate bus 420, and from the gate bus to the gate fingers (not shown). The current path from the gate pad 410, through the gate resistor 430, to the gate bus 420 can best be seen in the expanded view in FIG. 11B.

[0159] Measurement pads 440 are provided to allow accurate measurement of lumped gate resistor 430. Probes can be placed on gate pad 410 and measurement pad 440 to measure the resistance of lumped gate resistor 430.

[0160] Figure 12A is a schematic plan view of a power semiconductor device 500 according to a further embodiment of the present invention, and Figure 12B is an enlarged view of the gate pad area of ​​the power semiconductor device 500 of Figure 12A.

[0161] 12A-12B, it can be seen that power semiconductor device 500 is very similar to power semiconductor device 400 of Figures 11A-11B. In particular, power semiconductor device 500 includes gate pad 510, gate bus 520 including gate bus segments 522-1 through 522-7, measurement pad 540, and source metallization 550, all of which are located in the same locations as the corresponding components of power semiconductor device 400. Power semiconductor device 500 differs from power semiconductor device 400 in that multiple smaller lumped gate resistors 530-1 through 530-10 are used in power semiconductor device 500 instead of the large lumped gate resistor 430 of power semiconductor device 400. Smaller lumped gate resistors 530 extend between the gate pad 510 and the gate bus 520 across either a first gap 524-1 or a second gap 524-2 between the gate pad 510 and the respective gate bus segments 522-1, 522-2. The gate resistors 530 electrically connect the gate pad 510 to the gate bus 520. The gate resistors 530 are spaced apart from one another by a dielectric pattern (i.e., the gaps 524-1, 524-2 are filled with the gate resistors 530 and a dielectric material (not shown)). Each gate resistor 530 has a length L g , width W g and thickness T gThe length refers to the distance the gate resistor 530 extends along an axis parallel to the major surface of the device's semiconductor layer structure and perpendicular to the edge of the gate pad 510 from which the gate resistor 530 extends. In other words, the length of each gate resistor 530 is the direction in which it extends across the gap 524. Because the first gap 524-1 and the second gap 524-2 extend in different vertical directions, the length of the gate resistor 530 extending across the first gap 524-1 is perpendicular to the length of the gate resistor 530 extending across the second gap 524-2. The width of each gate resistor 530 refers to the distance the gate resistor 530 extends along an axis parallel to the major surface of the device's semiconductor layer structure and perpendicular to the length of the gate resistor 530. The thickness of the gate resistor 530 refers to the extent of the gate resistor in a direction perpendicular to the major surface of the semiconductor layer structure. In the embodiment of Figures 12A-12B, the length of each gate resistor 530 is approximately the same as its width.

[0162] When gate current is applied to gate pad 510 from an external source, the gate current is shunted such that respective portions of the gate current flow through respective gate resistors 530 to gate bus 520, and from gate bus 520 to gate fingers (not shown). Because each gate resistor 530 is approximately the same size, a similar amount of gate current flows through each gate resistor 530, but the amount of current will have some variation due to differences in the resistance of gate bus 520 seen by each gate resistor 530.

[0163] Fig. 13A is a schematic plan view of another conventional power semiconductor device 600. Fig. 13B is an enlarged view of a gate pad region of the conventional power semiconductor device 600 of Fig. 13A. Fig. 13C is an enlarged view of a portion of a lumped gate resistor 630 included in the conventional power semiconductor device 600 of Fig. 13A.

[0164] 13A-13B, a conventional power semiconductor device 600 includes a gate pad 610, a gate bus 620, a single lumped gate resistor 630, a measurement pad 640, and source metallization 650. Measurement pad 640 is not actually part of conventional power semiconductor device 600, but represents an additional feature included to enable accurate measurement of gate resistance. In device 600, gate pad 610 is located next to a first side edge of device 600 approximately midway between two other side edges of the device. Gate bus 620 includes multiple gate bus segments 622-1 through 622-10 that are interconnected to form a continuous gate bus structure that extends around most of the periphery of power semiconductor device 600 and also extends into the interior of the device when viewed in plan view. First through fifth segments 622-1 through 622-5 of gate bus 620 are spaced from gate pad 610 by respective first through fifth gaps 624-1 through 624-5. A single lumped gate resistor 630 is inserted into a portion of first gap 624-1 between gate pad 610 and first gate bus segment 622-1 to electrically connect gate pad 610 to gate bus 620. Gate resistor 630 is the only electrical connection between gate pad 610 and gate bus 620, so that any gate current applied to gate pad 610 from an external source flows entirely through gate resistor 630 to gate bus 620 and from gate bus 620 to a gate finger (not shown).

[0165] The lower portion of gate pad 610 is wider than the upper portion of gate pad 610 such that gate pad 610 has an inverted L shape (alternatively, it may have an L shape, for example). Referring to Figure 13C, an enlarged plan view of gate resistor 630 is shown. As can be seen, the gate resistor has a length of X microns and a width of approximately 4X to 8X microns in the illustrative embodiment.

[0166] Figure 14A is a schematic plan view of a power semiconductor device 700 in accordance with yet a further embodiment of the present invention. Figure 14B is an enlarged view of the gate pad area of ​​the power semiconductor device 700 of Figure 14AB. Figure 14C is an enlarged view of some of the smaller lumped gate resistors 730 included in the power semiconductor device 700 of Figure 14A.

[0167] 14A-14B, it can be seen that power semiconductor device 700 is similar to power semiconductor device 600 of FIGS. 13A-13C. In particular, power semiconductor device 700 includes a gate pad 710, a gate bus 720 including gate bus segments 722-1 through 722-10, a measurement pad 740, and a source metallization 750, all of which are located in the same locations as the corresponding components of power semiconductor device 600. Power semiconductor device 700 differs from power semiconductor device 600 in that multiple smaller lumped gate resistors 730 are used in power semiconductor device 700 instead of the single large lumped gate resistor 630 of power semiconductor device 600. Each of the smaller lumped gate resistors 730 extends between gate pad 710 and gate bus 720. In particular, the lumped gate resistors 730 extend from all six sides of gate pad 710. 14A-14B, it can be seen that the lumped gate resistor 730 substantially surrounds the gate pad 710 when the semiconductor device 700 is viewed in plan view. The gate pad 710 is separated from the gate bus 720 by a continuous gap 724 that extends all the way around the gate pad 710. The lumped gate resistor 730 extends across this gap 724. The lumped gate resistor 730 electrically connects the gate pad 710 to the gate bus 720. It will be understood that the lumped gate resistor 730 may extend outward from fewer than all of the sides of the gate pad 710 in other embodiments. For example, the lumped gate resistor 730 may extend outward from one, two, three, four, or five of the sides of the gate pad 710 in other embodiments. As can be seen, the lumped gate resistor 730 may extend outward from opposing sides of the gate pad 710. For example, lumped gate resistor 730 may extend from the top and bottom sides of gate pad 710 in the view of FIG. 14A, and / or from both the left and right sides of gate pad 710.

[0168] As shown in FIGS. 14A-14B , some of the lumped gate resistors 730 extend outward from the side edges of the gate pad 710 to contact a portion of the gate bus 720 that extends along a first outer edge of the semiconductor device 700 (here, the upper outer edge in the plan view of FIGS. 14A-14B ). Lumped gate resistors would not typically be positioned in this location. In some embodiments, a first one of the lumped gate resistors 730 may contact a portion of the gate bus 720 that extends along the first outer edge of the semiconductor device 700, while a second one of the lumped gate resistors 730 may contact a first linear segment of the gate bus 720 that contacts a second linear segment of the gate bus 720 that extends perpendicular to the first linear segment of the gate bus 720 through the active region of the semiconductor device 700. For example, with reference to FIGS. 14A-14B , a first lumped gate resistor 730 (one of four lumped gate resistors 730) may extend from a side edge of gate pad 710 to contact a portion of gate bus segment 722-3 that extends along the outer edge of semiconductor device 700, while a second lumped gate resistor 730 (one of six lumped gate resistors 730) contacts gate bus segment 722-1, which in turn contacts gate bus segment 722-2, which extends perpendicular to gate bus segment 722-1 and through the active region of semiconductor device 700.

[0169] In some embodiments, semiconductor device 700 may include at least four lumped gate resistors 730. In other embodiments, semiconductor device 700 may include at least eight lumped gate resistors 730, at least twelve lumped gate resistors 730, at least sixteen lumped gate resistors 730, at least twenty lumped gate resistors 730, at least twenty-four lumped resistors 730, or at least thirty-two lumped gate resistors 730.

[0170] The lumped gate resistors 730 are spaced apart from one another by a dielectric pattern. In other words, a dielectric material (e.g., silicon dioxide) is provided between each pair of adjacent lumped gate resistors 730. The lumped gate resistors 730 may be spaced apart from one another by approximately equal amounts to improve heat dissipation. By having the lumped gate resistors 730 extend from all six sides of the gate pad 710, the heat dissipation performance of the power semiconductor device 700 may be improved. Each gate resistor 730 has a length L defined as described above with reference to the gate resistors 530. g , width W g and thickness T g Each gate resistor 730 has a length L g is its width W g (in the illustrated embodiment, the length is greater than four times the width).

[0171] In some embodiments, the lumped gate resistors 730 may be substantially uniformly spaced from adjacent lumped gate resistors 730. Furthermore, in some embodiments, the lumped gate resistors 730 may have a width that is less than the spacing between adjacent lumped gate resistors 730, which may enhance heat dissipation. For example, with reference to FIG. 14C , first, second, and third lumped gate resistors 730-1 through 730-3 may extend from a first side of the gate pad 710, with the second lumped gate resistor 730-2 being directly adjacent to and between the first lumped gate resistor 730-1 and the third lumped gate resistor 730-3. The width W of the second lumped gate resistor 730-2 may be 1 / 2 . g (where each lumped gate resistor 730 has the same width) may be smaller than the first distance D1 between the first lumped gate resistor 730-1 and the second lumped gate resistor 730-2, and the width W gmay also be less than the second distance D2 between the second lumped gate resistor 730-2 and the third lumped gate resistor 730-3. In some embodiments, D1 may be equal to D2. In an example embodiment, L g is W g In some embodiments, the first distance D1 may be 3 to 6 times larger than the width W of the second lumped gate resistor 730-2. g and / or the second distance D2 may be greater than two, greater than three, or even greater than four times the width W of the second lumped gate resistor 730-2. g It may be more than two times, more than three times, or even more than four times.

[0172] 15A and 15B are schematic plan views generally corresponding to FIG. 14C illustrating how selection of the aspect ratio of lumped gate resistors can improve heat dissipation. As shown in FIG. 15A, a power semiconductor device 800 has multiple lumped gate resistors 830 extending between a gate pad 810 and a gate bus 820. Each lumped gate resistor has a length L of 50 arbitrary units (e.g., microns). g and 20 arbitrary unit width W g and adjacent lumped gate resistors of the lumped gate resistor 830 are spaced apart by a distance D g 15B shows a power semiconductor device 800' having the same overall lumped gate resistors as power semiconductor device 800, except that in power semiconductor device 800', each lumped gate resistor 830' has a length L of 100 arbitrary units (e.g., microns). g and width W in 50 arbitrary units g and adjacent lumped gate resistors of the lumped gate resistor 830′ are spaced apart by a distance D g = 50 arbitrary units apart from each other.

[0173] As discussed above, heat generated in each lumped gate resistor 830 diffuses laterally as it propagates through the semiconductor layer structure of the power semiconductor device 800. To maximize heat dissipation, heat generated by a first one of the lumped gate resistors 830 should not exit through the same portion of the semiconductor layer structure as heat generated by an adjacent second one of the lumped gate resistors 830. It is therefore advantageous to position adjacent lumped gate resistors sufficiently far apart from each other so that this condition is met.

[0174] As can be seen by comparing FIGS. 15A and 15B, to increase the distance between adjacent lumped gate resistors 830, it is necessary to shorten the length of each lumped gate resistor 830 if the total lumped gate resistance is to be held constant. In the example shown in FIGS. 15A-15B, halving the length of the gate resistors 830′ in the power semiconductor device 800′ can increase the distance between adjacent gate resistors to 50-70°. While tolerances and other considerations can reduce the length of the lumped gate resistors to be too small, generally speaking, in some embodiments it may be advantageous not to make the length significantly larger than the width of each gate resistor, and in some cases it may be advantageous to have gate resistors with widths greater than their lengths.

[0175] Thus, in some embodiments, the length L of some or all of the lumped gate resistors 730 g is the width W of each lumped gate resistor 730 g In other embodiments, the length of some or all of the lumped gate resistors 730 may be less than five times the width W of each lumped gate resistor 730. g In some embodiments, substantially all of the lumped gate resistors 730 may have a width less than three times or less than two times their respective width W g Length L less than twice the gIn some embodiments, the at least one lumped gate resistor 730 may have a width W g Length L is smaller than g may have:

[0176] 14A-14C, when gate current is applied to gate pad 710 from an external source, the total gate current is shunted such that respective portions of the gate current flow through respective gate resistors 730 to gate bus 720, and from gate bus 720 to gate fingers (not shown). Because each gate resistor 730 is approximately the same size, a similar amount of gate current flows through each gate resistor 730, but the amount of current will have some variation due to differences in the resistance of gate bus 720 seen by each gate resistor 730.

[0177] To compare the performance of a single large lumped gate resistor with that of multiple smaller lumped gate resistors, the devices shown in Figures 13A-13C and 14A-14C were fabricated and then subjected to various tests. These tests included DC, pulse, and high frequency tests. During testing, the test devices were mounted on an active heat sink.

[0178] For DC testing, five DC voltage pulses were applied to the gate, where the pulse was applied for 5 seconds and then removed for 5 seconds. Five-second pulses were determined to be sufficient to allow the lumped gate resistor to reach a steady state during the heating (on) and cooling (off) intervals. The applied DC voltage was incrementally increased until each of the tested power semiconductor devices failed. For pulse testing, pulses having a duration of 10 microseconds were each applied to the gate of the device under test. The magnitude of the pulse was increased until the device failed.

[0179] The power semiconductor device 600 of FIGS. 13A-13C failed the DC test at an applied voltage of 27.5 volts and a current of 1.5 Amp, thus failing at a power level of 41.25 watts. In contrast, the power semiconductor device 700 of FIGS. 14A-14C failed the DC test at an applied voltage of 45 volts and a current of 4.9 Amp, thus failing at a power level of 220 watts. With respect to pulse testing, for multiple samples, the power semiconductor device 600 of FIGS. 13A-13C failed at power levels between 55 watts and 160 watts, while samples of the power semiconductor device 700 of FIGS. 14A-14C always failed at a power level of approximately 700 watts. These test results suggest that the robustness of the power semiconductor device 700 of FIGS. 14A-14C is approximately four times better than the robustness of the power semiconductor device 600 of FIGS. 13A-13C.

[0180] For the high-frequency tests, high-frequency pulses were applied to the gate for a period of 10 minutes, where the on-time and off-time of the pulses were equal. Tests were conducted at switching frequencies between 500 kHz and 2.5 MHz. Samples of the power semiconductor device 600 of FIGS. 13A-13C failed at temperatures between 400-410°C at a switching frequency of 2 MHz. In contrast, samples of the power semiconductor device 700 of FIGS. 14A-14C remained functional at temperatures between 450-500°C at switching frequencies between 2.25-2.5 MHz. Testing on these samples was terminated after some portions of the device desoldered due to the high device temperatures.

[0181] It will be appreciated that semiconductor devices according to embodiments of the present invention may have a gate electrode extending over the top of a wide bandgap semiconductor layer structure, or may have a gate electrode extending into a trench formed in the wide bandgap semiconductor layer structure.

[0182] The use of multiple lumped gate resistors instead of a single lumped gate resistor is counterintuitive for several reasons. When a single large lumped gate resistor is used, etching variations, which may be caused by unintentional variations and / or tolerances in both the photomask and the actual etching, occur exclusively along the outer boundary of the single lumped gate resistor. As a result, the total variation from the desired value can be reduced or minimized. When multiple smaller lumped gate resistors are used instead, the increase in the overall outer boundary increases the variation. This increase can result in greater variation in resistance and may increase the likelihood of device failure. Furthermore, the goal of a lumped gate resistor is to provide a purely lumped resistor. Distributing the lumped gate resistors introduces the possibility that multiple lumped gate resistors may exhibit distributed resistance behavior. Therefore, those skilled in the art would be drawn away from the design concept of the present invention. However, a single large lumped gate resistor can substantially increase the temperature of a small region of the semiconductor layer structure, which can cause premature device failure. Therefore, by replacing a single large lumped gate resistor with multiple smaller spaced apart lumped gate resistors, the overall performance of a power semiconductor device can be improved.

[0183] Doped polysilicon layers included in power semiconductor devices according to embodiments of the present invention can be used to form, for example, gate fingers, gate resistors, and possibly gate buses. These layers can be doped during epitaxial growth, doped by ion implantation, and / or doped by a diffusion process. Doping these layers by ion implantation can improve the uniformity of the doping profile because the ion implantation process tends to break down polycrystalline layers into smaller crystals, and the smaller crystal size can improve the uniformity of sheet resistance. High-concentration dopant ions, such as BF2, can be used because they do a better job of breaking down the crystals into smaller units. Doping by ion implantation using a high-concentration dopant can improve the uniformity of gate resistance from the 10-20% range to the 5-10% range.

[0184] The gate resistor designs disclosed herein may be used in any gate-controlled device, including MOSFETs, IGBTs, JFETs, thyristors, GTOs, and the like.

[0185] The gate metal (e.g., gate pad, gate bus) contacting the lumped gate resistor according to embodiments of the present invention may form an ohmic contact with the lumped gate resistor. Suitable metals for forming such an ohmic contact include aluminum, titanium, and / or titanium nitride.

[0186] It will be understood that the semiconductor devices described above are n-type devices having source bond pads on their top sides and drain pads on their bottom sides, while these positions would be reversed in p-type devices. Furthermore, while the power MOSFETs described above and other devices described herein are shown as being silicon carbide-based semiconductor devices, it will be understood that embodiments of the present invention are not so limited. Instead, the semiconductor devices may include any wide bandgap semiconductor suitable for use in power semiconductor devices, including, for example, gallium nitride-based semiconductor devices and II-VI compound semiconductor devices.

[0187] As used herein, the term "cross-section" refers to a cross section taken along a plane that is parallel to the plane defined by the bottom surface of the semiconductor layer structure.

[0188] The present invention has been described above with reference to the accompanying drawings, in which embodiments of the invention are shown. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it will be understood that the element or layer can be directly on, directly connected to, or directly coupled to the other element or layer, or that intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly connected to" another element or layer, there are no intervening elements or layers present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Like numbers refer to like elements throughout unless expressly noted.

[0189] In this specification, the terms "first" and "second" are used to describe various regions, layers, and / or elements, but it will be understood that these regions, layers, and / or elements should not be limited by these terms. These terms are used merely to distinguish one region, layer, or element from another region, layer, or element. Thus, a first region, layer, or element described below may be referred to as a second region, layer, or element, and similarly, a second region, layer, or element may be referred to as a first region, layer, or element, without departing from the scope of the present invention.

[0190] Relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element, as shown in the figures. It will be understood that the relative terms are intended to encompass various orientations of the device in addition to the orientation depicted in the figures. For example, if a device in the figures were turned over, an element described as being on the "lower" side of another element would be oriented on the "upper" side of the other element. Thus, the exemplary term "lower" can encompass both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if a device in one of the figures were turned over, an element described as "below" or "below" another element would be oriented "above" that other element. Thus, the exemplary terms "below" or "below" can encompass both an orientation of top and bottom.

[0191] The terminology used in the present invention is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," as used herein, specify the presence of the described features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or groups thereof. As used herein, the term "plurality" means "at least two." As used herein, two elements of a semiconductor device "vertically overlap" if an axis perpendicular to a major surface of the semiconductor layer structure of the semiconductor device extends through both of the elements.

[0192] Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations. As such, variations from the shapes of the illustrations are to be expected as a result, for example, of manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein and are to include deviations in shape that result, for example, from manufacturing. For example, implanted regions illustrated as rectangles typically have rounded or curved features at their edges and / or a gradient of implant concentration rather than a binary transition from implanted to non-implanted regions. Accordingly, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to represent the actual shape of a region of a device and are not intended to limit the scope of the present invention.

[0193] It will be understood that the embodiments disclosed herein may be combined, and thus, features depicted and / or described with respect to a first embodiment may also be included in a second embodiment, and vice versa.

[0194] While the above embodiments are described with reference to certain figures, it should be understood that some embodiments of the invention may include additional and / or intervening layers, structures, or elements, and / or certain layers, structures, or elements may be omitted. While several illustrative embodiments of the invention have been described, those skilled in the art will readily appreciate that many modifications may be made to the illustrative embodiments without substantially departing from the novel teachings and advantages of the invention. Accordingly, all such modifications are intended to be included within the scope of the invention as set forth in the claims. Accordingly, it should be understood that the foregoing is illustrative of the invention and should not be construed as limited to the particular embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The invention is defined by the appended claims, including equivalents of the claims.

Claims

1. a gate pad; Gate Bus and a gate resistor structure electrically interposed between the gate pad and the gate bus; 1. A semiconductor device comprising: the gate resistor structure has a first resistance value with respect to a current flowing from the gate pad to the gate bus and a second resistance value with respect to a current flowing from the gate bus to the gate pad, the first resistance value being different from the second resistance value; The first and second resistance values ​​are set to improve balance of turn-on and turn-off switching behavior of the semiconductor device.

2. further comprising a wide bandgap semiconductor layer structure including an active area having a plurality of unit cell transistors; 2. The semiconductor device of claim 1, wherein said gate pad, said gate bus and said gate resistor structure are on an upper surface of said wide bandgap semiconductor layer structure.

3. The semiconductor device of claim 2 further comprising an internal dielectric pattern directly on the top surface of the gate resistor structure.

4. The gate resistor structure comprises: a plurality of first gate resistors; a plurality of first switches; a plurality of second gate resistors; a plurality of second switches; 4. The semiconductor device of claim 1, comprising:

5. 5. The semiconductor device of claim 4, wherein each of the plurality of first gate resistors and each first switch of the plurality of first switches is coupled between the gate pad and the gate finger, and each of the plurality of second gate resistors and each second switch of the plurality of second switches is coupled between the gate pad and the gate finger.

6. The semiconductor device of claim 5 , wherein each of the plurality of first switches includes a first diode and each of the plurality of second switches includes a second diode.

7. 7. The semiconductor device of claim 6, wherein each of the first diodes is implemented within a respective first gate resistor of the plurality of first gate resistors, and each of the second diodes is implemented within a respective second gate resistor of the plurality of second gate resistors.

8. 8. The semiconductor device of claim 7, wherein the first diode is configured to allow current to flow from the gate pad to the gate bus when forward biased, and the second diode is configured to allow current to flow from the gate bus to the gate pad when forward biased.

9. 5. The semiconductor device of claim 4, wherein each of the plurality of first gate resistors and each of the plurality of second gate resistors includes a first section of n-type semiconductor material, a second section of p-type semiconductor material, and a third section of p-type semiconductor material forming a p-n-p junction.

10. a plurality of first metal connectors each shorting the first section of each first gate resistor of the plurality of first gate resistors to the third section of each first gate resistor of the plurality of first gate resistors; a plurality of second metal connectors respectively shorting the first section of each second gate resistor of the plurality of second gate resistors to the second section of each second gate resistor of the plurality of second gate resistors; 10. The semiconductor device of claim 9, further comprising:

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