Semiconductor device and method for manufacturing the same

Abstract

To reduce the on-resistance of a semiconductor device.SOLUTION: A semiconductor device 10 includes a vertical transistor 48 and a semiconductor layer 12 in which a portion of the vertical transistor 48 is provided. The semiconductor layer 12 includes a first doped layer 62, a second doped layer 64 provided on the first doped layer 62, and a third doped layer 66 provided on the second doped layer 64. The n-type impurity concentration of the second doped layer 64 is higher than both the n-type impurity concentration of the first doped layer 62 and the n-type impurity concentration of the third doped layer 66.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] In recent years, trench-gate metal-oxide-semiconductor field effect transistors (MOSFETs) have been widely put to practical use. In a trench-gate MOSFET, a gate electrode is disposed in a trench provided in a semiconductor layer. Patent Document 1 discloses such a trench-gate MOSFET. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-129378

[0004] [overview] There is a demand for reducing the on-resistance of semiconductor devices.

[0005] A semiconductor device according to one embodiment of the present disclosure includes a vertical transistor and a semiconductor layer in which a portion of the vertical transistor is provided, the semiconductor layer including a first doped layer, a second doped layer provided on the first doped layer, and a third doped layer provided on the second doped layer, and a first conductivity type impurity concentration of the second doped layer is higher than both a first conductivity type impurity concentration of the first doped layer and a first conductivity type impurity concentration of the third doped layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of an example of an exemplary semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view of the semiconductor device taken along line F2-F2 in FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view showing an enlarged portion of the semiconductor device of FIG. [Figure 4] FIG. 4 is a graph showing the relationship between the position in the thickness direction of the semiconductor layer of the semiconductor device and the impurity concentration. [Figure 5] FIG. 5 is a graph showing the relationship between the concentration of impurities implanted into the first epitaxial layer of a semiconductor device and the breakdown voltage of the semiconductor device. [Figure 6] FIG. 6 is a graph showing the relationship between the concentration of impurities implanted into the first epitaxial layer and the on-resistance of the semiconductor device. [Figure 7] FIG. 7 is a schematic cross-sectional view illustrating an exemplary manufacturing process of a semiconductor device according to an embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 19] FIG. 19 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 20] FIG. 20 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 21] FIG. 21 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 22] FIG. 22 is a schematic cross-sectional view of a step subsequent to the step shown in FIG. [Figure 23] FIG. 23 is a graph showing the on-resistance of the semiconductor device of Sample 1. As shown in FIG. [Figure 24] FIG. 24 is a graph showing the on-resistance of the semiconductor device of Sample 2. As shown in FIG. [Figure 25] FIG. 25 is a graph showing the on-resistance of the semiconductor device of Sample 2 and the semiconductor device of the embodiment. [Figure 26] FIG. 26 is a schematic cross-sectional view of a semiconductor device according to a modified example.

[0007] [Detailed explanation] Hereinafter, several embodiments of semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The phrase "at least one" used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] As used in this disclosure, "the dimensions (width, length) of A are equal to the dimensions (width, length) of B" or "the dimensions (width, length) of A and the dimensions (width, length) of B are equal to each other" also includes a relationship in which the difference between the dimensions (width, length) of A and the dimensions (width, length) of B is, for example, within 10% of the dimensions (width, length) of A.

[0011] [Planar structure of semiconductor device] Referring to FIG. 1, a schematic planar structure of a semiconductor device 10 according to one embodiment will be described. Fig. 1 schematically shows the planar structure of a semiconductor device 10. In Fig. 1, the internal structure of the semiconductor device 10 is indicated by dashed lines. Note that the term "planar view" used in this disclosure refers to viewing the semiconductor device 10 in the Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in Fig. 1. Unless explicitly stated otherwise, "planar view" refers to viewing the semiconductor device 10 from above along the Z-axis.

[0012] 1, the semiconductor device 10 is, for example, a MISFET having a split-gate structure. The semiconductor device 10 includes a semiconductor layer 12, at least one gate trench 14 provided in the semiconductor layer 12, and an insulating layer 16 provided in the gate trench 14. In this embodiment, the semiconductor device 10 includes multiple gate trenches 14.

[0013] The semiconductor layer 12 can be made of, for example, silicon (Si). The semiconductor layer 12 includes a first surface 12A and a second surface 12B opposite to the first surface 12A (see FIG. 2 for both). The semiconductor layer 12 has a thickness in a direction (Z-axis direction) perpendicular to the first surface 12A. In other words, the Z-axis direction can be said to be the "thickness direction of the semiconductor layer 12."

[0014] Each gate trench 14 has an opening in the second surface 12B of the semiconductor layer 12. Each gate trench 14 extends in the Z-axis direction from the second surface 12B toward the first surface 12A. That is, each gate trench 14 has a depth in the Z-axis direction. It can also be said that each gate trench 14 is provided in the second surface 12B. Furthermore, each gate trench 14 extends in the Y-axis direction in a plan view. Therefore, each gate trench 14 has a width in the X-axis direction.

[0015] The multiple gate trenches 14 may be aligned in a stripe pattern. In one example, the multiple gate trenches 14 may be arranged at equal intervals in the X-axis direction in a plan view. A gate electrode 50 and a field plate electrode 52, which will be described later with reference to FIG. 2, may be disposed within the gate trench 14. Each gate trench 14 has a first end 14P and a second end 14Q as opposite ends in the Y-axis direction.

[0016] The semiconductor device 10 may further include a peripheral trench 18 provided in the semiconductor layer 12. In one example, the peripheral trench 18 is provided to be spaced apart from each gate trench 14 and to surround the plurality of gate trenches 14 in a plan view. In the example shown in FIG. 1 , the peripheral trench 18 has a rectangular frame shape in a plan view, with the X-axis direction being the short side direction and the Y-axis direction being the long side direction. A peripheral electrode (not shown) can be disposed within the peripheral trench 18, and is provided along the shape of the peripheral trench 18 in a plan view.

[0017] The second surface 12B of the semiconductor layer 12 is an n-type impurity-containing - a p-type region 20 containing p-type impurities; - and an n-type region 22 containing n-type impurities. +and a mold region 24. - The mold region 20 may surround the peripheral trench 18 in a plan view. - Type regions 22 and n + Both of the mold regions 24 may be surrounded by the peripheral trench 18 in plan view. - Type region 20 and p - Type region and n + The mold region 24 is separated by a peripheral trench 18 .

[0018] p - Type regions 22 and n + The mold regions 24 are arranged in the Y-axis direction. - A plurality of mold regions 22 (two in the example shown in FIG. 1) may be provided. - The type region 22 is, for example, n + They are provided in a distributed manner on both sides of the mold region 24 in the Y-axis direction. + The mold region 24 has two p - It is provided between the mold areas 22.

[0019] Each gate trench 14 is p - The first end 14P of the gate trench 14 can be disposed adjacent to the first end 14P of the gate trench 14. - The second end 14Q of the gate trench 14 can be adjacent to one of the p-type regions 22, and the second end 14Q of the gate trench 14 can be adjacent to one of the p-type regions 22. - The middle portion of the gate trench 14 may be adjacent to the remaining one of the n-type regions 22. + It may be adjacent to the mold area 24 .

[0020] The insulating layer 16 is formed on the n-type surface of the second surface 12B of the semiconductor layer 12. + The insulating layer 16 covers the region other than the mold region 24 and is embedded in each gate trench 14 and peripheral trench 18. The insulating layer 16 is a layer that insulates the gate electrode 50 and field plate electrode 52 from the semiconductor layer 12.

[0021] The semiconductor device 10 may further include a gate wiring 26 and a source wiring 28 provided on the insulating layer 16. Each of the gate wiring 26 and the source wiring 28 may be disposed so as to cover a portion of each gate trench 14 and a portion of the peripheral trench 18. The gate wiring 26 may be formed by connecting two p - The source wiring 28 can be disposed so as to at least partially overlap one of the two p-type regions 22. - The source wiring 28 can be disposed so as to at least partially overlap the other of the two type regions 22. The source wiring 28 can be disposed so as to be spaced apart from the gate wiring 26 and at least n + It may cover the entire mold area 24 .

[0022] The gate wiring 26 and the source wiring 28 can be made of a material containing at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a Cu alloy, and an Al alloy.

[0023] The semiconductor device 10 may further include a plurality of gate contact portions 30. Each gate contact portion 30 may connect a gate electrode 50 (see FIG. 2) disposed in each gate trench 14 to the gate wiring 26. The gate contact portion 30 may extend in the Z-axis direction to penetrate the insulating layer 16 located between the gate electrode 50 and the gate wiring 26. The gate contact portion 30 may be disposed in a region where the gate trench 14 and the gate wiring 26 overlap in a plan view. More specifically, the gate contact portion 30 may be disposed in a region where the first end 14P of the gate trench 14 and the gate wiring 26 overlap in a plan view.

[0024] The semiconductor device 10 may further include a plurality of source contact portions 32. Each source contact portion 32 may connect a field plate electrode 52 (see FIG. 2) disposed in each gate trench 14 to the source wiring 28. This electrically connects the field plate electrode 52 to the source wiring 28. The source contact portion 32 may extend in the Z-axis direction so as to penetrate the insulating layer 16 located between the field plate electrode 52 and the source wiring 28. Each source contact portion 32 may be disposed in a region where the gate trench 14 and the source wiring 28 overlap in a planar view. More specifically, each source contact portion 32 may be disposed in a region where the second end 14Q of the gate trench 14 and the source wiring 28 overlap in a planar view.

[0025] The semiconductor device 10 may further include one or more line contact portions 33 extending in the Y-axis direction in a plan view. The line contact portion 33 has at least n + The line contact portion 33 may extend in the Y-axis direction from one end of the gate region 24 to the other end of the gate trench 14. The line contact portion 33 may be disposed between two adjacent gate trenches 14. The line contact portion 33 may connect a body contact region 46 (see FIG. 2) formed in the semiconductor layer 12 to the source wiring 28. The line contact portion 33 may extend in the Z-axis direction to penetrate the semiconductor layer 12 and the insulating layer 16 located between the body contact region 46 and the source wiring 28.

[0026] The semiconductor device 10 may further include one or more contact portions 34 that connect a peripheral electrode (not shown) disposed in the peripheral trench 18 to the source wiring 28. The number and positions of the contact portions 34 are not limited to the example shown in FIG. 1 and can be changed as desired.

[0027] The gate contact portion 30, the source contact portion 32, and the contact portion 34 may be made of any metallic material. In one example, the contact portions 30, 32, 33, and 34 may be made of a material including at least one of tungsten (W), Ti, and titanium nitride (TiN).

[0028] [Cross-sectional structure of semiconductor device] The cross-sectional structure of the semiconductor device 10 will be described with reference to FIGS. Fig. 2 schematically shows a cross-sectional structure of the semiconductor device 10 taken along line F2-F2 in Fig. 1. Fig. 3 shows an enlarged schematic cross-sectional structure of one gate trench 14 and its surroundings in Fig. 2.

[0029] The semiconductor layer 12 may include a semiconductor substrate 36 that includes a first surface 12A of the semiconductor layer 12 and an epitaxial layer 38 that is disposed on the semiconductor substrate 36 and includes a second surface 12B of the semiconductor layer 12.

[0030] The semiconductor substrate 36 may be made of a material containing Si. In one example, the semiconductor substrate 36 may be an n-type Si substrate. The semiconductor substrate 36 may correspond to the drain region of the MISFET. In one example, the thickness TB of the semiconductor substrate 36 may be 50 μm or more and 100 μm or less. In another example, the n-type impurity concentration of the semiconductor substrate 36 may be 1×10 18 cm -3 More than 1×10 21 cm -3 In this embodiment, the n-type impurity concentration of the semiconductor substrate 36 can be 1×10 19 cm -3 More than 1×10 20 cm -3Hereinafter, the n-type will be referred to as the first conductivity type, and the p-type will be referred to as the second conductivity type. The n-type impurity may be, for example, phosphorus (P) or arsenic (As). The p-type impurity may be, for example, boron (B) or Al. In this embodiment, P is introduced into the semiconductor substrate 36 as the n-type impurity. In one example, the resistivity of the semiconductor substrate 36 can be set to 0.5 mΩ·cm or more and 5 mΩ·cm or less.

[0031] The epitaxial layer 38 may be a Si layer epitaxially grown on a Si substrate. The epitaxial layer 38 may include a drift region 40, a body region 42 provided on the drift region 40, and a source region 44 provided in a portion of the body region 42.

[0032] The body region 42 is a p-type impurity-containing - The p-type impurity concentration of the body region 42 may be, for example, 1×10 16 cm -3 More than 1×10 18 cm -3 The body region 42 may have a thickness of, for example, 0.5 μm or more and 1.5 μm or less.

[0033] The source region 44 has a higher n-type impurity concentration than the drift region 40. + The surface of the source region 44 (second surface 12B) may be an n-type region shown in FIG. + The source region 44 corresponds to the n-type region 24. The impurity concentration of the source region 44 may be higher than the impurity concentration of the body region 42. The n-type impurity concentration of the source region 44 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 It can be as follows:

[0034] In one example, the Y-direction dimension of the body contact region 46 is smaller than the Y-direction dimension of the gate trench 14. In one example, the Y-direction dimension of the body contact region 46 is equal to the Y-direction dimension of the source region 44.

[0035] The body contact region 46 is a p-type region containing p-type impurities. + The body contact region 46 may be a p-type region. The body contact region 46 is provided in a surface region of the body region 42. More specifically, the body contact region 46 is provided in the body region 42 between two gate trenches 14 that are adjacent to each other in the X-axis direction. The p-type impurity concentration of the body contact region 46 is higher than that of the body region 42. The p-type impurity concentration of the body contact region 46 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The detailed structure of the epitaxial layer 38 will be described later.

[0036] The semiconductor device 10 includes a vertical transistor 48. In this embodiment, the vertical transistor 48 may be a trench-gate MOSFET. The semiconductor layer 12 constitutes a part of the vertical transistor 48. The vertical transistor 48 may be provided in a region where the gate trench 14 is disposed. The semiconductor device 10 may further include a drain electrode 54 provided on the first surface 12A of the semiconductor layer 12. The drain electrode 54 may be made of at least one of Ti, Ni, Au, Ag, Cu, Al, a Cu alloy, and an Al alloy. The vertical transistor 48 is configured to enable control of the flow of electrons in the vertical direction (Z-axis direction) between the source wiring 28 and the drain electrode 54 via a channel formed in the semiconductor layer 12.

[0037] 3, each gate trench 14 includes a sidewall 14A and a bottom wall 14B. The sidewall 14A may extend along the Z-axis direction or may be inclined relative to the Z-axis direction. In one example, the sidewall 14A may be inclined relative to the Z-axis direction so that the width of the gate trench 14 decreases toward the bottom wall 14B of the gate trench 14. The bottom wall 14B does not necessarily have to be flat, and may be partially or entirely curved, for example.

[0038] Each gate trench 14 penetrates the body region 42 of the semiconductor layer 12 to reach the drift region 40. In one example, each gate trench 14 may have a depth of 2 μm or more and 10 μm or less. In this embodiment, the depth of each gate trench 14 is approximately 2 μm. Here, the depth of the gate trench 14 can be defined as the distance in the Z-axis direction from the second surface 12B of the semiconductor layer 12 to the bottom wall 14B of the gate trench 14 (or the deepest part of the gate trench 14 if the bottom wall 14B is curved).

[0039] A gate electrode 50 is buried in the gate trench 14 via an insulating layer 16. The gate electrode 50 may be electrically connected to a gate wiring 26. This allows a gate voltage to be applied to the gate electrode 50.

[0040] The gate electrode 50 is disposed closer to the body region 42 than the drift region 40 in the Z-axis direction. In one example, the gate electrode 50 may be disposed such that its bottom surface 50A is not closer to the bottom wall 14B of the gate trench 14 than the boundary 41 between the drift region 40 and the body region 42 in the Z-axis direction. In one example, the gate electrode 50 may be disposed such that its bottom surface 50A is at the same position in the Z-axis direction as the boundary 41 between the drift region 40 and the body region 42. In another example, the gate electrode 50 may be disposed such that its bottom surface 50A is closer to the second surface 12B of the semiconductor layer 12 than the boundary 41 between the drift region 40 and the body region 42.

[0041] The field plate electrode 52 is disposed within the gate trench 14, between the bottom surface 50A of the gate electrode 50 and the bottom wall 14B of the gate trench 14. The field plate electrode 52 can be set to the same potential as the source region 44. Applying a source voltage to the field plate electrode 52 alleviates electric field concentration within the gate trench 14, thereby improving the dielectric strength of the semiconductor device 10. In the cross-sectional view of FIG. 3, the field plate electrode 52 has a substantially rectangular shape with its length (longitudinal direction) in the Z-axis direction and its width (shortitudinal direction) in the X-axis direction. In the example shown in FIG. 3, the field plate electrode 52 has a tapered shape that narrows toward the bottom wall 14B of the gate trench 14. Both the gate electrode 50 and the field plate electrode 52 can be made of, for example, conductive polysilicon.

[0042] [Epitaxial layer] The detailed configuration of the epitaxial layer 38 in the semiconductor layer 12 will be described with reference to FIGS. 2 and 4 to 6. FIG. 4 is a graph showing the relationship between the position in the Z-axis direction of the semiconductor layer 12 and the n-type impurity concentration. FIG. 5 is a graph showing the relationship between the n-type impurity concentration of a second doped layer 64 (described later) and the breakdown voltage of the semiconductor device 10 when the thickness TE1 of the first epitaxial layer 38A (described later) is changed. FIG. 6 is a graph showing the relationship between the n-type impurity concentration of the second doped layer 64 and the on-resistance of the semiconductor device 10 when the thickness TE1 of the first epitaxial layer 38A is changed. Note that for the following explanation of the n-type impurity concentration, please refer to the graph in FIG. 4.

[0043] As shown in FIG. 2, the epitaxial layer 38 has a stacked structure of a first epitaxial layer 38A and a second epitaxial layer 38B. The first epitaxial layer 38A is provided on the semiconductor substrate 36. The second epitaxial layer 38B is provided on the first epitaxial layer 38A. The first epitaxial layer 38A includes a drift region 40. The second epitaxial layer 38B includes a portion of the drift region 40, a body region 42, and a source region 44. Each gate trench 14 is provided in the second epitaxial layer 38B. That is, the bottom wall 14B of each gate trench 14 is located closer to the second surface 12B of the semiconductor layer 12 than a boundary 38C between the first epitaxial layer 38A and the second epitaxial layer 38B. The thickness TE1 of the first epitaxial layer 38A is smaller than the thickness TE2 of the second epitaxial layer 38B.

[0044] The epitaxial layer 38 can be divided into a first doped layer 62, a second doped layer 64, and a third doped layer 66. The first doped layer 62 is provided on the semiconductor substrate 36. The second doped layer 64 is provided on the first doped layer 62. The third doped layer 66 is provided on the second doped layer 64. The first doped layer 62 is provided in the first epitaxial layer 38A. That is, the first epitaxial layer 38A includes the first doped layer 62. The second doped layer 64 is provided in both the first epitaxial layer 38A and the second epitaxial layer 38B, including a boundary 38C between the first epitaxial layer 38A and the second epitaxial layer 38B. That is, both the first epitaxial layer 38A and the second epitaxial layer 38B include the second doped layer 64. The third doped layer 66 is provided in the second epitaxial layer 38B. That is, the second epitaxial layer 38B includes the third doped layer 66.

[0045] The n-type impurity concentration of the first doped layer 62 decreases in the Z-axis direction toward the second doped layer 64. The n-type impurity concentration of the first doped layer 62 is 1×10 18 cm -3 More than 1×10 20 cm -3The first doped layer 62 is formed by the drift region 40. The thickness T1 of the first doped layer 62 may be less than the thickness T3 of the third doped layer 66.

[0046] The third doped layer 66 is a layer that includes the second surface 12B of the semiconductor layer 12. Therefore, the third doped layer 66 includes the source region 44. The third doped layer 66 also includes the body region 42. The n-type impurity concentration of the portion of the third doped layer 66 that is closer to the first doped layer 62 than the source region 44 is 1×10 16 cm -3 More than 1×10 17 cm -3 Therefore, it can be said that the n-type impurity concentration of the first doped layer 62 is higher than the n-type impurity concentration of the third doped layer 66.

[0047] The second doped layer 64 is arranged closer to the semiconductor substrate 36 than the center in the thickness direction (Z-axis direction) of the doped layer 68 (epitaxial layer 38) composed of the first doped layer 62, the second doped layer 64, and the third doped layer 66.

[0048] The second doped layer 64 contains As as an n-type impurity. The n-type impurity concentration of the second doped layer 64 is higher than both the n-type impurity concentration of the first doped layer 62 and the n-type impurity concentration of the third doped layer 66. The n-type impurity concentration of the second doped layer 64 increases from the first doped layer 62 side toward the center of the second doped layer 64 in the thickness direction (Z-axis direction) and also increases from the third doped layer 66 side toward the center of the second doped layer 64 in the Z-axis direction. In this embodiment, the profile of the n-type impurity concentration of the second doped layer 64 has a peak at the center of the second doped layer 64 in the Z-axis direction. As shown in FIG. 4 , the peak value of the n-type impurity concentration of the second doped layer 64 is higher than the n-type impurity concentration of the portion of the first doped layer 62 closer to the second doped layer 64 in the Z-axis direction. In another example, the peak value of the n-type impurity concentration of the second doped layer 64 may be lower than the n-type impurity concentration of an end portion of the first doped layer 62 closer to the semiconductor substrate 36 in the Z-axis direction. In this embodiment, the peak value of the n-type impurity concentration of the second doped layer 64 is higher than the n-type impurity concentration in a region closer to the second doped layer 64 than to the end portion of the first doped layer 62 closer to the semiconductor substrate 36 in the Z-axis direction. In addition, the n-type impurity concentration of the second doped layer 64 is lower than the n-type impurity concentration of the semiconductor substrate 36.

[0049] The n-type impurity concentration of the second doped layer 64 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The peak value of the n-type impurity concentration of the second doped layer 64 can be set to, for example, 1×10 19 cm -3 More than 1×10 20 cm -3 It can be as follows:

[0050] 2, the thickness T2 of the second doped layer 64 is thinner than the thickness T3 of the third doped layer 66. Also, in the example shown in FIG. 2, the thickness T2 of the second doped layer 64 is thinner than the thickness T1 of the first doped layer 62.

[0051] Each gate trench 14 is provided in the third doped layer 66. That is, each gate trench 14 is provided in the third doped layer 66 without reaching the second doped layer 64. Therefore, the bottom wall 14B of each gate trench 14 is located closer to the second surface 12B of the semiconductor layer 12 than the second doped layer 64. Therefore, both the gate electrode 50 and the field plate electrode 52 located in each gate trench 14 are located closer to the second surface 12B of the semiconductor layer 12 than the second doped layer 64.

[0052] It can be said that the insulating layer 16 is provided on the third doped layer 66. Since the insulating layer 16 is provided in each gate trench 14, it can be said that the insulating layer 16 is located closer to the second face 12B of the semiconductor layer 12 than the second doped layer 64.

[0053] 5 and 6, the thickness TE1 of the first epitaxial layer 38A is varied from 0.5 μm, 1.0 μm, 1.5 μm, 2.0 μm, 2.5 μm, and 3.0 μm. The horizontal axis in FIGS. 5 and 6 represents the concentration of n-type impurities doped into the first epitaxial layer 38A to form the second doped layer 64. In FIGS. 5 and 6, a graph G1 for a thickness TE1 of the first epitaxial layer 38A of 0.5 μm is shown by a solid line, a graph G2 for a thickness TE1 of 1.0 μm is shown by a dashed line, a graph G3 for a thickness TE1 of 1.5 μm is shown by a two-dot chain line, a graph G4 for a thickness TE1 of 2.0 μm is shown by a dashed dot line, a graph G5 for a thickness TE1 of 2.5 μm is shown by a thick solid line, and a graph G6 for a thickness TE1 of 3.0 μm is shown by a thick dashed line.

[0054] As can be seen from FIG. 5, when the thickness TE1 of the first epitaxial layer 38A is 0.5 μm, 1.0 μm, 1.5 μm, and 2.0 μm, the dielectric strength of the semiconductor device 10 is maintained at a constant value regardless of the dose. When the thickness TE1 of the first epitaxial layer 38A is 2.5 μm, the dielectric strength of the semiconductor device 10 decreases when the dose is relatively large. When the thickness TE1 of the first epitaxial layer 38A is 3.0 μm, the dielectric strength of the semiconductor device 10 decreases compared to when the thickness TE1 of the first epitaxial layer 38A is 2.5 μm or less. Furthermore, when the thickness TE1 of the first epitaxial layer 38A is 3.0 μm, the dielectric strength of the semiconductor device 10 decreases as the dose increases.

[0055] As described above, it can be seen that when the second doped layer 64 is excessively close to each gate trench 14, as in the case where the thickness TE1 of the first epitaxial layer 38A is 3.0 μm, the breakdown voltage of the semiconductor device 10 decreases. When the second doped layer 64 is far from each gate trench 14, the decrease in the breakdown voltage of the semiconductor device 10 decreases, and when the distance in the Z-axis direction between the second doped layer 64 and each gate trench 14 is equal to or greater than a predetermined value, the decrease in the breakdown voltage of the semiconductor device 10 becomes substantially zero.

[0056] As can be seen from FIG. 6, when the thickness TE1 of the first epitaxial layer 38A is 0.5 μm, 1.0 μm, or 1.5 μm, the on-resistance of the semiconductor device 10 does not change significantly depending on the thickness TE1 of the first epitaxial layer 38A. Furthermore, when the thickness TE1 of the first epitaxial layer 38A is 0.5 μm, 1.0 μm, or 1.5 μm, the on-resistance decreases as the dose increases. When the thickness TE1 of the first epitaxial layer 38A is 2.0 μm, the on-resistance is lower than when the thickness TE1 of the first epitaxial layer 38A is 1.5 μm or less. When the thickness TE1 of the first epitaxial layer 38A is 2.5 μm, the on-resistance is lower than when the thickness TE1 of the first epitaxial layer 38A is 2.0 μm. Furthermore, when the thickness TE1 of the first epitaxial layer 38A is 3.0 μm, the on-resistance is lower than when the thickness TE1 of the first epitaxial layer 38A is 2.5 μm or less. When the thickness TE1 of the first epitaxial layer 38A is 2.0 μm, 2.5 μm, and 3.0 μm, the on-resistance decreases as the dose increases.

[0057] Thus, the on-resistance decreases as the thickness TE1 of the first epitaxial layer 38A increases, and the on-resistance decreases as the dose increases. That is, as the second doped layer 64 approaches the semiconductor substrate 36 and the n-type impurity concentration of the second doped layer 64 increases, the on-resistance decreases.

[0058] 5 and 6, for example, if the thickness TE1 of the first epitaxial layer 38A is equal to or greater than 2 μm and less than 3 μm, it is possible to suppress a decrease in the breakdown voltage of the semiconductor device 10 and reduce the on-resistance. For example, if the thickness TE1 of the first epitaxial layer 38A is 2.5 μm and the dose amount is a value PA, it is possible to further suppress a decrease in the breakdown voltage of the semiconductor device 10 and further reduce the on-resistance.

[0059] [Method of manufacturing a semiconductor device] An example of a method for manufacturing the semiconductor device 10 will be described with reference to Figures 7 to 22. Figures 7 to 22 schematically show a cross-sectional structure taken along line F2-F2 in Figure 1.

[0060] 7, the method for manufacturing the semiconductor device 10 includes preparing a semiconductor substrate 36. The semiconductor substrate 36 may be, for example, a Si substrate. An n-type impurity is introduced into the semiconductor substrate 36. For example, P is used as the n-type impurity. Therefore, the semiconductor substrate 36 is made of a material containing P.

[0061] As shown in FIG. 8 , the method for manufacturing the semiconductor device 10 includes forming a first epitaxial layer 38A. The first epitaxial layer 38A is formed by epitaxial growth on the semiconductor substrate 36. In one example, the first epitaxial layer 38A is formed on the semiconductor substrate 36 by chemical vapor deposition (CVD). In this case, n-type impurities in the semiconductor substrate 36 diffuse into the first epitaxial layer 38A by thermal diffusion. As a result, a first doped layer 62 is formed in the first epitaxial layer 38A. In other words, the first epitaxial layer 38A includes the first doped layer 62.

[0062] 5 and 6, the first epitaxial layer 38A may be formed so that the thickness TE1 of the first epitaxial layer 38A is equal to or greater than 2 μm and less than 3 μm. In one example, the first epitaxial layer 38A may be formed so that the thickness TE1 of the first epitaxial layer 38A is 2.5 μm.

[0063] As shown in FIG. 9 , the method for manufacturing the semiconductor device 10 includes doping the first epitaxial layer 38A with an n-type impurity. For example, As is used as the n-type impurity. The n-type impurity is doped throughout the entire first epitaxial layer 38A in plan view, for example. As a result, a high-concentration region 70 is formed in the surface portion of the first epitaxial layer 38A. The high-concentration region 70 is a region that constitutes a part of the second doped layer 64. The n-type impurity concentration of the high-concentration region 70 is higher than the n-type impurity concentration of the first doped layer 62. More specifically, the n-type impurity concentration of the high-concentration region 70 is higher than the n-type impurity concentration of the region of the first doped layer 62 that is closer to the high-concentration region 70. Here, based on FIGS. 5 and 6 , the n-type impurity concentration with which the first epitaxial layer 38A is doped may be referred to as PA.

[0064] As shown in FIG. 10 , the method for manufacturing the semiconductor device 10 includes forming a second epitaxial layer 38B. The second epitaxial layer 38B is formed by epitaxial growth on the first epitaxial layer 38A. In one example, the second epitaxial layer 38B is formed on the first epitaxial layer 38A by a CVD method. In this case, the n-type impurities in the high-concentration region 70 (see FIG. 9 ) spread into the second epitaxial layer 38B by thermal diffusion. This results in the formation of a second doped layer 64 and a third doped layer 66. That is, the second doped layer 64 includes a boundary 38C between the first epitaxial layer 38A and the second epitaxial layer 38B, and is formed in both the first epitaxial layer 38A and the second epitaxial layer 38B. The third doped layer 66 is formed on the second doped layer 64. The n-type impurity concentration of the third doped layer 66 is lower than the n-type impurity concentration of the second doped layer 64. In other words, the n-type impurity concentration of the second doped layer 64 is higher than the n-type impurity concentration of the first doped layer 62 and the n-type impurity concentration of the third doped layer 66.

[0065] In this step, the second epitaxial layer 38B is formed to be thicker than the first epitaxial layer 38A. As a result, the second doped layer 64 is located closer to the semiconductor substrate 36 in the Z-axis direction than the center of the epitaxial layer 38 made up of the first epitaxial layer 38A and the second epitaxial layer 38B. Furthermore, the thickness T3 of the third doped layer 66 is thicker than the thickness T1 of the first doped layer 62. Through the above steps, the semiconductor layer 12 is formed.

[0066] As shown in FIG. 11 , the method for manufacturing the semiconductor device 10 includes forming a gate trench 14 in the second epitaxial layer 38B. In this step, the second epitaxial layer 38B (the second surface 12B of the semiconductor layer 12) is selectively removed by etching using a mask (not shown) with a predetermined pattern formed on the second epitaxial layer 38B. The gate trench 14 does not reach the first epitaxial layer 38A. More specifically, the gate trench 14 is formed in the third doped layer 66 of the second epitaxial layer 38B, but does not reach the second doped layer 64. The gate trench 14 may have a depth of 2 μm or more and 10 μm or less. In this embodiment, the depth of the gate trench 14 is approximately 2 μm.

[0067] 12, the method for manufacturing the semiconductor device 10 includes forming a first insulating layer 80 on the second epitaxial layer 38B. The first insulating layer 80 is formed along the second surface 12B of the semiconductor layer 12 and the sidewall 14A and bottom wall 14B of the gate trench 14. The first insulating layer 80 is SiO formed by, for example, thermal oxidation. In another example, the first insulating layer 80 may be formed by CVD.

[0068] 13 , the manufacturing method of the semiconductor device 10 includes forming a first conductive layer 82. The first conductive layer 82 is formed on a first insulating layer 80. As a result, the first conductive layer 82 is embedded in a recess space formed by the first insulating layer 80 in the gate trench 14. As a result, the gate trench 14 is embedded with the first insulating layer 80 and the first conductive layer 82. The first conductive layer 82 may be, for example, conductive polysilicon.

[0069] 14, the method for manufacturing semiconductor device 10 includes forming field plate electrode 52. Field plate electrode 52 is formed by removing a portion of first conductive layer 82 (see FIG. 13) by etching.

[0070] 15, the method for manufacturing semiconductor device 10 includes forming a second insulating layer 84. The second insulating layer 84 is formed so as to cover the first insulating layer 80 and the first conductive layer 82. That is, the second insulating layer 84 is embedded in the recess space formed by the first insulating layer 80 in the gate trench 14, thereby covering the field plate electrode 52. Like the first insulating layer 80, the second insulating layer 84 is formed of SiO. The second insulating layer 84 may be SiO formed by a CVD method or SiO formed by a thermal oxidation method.

[0071] 16, the method for manufacturing the semiconductor device 10 includes partially removing the first insulating layer 80 and the second insulating layer 84. This exposes the second surface 12B of the semiconductor layer 12. Furthermore, a portion of the sidewall 14A of the gate trench 14 is exposed. Meanwhile, the field plate electrode 52 is covered by the first insulating layer 80 and the second insulating layer 84.

[0072] 17, the method for manufacturing the semiconductor device 10 includes forming a third insulating layer 86 on the second epitaxial layer 38B. The third insulating layer 86 is formed to cover the second surface 12B of the semiconductor layer 12 exposed in FIG. 16 and the sidewall 14A of the gate trench 14. The third insulating layer 86 may be SiO formed by thermal oxidation, for example, or SiO formed by a CVD method.

[0073] 18, the method for manufacturing the semiconductor device 10 includes forming a second conductive layer 88 on the third insulating layer 86. The second conductive layer 88 may be formed of, for example, conductive polysilicon.

[0074] 19, the manufacturing method of the semiconductor device 10 includes forming the gate electrode 50. In this step, the gate electrode 50 is formed by etching an excess portion of the second conductive layer 88. As a result, the gate electrode 50 faces the sidewall 14A of the gate trench 14 with the third insulating layer 86 interposed therebetween.

[0075] 20 , the method for manufacturing the semiconductor device 10 includes forming a body region 42 and a source region 44 in the second epitaxial layer 38B. The body region 42 and the source region 44 are formed in a third doped layer 66 of the second epitaxial layer 38B. More specifically, after a p-type ion-implanted region is formed in the third doped layer 66, an n-type source region 44 is formed in a surface portion of the ion-implanted region. A region of the ion-implanted region closer to the second doped layer 64 than the source region 44 becomes the body region 42.

[0076] The body region 42 is formed so as to face at least a part of the gate electrode 50 with the third insulating layer 86 interposed therebetween. This allows a channel to be formed in the body region 42 when a gate voltage is applied to the gate electrode 50.

[0077] The n-type impurity concentration of the source region 44 is 1×10 19 cm -3 More than 1×10 21 cm-3 The p-type impurity concentration of the body region 42 can be set to 1×10 15 cm -3 More than 1×10 18 cm -3 It can be as follows:

[0078] 21 , the method for manufacturing the semiconductor device 10 includes forming a fourth insulating layer 90 on the third insulating layer 86 and the gate electrode 50. The fourth insulating layer 90 may be formed by, for example, a CVD method. Note that the first insulating layer 80, the second insulating layer 84, the third insulating layer 86, and the fourth insulating layer 90 can form the insulating layer 16.

[0079] Next, the method for manufacturing the semiconductor device 10 includes selectively etching a portion of the fourth insulating layer 90 and the second epitaxial layer 38B, thereby forming a line contact hole 92. The line contact hole 92 is formed between adjacent gate trenches 14.

[0080] Next, the manufacturing method of the semiconductor device 10 includes forming the body contact region 46. In this step, the body contact region 46 is formed by ion-implanting p-type impurities into the bottom of the line contact hole 92.

[0081] 22 , the manufacturing method of the semiconductor device 10 includes forming the line contact portion 33. In this step, the line contact portion 33 is formed so as to be embedded in the line contact hole 92. As a result, the line contact portion 33 comes into contact with the body contact region 46.

[0082] Next, the method for manufacturing the semiconductor device 10 includes forming a source wiring 28 on the insulating layer 16. Next, the method for manufacturing the semiconductor device 10 includes forming a drain electrode 54 on the first surface 12A of the semiconductor layer 12. Through the above steps, the vertical transistor 48 of the semiconductor device 10 is formed.

[0083] [Operation of the embodiment] The operation of the semiconductor device 10 of this embodiment will be described with reference to FIGS. 23 to 25 show the on-resistance of a semiconductor device, including the substrate resistance, protrusion resistance, resistance of the epitaxial layer, resistance of the gate trench (trench resistance), and resistance of the channel region (channel resistance). The substrate resistance indicates the resistance of the semiconductor substrate. The protrusion resistance indicates the resistance in a region where impurities are thermally diffused from the semiconductor substrate to the epitaxial layer when epitaxially grown on the semiconductor substrate. The resistance of the epitaxial layer indicates the resistance of a region of the epitaxial layer closer to the gate trench than the protrusion resistance region. The trench resistance indicates the resistance of the sidewalls and bottom wall of the gate trench closer to the semiconductor substrate than the body region. The channel resistance indicates the resistance of the body region.

[0084] Fig. 23 shows the resistances of the semiconductor device of Sample 1, which is a case where As is implanted into the semiconductor substrate as an impurity. Fig. 24 shows the resistances of the semiconductor device of Sample 2, which is a case where P is implanted into the semiconductor substrate as an impurity. Fig. 25 shows the resistances of the semiconductor device of Sample 2 and the resistances of the semiconductor device 10 of the embodiment. In Fig. 25, the resistances of the semiconductor device of Sample 2 are shown as open bars, and the resistances of the semiconductor device 10 of the embodiment are shown as hatched bars.

[0085] 23 and 24, by changing the impurity implanted into the semiconductor substrate from As to P, the substrate resistance decreases while the protrusion resistance increases. Furthermore, even when the impurity implanted into the semiconductor substrate is changed from As to P, the resistance of the epitaxial layer, the resistance of the gate trench, and the channel resistance do not change substantially.

[0086] In the semiconductor device 10 of the embodiment, P is implanted into the semiconductor substrate 36 as an impurity. The semiconductor layer 12 includes a first doped layer 62 closer to the semiconductor substrate 36, a third doped layer 66 closer to the gate trench 14, and a second doped layer 64 provided between the first doped layer 62 and the third doped layer 66 and having a higher n-type impurity concentration than the first doped layer 62 and the third doped layer 66. As a result, the second doped layer 64, which is a high-concentration region, is provided in a region where P is thermally diffused from the semiconductor substrate 36 to the epitaxial layer 38, thereby reducing the protrusion resistance, as shown in FIG. 25 . Therefore, the semiconductor device 10 of the embodiment can reduce the on-resistance compared to the semiconductor device of Sample 1 and the semiconductor device of Sample 2. Specifically, the semiconductor device 10 of the embodiment can reduce the on-resistance by approximately 10% compared to the semiconductor device of Sample 2.

[0087] [Effects of the embodiment] According to the semiconductor device 10 of this embodiment, the following effects can be obtained. (1) The semiconductor device 10 includes a vertical transistor 48 and a semiconductor layer 12 in which a portion of the vertical transistor 48 is provided. The semiconductor layer 12 includes a first doped layer 62, a second doped layer 64 provided on the first doped layer 62, and a third doped layer 66 provided on the second doped layer 64. The n-type impurity concentration of the second doped layer 64 is higher than both the n-type impurity concentration of the first doped layer 62 and the n-type impurity concentration of the third doped layer 66.

[0088] According to this configuration, the second doped layer 64 increases the n-type impurity concentration in a portion of the conduction path of the vertical transistor 48, thereby reducing the electrical resistance of the portion of the conduction path, thereby reducing the on-resistance of the semiconductor device 10.

[0089] (2) The n-type impurity concentration of the first doped layer 62 is higher than the n-type impurity concentration of the third doped layer 66 . According to this configuration, the first doped layer 62 increases the n-type impurity concentration in a portion of the conduction path of the vertical transistor 48, thereby reducing the electrical resistance of the portion of the conduction path. This reduces the on-resistance of the semiconductor device 10. Furthermore, the third doped layer 66 has a low n-type impurity concentration, which prevents a decrease in the breakdown voltage of the semiconductor device 10.

[0090] (3) The thickness T1 of the first doped layer 62 is smaller than the thickness T3 of the third doped layer 66. According to this configuration, the second doped layer 64 having a high concentration of n-type impurities is located away from the second surface 12B of the semiconductor layer 12, so that a decrease in the breakdown voltage of the semiconductor device 10 can be suppressed.

[0091] (4) The semiconductor substrate 36 is made of a material containing P. The second doped layer 64 contains As as an impurity. This configuration reduces the substrate resistance compared to when the semiconductor substrate is made of a material containing As. The second doped layer 64 also reduces elevated resistance. Furthermore, since the second doped layer 64 contains As as an impurity, the impurity in the second doped layer 64 is less susceptible to thermal diffusion than impurities such as P. Therefore, the impurity in the second doped layer 64 is less likely to diffuse into the third doped layer 66, preventing an increase in the n-type impurity concentration in the third doped layer 66. This prevents a decrease in the breakdown voltage of the semiconductor device 10.

[0092] (5) The semiconductor layer 12 includes a first surface 12A and a second surface 12B opposite the first surface 12A. The third doped layer 66 includes the second surface 12B. The semiconductor substrate 36 includes the first surface 12A. The second doped layer 64 is disposed closer to the semiconductor substrate 36 than the center in the Z-axis direction of a doped layer 68 composed of the first doped layer 62, the second doped layer 64, and the third doped layer 66.

[0093] According to this configuration, the second doped layer 64 having a high concentration of n-type impurities is positioned closer to the semiconductor substrate 36, in other words, the second doped layer 64 is away from the second surface 12B of the semiconductor layer 12, thereby suppressing a decrease in the dielectric strength voltage of the semiconductor device 10.

[0094] (6) The semiconductor device 10 includes a gate trench 14 provided in the third doped layer 66 and a gate electrode 50 disposed in the gate trench 14. The gate trench 14 is provided in the third doped layer 66 without reaching the second doped layer 64.

[0095] According to this configuration, the gate trench 14 is provided in the Z-axis direction away from the second doped layer 64 having a high concentration of n-type impurities, and is provided in the third doped layer 66 having a low concentration of n-type impurities, thereby suppressing a decrease in the dielectric strength voltage of the semiconductor device 10.

[0096] (7) A method for manufacturing the semiconductor device 10 includes preparing a semiconductor substrate 36, forming a first epitaxial layer 38A including a first doped layer 62 by epitaxial growth on the semiconductor substrate 36, doping the first epitaxial layer 38A with an n-type impurity, and forming a second epitaxial layer 38B including a third doped layer 66 by epitaxial growth on the first epitaxial layer 38A. In forming the second epitaxial layer 38B, a second doped layer 64 is formed across a boundary 38C between the first epitaxial layer 38A and the second epitaxial layer 38B. The n-type impurity concentration of the second doped layer 64 is higher than the n-type impurity concentration of the first doped layer 62 and the n-type impurity concentration of the third doped layer 66.

[0097] According to this configuration, the second doped layer 64 increases the n-type impurity concentration in a portion of the conduction path of the vertical transistor 48, thereby reducing the electrical resistance of the portion of the conduction path, thereby reducing the on-resistance of the semiconductor device 10.

[0098] <Example of change> The above embodiment can be modified as follows: Furthermore, the above embodiment and the following modifications can be combined with each other within the scope of technical compatibility.

[0099] The impurity implanted into the semiconductor substrate 36 is not limited to P. In one example, the impurity implanted into the semiconductor substrate 36 may be As. The impurity implanted into the semiconductor substrate 36 may be an impurity of the first conductivity type (n-type in the embodiment).

[0100] The thickness T1 of the first doped layer 62 can be changed arbitrarily. In one example, the thickness T1 of the first doped layer 62 may be equal to or greater than the thickness T3 of the third doped layer 66. The impurity implanted into the second doped layer 64 is not limited to As. The impurity implanted into the second doped layer 64 may be any impurity of the first conductivity type (n-type in the embodiment).

[0101] The thickness T2 of the second doped layer 64 can be changed as desired. For example, as shown in FIG. 26, the thickness T2 of the second doped layer 64 may be greater than the thickness T1 of the first doped layer 62. This can further reduce the rise resistance (see FIG. 25), thereby further reducing the on-resistance of the semiconductor device 10.

[0102] The position of the second doped layer 64 in the Z-axis direction can be changed as desired. For example, the second doped layer 64 may be located closer to the second surface 12B of the semiconductor layer 12 than the center in the Z-axis direction of the doped layer 68 made up of the first to third doped layers 62, 64, and 66.

[0103] The profile of the n-type impurity concentration of the second doped layer 64 can be changed as desired. In one example, the peak concentration of the n-type impurity concentration of the second doped layer 64 may be shifted from the center of the second doped layer 64 in the Z-axis direction.

[0104] Although the semiconductor layer 12 has been described as including the first epitaxial layer 38A and the second epitaxial layer 38B, this is not limitative. For example, the semiconductor layer 12 may be formed of a single epitaxial layer. Alternatively, for example, the semiconductor layer 12 may have a stacked structure of three or more epitaxial layers.

[0105] The configuration of the vertical transistor 48 of the semiconductor device 10 is not limited to a split gate structure and can be changed as desired. For example, the vertical transistor 48 may have a gate trench structure. That is, the field plate electrode 52 may be omitted from the semiconductor device 10. For example, the vertical transistor 48 may have a planar gate structure. That is, the gate trench 14 may be omitted from the semiconductor device 10.

[0106] One or more of the various examples described in the present disclosure may be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0107] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, the various structures according to this disclosure are not limited to the "up" and "down" in the Z-axis direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0108] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0109] [Appendix 1] a vertical transistor (48); a semiconductor layer (12) on which a portion of the vertical transistor (48) is provided; Equipped with The semiconductor layer (12) is a first doped layer (62); a second doped layer (64) provided on the first doped layer (62); a third doped layer (66) provided on the second doped layer (64); Including, The second doped layer (64) has a first conductivity type (n) impurity concentration higher than both the first conductivity type (n) impurity concentration of the first doped layer (62) and the third doped layer (66). A semiconductor device (10).

[0110] [Appendix 2] The first doped layer (62) has a higher impurity concentration of the first conductivity type (n) than the third doped layer (66). 2. The semiconductor device according to claim 1.

[0111] [Appendix 3] The thickness (T1) of the first doped layer (62) is less than the thickness (T3) of the third doped layer (66). 3. The semiconductor device according to claim 1 or 2.

[0112] [Appendix 4] The impurity concentration of the first conductivity type (n) in the first doped layer (62) decreases toward the second doped layer (64). 4. The semiconductor device according to any one of claims 1 to 3.

[0113] [Appendix 5] The impurity concentration of the first conductivity type (n) of the second doped layer (64) increases from the first doped layer (62) side toward the center of the thickness direction (Z) of the second doped layer (64), and also increases from the third doped layer (66) side toward the center of the thickness direction of the second doped layer (Z). 5. The semiconductor device according to any one of claims 1 to 4.

[0114] [Appendix 6] The first doped layer (62) has a first conductivity type (n) impurity concentration of 1×10 18 cm -3 More than 1×10 20 cm -3 is less than The second doped layer (64) has a first conductivity type (n) impurity concentration of 1×10 18 cm -3 More than 1×10 20 cm -3 is as follows: The third doped layer (66) has a first conductivity type (n) impurity concentration of 1×10 16 cm -3 More than 1×10 17 cm -3 is 6. The semiconductor device according to any one of claims 1 to 5.

[0115] [Appendix 7] The semiconductor layer (12) further includes a semiconductor substrate (36); The first doped layer (62) is disposed on the semiconductor substrate (36). 7. The semiconductor device according to any one of claims 1 to 6.

[0116] [Appendix 8] the semiconductor substrate (36) is made of a material containing phosphorus, The second doped layer (64) contains arsenic as an impurity. 8. The semiconductor device according to claim 7.

[0117] [Appendix 9] The semiconductor layer (12) includes a first surface (12A) and a second surface (12B) opposite to the first surface (12A), the third doped layer (66) includes the second surface (12B); the semiconductor substrate (36) includes the first surface (12A), The second doped layer (64) is disposed closer to the semiconductor substrate (36) than the center in the thickness direction (Z) of a doped layer (68) composed of the first doped layer (62), the second doped layer (64), and the third doped layer (66). 9. The semiconductor device according to claim 7 or 8.

[0118] [Appendix 10] The semiconductor layer (12) is a first epitaxial layer (38A) provided on the semiconductor substrate (36) and including the first doped layer (62); a second epitaxial layer (38B) provided on the first epitaxial layer (38A) and including the third doped layer (66); Including, The second doped layer (64) is provided on both the first epitaxial layer (38A) and the second epitaxial layer (38B), including the boundary (38C) between the first epitaxial layer (38A) and the second epitaxial layer (38B). 10. The semiconductor device according to any one of appendices 7 to 9.

[0119] [Appendix 11] a gate trench (14) provided in the third doped layer (66); a gate electrode (50) disposed within the gate trench (14); Contains 11. The semiconductor device according to any one of claims 1 to 10.

[0120] [Appendix 12] The gate trench (14) is provided in the third doped layer (66) without reaching the second doped layer (64). 12. The semiconductor device according to claim 11.

[0121] [Appendix 13] a field plate electrode (52) disposed within the gate trench (14); an insulating layer (16) provided on the third doped layer (66); a source wiring (28) provided on the insulating layer (16); Including, The field plate electrode (52) is electrically connected to the source wiring (28). 13. The semiconductor device according to claim 11 or 12.

[0122] [Appendix 14] Providing a semiconductor substrate (36); forming a first epitaxial layer (38A) including a first doped layer (62) by epitaxial growth on the semiconductor substrate (36); doping the first epitaxial layer (38A) with impurities of a first conductivity type (n); forming a second epitaxial layer (38B) including a third doped layer (66) by epitaxial growth on the first epitaxial layer (38A); Including, In forming the second epitaxial layer (38B), a second doped layer (64) is formed, the second doped layer (64) including a boundary (38C) between the first epitaxial layer (38A) and the second epitaxial layer (38B); The second doped layer (64) has a higher impurity concentration of the first conductivity type (n) than the first doped layer (62) and the third doped layer (66). A method for manufacturing a semiconductor device.

[0123] [Appendix 15] In forming the second epitaxial layer (38B), the second epitaxial layer (38B) is formed to be thicker than the first epitaxial layer (38A). 15. A method for manufacturing a semiconductor device according to claim 14.

[0124] [Appendix 16] In forming the first epitaxial layer (38A), the first epitaxial layer (38A) is formed so that the thickness of the first epitaxial layer (38A) is 2 μm or more and less than 3 μm. 16. A method for manufacturing a semiconductor device according to claim 14 or 15.

[0125] [Appendix 17] The semiconductor substrate (36) is made of a material containing phosphorus. A method for manufacturing a semiconductor device according to any one of appendices 14 to 16.

[0126] [Appendix 18] Doping the first epitaxial layer (38A) with the impurity includes doping the first epitaxial layer (38A) with arsenic as the impurity. A method for manufacturing a semiconductor device according to any one of appendices 14 to 17.

[0127] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0128] 10...Semiconductor device 12...Semiconductor layer 12A…Side 1 12B…Second side 14...Gate trench 14A…Side wall 14B…Bottom wall 14P...1st end 14Q...Second end 16...Insulating layer 18...Peripheral trench 20...n - type area 22...p- type area 24...n + type area 26...Gate wiring 28...Source wiring 30...Gate contact part 32...Source contact part 33...Line contact part 34...Contact part 36...Semiconductor substrate 38...Epitaxial layer 38A...First epitaxial layer 38B: Second epitaxial layer 38C…boundary 40...Drift region 41…boundary 42...Body area 44...Source region 46...Body contact area 48...Vertical transistor 50...Gate electrode 50A...Bottom 52...Field plate electrode 54...Drain electrode 62...First doped layer 64...Second doped layer 66...Third doped layer 68...Doped layer 70...High concentration area 80...First insulating layer 82...First conductive layer 84...Second insulating layer 86...Third insulating layer 88...Second conductive layer 90...Fourth insulating layer 92...Line contact hole TB: Semiconductor substrate thickness T1: Thickness of the first doped layer T2: Thickness of the second doped layer T3: Thickness of the third doped layer TE1: Thickness of the first epitaxial layer TE2: Thickness of the second epitaxial layer G1~G6...Graph

Claims

1. A vertical transistor; a semiconductor layer in which a part of the vertical transistor is provided; Equipped with The semiconductor layer is a first doped layer; and a second doped layer disposed on the first doped layer; a third doped layer disposed on the second doped layer; Including, The second doped layer has a first conductivity type impurity concentration higher than both the first conductivity type impurity concentration of the first doped layer and the first conductivity type impurity concentration of the third doped layer. Semiconductor device.

2. The first doped layer has a higher impurity concentration of the first conductivity type than the third doped layer. The semiconductor device according to claim 1 .

3. The thickness of the first doped layer is less than the thickness of the third doped layer. The semiconductor device according to claim 1 .

4. The concentration of the first conductivity type impurity in the first doped layer decreases toward the second doped layer. The semiconductor device according to claim 1 .

5. The impurity concentration of the first conductivity type of the second doped layer increases from the first doped layer side toward the center of the second doped layer in the thickness direction, and also increases from the third doped layer side toward the center of the second doped layer in the thickness direction. The semiconductor device according to claim 1 .

6. The first doped layer has a first conductivity type impurity concentration of 1×10 １８ cm －３ 1x10 or more ２０ cm －３ is less than The impurity concentration of the first conductivity type of the second doped layer is 1×10 １８ cm －３ 1x10 or more ２０ cm －３ is as follows: The impurity concentration of the first conductivity type of the third doped layer is 1×10 １６ cm －３ 1x10 or more １７ cm －３ is The semiconductor device according to claim 1 .

7. the semiconductor layer further comprises a semiconductor substrate; The first doped layer is disposed on the semiconductor substrate. The semiconductor device according to claim 1 .

8. the semiconductor substrate is made of a material containing phosphorus, The second doped layer contains arsenic as an impurity. The semiconductor device according to claim 7 .

9. the semiconductor layer includes a first surface and a second surface opposite the first surface; the third doped layer includes the second surface; the semiconductor substrate includes the first surface, The second doped layer is disposed closer to the semiconductor substrate than the center in the thickness direction of the doped layer composed of the first doped layer, the second doped layer, and the third doped layer. The semiconductor device according to claim 7 .

10. The semiconductor layer is a first epitaxial layer provided on the semiconductor substrate and including the first doped layer; a second epitaxial layer provided on the first epitaxial layer and including the third doped layer; Including, The second doped layer is provided in both the first epitaxial layer and the second epitaxial layer, including the boundary between the first epitaxial layer and the second epitaxial layer. The semiconductor device according to claim 7 .

11. a gate trench provided in the third doped layer; a gate electrode disposed in the gate trench; Contains The semiconductor device according to any one of claims 1 to 10.

12. The gate trench is provided in the third doped layer without reaching the second doped layer. The semiconductor device according to claim 11.

13. a field plate electrode disposed in the gate trench; an insulating layer disposed on the third doped layer; a source wiring provided on the insulating layer; Including, The field plate electrode is electrically connected to the source line. The semiconductor device according to claim 11.

14. Providing a semiconductor substrate; forming a first epitaxial layer including a first doped layer by epitaxial growth on the semiconductor substrate; doping the first epitaxial layer with impurities of a first conductivity type; forming a second epitaxial layer including a third doped layer by epitaxial growth on the first epitaxial layer; Including, forming the second epitaxial layer includes forming a second doped layer including a boundary between the first epitaxial layer and the second epitaxial layer; The second doped layer has a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the first doped layer and the first conductivity type impurity concentration of the third doped layer. A method for manufacturing a semiconductor device.

15. In forming the second epitaxial layer, the second epitaxial layer is formed to be thicker than the first epitaxial layer. The method for manufacturing a semiconductor device according to claim 14.

16. In forming the first epitaxial layer, the first epitaxial layer is formed so that the thickness of the first epitaxial layer is 2 μm or more and less than 3 μm. The method for manufacturing a semiconductor device according to claim 14.

17. The semiconductor substrate is made of a material containing phosphorus. The method for manufacturing a semiconductor device according to claim 14.

18. Doping the first epitaxial layer with the impurity includes doping the first epitaxial layer with arsenic as the impurity. The method for manufacturing a semiconductor device according to any one of claims 14 to 17.

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