Multilayer substrate
The multilayer substrate with varying thermal expansion coefficients in its insulating layers and a silicon-organic combination prevents cracking by managing stress dispersion, ensuring structural integrity.
Patent Information
- Application Number
- JP2024080004
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-05-16
- Publication Date
- 2025-11-28
AI Technical Summary
Glass substrates with multiple insulating layers are prone to cracking due to differences in thermal expansion coefficients between components mounted on the upper and lower layers.
A multilayer substrate design where at least two insulating layers have different thermal expansion coefficients, with the coefficients increasing or decreasing in a specific order to manage stress dispersion, and includes a silicon interposer with a lower expansion coefficient and an organic substrate with a higher expansion coefficient.
The design effectively reduces the difference in thermal expansion coefficients between layers, preventing cracks and enhancing structural integrity.
Smart Images
Figure 2025174018000001_ABST
Abstract
Description
[Technical Field]
[0001] The present invention relates to a multilayer substrate, and more particularly to a multilayer substrate in which a plurality of insulating layers containing a glass material are stacked. [Background technology]
[0002] Glass substrates are known in which multiple insulating layers containing glass materials are stacked. Generally, glass substrates have a lower coefficient of thermal expansion, higher flatness, and superior dimensional stability compared to organic substrates.
[0003] On the other hand, glass substrates are more brittle than organic substrates, so they require a bonding structure that prevents cracks from occurring during the manufacturing process.
[0004] Therefore, Patent Document 1 (JP 2022-135962 A) proposes a glass substrate in which multiple insulating layers including glass substrates are laminated via adhesive layers. The multilayer substrate disclosed in Patent Document 1 distributes internal stress among the adhesive layers, making it more advantageous in terms of crack prevention than glass substrates without adhesive layers. [Prior art documents] [Patent documents]
[0005] [Patent Document 1] Japanese Patent Publication No. 2022-135962 Summary of the Invention [Problem to be solved by the invention]
[0006] Incidentally, it is also envisioned that the glass substrate disclosed in Patent Document 1 may be mounted on another substrate, and another member having a different thermal expansion coefficient from that of the other substrate may be mounted on the glass substrate. As described above, the glass substrate is expected to have an adhesive layer to disperse internal stress, but cracks may occur due to the difference in the thermal expansion coefficient between the insulating layer of the glass substrate and the other substrate or member. In other words, there is a need to prevent cracks in a multilayer substrate even when the thermal expansion coefficients of the members provided on the upper and lower layers are different. [Means for solving the problem]
[0007] Therefore, the present invention has been made to solve the above-mentioned problems, and its object is to provide a multilayer substrate that can prevent the occurrence of cracks even when the thermal expansion coefficients of the components provided on the upper and lower layers are different.
[0008] In other words, the disclosed multilayer substrate is a multilayer substrate in which multiple insulating layers formed of at least a glass material are stacked, and the requirement is that at least two of the multiple insulating layers have different thermal expansion coefficients.
[0009] In addition, in the disclosed multilayer substrate, it is preferable that the multiple insulating layers are stacked in order so that the thermal expansion coefficient of each insulating layer from the second layer onwards is equal to or greater than the thermal expansion coefficient of the insulating layer immediately preceding it, as one moves towards the upper or lower layers.
[0010] Furthermore, it is preferable that the disclosed multilayer substrate has a first member containing a silicon material connected to the lower limit side of the thermal expansion coefficient, and a second member containing an organic material connected to the upper limit side of the thermal expansion coefficient.
[0011] Furthermore, it is preferable that the lower limit is 3 ppm / °C or more and 4 ppm / °C or less, and the upper limit is 10 ppm / °C or more and 17 ppm / °C or less. [Effects of the Invention]
[0012] According to the present invention, even if the thermal expansion coefficients of the components arranged on the upper and lower layers are different, by making at least two of the insulating layers of the glass substrate have different thermal expansion coefficients, the difference in the thermal expansion coefficient between each component and the insulating layer adjacent to each component can be reduced, and cracks in the multilayer substrate can be prevented. [Brief explanation of the drawings]
[0013] [Figure 1] FIG. 1 is a schematic cross-sectional view showing an example of a multilayer substrate. DETAILED DESCRIPTION OF THE INVENTION
[0014] The multilayer substrate 10 in each embodiment will be described in detail below with reference to the drawings. Fig. 1 is a schematic cross-sectional view showing an example of the multilayer substrate 10 in each embodiment. In all drawings used to explain each embodiment, components having the same function are given the same reference numerals, and repeated description thereof may be omitted.
[0015] Furthermore, in the multilayer substrate 10, for convenience, the "upper layer" or "lower layer" may be described based on the up-down direction in the drawing, but the upper and lower layers in the multilayer substrate 10 may not necessarily correspond to the actual up-down direction.
[0016] For convenience, the multilayer substrate 10 may be referred to as an "upper surface" or a "lower surface" based on the up-down direction in the drawings, but the upper and lower surfaces of the multilayer substrate 10 may not be aligned with the actual up-down direction. Furthermore, the multilayer substrate 10 may be referred to as a "side surface," but the side surface refers to the side surface in contrast to the above-mentioned upper and lower surfaces.
[0017] <Multilayer board> As shown in FIG. 1, the multilayer substrate 10 of this embodiment has a first member 30 as a silicon interposer mounted on the upper surface, and a second member 50 as an organic substrate mounted on the lower surface.
[0018] The multilayer substrate 10 is also formed by stacking a plurality of insulating layers 12 containing at least a glass material. More specifically, the multilayer substrate 10 is formed by stacking a plurality of insulating layers 12, each having a patterned metal layer 16 formed on its top and bottom surfaces, with adhesive layers 20 interposed between them. The metal layers 16 on the top and bottom surfaces of each insulating layer 12 are electrically connected to each other by vias 14, and the metal layers 16 of each insulating layer 12, separated by the adhesive layers 20, are electrically connected to each other by conductive paste 18.
[0019] <<Insulating layer>> The insulating layer 12 is usually flat. The average thickness of the insulating layer 12 may be, for example, from 10 μm to 200 μm, or from 30 μm to 100 μm, but is not particularly limited and can be appropriately selected depending on the purpose.
[0020] The insulating layers 12 may be made of, for example, quartz glass, synthetic quartz glass, borosilicate glass, or alkali-free glass, but are not limited to these and may be selected appropriately depending on the purpose. In particular, as will be described later, each layer of the insulating layers 12 may be made of a material having a thermal expansion coefficient that can prevent cracks in the multilayer substrate 10 as a whole.
[0021] <<Via>> As an example, the vias 14 can be formed by drilling through holes in the insulating layer 12 by laser processing. Types of laser processing include, but are not limited to, CO2 laser, YAG laser, etc., and can be appropriately selected depending on the purpose.
[0022] Furthermore, the size (opening diameter) of the through holes may be, for example, 50 μm or more and 500 μm or less, or 100 μm or more and 300 μm or less, but is not limited to these and can be selected appropriately depending on the purpose.
[0023] Further, as an example, via 14 is formed as a plated via in which plating is applied to the through hole, a paste via in which conductive paste is filled, or a hybrid via in which conductive paste is filled into a plating layer applied to the through hole, but is not limited to these and can be selected appropriately depending on the purpose.
[0024] <<Metal layer>> For example, the metal layer 16 is formed by plating the upper and lower surfaces of the insulating layer 12. The metal layer 16 is also formed into a predetermined pattern by etching.
[0025] The above-described plated via 14 and metal layer 16 may include a seed layer and a plating layer. The seed layer is formed by, for example, copper plating or nickel plating, and the plating layer is formed by, for example, copper plating.
[0026] <<adhesive layer>> The adhesive layer 20 is, for example, an insulating adhesive formed from a thermoplastic resin (for example, fluororesin, liquid crystal polymer (LCP), polyimide (PI), or polyphenylene ether (PPE)) and laminated with a separator (not shown), but is not limited to this and can be selected appropriately depending on the purpose.
[0027] <<Conductive paste>> The through holes in the adhesive layer 20 are filled with a conductive paste 18. As an example, the through holes can be formed by drilling through holes in the adhesive layer 20 (particularly, a semi-cured adhesive layer) by laser processing. Types of laser processing include, but are not limited to, CO2 laser and YAG laser, and can be appropriately selected depending on the purpose.
[0028] The size (opening diameter) of the through holes may be, for example, 50 μm or more and 500 μm or less, or 100 μm or more and 300 μm or less, but is not limited to these and can be selected appropriately depending on the purpose.
[0029] <<Thermal expansion coefficient>> Next, the thermal expansion coefficient of each insulating layer 12 in the multilayer substrate 10 will be described. Note that the multilayer substrate 10 in this embodiment has four insulating layers 12 stacked on top of each other, but this is not limited to this and the number of insulating layers can be selected appropriately depending on the purpose. More specifically, the insulating layers 12 may be two layers, or three or more layers. For ease of explanation, the insulating layers may be referred to as the first insulating layer 12a, the second insulating layer 12b, the third insulating layer 12c, and the fourth insulating layer 12d, in order from top to bottom.
[0030] At least two of the insulating layers 12 have different thermal expansion coefficients. Insulating layers 12 formed at least containing a glass material generally have a thermal expansion coefficient of approximately 1 ppm / °C or more and approximately 17 ppm / °C or less. For example, the thermal expansion coefficients of first insulating layer 12a and second insulating layer 12b can be 4 ppm / °C, and the thermal expansion coefficients of third insulating layer 12c and fourth insulating layer 12d can be 10 ppm / °C. This allows for dispersion of internal stress that would occur if the thermal expansion coefficients of the insulating layers 12 were uniform, even when a component containing a material with a thermal expansion coefficient of 3 ppm / °C (e.g., a silicon interposer) is connected to the top surface of multilayer substrate 10 and a component containing a material with a thermal expansion coefficient of 11 ppm / °C (e.g., a motherboard whose insulating layers are made of organic material) is connected to the bottom surface of multilayer substrate 10. This allows for prevention of cracks in multilayer substrate 10. The thermal expansion coefficients of the insulating layers are not limited to the above example and can be selected appropriately depending on the purpose.
[0031] As described above, the thermal expansion coefficient of each insulating layer 12 can be changed appropriately by selecting a material such as quartz glass, synthetic quartz glass, borosilicate glass, or alkali-free glass, or by changing the composition of these materials.
[0032] Furthermore, the multiple insulating layers 12 of the multilayer substrate 10 are preferably stacked in order so that the thermal expansion coefficient of each insulating layer 12 from the second layer onward is equal to or greater than that of the previous insulating layer, going upward or downward. For example, the thermal expansion coefficients of the first insulating layer 12a and the second insulating layer 12b may be 4 ppm / °C, the thermal expansion coefficient of the third insulating layer 12c may be 7 ppm / °C, and the thermal expansion coefficient of the fourth insulating layer 12d may be 10 ppm / °C. All of the insulating layers 12 may have different thermal expansion coefficients, or the multilayer substrate 10 may include two or more consecutive insulating layers 12 with the same thermal expansion coefficient. This further disperses internal stress that would occur if the thermal expansion coefficients of the insulating layers 12 were uniform, thereby preventing cracks in the multilayer substrate 10. The thermal expansion coefficients of the insulating layers are not limited to the above example and can be selected appropriately depending on the purpose.
[0033] Furthermore, it is preferable that the multilayer substrate 10 has a first member 30 containing a silicon material connected to the insulating layer 12 on the side of the lower limit of the thermal expansion coefficient, and a second member containing an organic material connected to the insulating layer 12 on the side of the upper limit of the thermal expansion coefficient. As an example, as shown in Fig. 1, the first member 30 as a silicon interposer is electrically connected to the top surface of the multilayer substrate 10 (i.e., the side of the first insulating layer 12a) via solder 28, and the second member 50 as an organic substrate (core substrate or motherboard) is connected to the bottom surface of the multilayer substrate 10 (i.e., the side of the fourth insulating layer 12d) via solder 62.
[0034] <<First component (silicon interposer)>> The first member 30 as a silicon interposer will be described in detail. As an example, as shown in FIG. 1, the silicon interposer 30 has a patterned metal layer 36 formed on the bottom surface and multiple insulating layers 32 containing silicon material stacked thereon. The metal layers 36 are electrically connected to each other by vias (particularly, plated vias) 34 formed inside the insulating layers 32. The silicon interposer 30 is not limited to the above example and can be appropriately selected depending on the purpose. That is, a known silicon interposer having multiple insulating layers 32 containing silicon material stacked thereon can be mounted on the top surface side of the multilayer substrate 10 (the insulating layer 12 side with the lower limit value of the thermal expansion coefficient).
[0035] Furthermore, an electronic component 40 is electrically connected to the upper surface side of the first member 30 via solder 42. Examples of the electronic component 40 include semiconductor elements such as a field programmable gate array (FPGA) chip and a silicon photonics chip.
[0036] The first member 30 is not limited to a silicon interposer, but may be a multi-layer substrate having the electronic components 40 therein and in which a plurality of insulating layers containing silicon material are stacked.
[0037] Furthermore, when the first member 30 is connected to the upper surface side of the multilayer substrate 10 (the insulating layer 12a side with the lower limit of the thermal expansion coefficient), the lower limit of the thermal expansion coefficient of the insulating layer 12 in the multilayer substrate 10 is preferably 3 ppm / °C or more and 4 ppm / °C or less. This reduces the difference in the thermal expansion coefficient between at least the first member 30 and the insulating layer 12 on the upper surface side of the multilayer substrate 10, thereby preventing cracks in the insulating layer 12. Furthermore, the lower limit of the thermal expansion coefficient of the insulating layer 12 in the multilayer substrate 10 is preferably equal to or greater than the thermal expansion coefficient of the insulating layer 32 of the first member 30.
[0038] <<Second component (organic substrate)>> The second member 50 as an organic substrate will be described in detail. As an example, as shown in FIG. 1, the organic substrate 50 has a plurality of insulating layers 52 containing organic materials laminated on top and bottom surfaces, with patterned metal layers 56 exposed or buried on the top and bottom surfaces. The metal layers 56 of each layer are electrically connected to each other by vias (particularly, conductive paste) 54 formed inside the insulating layers 52. The organic substrate 50 is not limited to the above example, and can be appropriately selected depending on the purpose. That is, a known organic substrate having a plurality of insulating layers 52 containing organic materials laminated on the bottom surface side (the insulating layer 12d side with the upper limit of the thermal expansion coefficient) of the multilayer substrate can be mounted.
[0039] Furthermore, the organic substrate 50 may be a core substrate or a motherboard. When the organic substrate 50 is a core substrate, a motherboard (not shown) may be further electrically connected to the lower surface side of the organic substrate 50 via solder (not shown).
[0040] Furthermore, when the second member 50 is connected to the lower surface side of the multilayer substrate 10 (the side of the insulating layer 12d with the upper limit of the thermal expansion coefficient), the upper limit of the thermal expansion coefficient of the insulating layer 12 in the multilayer substrate 10 is preferably 10 ppm / °C or more and 17 ppm / °C or less. This reduces the difference in the thermal expansion coefficient between at least the second member 50 and the insulating layer 12 on the lower surface side of the multilayer substrate 10, thereby preventing cracks in the insulating layer 12. Furthermore, the upper limit of the thermal expansion coefficient of the insulating layer 12 in the multilayer substrate 10 is preferably equal to or less than the thermal expansion coefficient of the insulating layer 52 of the second member 50.
[0041] The present invention is not limited to the above-described embodiment, and various modifications are possible without departing from the scope of the present invention. As an example, the multilayer substrate 10 may be an interposer, with a semiconductor element 40 mounted on the upper surface and a second member 50 mounted on the lower surface. In this case, the vias 14 of the multilayer substrate 10 may be formed so that the pitch becomes narrower toward the upper surface. [Explanation of symbols]
[0042] 10 Multilayer board 12 Insulating layer 14 Beer 16 metal layer 18 Conductive paste 20 Adhesive layer 30 First component (silicon interposer) 50 Second component (organic substrate)
Claims
1. A multilayer substrate in which a plurality of insulating layers formed by containing at least a glass material are stacked, At least two of the insulating layers have different thermal expansion coefficients. A multilayer substrate characterized by:
2. The plurality of insulating layers are laminated in order such that the thermal expansion coefficient of each insulating layer from the second layer onward becomes equal to or greater than the thermal expansion coefficient of the insulating layer immediately preceding it, going upward or downward.
2. The multilayer substrate according to claim 1,
3. a first member including a silicon material is connected to the lower limit side of the thermal expansion coefficient; A second member containing an organic material is connected to the upper limit value side of the thermal expansion coefficient.
3. The multilayer substrate according to claim 1 or 2, wherein:
4. The lower limit is 3 ppm / °C or more and 4 ppm / °C or less, and the upper limit is 10 ppm / °C or more and 17 ppm / °C or less.
4. The multilayer substrate according to claim 3,
Citation Information
Patent Citations
Circuit board, method for manufacturing circuit board and electronic equipment
JP2022135962A