Power storage device

Abstract

To provide a power storage device that performs deep discharge protection independently of over-discharge protection.SOLUTION: A power storage device 1 comprises a power storage element and a management device. The management device comprises a breaker 5 configured to interrupt a current path between the power storage element and connection terminals 4A and 4B for connecting the power storage element to an external device, a control unit, and an interruption control circuit 20. The control unit executes a first interruption process to interrupt the breaker 5, when a state in which a voltage of the power storage element is equal to or less than a predetermined first threshold value V1 continues for a predetermined first period T1. The interruption control circuit 20 executes a second interruption process to interrupt the breaker 5, when a state in which a voltage of the power storage element is equal to or less than a predetermined second threshold value V2, which is smaller than the first threshold value V1, continues for a predetermined second period T2. The second interruption process is executed independently of the first interruption process.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to an electricity storage device. [Background technology]

[0002] Conventionally, a power storage device has been developed that includes a power storage element, a switch provided in a current path from the power storage element to an external terminal, and a management unit that controls the on / off of the switch (for example, Patent Document 1 below). When the power storage element enters a low voltage state, the management unit shuts off the switch to protect the power storage element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-159930 Summary of the Invention [Problem to be solved by the invention]

[0004] The above-described energy storage device has two levels of low-voltage protection: over-discharge protection and deep-discharge protection. If the switch is tripped by over-discharge protection, the switch can be released when the voltage of the storage element exceeds a predetermined threshold due to charging. Deep-discharge protection is a protection that is implemented when the voltage of the storage element drops below the over-discharge protection level. If the storage element is repeatedly charged and discharged in the voltage range of the deep-discharge state, repeated copper elution and deposition may cause a short circuit between the electrodes. For this reason, if the switch is tripped by deep-discharge protection, the switch cannot be released even if the voltage of the storage element exceeds a predetermined threshold due to charging. In other words, the storage element cannot be reused.

[0005] Conventionally, deep discharge protection only functions after the over-discharge protection condition is met. Therefore, even if the voltage of the storage element suddenly drops to the voltage range of the deep discharge state, if the voltage recovers before the predetermined time required for over-discharge protection has elapsed, the deep discharge protection does not function. Therefore, even if the storage element has actually reached a state where it is difficult to reuse, the deep discharge protection may not function and the storage element may continue to be used.

[0006] The present disclosure was completed in light of the above circumstances, and has an object to provide an electricity storage device in which deep discharge protection is performed independently of over discharge protection. [Means for solving the problem]

[0007] The energy storage device of the present disclosure includes an energy storage element and a management device. The management device includes a circuit breaker that breaks a current path between the energy storage element and a connection terminal for connecting the energy storage element to an external device, a control unit, and a shutdown control circuit. The control unit executes a first shutdown process to shut off the circuit breaker when a state in which the voltage of the energy storage element is equal to or lower than a predetermined first threshold continues for a predetermined first period. The shutdown control circuit executes a second shutdown process to shut off the circuit breaker when a state in which the voltage of the energy storage element is equal to or lower than a predetermined second threshold that is lower than the first threshold continues for a predetermined second period. The second shutdown process is executed independently of the first shutdown process. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to provide an electricity storage device in which deep-discharge protection is performed independently of over-discharge protection. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 2 is a diagram illustrating an electrical configuration of the power storage device according to the embodiment. [Figure 2] FIG. 2 is a diagram illustrating an electrical configuration of a shutoff control circuit. [Figure 3] FIG. 2 is a circuit diagram of a low-voltage detection circuit. [Figure 4]FIG. 10 is an explanatory diagram illustrating the operation of the low-voltage detection circuit when the cell voltage is higher than a second threshold value. [Figure 5] FIG. 10 is an explanatory diagram illustrating the operation of the low-voltage detection circuit when the cell voltage is equal to or lower than the second threshold value. [Figure 6] FIG. 2 is a circuit diagram of a delay circuit and a discharge circuit. DETAILED DESCRIPTION OF THE INVENTION

[0010] (Outline of this embodiment) (1) A power storage device according to the present disclosure includes a power storage element and a management device. The management device includes a circuit breaker that breaks a current path between the power storage element and a connection terminal for connecting the power storage element to an external device, a control unit, and a shutdown control circuit. The control unit executes a first shutdown process to shut off the circuit breaker when a state in which the voltage of the power storage element is equal to or lower than a predetermined first threshold continues for a predetermined first period. The shutdown control circuit executes a second shutdown process to shut off the circuit breaker when a state in which the voltage of the power storage element is equal to or lower than a predetermined second threshold that is lower than the first threshold continues for a predetermined second period. The second shutdown process is executed independently of the first shutdown process.

[0011] According to this configuration, by providing the shutdown control circuit, the second shutdown process can be executed independently of the first shutdown process, thereby improving the safety of the power storage device compared to conventional configurations.

[0012] (2) In the storage device of (1) above, it is preferable that the management device includes a discharge circuit arranged between the gate and source of the circuit breaker, and in the second circuit breaker processing, the circuit breaker control circuit turns off a switch provided on the gate line of the circuit breaker and makes the discharge circuit conductive.

[0013] With this configuration, the charge between the gate and source of the circuit breaker is discharged by the discharge circuit, thereby shortening the time required for the circuit breaker to open, and as a result, thermal damage to the circuit breaker can be suppressed.

[0014] <Embodiment> An embodiment of the present disclosure will be described with reference to Figures 1 to 6. A power storage device 1 according to this embodiment is mounted on, for example, a motorcycle.

[0015] As shown in FIG. 1, the energy storage device 1 includes a battery pack 2 and a battery management system (hereinafter referred to as BMS) 3. The positive terminal of the energy storage device 1 is a connection terminal 4A, and the negative terminal of the energy storage device 1 is a connection terminal 4B. The battery pack 2 is an example of an energy storage element, and is configured by connecting multiple cells C in series. Each cell C is a rechargeable secondary battery, such as a lithium-ion battery. The battery pack 2 of this embodiment has four cells C. The battery pack may have only one cell, or two, three, five or more cells connected in series.

[0016] The BMS 3 is an example of a management device and includes a circuit breaker 5, a protection IC 6 (an example of a control unit), an internal power supply circuit 7, a shutdown control circuit 20, a control circuit 11, a reuse prohibition latch circuit 14, a recovery circuit 12, a discharge circuit 50, and the like.

[0017] The protection IC 6 has a central processing unit (hereinafter referred to as CPU) and memory. Various programs for controlling the operation of the BMS 3 are stored in the memory, and the CPU controls each part of the BMS 3 according to the programs read from the memory. The memory includes RAM and ROM. Note that the media on which the various programs are stored may be non-volatile memories such as a CD-ROM, a hard disk drive, or a flash memory, in addition to RAM.

[0018] The protection IC 6 monitors the state of each cell C. The monitored items are the cell voltage V cell , the total voltage, current, temperature, etc. of the battery pack 2.

[0019] The internal power supply circuit 7 is a power supply circuit for the protection IC 6 and the shutdown control circuit 20. The internal power supply circuit 7 includes a first power supply line L1, a second power supply line L2, a separation circuit 7A, and a backup circuit 7B. The first power supply line L1 is connected to the positive electrode of the battery pack 2. The second power supply line L2 is connected to the first power supply line L1 via the separation circuit 7A. The separation circuit 7A has the function of separating the two power supply lines L1 and L2 when the voltage of the battery pack 2 drops. The backup circuit 7B is a circuit that maintains the voltage of the second power supply line L2 for a predetermined time when the voltage of the battery pack 2 drops. The backup circuit 7B is composed of, for example, multiple capacitors.

[0020] The circuit breaker 5 is provided in the current path between the battery pack 2 and the connection terminal 4B. The circuit breaker 5 includes a discharge cutoff unit 5A and a charge cutoff unit 5B. The discharge cutoff unit 5A cuts off the current (discharge current) that flows when the battery pack 2 supplies power to a load or the like. The charge cutoff unit 5B cuts off the current (charge current) that flows when the battery pack 2 is charged by a charger or the like.

[0021] The discharge cutoff section 5A and the charge cutoff section 5B are configured by semiconductor switches such as FETs, etc. The discharge cutoff section 5A and the charge cutoff section 5B may be, for example, N-channel MOSFETs.

[0022] The gate of the discharge cutoff unit 5A and the gate of the charge cutoff unit 5B are connected to a second power supply line L2 via a gate line L3. A first switch 8A and a second switch 8B are provided on the gate line L3.

[0023] A gate source resistor 9 is connected to the gate line L3 connected to the gate of the discharge cutoff unit 5A. A gate source resistor 10 is connected to the gate line L3 connected to the gate of the charge cutoff unit 5B. The gate source resistors 9 and 10 are installed to prevent the discharge cutoff unit 5A and the charge cutoff unit 5B from floating and causing the circuit to malfunction.

[0024] When the first switch 8A and the second switch 8B are both in the closed (on) state, the voltage VDD1 (the potential of the second power supply line L2) is applied to the gates of the discharge cutoff unit 5A and the charge cutoff unit 5B from the internal power supply circuit 7, and the discharge cutoff unit 5A and the charge cutoff unit 5B are in the closed state. In other words, the discharge cutoff unit 5A and the charge cutoff unit 5B are released from cutoff.

[0025] When either the first switch 8A or the second switch 8B is in the open (off) state, no voltage is applied to the gates of the discharge cutoff unit 5A and the charge cutoff unit 5B, and the discharge cutoff unit 5A and the charge cutoff unit 5B are in the open state, i.e., the discharge cutoff unit 5A and the charge cutoff unit 5B are cut off.

[0026] (Over discharge protection) In this embodiment, the protection IC 6 detects the voltage V of each cell C. cell When the state where the voltage VV is equal to or less than a predetermined first threshold V1 continues for a predetermined first period T1, the protection IC 6 executes a first shutoff process to shut off the circuit breaker 5. Specifically, the protection IC 6 outputs a HIGH-level shutoff signal S1 to the control circuit 11, thereby switching the first switch 8A from closed to open. The first threshold V1 is set based on the voltage value when the cell C is in an over-discharge state. In other words, the first shutoff process is a process for over-discharge protection.

[0027] Even if the circuit breaker 5 is tripped by the first tripping process, the voltage V of each cell C is maintained by charging the battery pack 2. cell When the voltage V1 recovers to or exceeds the first threshold V1, the battery pack 2 is allowed to be used. Upon detecting external charging, the recovery circuit 12 returns the first switch 8A from open to closed, thereby enabling the battery pack 2 to be charged and reused.

[0028] (conventional deep discharge protection) Conventional deep-discharge protection is performed when both the over-discharge protection condition and the deep-discharge protection condition are met. Conventional deep-discharge protection is also included in this embodiment, and will be described with reference to FIG. 1. When the over-discharge protection condition is met, the protection IC 6 inputs the above-mentioned HIGH-level shutoff signal S1 to the AND circuit 13. Furthermore, when the deep-discharge protection condition is met, the protection IC 6 inputs a separate HIGH-level shutoff signal S2 to the AND circuit 13. When both the over-discharge protection condition and the deep-discharge protection condition are met, the AND circuit 13 inputs a HIGH-level shutoff signal S3 to the reuse prohibition latch circuit 14, and the second switch 8B opens.

[0029] The second switch 8B is not provided with a recovery circuit, so once the second switch 8B is opened, the battery pack 2 cannot be charged or reused.

[0030] According to conventional deep discharge protection, the voltage V of cell C cell Even if the voltage V drops suddenly to the voltage region of the deep discharge state, the voltage V cell When the voltage V1 recovers to a value greater than the first threshold V1, the deep-discharge protection does not function. Therefore, even if the cell C is in a state where it is difficult to reuse it, the deep-discharge protection does not function, and the battery pack 2 may continue to be used.

[0031] (Deep discharge protection in this embodiment) In order to address the above-mentioned issues, this embodiment is provided with a shutoff control circuit 20. The shutoff control circuit 20 controls the voltage V of each cell C. cell When the state where the voltage VV is equal to or less than a predetermined second threshold V2, which is lower than the first threshold V1, continues for a predetermined second period T2, the shutdown control circuit 20 executes a second shutdown process to shut off the circuit breaker 5. Specifically, the shutdown control circuit 20 switches the second switch 8B from closed to open by inputting a HIGH-level shutdown signal S4 to the reuse prohibition latch circuit 14. The second threshold V2 is set based on the voltage value when the cell C is in a deep-discharge state. In other words, the second shutdown process is a process for deep-discharge protection.

[0032] The second cutoff process is executed regardless of the presence or absence of the cutoff signal S1 from the protection IC 6. That is, the second cutoff process is executed independently of the first cutoff process. Therefore, according to the configuration of this embodiment, the deep discharge state can be detected more accurately than in the conventional configuration, and the safety of the energy storage device 1 can be further improved.

[0033] During the second period T2, the voltage V of the cell C is cell The second period T2 is set taking into consideration the time during which the power storage device 1 may decrease. For example, if the power storage device 1 has a function for starting an engine, the second period T2 is preferably set to be longer than the time required for cranking the engine. This prevents the second shutoff process from prohibiting reuse of the power storage device 1 during cranking.

[0034] Furthermore, a discharge circuit 50 may be provided on the gate line L3, and the trip control circuit 20 may input a high-level trip signal S5 to the discharge circuit 50 to make the discharge circuit 50 conductive when inputting a high-level trip signal S4 to the reuse prohibition latch circuit 14. With this configuration, the charge accumulated on the gate line L3 can be discharged, thereby increasing the tripping speed of the circuit breaker 5. Therefore, thermal damage to the circuit breaker 5 can be suppressed.

[0035] From the viewpoint of cost etc., it is preferable that the shutdown control circuit 20 is configured by hardware, unlike the protection IC 6. An example of the configuration and operation of the shutdown control circuit 20 will be described below.

[0036] (Configuration of shutoff control circuit 20) As shown in Fig. 2, the cutoff control circuit 20 of this embodiment includes a low-voltage detection circuit 30 and a delay circuit 40. The low-voltage detection circuit 30 is connected to the positive and negative electrodes of each cell C and the second power supply line L2. The low-voltage detection circuit 30 detects the voltage V of each cell C. cellbecomes equal to or less than the second threshold V2 (including negative values), a shutdown signal S6 is input to the delay circuit 40. The number of low voltage detection circuits 30 provided is the same as the number of cells C. The output terminals 30D (see FIG. 3) of the multiple low voltage detection circuits 30 are connected to each other.

[0037] The low-voltage detection circuit 30 can be configured, for example, as shown in FIG. 3. The low-voltage detection circuit 30 includes a first terminal 30A connected to the positive electrode of cell C, a second terminal 30B connected to the negative electrode of cell C, a power supply terminal 30C connected to the second power supply line L2, an output terminal 30D, N-channel FETs 31 and 32, and resistors 33, 34, and 35. The first terminal 30A is connected to the gate of FET 31. The second terminal 30B branches into two terminals connected to the sources of FET 31 and FET 32. The drain of FET 31 is connected to the gate of FET 32. Resistors 33 and 34 are connected in series between the drain of FET 32 and the power supply terminal 30C. The resistor 34 is disposed between the resistor 33 and FET 32. The output terminal 30D is connected between the resistors 33 and 34. The gate of FET 32 is connected to the power supply terminal 30C via resistor 35.

[0038] As shown in Figure 4, the voltage V of cell C cell is greater than the second threshold V2, i.e., when the gate voltage of FET 31 is greater than the second threshold V2, FET 31 is turned on. When FET 31 is turned on, the gate and source of FET 32 are at the same potential, so FET 32 is turned off. Because FET 32 is turned off, voltage VDD1 is applied to output terminal 30D, and a HIGH-level signal is input to delay circuit 40.

[0039] As shown in Figure 5, the voltage V of cell C cellis equal to or less than the second threshold V2, i.e., when the gate voltage of FET 31 is equal to or less than the second threshold V2, FET 31 is turned off. Therefore, the gate-source voltage of FET 32 is VDD1 minus the potential of second terminal 30B (negative electrode of cell C), and FET 32 is turned on. When FET 32 is turned on, a current flows between power supply terminal 30C and second terminal 30B (indicated by the two-dot chain arrow), and a voltage corresponding to the ratio of the resistance values ​​of resistors 33 and 34 is applied to output terminal 30D. The resistance value of resistor 33 is set to be larger than that of resistor 34, and a low-level shutoff signal S6 is input to delay circuit 40.

[0040] Since the output terminals 30D of the multiple low-voltage detection circuits 30 are connected to each other, when the output terminal 30D of at least one of the multiple low-voltage detection circuits 30 is at a low level (as shown in FIG. 5), the output terminals 30D of the other low-voltage detection circuits 30 also become low. Therefore, when the output terminal 30D of at least one low-voltage detection circuit 30 is at a low level, a low-level cutoff signal S6 is input to the delay circuit 40.

[0041] To summarize the above, the voltage V of at least one cell C cell is equal to or less than the second threshold V2, a low-level interruption signal S6 is input to the delay circuit 40. In other cases, that is, when the voltages V of all the cells C are cell is greater than the second threshold V2, a HIGH level signal is input to the delay circuit 40.

[0042] As shown in FIG. 2, when a LOW level shutdown signal S6 is input from the low voltage detection circuit 30, the delay circuit 40 inputs HIGH level shutdown signals S4 and S5 to the reuse prohibition latch circuit 14 and the discharge circuit 50, respectively, after the second period T2 has elapsed.

[0043] The delay circuit 40 is configured, for example, as shown in FIG. 6. The delay circuit 40 includes an input terminal 40A connected to the output terminal 30D of the low-voltage detection circuit 30, a power supply terminal 40B connected to the second power supply line L2, a first output terminal 40C, a second output terminal 40D, a P-channel FET 41, a capacitor 42, and resistors 43, 44, 45, and 46. The input terminal 40A is connected to the gate of the FET 41. The source of the FET 41 is connected to the power supply terminal 40B via the resistor 43. The drain of the FET 41 is connected to the capacitor 42 via the resistor 44. The drain of the FET 41 is connected to GND via the resistor 45. The capacitor 42 is connected to the first output terminal 40C via the resistor 46. The first output terminal 40C is connected to the reuse prohibition latch circuit 14. The capacitor 42 is connected to the second output terminal 40D. The second output terminal 40D is connected to an FET 51 of a discharge circuit 50, which will be described later.

[0044] When a low-level shutdown signal S6 is input to the input terminal 40A, the FET 41 is turned on. When the FET 41 is turned on, a voltage VDD1 is applied from the second power supply line L2. Due to the output transient response of the capacitor 42 (the time constant of the capacitor 42), the voltage VDD1 is applied to the first output terminal 40C and the second output terminal 40D after a second period T2 has elapsed since the FET 41 was turned on. As a result, high-level shutdown signals S4 and S5 are input to the reuse prohibition latch circuit 14 and the discharge circuit 50, respectively.

[0045] When a HIGH level shutoff signal S4 is input to the reuse prohibition latch circuit 14, as described above, the second switch 8B is turned off, the gate voltage applied to the circuit breaker 5 becomes zero, and the circuit breaker 5 is shut off.

[0046] The discharge circuit 50 includes, for example, an N-channel FET 51 and resistors 52 and 53. The sum of the resistance values ​​of the resistors 52 and 53 is set to be smaller than the resistance value of the gate-source resistors 9 and 10. The second output terminal 40D of the delay circuit 40 is connected to the gate of the FET 51. When the delay circuit 40 outputs a high-level interruption signal S5, the FET 51 is turned on. This allows the charge accumulated in the gate line L3 to be discharged, thereby increasing the interruption speed of the circuit breaker 5.

[0047] When a HIGH level signal is input to the input terminal 40A, the FET 41 is turned off. In this case, the first output terminal 40C and the second output terminal 40D are connected to GND. Therefore, the reuse prohibition latch circuit 14 is not driven, and the discharge circuit 50 is non-conductive.

[0048] To summarize, the voltage V of at least one cell C cell If the state where V is equal to or less than the second threshold V2 continues for a second period T2, that is, if it is estimated that at least one cell C is in a deep discharge state, the second switch 8B is turned off by the reuse prohibition latch circuit 14, thereby tripping the circuit breaker 5. Furthermore, when the second switch 8B is turned off, the charge on the gate line L3 is discharged through the discharge circuit 50, so that the circuit breaker 5 is quickly tripped.

[0049] The second cutoff process is performed by cutting off the voltage V of at least one cell C. cell is a negative value continues for the second period T2, so that the circuit breaker 5 is also tripped when the cell C is inverted. The protection IC 6 used in the energy storage device 1 may not be rated to a negative potential, and deep discharge protection using a conventional protection IC 6 may have difficulty in controlling the circuit breaker 5 to trip when the cell C is inverted. According to this embodiment, the circuit breaker 5 can be controlled to trip even when the cell C is inverted by using the circuit breaker control circuit 20 configured with simple hardware.

[0050] (Effects of the embodiment) The energy storage device 1 according to this embodiment includes a cutoff control circuit 20 separate from the protection IC 6 that performs over-discharge protection (first cutoff process), and the cutoff control circuit 20 performs deep-discharge protection (second cutoff process) independently of the over-discharge protection. This configuration makes it possible to detect the deep discharge state of cell C and polarity reversal of cell C, which were difficult to detect with conventional configurations, and to prohibit reuse of the energy storage device 1. This improves the safety of the energy storage device 1.

[0051] In this embodiment, a discharge circuit 50 is provided between the gate and source of the circuit breaker 5, and in the second circuit breaking process, the circuit breaker control circuit 20 turns off the second switch 8B provided on the gate line L3 of the circuit breaker 5 and makes the discharge circuit 50 conductive. With this configuration, the charge between the gate and source of the circuit breaker 5 is discharged by the discharge circuit 50, thereby shortening the time required for the circuit breaker 5 to break. As a result, thermal damage to the circuit breaker 5 can be suppressed.

[0052] <Other embodiments> The present disclosure is not limited to the embodiments described above and illustrated in the drawings, but is intended to include all modifications within the scope and meaning equivalent to the claims. The technical scope of the present disclosure also includes, for example, the following embodiments.

[0053] Although the power storage device 1 in the embodiment is for a motorcycle, the power storage device may be for a four-wheeled motor vehicle such as an automobile, or may be used for other mobile objects.

[0054] In the embodiment, the circuit breaker 5 includes the discharge cutoff section 5A and the charge cutoff section 5B, but the circuit breaker may include only the discharge cutoff section, and the charge cutoff section may be omitted.

[0055] In the embodiment, the configuration is such that conventional deep-discharge protection is performed, i.e., deep-discharge protection is also performed by the protection IC 6 via the AND circuit 13, but the storage device of the present disclosure does not need to adopt deep-discharge protection by the control unit. [Explanation of symbols]

[0056] 1: Energy storage device 2: Battery pack (energy storage element) 3:BMS (management device) 4A, 4B: Connection terminals 5: Circuit breaker 5A: Discharge circuit breaker 5B: Charge circuit breaker 6: Protection IC (control unit) 20:Shutdown control circuit 50:Discharge circuit

Claims

1. A storage element; A power storage device including a management device, the management device includes a circuit breaker that interrupts a current path between the energy storage element and a connection terminal for connecting the energy storage element to an external device, a control unit, and a circuit breaker control circuit; the control unit executes a first interruption process of interrupting the circuit breaker when a state in which the voltage of the storage element is equal to or lower than a predetermined first threshold value continues for a predetermined first period; the shutoff control circuit executes a second shutoff process to shut off the circuit breaker when a state in which the voltage of the storage element is equal to or lower than a predetermined second threshold value that is lower than the first threshold value continues for a predetermined second period; The second shutoff process is executed independently of the first shutoff process.

2. The management device includes a discharge circuit disposed between a gate and a source of the circuit breaker, The power storage device according to claim 1 , wherein in the second interruption process, the interruption control circuit turns off a switch provided on a gate line of the circuit breaker and brings the discharge circuit into conduction.

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