Write assist circuit and SRAM

Abstract

To provide a write assist circuit by which the amount of assist can be adjusted appropriately according to the quality of SRAM after manufacturing.SOLUTION: A write assist circuit 14 of an SRAM 10 has a first wiring 14a, a plurality of second wirings (victim wirings 14b1-14bN) that are subjected to noise in a negative potential direction by the first wiring 14a, and a selection circuit 14c. The write assist circuit C includes a selection circuit 14c that selects a first number of second wirings from the plurality of second wirings based on an input selection signal, and outputs a potential of a negative potential amount based on the negative potential applied to the first number of second wirings due to the noise.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a write assist circuit and an SRAM. [Background technology]

[0002] The miniaturization of semiconductor technology has led to increased manufacturing variability, resulting in increased variations in transistor characteristics and wiring resistance and capacitance. Furthermore, in recent years, the industrial use of AI (Artificial Intelligence) and big data has progressed. To ensure the computing power required to process the massive amounts of data required for AI and big data, the operating voltage of semiconductor integrated circuits such as processors is being reduced.

[0003] SRAM (Static Random Access Memory) is sometimes used as cache memory for processors. As manufacturing variations increase and operating voltages become lower, the performance of writing to SRAM memory cells may decline. To prevent this decline in write performance, a write assist circuit is sometimes used to expand the write margin for memory cells (see, for example, Patent Documents 1 and 2).

[0004] One of the assist methods for write assist circuits is the negative bit line (NBL) method, which assists writing to memory cells by lowering the potential of the bit line to a negative potential. For example, there are NBL write assist circuits that can adjust the amount of assistance using a capacitive element, and NBL write assist circuits that use parasitic capacitance between wirings instead of a capacitive element to prevent an increase in area. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2021-140848 [Patent Document 2] International Publication No. 2014 / 149093 Summary of the Invention [Problem to be solved by the invention]

[0006] However, the amount of assistance in conventional NBL-based write assist circuits that use inter-wiring capacitance is a fixed value, so even if manufacturing variations are not as expected after the SRAM is manufactured or if specifications change, the amount of assistance cannot be adjusted appropriately.

[0007] In one aspect, an object is to make it possible to appropriately adjust the amount of assistance provided by a write assist circuit in accordance with the quality of the SRAM after manufacturing. [Means for solving the problem]

[0008] In one embodiment, a write assist circuit for an SRAM is provided, which includes a first wiring, a plurality of second wirings that receive noise in the negative potential direction through the first wiring, and a selection circuit that selects a first number of second wirings from the plurality of second wirings based on an input selection signal, and outputs a potential of a negative potential amount based on the negative potential applied to the first number of second wirings due to the noise.

[0009] Also, in one embodiment, there is provided an SRAM having a memory cell array including memory cells connected to first bit lines and second bit lines, a write driver circuit that applies different potentials to the first bit lines and the second bit lines when writing to the memory cells, and a write assist circuit connected to the write driver circuit, wherein the write assist circuit has a first wiring, a plurality of second wirings that receive noise in the negative potential direction through the first wiring, and a selection circuit that selects a first number of second wirings from the plurality of second wirings based on an input selection signal, and outputs a potential of a negative potential amount based on the negative potential applied to the first number of second wirings due to the noise to the write driver circuit. [Effects of the Invention]

[0010] In one aspect, the amount of assistance provided by the write assist circuit can be appropriately adjusted to match the quality of the SRAM after manufacturing. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 2 is a diagram illustrating a configuration of a portion of an SRAM according to the first embodiment. [Figure 2] FIG. 10 is a diagram illustrating an example of a relationship between the number of selected victim wirings and the amount of negative potential. [Figure 3] FIG. 1 is a diagram illustrating an SRAM of a comparative example. [Figure 4] 10 is a timing chart showing an example of time changes in potential at each part during a write operation in an SRAM of a comparative example. [Figure 5] FIG. 10 is a diagram illustrating an example of the overall configuration of an SRAM according to a second embodiment. [Figure 6] FIG. 10 illustrates an example of the configuration of a write assist circuit according to a second embodiment; [Figure 7] FIG. 10 is a diagram showing an example of changes in the potential of each victim wiring during a write assist operation when no short circuit is provided. [Figure 8] FIG. 10 is a diagram showing an example of a change in bit line potential over time with respect to the value of the selection signal SW[2:0]. [Figure 9] FIG. 1 illustrates an example of a test system. [Figure 10] 10 is a flowchart showing the flow of an example of an adjustment process of the selection signals SW[2:0]. [Figure 11] FIG. 10 is a diagram illustrating an example of data held in a shift register that generates a selection signal SW[2:0]. [Figure 12] FIG. 10 is a diagram illustrating an SRAM according to a first modified example. [Figure 13] FIG. 10 is a diagram illustrating an SRAM according to a second modified example. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the invention will be described with reference to the drawings. (First embodiment) FIG. 1 is a diagram showing a configuration of a part of an SRAM according to the first embodiment.

[0013] The SRAM 10 has a memory cell array 11, a column switch 12, a write driver circuit 13, and a write assist circuit 14. Note that a decoder that decodes address signals, a timing control circuit that controls the operation timing of each component, an input / output circuit, a circuit that performs read-related operations, and the like are not shown in FIG.

[0014] The memory cell array 11 has a plurality of memory cells arranged in an array. Each memory cell is connected to a word line and two bit lines (hereinafter sometimes referred to as a bit line pair). A specific example of the memory cell array 11 will be described later (see FIG. 3).

[0015] The column switch 12 selects one of the bit line pairs in the memory cell array 11 based on a column selection signal supplied from the decoder. The write driver circuit 13 applies a potential corresponding to the write data to a selected bit line pair based on a timing signal output by the timing control circuit. Different potentials are applied to the first and second bit lines included in the bit line pair. For example, when a potential with a logic H (High) level is applied to the first bit line, a potential with a logic L (Low) level is applied to the second bit line. When a potential with a logic L level is applied to the first bit line, a potential with a logic H level is applied to the second bit line. A bit line pair consisting of the first and second bit lines is sometimes called a complementary bit line pair. Note that a high level potential corresponds to write data "1," and a low level potential corresponds to write data "0."

[0016] The write assist circuit 14 increases the write operation margin (potential difference between the first bit line and the second bit line) to the memory cell in order to suppress degradation of write performance due to manufacturing variations, a drop in operating voltage, and the like.

[0017] The write assist circuit 14 includes a first wiring 14a, second wirings (hereinafter referred to as victim wirings) 14b1, 14b2, . . . , 14bN, a selection circuit 14c, and a write assist control circuit 14d.

[0018] The first wiring 14a is connected to a write assist control circuit 14d. When write assist is performed, the potential of the first wiring 14a is transitioned from an H-level potential to an L-level potential by the write assist control circuit 14d.

[0019] In the example of FIG. 1, the first wiring 14a includes a plurality of wiring portions (hereinafter referred to as aggressor wirings) 14a1, 14a2, ..., 14aN arranged in the same direction as the wiring direction of the victim wirings 14b1 to 14bN. Each of the aggressor wirings 14a1 to 14aN is arranged adjacent to one of the victim wirings 14b1 to 14bN at a closer distance than the other victim wirings. This makes it possible to make the magnitude of the inter-wiring capacitance between adjacent wirings uniform between each pair of adjacent wirings. This improves the accuracy of adjusting the assist amount.

[0020] The victim wirings 14b1 to 14bN are subjected to noise in the negative potential direction by the first wiring 14a, based on the magnitude of the inter-wiring capacitance. In the example of FIG. 1, inter-wiring capacitances Cc1, Cc2, ..., CcN are shown. The inter-wiring capacitance Cc1 is the inter-wiring capacitance between the aggressor wiring 14a1 and the victim wiring 14b1. The inter-wiring capacitance Cc2 is the inter-wiring capacitance between the aggressor wiring 14a2 and the victim wiring 14b2. The inter-wiring capacitance CcN is the inter-wiring capacitance between the aggressor wiring 14aN and the victim wiring 14bN.

[0021] FIG. 1 also shows ground capacitances Cg1, Cg2, . . . , CgN, which are parasitic capacitances connected to the victim wirings 14b1 to 14bN, respectively. The selection circuit 14c selects a first number of victim wirings from the victim wirings 14b1 to 14bN based on an input selection signal. The selection circuit 14c then outputs a potential with a negative potential amount based on the negative potential applied to the first number of victim wirings due to noise. The first number is determined by the value of the selection signal, and will be referred to as the selection number in the following description. The selection number is an integer equal to or greater than 0. The selection number includes 0 because write assist may not be necessary depending on the quality of the SRAM 10 after manufacturing. The selection signal is input, for example, from outside the SRAM 10.

[0022] 1, the selection circuit 14c can be realized using switches 14c1, 14c2, ..., 14cN. The selection circuit 14c turns on one or more of the switches 14c1 to 14cN in response to a selection signal, and electrically connects the victim wirings 14b1 to 14bN, the number of which corresponds to the selection number, to the write driver circuit 13. The victim wirings, the number of which corresponds to the selection number, are electrically connected to a low-potential power supply terminal of the write driver circuit 13. The low-potential power supply terminal of the write driver circuit 13 is, for example, a power supply terminal to which a ground potential VSS (e.g., 0 V) ​​is applied when an assist operation is not being performed.

[0023] The write assist control circuit 14d receives an assist signal from the timing control circuit to instruct execution of write assist. When the assist signal is input, the write assist control circuit 14d changes the potentials of the aggressor wirings 14a1 to 14aN from H level to L level.

[0024] Furthermore, when the assist signal is input, the write assist control circuit 14d enables the electrical connection between the write driver circuit 13 and the selection circuit 14c. Note that the ground capacitance Cgd of the wiring 15 connecting the write driver circuit 13 and the write assist circuit 14 is shown in FIG.

[0025] Next, an example of the write assist operation by the write assist circuit 14 of the first embodiment will be described. When writing data to the memory cell array 11, the write assist control circuit 14d puts the victim wirings 14b1 to 14bN and the wiring 15 into a floating state at the timing when the assist signal is input.

[0026] Furthermore, the write assist control circuit 14d transitions the potentials of the aggressor wirings 14a1-14aN from H level to L level, which causes the victim wirings 14b1-14bN to receive noise in the negative potential direction based on the magnitude of the inter-wiring capacitances Cc1-CcN from the aggressor wirings 14a1-14aN, generating a negative potential.

[0027] When the selection circuit 14c selects a victim wiring based on the input selection signal, the negative potential applied to the selected victim wiring is transmitted to the wiring 15. The amount of negative potential of the wiring 15 corresponds to the amount of assist.

[0028] When the amount of negative potential is represented as ΔVneg, the magnitude of the inter-wire capacitance Cc1 to CcN as Cc1 to CcN, the magnitude of the ground capacitance Cg1 to CgN, Cgd as Cg1 to CgN, Cgd, and the power supply potential on the high potential side as VDD, ΔVneg can be expressed by the following equation (1).

[0029] ΔVneg=-(CcN+…+Cc2+Cc1) / (CcN+…+Cc2+Cc1+CgN+…+Cg2+Cg1+Cgd)×VDD (1) In this case, if it is assumed that Cc1 to CcN each have the same value (=Cc) and Cg1 to CgN each have the same value (=Cg), then equation (1) can be expressed as the following equation (2).

[0030] ΔVneg=-N×Cc / (N×Cc+N×Cg+Cgd)×VDD (2) Note that equation (2) represents the amount of negative potential when all N victim wirings 14b1 to 14bN are selected. If the number of selected victim wirings is n instead of N, the relationship between the number of selected victim wirings and the amount of negative potential can be expressed, for example, as follows based on equation (2):

[0031] 2 is a diagram showing an example of the relationship between the number of selected victim wirings and the amount of negative potential, where the horizontal axis represents the number of selected victim wirings (n) and the vertical axis represents the amount of negative potential (ΔVneg).

[0032] As shown in Figure 2, increasing the number of victim wirings selected by the selection signal increases the amount of negative potential, i.e., the amount of assist. Conversely, decreasing the number of victim wirings selected by the selection signal decreases the amount of assist.

[0033] As a comparative example, a write assist circuit that utilizes the capacitance between a pair of aggressor and victim wirings and its problems will be specifically described below. (Comparative Example) 3 is a diagram showing an SRAM of a comparative example, in which the same elements as those shown in FIG.

[0034] In the SRAM 20 of the comparative example, the write assist circuit 21 includes an aggressor wiring 21a, a victim wiring 21b, and a write assist control circuit 14d. The aggressor wiring 21a and the victim wiring 21b are connected to the write assist control circuit 14d. The parasitic capacitance Cc is the capacitance between the aggressor wiring 21a and the victim wiring 21b. In FIG. 3, the potential of the aggressor wiring 21a is denoted as "NBLenb."

[0035] Fig. 3 shows an example of the configuration of the write assist control circuit 14d also shown in Fig. 1. The write assist control circuit 14d has an inverter circuit 14d1, a buffer circuit 14d2, and a transistor 14d3.

[0036] An enable signal NBLen is input to the inverter circuit 14d1 from, for example, a timing control circuit (not shown). When the potential of the enable signal NBLen is at H level, the enable signal NBLen corresponds to the above-mentioned assist signal.

[0037] The output signal of the inverter circuit 14d1 is input to the buffer circuit 14d2, and the output potential of the buffer circuit 14d2 becomes the potential NBLenb of the aggressor wiring 21a. The transistor 14d3 functions as a switch that switches between enabling and disabling the electrical connection between the write driver circuit 13 and the victim wiring 21b. In the example of FIG. 3, the transistor 14d3 is an n-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The output signal of the inverter circuit 14d1 is input to the gate of the transistor 14d3. The drain of the transistor 14d3 is electrically connected to the victim wiring 21b and the low-potential power supply terminal of the write driver circuit 13. The source of the transistor 14d3 is grounded.

[0038] 3 shows an example of the configuration of the memory cell array 11, the column switch 12, and the write driver circuit 13, which are also shown in FIG. The memory cell array 11 includes memory cells 11a0 to 11an, bit lines BL and BLB, and word lines WL[0] to WL[n]. The memory cells 11a0 to 11an are connected to the bit lines BL and BLB. The memory cell 11a0 is connected to the word line WL[0]. The memory cell 11an is connected to the word line WL[n]. The word lines WL[0] to WL[n] are connected to a decoder (not shown).

[0039] For example, when writing data to the memory cell 11a0, the potential of the word line WL[0] becomes H level. When writing data to the memory cell 11an, the potential of the word line WL[n] becomes H level.

[0040] 3 shows an example of the configuration of memory cells 11a0 and 11an. The following description will be given using memory cell 11an as an example, but other memory cells are also realized with the same configuration. Memory cell 11an has transistors TR1, TR2, TR3, TR4, TR5, and TR6. In the example of FIG. 3, transistors TR1 and TR2 are p-channel MOSFETs. Transistors TR3 to TR6 are n-channel MOSFETs.

[0041] A power supply potential is applied to the sources of transistors TR1 and TR2. The drain of transistor TR1 is connected to the drain of transistor TR3, the gates of transistors TR2 and TR4, and either the drain or source of transistor TR5. The drain of transistor TR2 is connected to the drain of transistor TR4, the gates of transistors TR1 and TR3, and either the drain or source of transistor TR6. The gates of transistors TR1 and TR3 are connected to each other, and the gates of transistors TR2 and TR4 are also connected to each other. The sources of transistors TR3 and TR4 are grounded.

[0042] The other of the drain or source of transistor TR5 is connected to the bit line BL. The other of the drain or source of transistor TR6 is connected to the bit line BLB. The gates of transistors TR5 and TR6 are connected to the word line WL[n]. Transistors TR5 and TR6 are sometimes called transfer gates.

[0043] The column switch 12 includes transistors 12a and 12b. The write driver circuit 13 includes inverter circuits 13a and 13b. In the example of FIG. 3, the transistors 12a and 12b are n-channel MOSFETs. One of the drain and source of the transistor 12a is connected to the bit line BL, and the other is connected to the output terminal of the inverter circuit 13a. One of the drain and source of the transistor 12b is connected to the bit line BLB, and the other is connected to the output terminal of the inverter circuit 13b. The gates of the transistors 12a and 12b are connected to each other, and a column selection signal WCOL is applied to them from a decoder (not shown).

[0044] Of the complementary write data / DT, / DB, the write data / DT is input to the inverter circuit 13a. Of the complementary write data / DT, / DB, the write data / DB is input to the inverter circuit 13b. The low-potential power supply terminals of the inverter circuits 13a and 13b, which correspond to the low-potential power supply terminal of the write driver circuit 13, are connected to the write assist circuit 21.

[0045] In FIG. 3, the potential of the wiring 15 connecting the low-potential power supply terminals of the inverter circuits 13a and 13b and the write assist circuit 21 is denoted as "NVSS." Fig. 4 is a timing chart showing an example of the change over time in potential of each part during a write operation in the SRAM of the comparative example. Fig. 4 shows the change over time in potential of the word line WL, which is one of the word lines WL[0] to WL[n] shown in Fig. 3, the potential of the column selection signal WCOL, the potential of the write data / DT, / DB, and the potential of the enable signal NBLen. Furthermore, the change over time in potential NBLenb of the aggressor wiring 21a, the potential NVSS of the wiring 15, and the potential of the bit lines BL, BLB are shown.

[0046] When the potential of the column selection signal WCOL rises from L level (ground potential VSS) to H level (power supply potential VDD) (timing t1), the potentials of the write data / DT and / DB are transmitted to the bit lines BL and BLB. In the example of Figure 4, the potential of the bit line BL is L level, and the potential of the bit line BLB is H level.

[0047] When the potential of the word line WL rises from L level to H level (timing t2), the memory cell connected to the word line WL is selected. For example, when the memory cell 11an shown in FIG. 3 is selected, the transistors TR5 and TR6 are turned on. This starts writing the write data / DT and / DB to the memory cell 11an.

[0048] When the enable signal NBLen rises from L level to H level (timing t3), the write assist starts. The potential NBLenb of the aggressor wiring 21a falls from H level to L level, and the victim wiring 21b receives noise in the negative potential direction based on the magnitude of the capacitance Cc from the aggressor wiring 21a, generating a negative potential. As a result, the potential NVSS of the wiring 15 falls below the ground potential VSS (e.g., 0 V) ​​and becomes negative.

[0049] When the potential NVSS of the line 15 becomes negative, the potential of the bit line BL also drops to a negative potential by α, which is a negative potential amount based on the magnitude of the capacitance between the lines. As a result, the gate-source potential VgsAC of the transfer gate of the memory cell (for example, transistor TR5 in FIG. 3) increases by α. The increase in the gate-source potential VgsAC increases the driving force of the transfer gate, improving the write performance of the memory cell.

[0050] However, in the write assist circuit 21 of the comparative example, the assist amount (amount of negative potential) is a fixed value. Therefore, even if manufacturing variations are not as expected after manufacturing the SRAM 20 or if specifications change, the assist amount cannot be adjusted to an appropriate amount. In this case, for example, the following problems may occur.

[0051] If the transistor performance of the manufactured SRAM 20 is lower than expected, or if the capacitance between wires is smaller than expected, the expected assist amount may not be sufficient, making writing impossible and reducing yield.

[0052] If the operating voltage is increased due to a change in the specifications of the SRAM 20 after manufacture, a situation may arise in which it is desirable to set the assist amount to 0 or to reduce it from the viewpoint of reliability. However, in the write assist circuit 21 of the comparative example, the assist amount is fixed, so it cannot handle such a situation, which may result in a decrease in yield.

[0053] Due to the quality of SRAM20 after manufacturing, even if the amount of assistance becomes excessive, it is not possible to reduce the amount of assistance, which may result in unnecessary power consumption. In contrast to the write assist circuit 21 of the comparative example, the write assist circuit 14 of the first embodiment can adjust the amount of assistance even after manufacturing.

[0054] That is, the write assist circuit 14 includes a first wiring 14a, victim wirings 14b1-14bN that receive noise in the negative potential direction through the first wiring 14a, and a selection circuit 14c. The selection circuit 14c selects a first number of victim wirings from the victim wirings 14b1-14bN based on an input selection signal, and outputs a potential of a negative potential amount based on the negative potential applied to the victim wirings selected by the noise.

[0055] With this configuration, the assist amount can be adjusted by the selection signal even after the SRAM 10 is manufactured. This allows the assist amount by the write assist circuit 14 to be appropriately adjusted in accordance with the quality of the SRAM 10 after manufacturing.

[0056] Furthermore, the write assist circuit 14 does not adjust the assist amount using an actual capacitive element. In the case of a write assist circuit that adjusts the assist amount using a capacitive element, increasing the adjustment variation or adjustment amount results in an increase in area. The write assist circuit 14 of the first embodiment adjusts the assist amount using inter-wiring capacitances Cc1 to CcN, thereby suppressing an increase in area.

[0057] Therefore, it is possible to deal with manufacturing variations and reliability issues after manufacturing without changing the design, improving yield. In addition, it is possible to prevent excessive assist amounts, thereby reducing wasted power.

[0058] The first wiring 14a including the aggressor wirings 14a1-14aN and the victim wirings 14b1-14bN can be mounted in a wiring layer above the wiring layer of the memory cell array 11. This makes it possible to further suppress an increase in area compared to a write assist circuit that adjusts the amount of assistance using a capacitive element.

[0059] (Second embodiment) FIG. 5 is a diagram illustrating an example of the overall configuration of an SRAM according to the second embodiment. The SRAM 30 includes a memory cell array 31, a write column switch 32, a write driver circuit 33, and a write assist circuit 34. The SRAM 30 further includes a read column switch 35, a read circuit 36, an input / output circuit 37, a timing control circuit 38, and a decoder 39.

[0060] The memory cell array 31 has a plurality of memory cells arranged in an array. Each memory cell is connected to a word line WL[0], WL[1], ..., WL[n] and a bit line pair. A specific example of the memory cell array 31 will be described later (see FIG. 6).

[0061] During a write operation, the column switch 32 selects one of the bit line pairs in the memory cell array 31 based on a column selection signal supplied from the decoder 39 . The write driver circuit 33 applies a potential corresponding to the write data input from the input / output circuit 37 to the selected bit line pair based on the timing signal output from the timing control circuit 38 .

[0062] The write assist circuit 34 increases the margin of the write operation to the memory cells in order to prevent a decrease in write performance. During a read operation, the column switch 35 selects one of the bit line pairs of the memory cell array 31 based on a column selection signal supplied from the decoder 39 .

[0063] The read circuit 36 ​​transmits read data based on the potential of the selected bit line pair to the input / output circuit 37 based on a timing signal output by the timing control circuit 38 . The input / output circuit 37 receives write data input from outside the SRAM 30 based on a timing signal output by the timing control circuit 38. The input / output circuit 37 also outputs read data to outside the SRAM 30 based on a timing signal output by the timing control circuit 38.

[0064] The timing control circuit 38 controls the operation timing of each part of the SRAM 30 . The decoder 39 decodes an address signal input from outside the SRAM 30 and determines the word lines WL[0] to WL[n] to be made active (H-level potential). The decoder 39 also decodes the address signal and generates a column selection signal.

[0065] 6 is a diagram showing an example of the configuration of a write assist circuit according to the second embodiment, which also shows an example of the configuration of a memory cell array 31, a column switch 32, and a write driver circuit 33.

[0066] The memory cell array 31 includes memory cells 31a0 to 31an, bit lines BL and BLB, and word lines WL[0] to WL[n]. The memory cells 31a0 to 31an are connected to the bit lines BL and BLB. The memory cell 31a0 is connected to the word line WL[0]. The memory cell 31an is connected to the word line WL[n]. The word lines WL[0] to WL[n] are connected to a decoder 39.

[0067] For example, when writing data to the memory cell 31a0, the potential of the word line WL[0] becomes H level. When writing data to the memory cell 31an, the potential of the word line WL[n] becomes H level.

[0068] The configuration of the memory cells 31a0 to 31an is the same as that of the memory cells 11a0 and 11an shown in FIG. 3, and therefore a description thereof will be omitted. The column switch 32 includes transistors 32a and 32b. The write driver circuit 33 includes inverter circuits 33a and 33b. In the example of FIG. 6, the transistors 32a and 32b are n-channel MOSFETs. The drain of the transistor 32a is connected to the bit line BL, and the source is connected to the output terminal of the inverter circuit 33a. The drain of the transistor 32b is connected to the bit line BLB, and the source is connected to the output terminal of the inverter circuit 33b. The gates of the transistors 32a and 32b are connected to each other, and a column selection signal WCOL is applied from the decoder 39.

[0069] Of the complementary write data / DT, / DB, the write data / DT is input to the inverter circuit 33a. Of the complementary write data / DT, / DB, the write data / DB is input to the inverter circuit 33b. The low-potential power supply terminals of the inverter circuits 33a and 33b, which correspond to the low-potential power supply terminal of the write driver circuit 33, are connected to the write assist circuit 34.

[0070] The inverter circuit 33a includes transistors 33a1 and 33a2. In the example of FIG. 6, the transistor 33a1 is a p-channel MOSFET, and the transistor 33a2 is an n-channel MOSFET. The source of the transistor 33a1 corresponds to the high-potential power supply terminal of the inverter circuit 33a, and a power supply potential is applied to the source. The drain of the transistor 33a1 is connected to the drain of the transistor 33a2. The drains of the transistors 33a1 and 33a2 correspond to the output terminal of the inverter circuit 33a. The gates of the transistors 33a1 and 33a2 are connected to each other, and write data / DT is input to each gate. The gates of the transistors 33a1 and 33a2 correspond to the input terminal of the inverter circuit 33a. The source of the transistor 33a2 corresponds to the low-potential power supply terminal of the inverter circuit 33a, and the write assist circuit 34 is connected to the source via wiring 40.

[0071] The configuration of the inverter circuit 33b is the same as that of the inverter circuit 33a, and therefore a description thereof will be omitted. Note that in Fig. 6, the potential of the wiring 40 connecting the low-potential power supply terminals of the inverter circuits 33a and 33b and the write assist circuit 34 is denoted as "NVSS."

[0072] The write assist circuit 34 includes aggressor wirings 34a0, 34a1, and 34a2, victim wirings 34b0, 34b1, and 34b2, a selection circuit 34c, a write assist control circuit 34d, and a short-circuit circuit 34e. Note that, although there are three aggressor wirings 34a0 to 34a2 and three victim wirings 34b0 to 34b2 in the example of FIG. 6, the number of the aggressor wirings 34a0 to 34a2 and the number of the victim wirings 34b0 to 34b2 are not limited to three.

[0073] The aggressor wirings 34a0 to 34a2 are connected to a write assist control circuit 34d. When write assist is performed, the potential NBLenb of the aggressor wirings 34a0 to 34a2 transitions from the H level to the L level.

[0074] During the write assist operation, the victim wirings 34b0-34b2 are subjected to negative noise due to the magnitude of the inter-wiring capacitance from the aggressor wirings 34a0-34a2, and become negative potentials. In the example of FIG. 6, inter-wiring capacitances Cc0, Cc1, and Cc2 are shown. The inter-wiring capacitance Cc0 is the inter-wiring capacitance between the aggressor wiring 34a0 and the victim wiring 34b0. The inter-wiring capacitance Cc1 is the inter-wiring capacitance between the aggressor wiring 34a1 and the victim wiring 34b1. The inter-wiring capacitance Cc2 is the inter-wiring capacitance between the aggressor wiring 34a1 and the victim wiring 34b2. In FIG. 6, the potential of the victim wiring 34b0 is denoted as "NVSS0," the potential of the victim wiring 34b1 as "NVSS1," and the potential of the victim wiring 34b2 as "NVSS2."

[0075] The selection circuit 34c has switches 34c0, 34c1, and 34c2. In the example of FIG. 6, the switches 34c0 to 34c2 are each an n-channel MOSFET. One of the source or drain of the switch 34c0 is connected to the victim wiring 34b0. One of the source or drain of the switch 34c1 is connected to the victim wiring 34b1. One of the source or drain of the switch 34c2 is connected to the victim wiring 34b2. A signal SW[0] is input to the gate of the switch 34c0, a signal SW[1] is input to the gate of the switch 34c1, and a signal SW[2] is input to the gate of the switch 34c2. The other of the source or drain of the switches 34c0 to 34c2 is connected to the write assist control circuit 34d and the low-potential power supply terminal of the write driver circuit 33.

[0076] When the potential of the signal SW[0] is at H level, the switch 34c0 is turned on and the victim wiring 34b0 is in a selected state. When the potential of the signal SW[0] is at L level, the switch 34c0 is turned off and the victim wiring 34b0 is in a non-selected state.

[0077] When the potential of the signal SW[1] is at H level, the switch 34c1 is turned on and the victim wiring 34b1 is in a selected state. When the potential of the signal SW[1] is at L level, the switch 34c1 is turned off and the victim wiring 34b1 is in a non-selected state.

[0078] When the potential of the signal SW[2] is at H level, the switch 34c2 is turned on and the victim wiring 34b2 is in a selected state. When the potential of the signal SW[2] is at L level, the switch 34c2 is turned off and the victim wiring 34b2 is in a non-selected state.

[0079] The victim wiring in the selected state is electrically connected to the low potential side power supply terminal of the write driver circuit 33 . Hereinafter, the signals SW[0] to SW[2] may be collectively referred to as the selection signal SW[2:0]. The selection signal SW[2:0] indicates the number of victim wirings 34b0 to 34b2 that are selected.

[0080] The selection signal SW[2:0] is input, for example, from outside the SRAM 10. For example, the selection signal SW[2:0] is input by a test device during testing after manufacturing the SRAM 30. After an appropriate value of the selection signal SW[2:0] is determined, the value of the selection signal SW[2:0] may be fixed, for example, using a read-only memory (ROM).

[0081] The write assist control circuit 34d includes an inverter circuit 34d1, a buffer circuit 34d2, and a transistor 34d3. The inverter circuit 34d1 receives an enable signal NBLen from the timing control circuit 38, for example.

[0082] The output signal of the inverter circuit 34d1 is input to the buffer circuit 34d2. The output potential of the buffer circuit 34d2 becomes the potential NBLenb of the aggressor wirings 34a0 to 34a2.

[0083] The transistor 34d3 functions as a switch that switches between enabling and disabling the electrical connection between the write driver circuit 33 and the selection circuit 34c. In the example of FIG. 6, the transistor 34d3 is an n-channel MOSFET. The output signal of the inverter circuit 34d1 is input to the gate of the transistor 34d3. The drain of the transistor 34d3 is electrically connected to the selection circuit 34c and the low-potential power supply terminal of the write driver circuit 33. The source of the transistor 34d3 is grounded.

[0084] The short circuit 34e shorts the victim wirings 34b0 to 34b2 that are in a non-selected state to the ground potential based on the selection signal SW[2:0]. In the example of Fig. 6, the short circuit 34e has switches 34e0, 34e1, and 34e2.

[0085] In the example of FIG. 6, the switches 34e0 to 34e2 are each an n-channel MOSFET. The drain of the switch 34e0 is connected to the victim wiring 34b0, the drain of the switch 34e1 is connected to the victim wiring 34b1, and the drain of the switch 34e2 is connected to the victim wiring 34b2. A signal / SW[0] obtained by inverting the polarity of the potential of the signal SW[0] from H level to L level or from L level to H level is input to the gate of the switch 34e0. Similarly, a signal / SW[1] obtained by inverting the polarity of the potential of the signal SW[1] is input to the gate of the switch 34e1, and a signal / SW[2] obtained by inverting the polarity of the potential of the signal SW[2] is input to the gate of the switch 34e2. The sources of the switches 34e0 to 34e2 are grounded.

[0086] The write assist circuit 34 may include an inverter circuit that inverts the potential levels of the signals SW[0] to SW[2] and outputs the signals / SW[0] to / SW[2].

[0087] Next, an example of the write assist operation by the write assist circuit 34 of the second embodiment will be described. When the potential of the enable signal NBLen input from the timing control circuit 38 is at the L level, the write assist circuit 34 is in an inactive state (a state in which the write assist operation is not performed). At this time, the potential of the output signal of the inverter circuit 34d1 of the write assist control circuit 34d is at the H level, so the transistor 34d3 is turned on. As a result, the potential NVSS of the wiring 40 is at the ground potential. Furthermore, of the victim wirings 34b0 to 34b2, the victim wiring selected by the selection signal SW[2:0] is also at the ground potential. The potentials of the aggressor wirings 34a0 to 34a2 are at the H level when the potential of the output signal of the inverter circuit 34d1 is at the H level.

[0088] When the potential of the enable signal NBLen transitions to the H level, the write assist circuit 34 is activated (a state in which a write assist operation is performed). At this time, the potential of the output signal of the inverter circuit 34d1 of the write assist control circuit 34d becomes the L level, and the transistor 34d3 is turned off. As a result, the wiring 40 and the victim wiring selected by the selection signal SW[2:0] change from the ground potential state to the floating state. Note that the victim wiring not selected by the selection signal SW[2:0] remains at the ground potential.

[0089] On the other hand, the aggressor wirings 34a0 to 34a2 receive the change in potential of the output signal of the inverter circuit 34d1 via the buffer circuit 34d2, causing the potential of the aggressor wirings 34a0 to 34a2 to transition from H level to L level.

[0090] Due to the above-described potential transitions of the aggressor wirings 34a0-34a2, the victim wirings 34b0-34b2 receive noise in the negative potential direction based on the magnitude of the inter-wiring capacitances Cc0-Cc2 due to capacitive coupling between the wirings, which causes the potentials of the victim wirings 34b0-34b2 to become negative.

[0091] Furthermore, the wiring 40, through which the potential NVSS, which is the output potential of the write assist circuit 34, propagates, also becomes negative due to charge redistribution. The wiring 40 is connected to the low-potential power supply terminal of the inverter circuits 33a and 33b of the write driver circuit 33. Therefore, when the potential of the output signal of either of the inverter circuits 33a and 33b becomes L level during writing, the potential becomes negative. Then, of the bit lines BL and BLB, the bit line through which the output signal propagates also becomes negative. As a result, write assistance is performed with an assist amount (negative potential amount) according to the value of the selection signal SW[2:0].

[0092] The reason for providing the short circuit 34e will now be explained. Fig. 7 is a diagram showing an example of changes in the potential of each victim wiring during a write assist operation when no short circuit is provided. Fig. 7 shows changes in the potentials NVSS0 to NVSS2 of the victim wirings 34b0 to 34b2 when no short circuit 34e is provided. Timings t10 to t11 represent the period during which write assist is performed.

[0093] For example, assume that victim wiring 34b0 is in a selected state and victim wirings 34b1 and 34b2 are in a non-selected state. In this case, victim wirings 34b1 and 34b2, which are floating, may have an unexpectedly large negative potential relative to victim wiring 34b0, which is connected to the low-potential power supply terminals of inverter circuits 33a and 33b of write driver circuit 33.

[0094] As shown in FIG. 7, between timings t10 and t11, the potentials NVSS1 and NVSS2 of the victim wirings 34b1 and 34b2 transition more negatively than the potential NVSS0 of the victim wiring 34b0.

[0095] If the potential of a non-selected victim wiring line changes significantly to the negative side, the drain-gate voltage of the n-channel MOSFET switches 34c0-34c2 may exceed the threshold voltage. In this case, the switches 34c0-34c2 may not be able to maintain the off state. This may result in the inability to properly control the negative potential. Furthermore, because the PN junctions included in the switches 34c0-34c2 are forward biased, excessive swings to the negative potential side may pose a risk of latch-up.

[0096] This situation can be avoided by providing the short circuit 34e. When the victim wiring 34b0 is unselected (when the potential of the signal SW[0] is low), the switch 34e0 of the short circuit 34e is turned on because the potential of the signal / SW[0] is high. This shorts the victim wiring 34b0 to ground potential. When the victim wiring 34b1 is unselected (when the potential of the signal SW[1] is low), the switch 34e1 of the short circuit 34e is turned on because the potential of the signal / SW[1] is high. This shorts the victim wiring 34b1 to ground potential. When the victim wiring 34b2 is unselected (when the potential of the signal SW[2] is low), the switch 34e2 of the short circuit 34e is turned on because the potential of the signal / SW[2] is high. As a result, the victim wiring 34b2 is short-circuited to the ground potential.

[0097] In this way, the short circuit 34e shorts the potential of the unselected victim wiring to the ground potential, thereby preventing the potential of the unselected victim wiring from becoming excessively negative.

[0098] According to the write assist circuit 34 of the second embodiment described above, like the write assist circuit 14 of the first embodiment, the amount of assistance can be adjusted by the selection signal SW[2:0] even after the SRAM 30 has been manufactured.

[0099] 8 is a diagram showing an example of a change in the bit line potential over time in response to the value of the selection signal SW[2:0]. The diagram shows the change in the potential NVSS, which is the output potential of the write assist circuit 34, and the potentials of the bit lines BL and BLB over time in response to the value of the selection signal SW[2:0].

[0100] In FIG. 8, SW[2:0]="001" indicates that the potential of signal SW[0] is H level and the potentials of signals SW[1] and SW[2] are L level. In this case, victim wiring 34b0 is selected, and victim wirings 34b1 and 34b2 are unselected. SW[2:0]="011" indicates that the potentials of signals SW[0] and SW[1] are H level and the potential of signal SW[2] is L level. In this case, victim wirings 34b0 and 34b1 are selected, and victim wiring 34b2 is unselected. SW[2:0]="111" indicates that the potentials of signals SW[0] to SW[2] are H level. In this case, victim wirings 34b0 to 34b2 are selected.

[0101] As shown in FIG. 8, the greater the number of victim wirings in the selected state, the greater the amount of negative potential, that is, the greater the amount of assistance. (Adjustment of selection signal SW[2:0]) Next, we will explain the adjustment process of the selection signal SW[2:0] to set an appropriate assist amount according to the post-manufacturing quality of the SRAM 30. The adjustment process of the selection signal SW[2:0] can be automatically performed by a test device connected to the SRAM 30, for example, during a wafer test of the SRAM 30 or an assembly test after packaging.

[0102] 9 is a diagram showing an example of a test system. The test system includes an SRAM 30 and a test device 50 connected to the SRAM 30. The test device 50 includes a storage unit 51 and a test processing unit 52 .

[0103] The storage unit 51 stores a program for executing a function test and various data used in executing the function test. The storage unit 51 may include a volatile semiconductor memory such as a RAM (Random Access Memory), or may include a non-volatile storage such as an HDD (Hard Disk Drive) or a flash memory. The storage unit 51 may also include both a volatile semiconductor memory and a non-volatile storage.

[0104] The test processing unit 52 executes a program stored in the storage unit 51 to perform a function test on the SRAM 30. In the example of Fig. 9, the test processing unit 52 includes a shift register 52a used to generate the selection signal SW[2:0].

[0105] Although not shown, the test processing unit 52 may include, for example, a processor such as a CPU (Central Processing Unit), a test pattern generator that generates test patterns, a timing generator that generates timing signals, and the like.

[0106] Fig. 10 is a flowchart showing an example of the flow of an adjustment process of the selection signal SW[2:0], and Fig. 11 is a diagram showing an example of data held in a shift register that generates the selection signal SW[2:0].

[0107] The shift register 52a of the test device 50 holds, for example, 6-bit data as shown in Fig. 11. The shift register 52a then outputs the upper 3 bits as the selection signal SW[2:0].

[0108] Step S1: First, the selection signal SW[2:0] is set to "000". Step S2: A function test is performed on the SRAM 30. In the function test, it is tested whether the SRAM 30 operates as designed. In the first test, the selection signal SW[2:0] is set to "000" in the processing of step S1. Therefore, when a write operation to the SRAM 30 is performed in the function test, all victim wirings are in a non-selected state. As a result, the assist amount is 0.

[0109] If the SRAM 30 operates as designed, it is judged as "Pass" and the adjustment process of the selection signal SW[2:0] is completed. In this case, the SRAM 30 is deemed to be a non-defective product. If the SRAM 30 does not operate as designed, it is judged as "Fail" and the process of step S3 is performed. For example, if the expected value is not properly written to the SRAM 30, it is judged as "Fail." In this case, the amount of assistance provided by the write assist circuit 34 may be insufficient.

[0110] Step S3: The test apparatus 50 determines whether the selection signal SW[2:0] is "111," which indicates that all victim wirings are selected. If it is determined that the selection signal SW[2:0] is "111," the assist amount setting process ends. In this case, the SRAM 30 is deemed to be defective. If it is determined that the selection signal SW[2:0] is not "111," the process of step S4 is performed.

[0111] Step S4: The test apparatus 50 shifts the data held in the shift register 52a to the left, and then performs the process of step S2 again. 11, when the data held in the shift register 52a is "000111" during the first function test, the held data becomes "001110" after being shifted to the left. Of these, the upper three bits of the selection signal SW[2:0]="001" are used in the second function test. When a write operation is performed in the second function test, the victim wiring 34b0 is selected, and the assist amount increases compared to the first function test.

[0112] When the data held in the shift register 52a is "001110" during the second function test, the held data becomes "011100" after being shifted to the left. Of these, the upper three bits of the selection signal SW[2:0]="011" are used in the third function test. When a write operation is performed in the third function test, the victim wirings 34b0 and 34b1 are selected, and the assist amount increases compared to the second function test.

[0113] When the data held in the shift register 52a is "011100" during the fourth function test, the held data becomes "111000" after being shifted left. Of these, the most significant three bits of the selection signal SW[2:0]="111" are used in the fourth function test. When a write operation is performed in the fourth function test, the victim wirings 34b0 to 34b2 are selected, and the assist amount increases compared to the third function test.

[0114] In this way, by performing a function test by applying the assist amounts in order from the smallest to the largest, it is possible to prevent excessive voltage from being applied to the memory cells 31a0 to 31an and the transistors of the write assist circuit 34. This makes it possible to set an appropriate assist amount in terms of reliability and power consumption.

[0115] (Variation) Fig. 12 is a diagram showing an SRAM according to a first modified example, in which the same elements as those shown in Fig. 6 are denoted by the same reference numerals.

[0116] 6, one write driver circuit 33 is provided for one column of memory cells, but this is not limiting. In the SRAM 30a shown in FIG. 12, one write driver circuit 33 is provided in common for multiple columns of memory cells (four columns in FIG. 12).

[0117] Memory cells 31a0-0 to 31an-0 are connected to write driver circuit 33 via bit lines BL0 and BLB0 and column switch 32-0. Memory cells 31a0-1 to 31an-1 are connected to write driver circuit 33 via bit lines BL1 and BLB1 and column switch 32-1. Memory cells 31a0-2 to 31an-2 are connected to write driver circuit 33 via bit lines BL2 and BLB2 and column switch 32-2. Memory cells 31a0-3 to 31an-3 are connected to write driver circuit 33 via bit lines BL3 and BLB3 and column switch 32-3.

[0118] The column switches 32-0 to 32-3 can independently select memory cell columns by means of column selection signals. During a write operation of the SRAM 30a, the write driver circuit 33 reduces the potential of one of the bit lines BL0 to BL3 or one of the bit lines BLB0 to BLB3 to a negative potential according to the assist amount generated by the write assist circuit .

[0119] Fig. 13 is a diagram showing an SRAM according to a second modified example, in which the same elements as those shown in Figs. 6 and 12 are denoted by the same reference numerals. 6, one write assist circuit 34 is provided for one write driver circuit 33, but this is not limiting. In the SRAM 30b shown in FIG. 13, one write assist circuit 34 is provided in common for a plurality of (two in FIG. 13) write driver circuits 33-0 and 33-1.

[0120] The write driver circuit 33-0 is connected to the bit lines BL0 and BLB0 via the column switch 32-0, and also to the bit lines BL1 and BLB1 via the column switch 32-1.

[0121] The write driver circuit 33-1 is connected to the bit lines BL2 and BLB2 via a column switch 32-2, and to the bit lines BL3 and BLB3 via a column switch 32-3.

[0122] During such a write operation of the SRAM 30b, the write driver circuits 33-0 and 33-1 lower the potential of the bit lines BL0 to BL3 or the bit lines BLB0 to BLB3 to a negative potential in accordance with the assist amount generated by the write assist circuit .

[0123] When one write assist circuit 34 is connected to the write driver circuits 33-0 and 33-1, the assist amount (amount of negative potential) when using the same selection signal SW[2:0] may be reduced compared to when one write assist circuit 34 is connected to one write driver circuit 33. In this case, a selection signal SW[2:0] may be applied to the write assist circuit 34 such that the number of victim wirings selected is increased compared to when one write assist circuit 34 is connected to one write driver circuit 33.

[0124] The write assist circuit and SRAM of the present invention have been described from one aspect based on the embodiment, but these are merely examples and the present invention is not limited to the above description. [Explanation of symbols]

[0125] 10 SRAM 11 Memory Cell Array 12 Column Switch 13 Write driver circuit 14 Write assist circuit 14a1~14aN Aggressor wiring 14b1~14bN victim wiring 14c Selection circuit 14c1~14cN switches 14d Write assist control circuit 15 Wiring Cc1~CcN Inter-wiring capacitance Cg1~CgN,Cgd Grounding capacity

Claims

1. In the write assist circuit of the SRAM, A first wiring; a plurality of second wirings that receive noise in a negative potential direction through the first wirings; a selection circuit that selects a first number of second wirings from the plurality of second wirings based on an input selection signal, and outputs a potential having a negative potential amount based on the negative potential applied to the first number of second wirings due to the noise; A write assist circuit having:

2. the first wiring includes a plurality of wiring portions arranged in the same direction as the wiring direction of the plurality of second wirings, 2. The write assist circuit according to claim 1, wherein each of the plurality of wiring portions is disposed adjacent to one of the plurality of second wirings at a closer distance than the other second wirings.

3. 2. The write assist circuit according to claim 1, wherein the selection circuit outputs the potential with a larger negative potential amount as the number of selected second wirings increases.

4. 2. The write assist circuit according to claim 1, wherein said selection circuit electrically connects the selected second wiring to a power supply terminal on a low potential side of a write driver circuit of said SRAM.

5. 2. The write assist circuit according to claim 1, further comprising a short circuit that shorts, to a ground potential, a second wiring that is in a non-selected state among the plurality of second wirings based on the selection signal.

6. The write assist circuit of claim 1 , wherein the first number is an integer greater than or equal to 0.

7. 2. The write assist circuit according to claim 1, wherein the amount of negative potential is adjusted by increasing the first number from 0 by one in response to the selection signal.

8. a memory cell array including memory cells connected to first bit lines and second bit lines; a write driver circuit that applies different potentials to the first bit line and the second bit line when writing to the memory cell; a write assist circuit connected to the write driver circuit; and The write assist circuit A first wiring; a plurality of second wirings that receive noise in a negative potential direction through the first wirings; a selection circuit that selects a first number of second wirings from the plurality of second wirings based on an input selection signal, and outputs to the write driver circuit a potential having a negative potential amount based on a negative potential applied to the first number of second wirings due to the noise; An SRAM having:

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