Semiconductor device

Abstract

To provide a wide bandgap semiconductor device that has high robustness against misalignment between a gate electrode (trench) and a punch-through stopper layer.SOLUTION: The technical idea is to configure the planar shape of a punch-through stopper layer from a pattern having periodicity in each of X and Y directions that configure the plane, on the premise that trenches extending in the Y direction of the X and Y directions that configure the plane are arranged at predetermined intervals in the X direction.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device that uses a wide bandgap semiconductor material having a bandgap larger than that of silicon. [Background technology]

[0002] Japanese Patent Application Laid-Open No. 2019-117859 (Patent Document 1) describes a technique for forming a semiconductor region of the opposite conductivity type to that of the drift layer within the drift layer, the semiconductor region being deeper than the trench. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-117859 Summary of the Invention [Problem to be solved by the invention]

[0004] There are semiconductor devices that use wide bandgap semiconductor materials with a wider bandgap than silicon in their epitaxial layers. Due to the larger bandgap, these wide bandgap semiconductor devices can increase the breakdown voltage of the epitaxial layer even if the epitaxial layer is thin. In other words, wide bandgap semiconductor devices can achieve both reduced on-resistance and improved breakdown voltage, which are in a trade-off relationship.

[0005] Therefore, wide bandgap semiconductor devices can operate at high voltages. However, for example, in a wide bandgap semiconductor device including a field-effect transistor in which a gate electrode is filled in a trench formed in an epitaxial layer via a gate insulating film, the electric field strength near the corners of the bottom of the trench increases as the operating voltage increases. This can result in dielectric breakdown of the gate insulating film formed in the trench.

[0006] For this reason, in wide bandgap semiconductor devices, it is necessary to suppress the electric field concentration near the bottom of the trench, and therefore, the formation of a punch-through stopper layer of the opposite conductivity type to the epitaxial layer in the epitaxial layer deeper than the trench is being considered.

[0007] In this regard, the present inventors have newly discovered that misalignment between a gate electrode formed in a trench and a punch-through stopper layer formed in an epitaxial layer is a factor that causes fluctuations in the characteristics of wide bandgap semiconductor devices.

[0008] For this reason, there is a demand for a semiconductor device that has high robustness against misalignment between the gate electrode and the punch-through stopper layer.

[0009] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0010] A semiconductor device in one embodiment includes a punch-through stopper layer whose planar shape is formed from patterns having periodicity in each of the X and Y directions that form the plane, on the premise that trenches extending in the Y direction out of the X and Y directions that form the plane are arranged at predetermined intervals in the X direction. [Effects of the Invention]

[0011] According to one embodiment, it is possible to provide a wide bandgap semiconductor device that is highly robust against misalignment between the gate electrode (trench) and the punch-through stopper layer. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a diagram showing the configuration of a wide bandgap semiconductor device including a MOSFET with a trench gate structure. [Figure 2]10A and 10B are diagrams illustrating an example of forming a punch-through stopper layer. [Figure 3] 10A and 10B are diagrams illustrating an example of forming a punch-through stopper layer. [Figure 4] FIG. 10 is a diagram showing the planar positional relationship between a trench and a punch-through stopper layer in the related art. [Figure 5] FIG. 1 is a diagram showing one shot in photolithography for forming a trench and a punch-through stopper layer. [Figure 6] FIG. 10 is a diagram for calculating δθ. [Figure 7] 1 is a diagram showing a semiconductor chip according to a first embodiment. [Figure 8] FIG. 2 is an enlarged view of a cell block. [Figure 9] 10 is a diagram showing an example in which a relative misalignment δY occurs in the Y direction between the trench and the punch-through stopper layer. FIG. [Figure 10] 10 is a diagram showing an example in which a relative misalignment δX occurs in the X direction between the trench and the punch-through stopper layer. FIG. [Figure 11] FIG. 10 is a diagram illustrating a first modification of the first embodiment. [Figure 12] FIG. 10 is a diagram illustrating a second modification of the first embodiment. [Figure 13] FIG. 10 is a diagram showing an area of ​​interest in a cell block according to a second embodiment. [Figure 14] FIG. 10 is a diagram showing a pattern configuration A. [Figure 15] FIG. 10 is a diagram showing a pattern configuration B. [Figure 16] FIG. 10 is a diagram for explaining a third embodiment. [Figure 17] FIG. 10 is a diagram showing a process for realizing the configuration A of the third embodiment. [Figure 18] FIG. 18 is a diagram showing a step following FIG. 17. [Figure 19] FIG. 19 is a diagram showing a step following FIG. 18. [Figure 20] FIG. 20 is a diagram showing a step following FIG. 19. [Figure 21]FIG. 10 is a diagram showing a process for realizing the configuration B of the third embodiment. [Figure 22] FIG. 22 is a diagram showing a step following FIG. 21. [Figure 23] FIG. 10 is a diagram showing a process for realizing the configuration C of the third embodiment. [Figure 24] FIG. 24 is a diagram showing a step following FIG. 23. [Figure 25] FIG. 25 is a diagram showing a step following FIG. 24. [Figure 26] FIG. 10 is a diagram showing a process for realizing the configuration D of the third embodiment. [Figure 27] FIG. 27 is a diagram showing a step following FIG. 26. [Figure 28] FIG. 28 shows a step following FIG. 27. [Figure 29] FIG. 29 shows a step following FIG. 28. DETAILED DESCRIPTION OF THE INVENTION

[0013] In all the drawings for explaining the embodiments, the same components are generally designated by the same reference numerals, and repeated explanations thereof will be omitted. In addition, hatching may be used even in plan views to make the drawings easier to understand.

[0014] Semiconductor devices having epitaxial layers mainly composed of wide bandgap semiconductor materials with a bandgap larger than that of silicon (hereinafter referred to as wide bandgap semiconductor devices) have attracted attention because a wide bandgap means high dielectric breakdown strength, making it easier to achieve high breakdown voltage.

[0015] Furthermore, if the semiconductor material itself has a high dielectric breakdown strength, the breakdown voltage can be ensured even if the epitaxial layer (also called the drift layer) that maintains the breakdown voltage is thin. For this reason, for example, by thinning the epitaxial layer and increasing the impurity concentration, the on-resistance of a wide bandgap semiconductor device can be reduced.

[0016] That is, wide bandgap semiconductor devices are advantageous in that they can achieve both improved breakdown voltage and reduced on-resistance, which are in a trade-off relationship with each other. Therefore, wide bandgap semiconductor devices are expected to be semiconductor devices that can achieve high performance.

[0017] Examples of semiconductor materials with a band gap larger than that of silicon include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond, etc. The following description focuses on silicon carbide.

[0018] <Background of the review> <<Usefulness of punch-through stopper layer>> For example, a wide bandgap semiconductor device includes a field effect transistor (hereinafter sometimes referred to as a MOSFET) with a trench gate structure in which a gate electrode is filled in a trench formed in an epitaxial layer on a semiconductor substrate via a gate insulating film.

[0019] Fig. 1 is a diagram showing the configuration of a wide bandgap semiconductor device 100 including a MOSFET with a trench gate structure. As shown in Fig. 1, the wide bandgap semiconductor device 100 has a drain electrode DE, a semiconductor substrate SUB, an epitaxial layer EPI, a trench TR, a gate insulating film GOX, a gate electrode GE, a source region SR, a body contact region BC, a channel layer CH, an insulating layer IL, a source electrode SE, and a surface protective film PAS.

[0020] The semiconductor substrate SUB, the epitaxial layer EPI, and the source region SR are made of n-type semiconductor regions, while the body contact region BC and the channel layer CH are made of p-type semiconductor regions.

[0021] To turn on the MOSFET, a gate voltage equal to or greater than the threshold voltage is applied to the gate electrode GE. As a result, a channel consisting of an inversion layer (n-type semiconductor region) is formed in the channel layer CH that contacts the side surface of the trench TR. This causes current to flow through the drain electrode DE → semiconductor substrate SUB → epitaxial layer EPI → channel (inversion layer) → source region SR → source electrode SE. In this way, the MOSFET turns on.

[0022] To turn off the MOSFET, a gate voltage lower than the threshold voltage is applied to the gate electrode GE. As a result, the channel consisting of the inversion layer formed in the channel layer CH adjacent to the side of the trench TR disappears. This cuts off the current path between the drain electrode DE and the source electrode SE. In this way, the MOSFET turns off.

[0023] When the MOSFET is in an off state, for example, 0 V is applied to the source electrode SE, source region SR, body contact region BC, and channel layer CH. Meanwhile, a positive potential (several hundred to several thousand volts) is applied to the drain electrode DE, semiconductor substrate SUB, and epitaxial layer EPI. As a result, a reverse bias is applied to the pn junction between the channel layer CH (p-type semiconductor region) and the epitaxial layer EPI (n-type semiconductor region). Therefore, a depletion layer extends from the pn junction into the channel layer CH and from the pn junction into the epitaxial layer EPI. An electric field is generated in this depletion layer in response to the source-drain voltage applied between the source electrode SE and the drain electrode DE. In particular, in the wide bandgap semiconductor device 100, the source-drain voltage is high. Therefore, the electric field strength in the depletion layer increases. As a result, for example, in FIG. 1, the electric field strength increases near the bottom of the trench TR in the depletion layer extending into the epitaxial layer EPI. This may cause a dielectric breakdown of the gate insulating film GOX formed in the trench TR.

[0024] Therefore, in order to suppress the electric field concentration near the bottom of the trench TR, it is being considered to form a punch-through stopper layer (p-type semiconductor region) of the opposite conductivity type to that of the epitaxial layer EPI in the epitaxial layer EPI deeper than the trench TR.

[0025] In this case, in the region where the punch-through stopper layer is disposed, the voltage applied to the drain is mainly applied to the pn junction formed by the punch-through stopper layer and the epitaxial layer EPI, so depletion of the pn junction formed by the upper channel layer CH and the epitaxial layer EPI is suppressed. Similarly, the increase in the electric field at the bottom of the trench TR is also suppressed. Therefore, by forming the punch-through stopper layer in the epitaxial layer EPI, it is possible to suppress dielectric breakdown of the gate insulating film GOX formed in the trench TR.

[0026] FIG. 2 is a diagram showing an example of forming the punch-through stopper layer PTS1.

[0027] In FIG. 2, the punch-through stopper layer PTS1 is formed in the epitaxial layer EPI below the trench TR. In this case, an increase in the electric field strength near the bottom of the trench TR can be effectively suppressed. On the other hand, if the punch-through stopper layer PTS1 is formed at the position shown in FIG. 2, it will obstruct the current path of the MOSFET. Therefore, if the punch-through stopper layer PTS1 is formed in the epitaxial layer EPI below the trench TR, the electric field concentration near the bottom of the trench TR can be efficiently alleviated, but the on-resistance of the MOSFET will increase.

[0028] FIG. 3 is a diagram showing an example of forming the punch-through stopper layer PTS2.

[0029] 3, the punch-through stopper layer PTS2 is formed in the epitaxial layer EPI away from below the trench TR. In other words, in a cross-sectional view, the punch-through stopper layer PTS2 is formed at a position that does not overlap with the trench TR. In this case, the punch-through stopper layer PTS2 is less likely to obstruct the current path of the MOSFET, and therefore an increase in the on-resistance of the MOSFET due to the provision of the punch-through stopper layer PTS2 can be suppressed. On the other hand, the effect of suppressing an increase in the electric field strength near the bottom of the trench TR is smaller than that of the punch-through stopper layer PTS1 shown in FIG.

[0030] Therefore, the following related techniques are being studied regarding the punch-through stopper layer.

[0031] <<Description of Related Art>> In this specification, the term "related art" refers to art that is not publicly known, but has problems that the inventors have discovered, and is a technology that serves as a premise for the present disclosure.

[0032] FIG. 4 is a diagram showing the planar positional relationship between the trench TR and the punch-through stopper layer in the related technology. In FIG. 4, the punch-through stopper layer in the related technology is composed of the punch-through stopper layer PTS1 shown in FIG. 2 and the punch-through stopper layer PTS2 shown in FIG. 3. That is, the AA cross section of FIG. 4 is FIG. 2, and the BB cross section of FIG. 4 is FIG. 3. In this way, the related technology has the punch-through stopper layer PTS1 and the punch-through stopper layer PTS2. The punch-through stopper layer PTS1 is formed below the trench TR. On the other hand, the punch-through stopper layer PTS2 is formed at a position that does not overlap with the trench TR in a plan view.

[0033] As a result, according to the related technology, the on-resistance of the MOSFET can be reduced more than when all punch-through stopper layers are configured from the punch-through stopper layer PTS1. Also, according to the related technology, the electric field concentration near the bottom of the trench TR can be alleviated more efficiently than when all punch-through stopper layers are configured from the punch-through stopper layer PTS2.

[0034] Therefore, the related technology can alleviate the electric field concentration near the bottom of the trench TR and reduce the on-resistance of the MOSFET at the same time.

[0035] <<Consideration of improvements in related technologies>> However, the present inventors have newly discovered that misalignment between the gate electrode formed in the trench and the punch-through stopper layer formed in the epitaxial layer is a factor that causes fluctuations in the characteristics of wide bandgap semiconductor devices.

[0036] For example, in FIG. 4, if the formation positions of the punch-through stopper layers PTS1 and PTS2 are misaligned in the X direction, the relative positional relationship between the trench TR and the punch-through stopper layer PTS1 and the relative positional relationship between the trench TR and the punch-through stopper layer PTS2 change. As a result, the characteristics of the wide bandgap semiconductor device fluctuate. That is, the related art has room for improvement in terms of ensuring robustness against misalignment between the gate electrode formed in the trench and the punch-through stopper layer formed in the epitaxial layer. For this reason, a wide bandgap semiconductor device with high robustness against misalignment between the gate electrode (trench) and the punch-through stopper layer is desired. That is, a technical concept for overcoming the room for improvement in the related art is desired.

[0037] <Components of misalignment> First, before explaining the technical concept, the components of misalignment that should be considered as misalignment between the trench and the punch-through stopper layer will be explained.

[0038] For example, in the XY plane, the independent components of the misalignment between the trench and the punch-through stopper layer are misalignment δX in the X direction, misalignment δY in the Y direction, and misalignment δθ in the θ direction. Therefore, in order to realize a wide bandgap semiconductor device that is highly robust against misalignment between the trench and the punch-through stopper layer, it is important to find a planar shape of the punch-through stopper layer that can reduce the change in the relative positional relationship between the trench and the punch-through stopper layer caused by δX, δY, and δθ.

[0039] In this regard, it is noted that δθ can be neglected.

[0040] FIG. 5 is a diagram showing one shot ST in photolithography technology for forming a trench and a punch-through stopper layer. In FIG. 5, one shot ST, which is an exposure area, is, for example, 1000 μm × 1000 μm in size. The exposure area includes alignment marks AM1 and AM2. The alignment marks AM1 and AM2 align the trench and the punch-through stopper layer. Misalignment between the alignment marks AM1 and AM2 causes δX, δY, and δθ. δθ will be estimated below.

[0041] Fig. 6 is a diagram for calculating Δθ. As shown in Fig. 6, the position coordinates of alignment mark AM1 and alignment mark AM2 are defined. In this case, θ1 is expressed by the following formula 1. Furthermore, θ2 is expressed by the following formula 2.

[0042]

number

[0043]

number

[0044] From the above, when considering the XY plane, the non-negligible independent components of the misalignment between the trench and the punch-through stopper layer are δX and δY. Because δθ can be ignored in this way, in order to realize a wide bandgap semiconductor device that is highly robust against misalignment between the trench and the punch-through stopper layer, it is necessary to find a planar shape of the punch-through stopper layer that can reduce the change in the relative positional relationship between the trench and the punch-through stopper layer that is caused by δX and δY.

[0045] Therefore, the following will describe a technical concept regarding the planar shape of the punch-through stopper layer that can reduce the change in the relative positional relationship between the trench and the punch-through stopper layer caused by δX and δY.

[0046] <Basic philosophy> The basic concept is to configure the planar shape of the punch-through stopper layer from a pattern that has periodicity in both the X and Y directions that form the plane, assuming that trenches extending in the Y direction of the X and Y directions that form the plane are arranged at predetermined intervals in the X direction. As a result, even if a relative misalignment occurs between the trenches and the punch-through stopper layer, the change in the relative positional relationship between the trenches and the punch-through stopper layer due to the misalignment can be reduced when viewed as a whole chip. As a result, according to this basic concept, it is possible to suppress fluctuations in the characteristics of the wide bandgap semiconductor device. In other words, according to this basic concept, it is possible to provide a wide bandgap semiconductor device that is highly robust against misalignment between the trenches and the punch-through stopper layer.

[0047] For example, in a plan view, the punch-through stopper layer is divided into a plurality of portions. Each of the plurality of portions has the same size. Some of the plurality of portions are adjacent to each other. The basic idea is that a first pattern having the same planar shape is formed in each of the adjacent portions. The first pattern is made up of one or more sub-patterns. Here, in a plan view, each of the one or more sub-patterns constituting the first pattern partially overlaps one of the plurality of gate electrodes (multiple trenches).

[0048] As a result, assuming that the trench and the punch-through stopper layer have portions that partially overlap in plan view, the planar shape of the punch-through stopper layer is composed of a pattern that has periodicity in both the X direction and the Y direction that make up the plane.

[0049] For example, the planar shape of the punch-through stopper layer forms a geometric pattern consisting of repetitions of the above-described first pattern as a unit pattern.

[0050] In this specification, the term "geometric pattern" refers to a certain type of pattern, and is specifically defined to have the following meaning. That is, a "geometric pattern" refers to a pattern created by continuously combining and arranging simple geometric components, such as polygons (e.g., triangles, squares, and hexagons), circles, ellipses, and straight lines, while performing operations such as translation, inversion, and rotation. A "geometric pattern" can be infinitely expanded by repeating the same operations. A "geometric pattern" can also be described as a figure generated by a geometric curve that can be expressed by a periodic function.

[0051] Based on the above, the first pattern is composed of one or more subpatterns including any of straight lines, rectangles, circles, or curves. In particular, the first pattern is composed of a tessellable pattern. Here, the "tessellable pattern" as used in this specification is a pattern that can be used to tile a surface using a finite number of plane figures without adjacent plane figures overlapping each other and without gaps between adjacent plane figures. Note that this does not exclude the provision of openings inside the plane figures.

[0052] For example, the first pattern can be composed of a tessellable pattern. In this case, the first pattern is composed of a plurality of subpatterns, and the plurality of subpatterns are composed of a combination of a plurality of single figures. In this case, the single figure is a triangle, a rectangle, or a hexagon. Furthermore, the first pattern can also be composed of a tessellable pattern using a combination of multiple types of figures, rather than the combination of multiple single figures described above. Specifically, the first pattern is composed of a plurality of subpatterns, and the plurality of subpatterns are composed of a combination of multiple types of figures.

[0053] The basic concept is based on the premise that trenches extending in the Y direction of the X and Y directions constituting a plane are arranged at predetermined intervals in the X direction. The basic concept also assumes that, in plan view, the trenches and the punch-through stopper layer have portions that partially overlap. A specific example of this premise is the following configuration: That is, each of the multiple gate electrodes extends in a first direction (Y direction), and, in plan view, each of one or more sub-patterns constituting the first pattern extends in a second direction (X direction) that intersects with the first direction. This satisfies the premise.

[0054] The punch-through stopper layer may have not only the first pattern, but also a ring-shaped second pattern surrounding the first pattern in a plan view in each of the first and second portions of the punch-through stopper layer. The first pattern is connected to the second pattern, for example. A ground potential is supplied to the second pattern. Therefore, the configuration of the punch-through stopper layer in the basic concept includes a mode in which the ground potential is supplied.

[0055] The following describes a first embodiment, which is an example that embodies the basic idea.

[0056] <First Embodiment> <<Configuration of Wide Bandgap Semiconductor Device>> FIG. 7 is a diagram showing the semiconductor chip CHP according to the first embodiment.

[0057] 7, the semiconductor chip CHP has an active region ACT, a floating ring FR1, and a floating ring FR2. The active region ACT is a region in which semiconductor elements such as MOSFETs are formed. The floating ring FR1 is formed to surround the active region ACT in a planar view. The floating ring FR2 is formed to surround the floating ring FR1 in a planar view. The floating rings FR1 and FR2 are provided to ensure the dielectric strength voltage of the semiconductor chip CHP.

[0058] The active region ACT has a plurality of trenches TR. Each of the plurality of trenches TR extends in the Y direction. The plurality of trenches TR are formed to be aligned in the X direction at predetermined intervals. In this embodiment, the active region ACT has a plurality of cell blocks CB. For example, as shown in FIG. 7, the plurality of cell blocks CB include a cell block CB1 and a cell block CB2 adjacent to each other. The cell block CB1 is a region in which a first portion of the punch-through stopper layer is formed. The cell block CB2 is a region in which a second portion of the punch-through stopper layer is formed.

[0059] The cell block CB1 and the cell block CB2 are the same size. A first pattern having the same planar shape is formed in each of the adjacent cell blocks CB1 and CB2. The following describes the configuration of the cell block CB on which the first pattern is formed.

[0060] 8 is an enlarged view of the cell block CB, which includes a trench TR, a pattern PTN1, and a pattern PTN2.

[0061] The trenches TR extend in the Y direction and are arranged at predetermined intervals in the X direction. In Fig. 8, four trenches TR are shown arranged at predetermined intervals in the X direction.

[0062] The pattern PTN1 is composed of one or more subpatterns. For example, in FIG. 8, the pattern PTN1 is composed of subpatterns SPN1, SPN2, SPN3, SPN4, and SPN5. That is, the pattern PTN1 shown in FIG. 8 is composed of five subpatterns. Each of the subpatterns SPN1, SPN2, SPN3, SPN4, and SPN5 is a pattern of the punch-through stopper layer PTS. Therefore, the pattern PTN1 is composed of a combination of patterns of the punch-through stopper layer PTS. For example, in FIG. 8, the pattern PTN1 is composed of five subpatterns, each of which is composed of diagonal straight lines.

[0063] Each of the sub-patterns SPN1, SPN2, SPN3, SPN4, and SPN5 constituting the pattern PTN1 partially overlaps with one of the plurality of trenches TR (four trenches TR in FIG. 8). In other words, taking into consideration that a gate electrode is formed inside the trench TR, each of the sub-patterns SPN1, SPN2, SPN3, SPN4, and SPN5 partially overlaps with one of the plurality of gate electrodes (four gate electrodes in FIG. 8). Specifically, in FIG. 8, each of the plurality of trenches TR (multiple gate electrodes) extends in the Y direction, and in a plan view, each of the five sub-patterns constituting the pattern PTN1 extends in the X direction intersecting with the Y direction.

[0064] The pattern PTN2 has a ring shape surrounding the pattern PTN1 in a plan view. That is, the pattern PTN2 has a ring shape surrounding the five sub-patterns that make up the pattern PTN1 in a plan view. The pattern PTN2 is connected to the pattern PTN1. That is, the planar shape of the punch-through stopper layer PTS is composed of a combination of the pattern PTN1 consisting of five sub-patterns and the pattern PTN2 having a ring shape that surrounds the pattern PTN1 in a plan view.

[0065] The cross-sectional view taken along line AA in Fig. 8 is almost the same as Fig. 2. Moreover, the cross-sectional view taken along line BB in Fig. 8 is almost the same as Fig. 3. Note that the punch-through stopper layer PTS1 in Fig. 2 becomes the punch-through stopper layer PTS in the cross-sectional view taken along line AA in Fig. 8. Moreover, the punch-through stopper layer PTS2 in Fig. 3 becomes the punch-through stopper layer PTS in the cross-sectional view taken along line BB in Fig. 8.

[0066] The wide band gap semiconductor device in the first embodiment has a drain electrode DE, a semiconductor substrate SUB, an epitaxial layer EPI, a trench TR, a gate insulating film GOX, a gate electrode GE, a source region SR, a body contact region BC, a channel layer CH, a punch-through stopper layer PTS, an insulating layer IL, a source electrode SE, and a surface protective film PAS.

[0067] The semiconductor substrate SUB is made of, for example, silicon carbide doped with n-type impurities (donors). A drain electrode DE is formed below the lower surface of the semiconductor substrate SUB. Meanwhile, an epitaxial layer EPI is formed on the upper surface of the semiconductor substrate SUB. The epitaxial layer EPI is an n-type semiconductor layer made of silicon carbide.

[0068] The channel layer CH is a p-type semiconductor layer formed in the epitaxial layer EPI. The trench TR is formed to penetrate the channel layer CH and reach the inside of the epitaxial layer EPI. The gate insulating film GOX is formed on the inner wall of the trench TR. The gate electrode GE is filled in the trench TR via the gate insulating film GOX.

[0069] The punch-through stopper layer PTS is formed in the epitaxial layer EPI. The punch-through stopper layer PTS is a p-type semiconductor layer formed at a position deeper than the trench TR. The source region SR is an n-type semiconductor region formed in the channel layer CH. The source region SR is in contact with the trench TR. The body contact region BC is a p-type semiconductor region formed in the channel layer CH. The impurity concentration of the body contact region BC is higher than the impurity concentration of the channel layer CH.

[0070] The source electrode SE is formed on the insulating layer IL and in a contact hole penetrating the insulating layer IL. The source electrode SE is electrically connected to the source region SR and the body contact region BC. Therefore, the source region SR and the body contact region BC are electrically connected via the source electrode SE. A surface protective film PAS is formed on the source electrode SE. In this manner, the wide bandgap semiconductor device according to the first embodiment is configured.

[0071] <<Features of the First Embodiment>> Next, the features of the first embodiment will be described.

[0072] The first embodiment is characterized by the premise that, as shown in FIG. 7, a plurality of cell blocks CB of the same size are included in a plan view. The feature also assumes that a pattern PTN1 having the same planar shape is formed in each of the plurality of cell blocks CB. Under these assumptions, as shown in FIG. 8, the pattern PTN1 is composed of a plurality of subpatterns. In FIG. 8, the plurality of subpatterns are subpatterns SPN1, SPN2, SPN3, SPN4, and SPN5. Each of the plurality of subpatterns constituting the pattern PTN1 partially overlaps one of the plurality of trenches TR in a plan view. Thus, the feature is that the planar shape of the punch-through stopper layer PTS constitutes the pattern PTN1 having the above-described configuration.

[0073] Thus, according to the first embodiment, on the assumption that the trench TR and the punch-through stopper layer PTS have portions that partially overlap in plan view, the planar shape of the punch-through stopper layer PTS can be configured from a pattern that has periodicity in each of the X and Y directions that form the plane. As a result, according to the first embodiment, even if a relative misalignment (δX or δY) occurs between the trench TR and the punch-through stopper layer PTS, it is possible to reduce a change in the relative positional relationship between the trench TR and the punch-through stopper layer PTS caused by the misalignment when viewed as a whole chip. As a result, according to the characteristic point, it is possible to suppress fluctuations in the characteristics of the wide bandgap semiconductor device. In other words, according to the characteristic point, it is possible to provide a wide bandgap semiconductor device that is highly robust against misalignment between the trench TR and the punch-through stopper layer PTS.

[0074] The following provides a detailed explanation.

[0075] In Fig. 8, there is no relative misalignment between the trench TR and the punch-through stopper layer PTS. In Fig. 8, there is a portion in the cell block CB that corresponds to the positional relationship between the trench TR and the punch-through stopper layer PTS shown in the AA cross section (Fig. 2). In addition, in Fig. 8, there is also a portion that corresponds to the positional relationship between the trench TR and the punch-through stopper layer PTS shown in the BB cross section (Fig. 3).

[0076] Fig. 9 is a diagram showing an example in which a relative misalignment δY occurs in the Y direction between the trench TR and the punch-through stopper layer PTS. Fig. 9 also shows a portion in the cell block CB that corresponds to the positional relationship between the trench TR and the punch-through stopper layer PTS shown in the AA cross section (Fig. 2). Fig. 9 also shows a portion that corresponds to the positional relationship between the trench TR and the punch-through stopper layer PTS shown in the BB cross section (Fig. 3).

[0077] Fig. 10 is a diagram showing an example in which a relative misalignment δX occurs in the X direction between the trench TR and the punch-through stopper layer PTS. Fig. 10 also shows a portion in the cell block CB that corresponds to the positional relationship between the trench TR and the punch-through stopper layer PTS shown in the AA cross section (Fig. 2). Fig. 10 also shows a portion that corresponds to the positional relationship between the trench TR and the punch-through stopper layer PTS shown in the BB cross section (Fig. 3).

[0078] 8, 9, and 10, even if a relative misalignment (δX or δY) occurs between the trench TR and the punch-through stopper layer PTS, there are portions in the cell block CB that correspond to the positional relationship between the trench TR and the punch-through stopper layer PTS shown in the AA cross section (FIG. 2) and to the positional relationship between the trench TR and the punch-through stopper layer PTS shown in the BB cross section (FIG. 3). This means that, when viewed as a whole chip, changes in the relative positional relationship between the trench TR and the punch-through stopper layer PTS due to misalignment can be reduced. Therefore, according to the first embodiment, it is possible to suppress fluctuations in the characteristics of the wide bandgap semiconductor device. In other words, according to the first embodiment, it is possible to provide a wide bandgap semiconductor device that is highly robust against misalignment between the trench TR and the punch-through stopper layer PTS.

[0079] <<First Modification of First Embodiment>> FIG. 11 is a diagram illustrating a first modification of the first embodiment.

[0080] 11, the planar shape of the punch-through stopper layer PTS forms a pattern PTN1. In Modification 1, the pattern PTN1 is made up of sub-patterns SPN1, SPN2, SPN3, SPN4, SPN5, SPN6, SPN7, SPN8, SPN9, and SPN10.

[0081] Even in the first modification configured as described above, provided that the trenches TR and the punch-through stopper layer PTS have portions that partially overlap in a planar view, the planar shape of the punch-through stopper layer PTS can be configured from a pattern that has periodicity in each of the X and Y directions that form the plane. As a result, even in the first modification, even if a relative misalignment (δX or δY) occurs between the trenches TR and the punch-through stopper layer PTS, it is possible to reduce changes in the relative positional relationship between the trenches TR and the punch-through stopper layer PTS due to the misalignment when viewed as a whole chip. This makes it possible to suppress fluctuations in the characteristics of the wide bandgap semiconductor device, even with the first modification. In other words, even with the first modification, it is possible to provide a wide bandgap semiconductor device that is highly robust against misalignment between the trenches TR and the punch-through stopper layer PTS.

[0082] <<Modification 2 of Embodiment 1>> FIG. 12 is a diagram illustrating a second modification of the first embodiment.

[0083] 12, the planar shape of the punch-through stopper layer PTS forms a pattern PTN1. In Modification 2, the pattern PTN1 is made up of a plurality of sub-patterns SPN, and the plurality of sub-patterns SPN are made up of a combination of a plurality of single figures. That is, the sub-pattern SPN has a hexagonal shape (single figure), and the plurality of sub-patterns SPN form a "plane-fillable pattern."

[0084] Even in the second modification configured as above, provided that the trenches TR and the punch-through stopper layer PTS have portions that partially overlap in plan view, the planar shape of the punch-through stopper layer PTS can be configured from a pattern that has periodicity in each of the X and Y directions that form the plane. As a result, even in the second modification, even if a relative misalignment (δX or δY) occurs between the trenches TR and the punch-through stopper layer PTS, it is possible to reduce changes in the relative positional relationship between the trenches TR and the punch-through stopper layer PTS due to the misalignment when viewed as a whole chip. This makes it possible to suppress fluctuations in the characteristics of the wide bandgap semiconductor device, even with the second modification. In other words, even with the second modification, it is possible to provide a wide bandgap semiconductor device that is highly robust against misalignment between the trenches TR and the punch-through stopper layer PTS.

[0085] <Embodiment 2> 13 is a diagram showing an area RA in the outermost cell block CB that is the focus of attention in the second embodiment. In the second embodiment, the configuration of a pattern PTN2 in the area RA will be described. The configuration of the pattern PTN2 may be either configuration A or configuration B shown below.

[0086] <<Configuration A of Second Embodiment>> 14 is a diagram showing a configuration A of the pattern PTN2. As shown in Fig. 14, in the configuration A, an offset OS is provided between the center line CL in the Y direction of the pattern PTN2 extending in the X direction and the trench TR. As a result, the configuration A can ensure a sufficient margin for misalignment ±δY in the Y direction between the trench TR and the pattern PTN2 (punch-through stopper layer).

[0087] <<Configuration B of Second Embodiment>> 15 is a diagram showing a configuration B of the pattern PTN2. As shown in Fig. 15, in the configuration B, there is no offset between the center line CL in the Y direction of the pattern PTN2 extending in the X direction and the trench TR. This allows the chip size to be reduced.

[0088] <Third Embodiment> For example, in the related art shown in Figure 4, the potentials of the punch-through stopper layers PTS1 and PTS2 are floating potentials. In this case, repeated switching of the MOSFET causes a temporary potential shift due to the accumulation of holes, particularly in the punch-through stopper layer PTS1. This affects the dynamic characteristics of the wide bandgap semiconductor device including the MOSFET.

[0089] One possible solution is to fix the potential of the punch-through stopper layer to ground potential (0V). This fixes the potential of the punch-through stopper layer to ground potential, which can suppress potential shifts in the punch-through stopper layer even when the MOSFET switches repeatedly. As a result, the impact on the dynamic characteristics of wide bandgap semiconductor devices including MOSFETs is reduced.

[0090] 8 showing the first embodiment, the punch-through stopper layer PTS has a planar shape that is made up of a pattern PTN1 made up of a plurality of sub-patterns SPN1 to SPN5 and a ring-shaped pattern PTN2 that surrounds the pattern PTN1. If a configuration can be realized in which the ground potential is supplied to the punch-through stopper layer PTS configured in this way, the punch-through stopper layer PTS can be fixed to the ground potential.

[0091] An example of a configuration in which a ground potential is supplied to the punch-through stopper layer PTS will be described below, specifically with reference to a manufacturing process diagram of the AA cross section in FIG.

[0092] <<Configuration A of Third Embodiment>> 17, an epitaxial layer EPI1 is formed on an n-type semiconductor substrate SUB by epitaxial growth. Next, aluminum, which is a p-type impurity (acceptor), is introduced into the epitaxial layer EPI1 by photolithography and ion implantation. This forms a punch-through stopper layer PTS in the epitaxial layer EPI1.

[0093] 18, an epitaxial layer EPI2 is formed by epitaxial growth on the epitaxial layer EPI1 on which the punch-through stopper layer PTS has been formed. After that, a p-type plug PLG is formed in the epitaxial layer EPI2 by photolithography and ion implantation. The p-type plug PLG is connected to the punch-through stopper layer PTS.

[0094] 19, a p-type impurity is introduced into the epitaxial layer EPI2 by using a photolithography technique and an ion implantation method to form a channel layer CH, and an n-type impurity is introduced into the channel layer CH by using a photolithography technique and an ion implantation method to form a source region SR.

[0095] 20, a trench TR is formed by using photolithography and etching. Then, a gate insulating film GOX is formed on the inner wall of the trench TR, and then a gate electrode GE is formed in the trench TR with the gate insulating film GOX interposed therebetween. In this manner, the epitaxial layer EPI1, punch-through stopper layer PTS, epitaxial layer EPI2, p-type plug PLG, channel layer CH, source region SR, trench TR, gate insulating film GOX, and gate electrode GE can be formed.

[0096] Here, the source region SR and the channel layer CH are electrically connected and supplied with the ground potential. That is, the ground potential is supplied to each of the source region SR and the channel layer CH. The punch-through stopper layer PTS is electrically connected to the channel layer CH, to which the ground potential is supplied, by a p-type plug PLG. Therefore, the ground potential is supplied to the punch-through stopper layer PTS. In this way, a configuration in which the ground potential is supplied to the punch-through stopper layer PTS can be realized.

[0097] The advantage of manufacturing such structure A is that the p-type plug PLG can be formed by a single high-energy ion implantation, which simplifies the manufacturing process.

[0098] <<Configuration B of Third Embodiment>> 17, an epitaxial layer EPI1 is formed on an n-type semiconductor substrate SUB by epitaxial growth. Next, aluminum, which is a p-type impurity (acceptor), is introduced into the epitaxial layer EPI1 by photolithography and ion implantation. This forms a punch-through stopper layer PTS in the epitaxial layer EPI1.

[0099] 21, a lower epitaxial layer EPI2B in which a punch-through stopper layer PTS is formed is formed. By using photolithography and ion implantation, a p-type plug PLG1 (lower-layer plug) is formed in the lower epitaxial layer EPI2B. The p-type plug PLG1 is connected to the punch-through stopper layer PTS.

[0100] Next, a middle epitaxial layer EPI2M is formed on the lower epitaxial layer EPI2B in which the p-type plug PLG1 has been formed. A p-type plug PLG2 (middle-layer plug) is formed in the middle epitaxial layer EPI2M using photolithography and ion implantation. The p-type plug PLG2 is connected to the p-type plug PLG1. After that, an upper epitaxial layer EPI2U is formed on the middle epitaxial layer EPI2M in which the p-type plug PLG2 has been formed. The lower epitaxial layer EPI2B, the middle epitaxial layer EPI2M, and the upper epitaxial layer EPI2U constitute the epitaxial layer EPI2.

[0101] 22, a p-type impurity is introduced into the upper epitaxial layer EPI2U by using a photolithography technique and an ion implantation method to form a channel layer CH. Then, an n-type impurity is introduced into the channel layer CH by using a photolithography technique and an ion implantation method to form a source region SR.

[0102] Next, a trench TR is formed using photolithography and etching. A gate insulating film GOX is formed on the inner wall of the trench TR, and then a gate electrode GE is formed in the trench TR via the gate insulating film GOX. In this manner, the epitaxial layer EPI1, punch-through stopper layer PTS, lower epitaxial layer EPI2B, middle epitaxial layer EPI2M, upper epitaxial layer EPI2U, p-type plug PLG1, p-type plug PLG2, channel layer CH, source region SR, trench TR, gate insulating film GOX, and gate electrode GE are formed.

[0103] The source region SR and the channel layer CH are electrically connected and supplied with the ground potential. That is, the ground potential is supplied to each of the source region SR and the channel layer CH. The punch-through stopper layer PTS is electrically connected to the channel layer CH, to which the ground potential is supplied, via the p-type plugs PLG1 and PLG2. Therefore, the ground potential is supplied to the punch-through stopper layer PTS. In this way, a configuration in which the ground potential is supplied to the punch-through stopper layer PTS can be realized.

[0104] An advantage of manufacturing such a structure B is that the p-type plugs PLG1 and PLG2 can be formed by low-energy ion implantation.

[0105] <<Configuration C of Third Embodiment>> 17, an epitaxial layer EPI1 is formed on an n-type semiconductor substrate SUB by epitaxial growth. Next, aluminum, which is a p-type impurity (acceptor), is introduced into the epitaxial layer EPI1 by photolithography and ion implantation. This forms a punch-through stopper layer PTS in the epitaxial layer EPI1.

[0106] 23, an epitaxial layer EPI2 is formed on the epitaxial layer EPI1 on which the punch-through stopper layer PTS has been formed by epitaxial growth. Then, as shown in Fig. 24, a p-type impurity is introduced into the epitaxial layer EPI2 by photolithography and ion implantation to form a channel layer CH. Then, an n-type impurity is introduced into the channel layer CH by photolithography and ion implantation to form a source region SR.

[0107] Next, as shown in FIG. 25, a trench TR is formed using photolithography and etching. A gate insulating film GOX is formed on the inner wall of the trench TR, and then a gate electrode GE and a dummy electrode DMY that does not function as a gate electrode are formed in the trench TR via the gate insulating film GOX. A p-type plug PLG containing the dummy electrode DMY is then formed using photolithography and oblique ion implantation. The p-type plug PLG is connected to the punch-through stopper layer PTS. In this manner, the epitaxial layer EPI1, the punch-through stopper layer PTS, the epitaxial layer EPI2, the p-type plug PLG, the channel layer CH, the source region SR, the trench TR, the gate insulating film GOX, the gate electrode GE, and the dummy electrode DMY can be formed.

[0108] The source region SR and the channel layer CH are electrically connected and supplied with the ground potential. That is, the ground potential is supplied to each of the source region SR and the channel layer CH. The punch-through stopper layer PTS is electrically connected to the channel layer CH, to which the ground potential is supplied, by a p-type plug PLG. Therefore, the ground potential is supplied to the punch-through stopper layer PTS. In this way, a configuration in which the ground potential is supplied to the punch-through stopper layer PTS can be realized.

[0109] An advantage of manufacturing such structure C is that the p-type plug PLG can be formed by low-energy ion implantation using the oblique ion implantation method.

[0110] <<Configuration D of Third Embodiment>> 26, an epitaxial layer EPI1 is formed on an n-type semiconductor substrate SUB by epitaxial growth. Next, aluminum, which is a p-type impurity (acceptor), is introduced into the epitaxial layer EPI1 by photolithography and ion implantation. This forms a punch-through stopper layer PTSB in the epitaxial layer EPI1.

[0111] Next, as shown in FIG. 27, a lower epitaxial layer EPI2B is formed on the epitaxial layer EPI1 on which the punch-through stopper layer PTSB has been formed. Aluminum, which is a p-type impurity (acceptor), is introduced into the lower epitaxial layer EPI2B using photolithography and ion implantation. This forms a punch-through stopper layer PTSU in the lower epitaxial layer EPI2B. The punch-through stopper layer PTSU is connected to the punch-through stopper layer PTSB.

[0112] Then, a middle epitaxial layer EPI2M is formed on the lower epitaxial layer EPI2B on which the punch-through stopper layer PTSU has been formed. A p-type plug PLG is formed in the middle epitaxial layer EPI2M using photolithography and ion implantation. The p-type plug PLG is connected to the punch-through stopper layer PTSU. An upper epitaxial layer EPI2U is formed on the middle epitaxial layer EPI2M on which the p-type plug PLG has been formed. The lower epitaxial layer EPI2B, the middle epitaxial layer EPI2M, and the upper epitaxial layer EPI2U constitute the epitaxial layer EPI2.

[0113] 28, a p-type impurity is introduced into the upper epitaxial layer EPI2U by using a photolithography technique and an ion implantation method to form a channel layer CH. Then, an n-type impurity is introduced into the channel layer CH by using a photolithography technique and an ion implantation method to form a source region SR.

[0114] 29, a trench TR is formed by using photolithography and etching. Then, a gate insulating film GOX is formed on the inner wall of the trench TR, and then a gate electrode GE is formed in the trench TR with the gate insulating film GOX interposed therebetween. In this manner, the epitaxial layer EPI1, punch-through stopper layer PTSB, lower epitaxial layer EPI2B, punch-through stopper layer PTSU, middle epitaxial layer EPI2M, p-type plug PLG, upper epitaxial layer EPI2U, channel layer CH, source region SR, trench TR, gate insulating film GOX, and gate electrode GE can be formed.

[0115] The punch-through stopper layer is composed of a punch-through stopper layer PTSB formed in the epitaxial layer EPI1 and a punch-through stopper layer PTSU formed in the lower epitaxial layer EPI2B.

[0116] The source region SR and the channel layer CH are electrically connected and supplied with the ground potential. That is, the ground potential is supplied to each of the source region SR and the channel layer CH. The punch-through stopper layer PTSU is electrically connected to the channel layer CH, to which the ground potential is supplied, by a p-type plug PLG. Therefore, the ground potential is supplied to the punch-through stopper layer PTSU. The punch-through stopper layer PTSB is also connected to the punch-through stopper layer PTSU. Therefore, the ground potential is also supplied to the punch-through stopper layer PTSB. This makes it possible to realize a configuration in which the ground potential is supplied to the punch-through stopper layer PTSB and the punch-through stopper layer PTSU.

[0117] The advantages of manufacturing such a structure D include the following: The punch-through stopper layer is composed of a punch-through stopper layer PTSB formed in the epitaxial layer EPI1 and a punch-through stopper layer PTSU formed in the lower epitaxial layer EPI2B. This improves the degree of freedom in arranging the punch-through stopper layer to achieve both a shielding effect of efficiently alleviating electric field concentration near the trench bottom and a reduction in on-resistance (improvement of the electrical characteristics of the MOSFET) by making it easier to ensure a current path for the MOSFET.

[0118] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0119] 100 Wide band gap semiconductor device ACT Active Area AM1 alignment mark AM2 alignment mark BC Body Contact Area CB Cell Block CB1 Cell Block CB2 Cell Block CH channel layer CHP semiconductor chip CL center line DE drain electrode DMY Dummy electrode EPI epitaxial layer EPI1 epitaxial layer EPI2 epitaxial layer EPI2B Lower epitaxial layer EPI2M middle epitaxial layer EPI2U Upper epitaxial layer FR1 Floating Ring FR2 Floating Ring GE gate electrode GOX gate insulating film IL insulating layer OS Offset PAS surface protection film PLG p-type plug PLG1 P-type plug PLG2 p-type plug PTN1 pattern PTN2 pattern PTS punch-through stopper layer PTSB punch-through stopper layer PTSU Punch-through stopper layer PTS1 punch-through stopper layer PTS2 punch-through stopper layer RA area SE source electrode SPN subpattern SPN1 subpattern SPN2 subpattern SPN3 subpattern SPN4 subpattern SPN5 subpattern SPN6 subpattern SPN7 subpattern SPN8 subpattern SPN9 subpattern SPN10 subpattern SR Source Region ST 1 shot SUB Semiconductor substrate TR Trench

Claims

1. a first conductivity type epitaxial layer made of a wide bandgap semiconductor material having a bandgap larger than that of silicon; a plurality of trenches formed in the epitaxial layer; a plurality of gate electrodes formed in the plurality of trenches via gate insulating films; a punch-through stopper layer formed in the epitaxial layer, at a position deeper than the plurality of trenches, and of a second conductivity type opposite to the first conductivity type; A semiconductor device comprising: the punch-through stopper layer includes a first portion and a second portion adjacent to each other in a plan view; In a plan view, the first portion and the second portion each have a first pattern having the same planar shape; the first pattern is made up of one or more sub-patterns; In a plan view, each of the one or more sub-patterns constituting the first pattern partially overlaps any one of the plurality of gate electrodes.

2. 2. The semiconductor device according to claim 1, The planar shape of the punch-through stopper layer forms a geometric pattern consisting of repetitions of the first pattern as a unit pattern.

3. 2. The semiconductor device according to claim 1, The first pattern is composed of one or more sub-patterns including any of straight lines, rectangles, circles, and curves.

4. 2. The semiconductor device according to claim 1, the first pattern is composed of a tessellable pattern, The plane tessellating pattern is a pattern that can be used to tile a plane without overlapping or gaps using a finite number of plane figures.

5. 5. The semiconductor device according to claim 4, the first pattern is composed of a plurality of sub-patterns; The plurality of sub-patterns are made up of a combination of a plurality of single figures.

6. 5. The semiconductor device according to claim 4, the first pattern is composed of a plurality of sub-patterns; The plurality of sub-patterns are made up of a combination of a plurality of types of graphics.

7. 2. The semiconductor device according to claim 1, Each of the plurality of gate electrodes extends in a first direction, In a plan view, each of the one or more sub-patterns constituting the first pattern extends in a second direction intersecting the first direction.

8. 2. The semiconductor device according to claim 1, Each of the first portion and the second portion has a ring-shaped second pattern surrounding the first pattern in a plan view.

9. 9. The semiconductor device according to claim 8, The first pattern is connected to the second pattern.

10. 10. The semiconductor device according to claim 9, The first pattern and the second pattern are supplied with a ground potential.

11. 11. The semiconductor device according to claim 10, the epitaxial layer includes a first epitaxial layer of the first conductivity type and a second epitaxial layer of the first conductivity type formed on the first epitaxial layer; The semiconductor device includes: the punch-through stopper layer formed in the first epitaxial layer; a plug formed in the second epitaxial layer, connected to the punch-through stopper layer, and filled with a semiconductor material of the second conductivity type; a channel layer of the second conductivity type formed in the second epitaxial layer and electrically connected to the plug; a source region of the first conductivity type formed in the second epitaxial layer and on the channel layer; and The source region is electrically connected to the channel layer.

12. 12. The semiconductor device according to claim 11, the second epitaxial layer includes a second lower epitaxial layer of the first conductivity type, a second intermediate epitaxial layer of the first conductivity type formed on the second lower epitaxial layer, and a second upper epitaxial layer of the first conductivity type formed on the second intermediate epitaxial layer; the plug is composed of a lower-layer plug formed in the second lower epitaxial layer and an intermediate-layer plug formed in the second intermediate epitaxial layer and connected to the lower-layer plug; the channel layer is formed in the second upper epitaxial layer; The source region is formed in the second upper epitaxial layer.

13. 11. The semiconductor device according to claim 10, the epitaxial layer includes a first epitaxial layer of the first conductivity type and a second epitaxial layer of the first conductivity type formed on the first epitaxial layer; The semiconductor device includes: the punch-through stopper layer formed in the first epitaxial layer; a plug formed in the second epitaxial layer, connected to the punch-through stopper layer, and filled with a semiconductor material of the second conductivity type; a dummy electrode that is included in the plug and does not function as a gate electrode; a channel layer of the second conductivity type formed in the second epitaxial layer and electrically connected to the plug; a source region of the first conductivity type formed in the second epitaxial layer and on the channel layer; and The source region is electrically connected to the channel layer.

14. 11. The semiconductor device according to claim 10, the epitaxial layer includes a first epitaxial layer of the first conductivity type and a second epitaxial layer of the first conductivity type formed on the first epitaxial layer; The punch-through stopper layer is composed of a first punch-through stopper layer formed in the first epitaxial layer, and a second punch-through stopper layer formed in the second epitaxial layer and connected to the first punch-through stopper layer.

15. 2. The semiconductor device according to claim 1, The wide bandgap semiconductor material is silicon carbide.

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