Semiconductor laminated wafer

Abstract

To provide a semiconductor laminated wafer that improves yields of laminated wafers.SOLUTION: A semiconductor laminated wafer 100 includes a plurality of wafers W0 to W7, a reserved wafer, and a repair information block. Each wafer may include a plurality of dies D, and each wafer may include a logic wafer having a plurality of logic dies. The reserved wafer repairs a target wafer among the wafers based on a repair enable signal and a repair information signal. The repair information block is located within the reserved wafer or the logic wafer, and the repair information block accepts input of an input signal and outputs the repair enable signal and the repair information signal based on the input signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, and more particularly to laminated semiconductor wafers with repair schemes that can improve yield of the laminated semiconductor wafers. [Background technology]

[0002] Stacked wafers, which contain multiple semiconductor wafers, have been developed and used to manufacture high-bandwidth and high-capacity memory devices. Stacked wafers can be formed by stacking multiple semiconductor wafers together. However, as the number of wafers increases, the yield of stacked wafers drops sharply.

[0003] New techniques are needed to improve the yield of stacked wafers. Summary of the Invention [Problem to be solved by the invention]

[0004] As the number of wafers increases, the yield of stacked wafers drops off sharply. [Means for solving the problem]

[0005] In some embodiments, the semiconductor laminate wafer includes multiple wafers, a spare wafer, and a repair information block. Each wafer can include multiple dies, and the wafers can include a logic wafer and a target wafer. The spare wafer is configured to repair a target wafer among the wafers based on the repair enable signal and the repair information signal. The repair information block is located in the spare wafer or the logic wafer, and the repair information block receives the input signal and outputs the repair enable signal and the repair information signal based on the input signal.

[0006] According to some embodiments, a semiconductor laminate wafer includes multiple wafers, a spare wafer, and a repair information block. Each wafer includes multiple dies, and the wafers include a logic wafer and a target wafer. Each die of the wafer includes multiple input / output (IO) segments. The spare wafer is configured to repair a target wafer in the wafer based on the repair information signal. The spare wafer includes multiple spare dies, and each spare die includes multiple spare IO segments corresponding to the IO segments of each die of the wafer. The repair information block is located in the spare wafer or the logic wafer, and the repair information block receives an input signal and generates a repair information signal. The target wafer is repaired IO segment by IO segment, and in a repair operation, the target IO segment in the target wafer is replaced with the spare IO segment in the spare wafer.

[0007] According to an embodiment of the present invention, the yield of wafer stacking is improved by adding spare wafers to a stacked semiconductor wafer. Because target wafers in a stacked semiconductor wafer can be repaired by die, pseudo channel, memory bank, or memory row, the repair scheme of the present invention can be effectively and flexibly applied to a wide range of products. Furthermore, the proposed repair scheme can be used to repair IO segments (or IO units) of target wafers in a stacked semiconductor wafer. Therefore, the flexibility of the repair scheme is further improved. [Effects of the Invention]

[0008] The wafer stack yield is improved and the repair scheme flexibility is further improved. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic diagram of a laminated semiconductor wafer according to some embodiments. [Figure 2] FIG. 1 is a schematic diagram of a memory device formed by stacking multiple memory dies of a stacked semiconductor wafer in accordance with some embodiments. [Figure 3A]FIG. 1 is a schematic diagram of a repair information block for repairing a target die of a target wafer in accordance with some embodiments. [Figure 3B] FIG. 10 is a waveform diagram of signals in a semiconductor stack wafer for repairing a target die according to some embodiments. [Figure 3C] FIG. 10 is a waveform diagram of signals in a semiconductor stack wafer for repairing a target die according to some embodiments. [Figure 4A] FIG. 1 is a schematic diagram of a repair information block for repairing a target pseudo channel, a target memory bank, or a target row of a target wafer, in accordance with some embodiments. [Figure 4B] 10A-10C illustrate waveform diagrams of signals in a semiconductor stack wafer for repairing a target pseudo channel, a target bank, or a target row according to some embodiments. [Figure 4C] 10A-10C illustrate waveform diagrams of signals in a semiconductor stack wafer for repairing a target pseudo channel, a target bank, or a target row according to some embodiments. [Figure 5A] FIG. 1B is a schematic diagram of a repair information block for repairing a target column in a target wafer according to some embodiments. [Figure 5B] FIG. 10 is a waveform diagram of signals in a semiconductor stack wafer for repairing a target column according to some embodiments. [Figure 5C] FIG. 10 is a waveform diagram of signals in a semiconductor stack wafer for repairing a target column according to some embodiments. [Figure 5D] 1 is a schematic diagram of an IO segment in a memory bank of a semiconductor laminate wafer according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010] Reference will now be made in detail to preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings, in which: Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0011] FIG. 1 is a schematic diagram of a laminated semiconductor wafer 100 according to some embodiments. The laminated semiconductor wafer 100 may include multiple wafers W0, W1, W2, W3, W4, W5, W6, and W7 stacked on top of each other. The wafers W0 to W7 of the laminated semiconductor wafer 100 may be stacked on top of each other using wafer-on-wafer stacking techniques. Each of the wafers W0 to W7 may include multiple semiconductor dies D (also referred to as die D) that can be stacked on top of each other to form a memory device such as a high bandwidth memory (HBM). It should be understood that the number of wafers W0 to W7 in the laminated semiconductor wafer 100 and the number of dies D per wafer are not limited to a specific number. The memory device formed by stacking the dies of the laminated semiconductor wafer 100 may be a volatile memory or a non-volatile memory. For example, the memory device may be a dynamic random-access memory (DRAM), although the present invention is not limited thereto.

[0012] Wafers W0 to W7 of the laminated semiconductor wafer 100 may include a logic wafer, a spare wafer, and multiple memory wafers. For simplicity, wafer W0 of the laminated semiconductor wafer 100 will be referred to as a logic wafer or a system-on-chip (SoC) wafer, wafer W1 will be referred to as a spare wafer, and wafers W2 to W7 will be referred to as memory wafers. In some embodiments, memory wafer W7 is also referred to as a target wafer or a defective wafer and is used for repair operations. It should be noted that the present invention does not intend to limit the number of logic wafers, spare wafers, and memory wafers in the laminated semiconductor wafer 100. Furthermore, the positions and arrangements of the logic wafers, spare wafers, and memory wafers in the laminated semiconductor wafer 100 can be changed according to design requirements.

[0013] FIG. 2 illustrates a schematic diagram of a memory device 200 formed by stacking multiple dies D0, D1, D2, D3, D4, D5, D6, and D7 according to some embodiments. The memory device 200 may be a DRAM, but the present invention is not limited thereto. The dies D0-D7 are dies of wafers W0-W7, respectively. The die D0 in the logic wafer W0 may be referred to as the logic die D0, the spare die D1 in the spare wafer W1 may be referred to as the spare die D1, and the dies D2-D7 in the memory wafers W2-W7 may be referred to as the memory dies D2-D7. The memory device 200 may include memory ranks R0 and R1 corresponding to multiple wafers, respectively. For example, the first memory rank R0 may correspond to wafers W0-W3, and the second memory rank R1 may correspond to wafers W4-W7. The memory ranks R0 and R1 may be selected by the logic states of rank select signals SID[0] and SID[1]. For example, when rank select signal SID[0] is at a high logic state, the first rank R0 is selected, and when rank select signal SID[1] is at a high logic state, the second rank R1 is selected.

[0014] Each of the dies D0-D7 may include a plurality of pseudo channels PC0, PC1, PC2, and PC3, and each of the pseudo channels PC0-PC3 may include a plurality of memory banks BK0-BK15. Each of the memory banks BK0-BK15 may include a plurality of memory rows (not shown) and a plurality of memory columns (not shown). Each of the dies D0-D7 may further include a plurality of input / output (IO) segments.

[0015] In order to improve the yield of the stacked dies, when it is determined that there is a defective wafer (i.e., target die W7) in the laminated semiconductor wafer 100, a spare wafer (i.e., spare wafer W1) is added to the laminated semiconductor wafer 100, and the target wafer (i.e., target wafer W7) is repaired. In this way, the yield of the laminated semiconductor wafer 100 is improved.

[0016] In some embodiments, the target wafer W7 can be repaired on a die-by-die basis. That is, a target die in the target wafer W7 can be replaced with a spare die in the spare wafer W1. In some alternative embodiments, the target wafer W7 can be repaired on a pseudo channel-by-pseudo channel, memory bank-by-memory row-by-memory row basis. Furthermore, a target IO segment of a target die in the target wafer W7 can also be repaired using the spare wafer W1.

[0017] 3A is a schematic diagram of a repair information block 310 for repairing a target wafer W7 on a die-by-die basis according to some embodiments. That is, the repair information block 310 can be used to replace a target die in the target wafer W7 with a corresponding spare die in the spare wafer W1. The repair information block 310 can be located in the logic wafer W0 or the spare wafer W1 of the semiconductor laminate wafer 100. The repair information block 310 can be implemented in hardware circuits, software, or firmware.

[0018] The repair information block 310 can receive an input signal IN_S and generate a repair enable signal TSV_REDUN_MISS and a repair information signal RE_S1. The input signal IN_S can include rank select signals SID[0:1], bank select signals BA[0:15], and row select signals RA_LAT[0:13]. The rank select signals SID[0:1] are configured to select a memory rank for the repair operation, the bank select signals BA[0:15] are configured to select a target memory bank for the repair operation, and the row select signals RA_LAT[0:13] are configured to select a memory row for the repair operation.

[0019] The repair enable signal TSV_REDUN_MISS may indicate whether to perform a repair operation on the laminated semiconductor wafer 100. For example, when the repair enable signal TSV_REDUN_MISS is in a high logic state, a repair operation is not performed on the laminated semiconductor wafer 100. When the repair enable signal TSV_REDUN_MISS is in a low logic state, a repair operation is performed to repair a target wafer (i.e., target wafer W7) of the laminated semiconductor wafer 100.

[0020] The repair information signal RE_S1 may include a wafer select signal WS[0:7], a spare wafer select signal WS_RED, a bank select signal BA[0:15], and a row select signal RA_LAT[0:13]. The wafer select signal WS[0:7] is configured to select a target wafer for a repair operation, and the spare wafer select signal WS_RED is configured to select a spare wafer for a repair operation. The bank select signals BA[0:15] and row select signals RA_LAT[0:13] may remain the same as the bank select signals BA[0:15] and row select signals RA_LAT[0:13] input to the repair information block 310.

[0021] The repair information block 310 sends wafer select signals WS[0:7] to each die of wafers W0 to W7. A spare wafer select signal WS_RED is sent to each die of spare wafer W1, and bank select signals BA[0:15] and row select signals RA_LAT[0:130] are sent to all dies of wafers W0 to W7.

[0022] 3B and 3C illustrate waveform diagrams of signals in the laminated semiconductor wafer 100 according to some embodiments. The signals illustrated in FIGS. 3B and 3C include a repair enable signal TSV_REDUN_MISS, rank select signals SID[0] and SID[1], wafer select signals WS[0:3] and WS[4:7], a spare wafer select signal WS_RED, bank select signals BA[0] and BA[1:15], row select signals RA_LAT[0:13], and a read / write signal RD / WR.

[0023] The rank select signals SID[0] and SID[1] can indicate a selected memory rank among memory ranks R0 and R1. The wafer select signals WS[0:3] are sent to the dies of wafers W0-W3, and the wafer select signals WS[4:7] are sent to the dies of wafers W4-W7. The logic state of the wafer select signals WS[0:7] can indicate which wafer among wafers W0-W7 is selected for a repair operation. The spare wafer select signal WS_RED is sent to the spare die of spare wafer W1 and indicates whether spare wafer W1 is selected for a repair operation. The bank select signals BA[0:15] are sent to memory banks BK0-BK15 and indicate which memory bank is selected, and the row select signal RA_LAT[0:13] indicates which memory row is selected. The read / write signal RD / WR can indicate the memory operation (i.e., a read operation or a write operation) to be performed.

[0024] Referring to FIG. 3B, assume that memory bank BK0 of the second rank R1 is selected and a repair operation is not performed. Because a repair operation is not performed, the repair enable signal TSV_REDUN_MISS is in a high logic state, and the spare wafer select signal WS_RED is in a low logic state. Furthermore, because memory rank R1 is selected, the first rank select signal SID[0] is in a low logic state, and the second rank select signal SID[1] is in a high logic state. FIG. 3B further shows that wafer select signals WS[0:3] are in a low logic state, and wafer select signals WS[4:7] are in a high logic state. This indicates that wafers W0-W3 are not selected, and wafers W4-W7 are selected. Because bank select signal BA[0] is in a high logic state, and bank select signals BA[1:15] are in a low logic state, memory bank BK0 is selected. The row select signal RA_LAT[0:13] sent to the memory row of the selected memory bank BK0 may be at a low logic state or at a high logic state depending on the selected memory row for the memory operation (i.e., a read operation or a write operation). The read / write signal RD / WR may be at a low logic state or at a high logic state depending on whether a read operation or a write operation is to be performed on the selected memory row.

[0025] 3C, assume that memory bank BK0 of the second memory rank R1 is selected to perform a repair operation to repair target wafer W7. To perform the repair operation, the repair enable signal TSV_REDUN_MISS is at a low logic state, and the spare wafer select signal WS_RED is at a high logic state. To select target wafer W7 of the second memory rank R1 for the repair operation, the first rank select signal SID[0] is at a low logic state, the second rank select signal SID[1] is at a high logic state, the wafer select signals WS[0:3,7] sent to the dies of wafers W0-W3 and target wafer W7 are at a low logic state, and the wafer select signals WS[4:6] sent to the dies of wafers W4-W6 are at a high logic state. The logic states of the bank select signals BA[0:15], row select signals RA_LAT[0:13], and read / write signals RD / WR in FIG. 3C are the same as those in FIG. 3B, so detailed descriptions of these signals will be omitted.

[0026] The target die of the target wafer W7 receives the wafer select signal W7 at a low logic state, while the non-target die of the target wafer W7 receives the wafer select signal W7 at a high logic state. Meanwhile, the spare wafer select signal WS_RED can select the corresponding spare die in the spare wafer W1. Thus, the target die in the target wafer W7 can be replaced with the corresponding spare die in the spare wafer W1. In this way, the target wafer W7 can be repaired on a die-by-die basis using the spare wafer and the repair information signal RE_S1 output by the repair information block 310.

[0027] In some embodiments, information about target dies on target wafer W7 can be stored in repair information block 310. In normal operation, when target dies on target wafer W7 are accessed, access to the faulty dies can be replaced with access to the corresponding spare dies in spare wafer W1.

[0028] 4A is a schematic diagram of a repair information block 410 for repairing a target pseudo channel, a target memory bank, or a target row of a target wafer according to some embodiments. Assume that the target pseudo channel is pseudo channel PC2, the target memory bank is memory bank BK0, and the target wafer is wafer W7.

[0029] The repair information block 410 receives the input signal IN_S and generates a repair enable signal TSV_REDUN_MISS and a repair information signal RE_S2. The input signal IN_S and the repair enable signal TSV_REDUN_MISS of the repair information block 410 in FIG. 4A may be the same as the input signal IN_S and the repair enable signal TSV_REDUN_MISS of the repair information block 310 in FIG. 3A, so details of the input signal IN_S and the repair enable signal TSV_REDUN_MISS in FIG. 4A will not be described again.

[0030] When the target wafer W7 is repaired on a pseudo-channel basis, the repair information signal RE_S2 may include a wafer selection signal WS[0:7], a spare wafer selection signal WS_RED, a pseudo-channel selection signal PS[0:7], and a spare pseudo-channel selection signal PS_RED[0:7]. When the target wafer W7 is repaired on a pseudo-channel basis, the target pseudo-channel PC2 in the target wafer W7 can be replaced with the corresponding spare pseudo-channel in the spare wafer W1.

[0031] When the target wafer W7 is repaired in units of memory banks, the repair information signal RE_S2 may further include a bank selection signal BA[0:15] in addition to the wafer selection signal WS[0:7], the spare wafer selection signal WS_RED, the pseudo channel selection signal PS[0:7], and the spare pseudo channel selection signal PS_RED[0:7]. When the target wafer W7 is repaired in units of memory banks, the target memory bank BK0 in the target wafer W7 can be replaced with the corresponding spare memory bank in the spare wafer W1.

[0032] When the target wafer W7 is repaired in units of memory rows, the repair information signal RE_S2 can include the wafer selection signal WS[0:7], the spare wafer selection signal WS_RED, the pseudo channel selection signal PS[0:7], the spare pseudo channel selection signal PS_RED[0:7], and the bank selection signal BA[0:15], as well as the row selection signal RA_LAT[0:13]. When the target wafer W7 is repaired in units of memory rows, the target memory rows in the target wafer W7 can be replaced with the corresponding spare memory rows in the spare wafer W1.

[0033] The wafer select signal WS[0:7] is configured to select the target wafer (i.e., wafer W7) for the repair operation, and the spare wafer select signal WS_RED is configured to select the spare wafer (i.e., wafer W1) for the repair operation. The pseudo channel select signal PS[0:7] is configured to select the target pseudo channel (i.e., pseudo channel PC2) for the repair operation, and the spare pseudo channel select signal PS_RED[0:7] is configured to select the corresponding spare pseudo channel in the spare wafer W1 for the repair operation. The bank select signal BA[0:15] is configured to select the target memory bank (i.e., memory bank BK0) for the repair operation. The row select signal RA_LAT[0:13] is configured to select the target memory row for the repair operation. The bank select signal BA[0:15] and the row select signal RA_LAT[0:13] may remain the same as the bank select signal BA[0:15] and the row select signal RA_LAT[0:13] input to the repair information block 410.

[0034] The repair information block 410 transmits a wafer select signal WS[0:7] and a pseudo channel select signal PS[0:7] to each die on wafers W0-W7. A spare wafer select signal WS_RED and a spare pseudo channel select signal PS_RED[0:7] are transmitted to each die on spare wafer W1. A bank select signal BA[0:15] and a row select signal RA_LAT[0:130] are transmitted to all dies on wafers W0-W7.

[0035] 4B and 4C show waveform diagrams of signals in the semiconductor stack wafer 100 for repairing a target pseudo channel, a target bank, or a target row according to some embodiments of the present invention. The signals shown in FIGS. 4B and 4C include all signals shown in FIGS. 3B and 3C. Additionally, FIGS. 4B and 4C further show waveform diagrams of the pseudo channel selection signal PS[0:7] and the spare pseudo channel selection channel PS_RED[0:7].

[0036] 4B, the waveforms of the repair enable signal TSV_REDUN_MISS, the rank select signals SID[0] and SID[1], the wafer select signals WS[0:3] and WS[4:7], the spare wafer select signal WS_RED, the bank select signal BA[0:15], the row select signal RA_LAT[0:13], and the read / write signal RD / WR in FIG. 4B are the same as those in FIG. 3B, and therefore will not be described in detail below. FIG. 4B also shows the waveforms of the pseudo channel select signals PS[2] and PS[0:1,3:7] and the spare pseudo channel select signals PS_RED[2] and PS_RED[0:1,3:7]. In FIG. 4B, the pseudo channel select signals PS[2] and PS[0:1,3:7] are in a high logic state, and the spare pseudo channel select signals PS_RED[2] and PS_RED[0:1,3:7] are in a low logic state. Therefore, neither the pseudo channel of the target wafer W7 nor the spare pseudo channel of the spare wafer W1 is selected, and no repair operation is performed.

[0037] Referring to Figure 4C, the waveforms of the repair enable signal TSV_REDUN_MISS, rank selection signals SID[0] and SID[1], wafer selection signals WS[0:3] and WS[4:7], spare wafer selection signal WS_RED, bank selection signal BA[0:15], row selection signal RA_LAT[0:13], and read / write signal RD / WR in Figure 4C are the same as those in Figure 3C, so detailed description will be omitted below.

[0038] 4C further illustrates the waveforms of the pseudo channel selection signals PS[2] and PS[0:1,3:7] and the preliminary pseudo channel selection signals PS_RED[2] and PS_RED[0:1,3:7]. In FIG. 4C, the pseudo channel selection signal PS[2] sent to the target pseudo channel PC2 of the target wafer W7 is in a low logic state, and the pseudo channel selection signals [0:1,3:7] sent to the non-target pseudo channels PC0-PC1 and PC3-PC7 of the target wafer W7 are in a high logic state. The preliminary pseudo channel selection signal PS_RED[2] sent to the preliminary pseudo channel corresponding to the target pseudo channel PC2 is in a high logic state, and the preliminary pseudo channel selection signal PS_RED[0:1,3:7] sent to the preliminary pseudo channels corresponding to the non-target pseudo channels PC0-PC1 and PC3-PC7 of the target wafer W7 is in a low logic state. In this way, the target pseudo channel PC2 can be replaced with the corresponding spare pseudo channel in the spare wafer W1 in the repair operation. Thus, the target wafer W7 is repaired on a pseudo channel-by-pseudo channel basis.

[0039] When the target wafer W7 is repaired in units of memory banks, the repair information signal RE_S2 further includes bank select signals BA[0] and BA[1:15]. As shown in FIG. 4C, the bank select signal BA[0] may be in a high logic state, and the bank select signals BA[1:15] may be in a low logic state. In this way, during the repair operation, the target memory bank BK0 of the target pseudo channel PC2 of the target wafer W7 can be replaced with the corresponding spare memory bank of the spare wafer W1.

[0040] When the target wafer W7 is repaired row by row, the repair information signal RE_S2 further includes a row select signal RA_LAT[0:13]. As shown in FIG. 4C, the row select signal RA_LAT[0:13] may be selectively set to a low logic state or a high logic state depending on which row of the target memory bank is to be repaired. The row select signal sent to the target row is set to a high logic state, and the row select signal sent to the non-target row is set to a low logic state. Therefore, the target memory row of the target memory bank of the target pseudo channel of the target wafer can be repaired. In this way, the defective wafer W7 can be repaired row by row.

[0041] 5A illustrates a schematic diagram of a repair information block 510 for repairing a target wafer W7 in units of IO segments, according to some embodiments. The repair information block 510 may include an IO repair information block 512 and a decoder 514. The IO repair information block 512 is located in the logic die W0 or the spare die W1, and the decoder 514 is located in all dies of the wafers W0-W7.

[0042] 5A, input signals of IO repair information block 512 include column address signals CA_LAT[0:4], and output signals of IO repair information block 512 include column address signals CA_LAT[0:4], IO segment select signals CA_SEG[0:31], and spare IO segment select signals CA_SEG_RED[0:31]. The output signals of IO repair information block 512 are provided to decoders 514. The decoders 514 in the spare dies of spare wafer W1 can be controlled by the spare IO segment select signals CA_SEG_RED[0:31], and the decoders 514 in the dies of wafers W0 and W1-W7 can be controlled by the IO segment select signals CA_SEG[0:31]. Each decoder 514 is configured to decode the column address signals CA_LAT[0:4] and generate column select signals CSL[0:31] to perform a repair operation.

[0043] In some embodiments, the column address signal CA_LAT[0:4] output by the IO repair information block 512 is the same as the column address signal CA_LAT[0:4] input to the IO repair information block 512. The IO segment select signal CA_SEG[0:31] can be used by a target die of the target wafer W7 to control the IO segments of the target wafer W7. The spare IO segment select signal CA_SEG_RED[0:31] can be used by a spare die of the spare wafer W1 to control the spare IO segments of the spare wafer W1. The IO segment select signal CA_SEG[0:31] can be the inverse of the spare IO segment select signal CA_SEG_RED[0:31].

[0044] 5B and 5C illustrate waveform diagrams of signals for repairing IO segment SEG0 of target wafer W7 according to some embodiments. The signals illustrated in FIGS. 5B and 5C include column address signals CA_LAT[0:4], IO segment select signals CA_SEG[0] and CA_SEG[1:31], spare IO segment select signals CA_SEG_RED[0] and CA_SEG_RED[1:31], column select signals CSL0[0]@target_die and CSL1[0]-CSL31[0]@target_die, and column select signals CSL0[0]@reserve_die and CSL1[0]-CSL31[0]@reserve_die. The IO segment select signals CA_SEG[0] and CA_SEG[1:31] can select IO segments within target wafer W7 for repair operations. The spare IO segment select signals CA_SEG_RED[0] and CA_SEG_RED[1:31] can select spare IO segments in spare wafer W1 for repair operations. The column select signals CSL0[0]@target_die and CSL1[0]-CSL31[0]@target_die can select columns in the target die (i.e., target die W7) for repair operations. The column select signals CSL0[0]@reserve_die and CSL1[0]-CSL31[0]@target_die can select columns in the spare die for repair operations.

[0045] FIG. 5B illustrates signal waveforms when a column repair operation is not enabled. As shown in FIG. 5B, all IO segment select signals CA_SEG[0] and CA_SEG[1:31] are at a high logic state. Meanwhile, all spare IO segment select signals CA_SEG_RED[0] and CA_SEG_RED[1:31] are at a low logic state. Additionally, column select signals CSL0[0]@target_die and CSL1[0]-CSL31[0]@target_die are at a high logic state, and column select signals CSL0[0]@reserve_die and CSL1[0]-CSL31[0]@reserve_die are at a low logic state. Therefore, a repair operation to repair the target IO segments in the target wafer W7 is not performed.

[0046] 5C illustrates signal waveforms when a repair operation is enabled to repair an IO segment SEG0 of a wafer W7 according to some embodiments. As shown in FIG. 5C, the IO segment select signal CA_SEG[0] sent to the target IO segment SEG0 in the target wafer W7 is in a low logic state, and the IO segment select signals CA_SEG[1:31] sent to the non-target segments are in a high logic state. Meanwhile, the spare IO segment select signal CA_SEG_RED[0] sent to the spare IO segment corresponding to the target IO segment SEG0 is in a high logic state, and the IO segment select signals CA_SEG_RED[1:31] sent to the spare IO segments corresponding to the non-target IO segments are in a low logic state. Therefore, the target IO segment SEG0 in the target wafer W7 and the spare IO segment SEG0 in the spare wafer W1 are selected to perform the repair operation.

[0047] FIG. 5C further shows that the column select signal CSL0[0]@target_die sent to the target IO segment is in a low logic state, and the column select signals CSL1[0]-CSL31[0]@target_die sent to the non-target IO segments are in a high logic state. Meanwhile, the spare column select signal CSL0[0]@reserve_die is in a high logic state, and the spare column select signals CSL1[0]-CSL31[0]@reserve_die are in a low logic state. Therefore, the target IO segment in the target die and the spare IO segment in the spare die are selected to perform the repair operation. The target IO segment in the target die of the target wafer (i.e., wafer W7) can be replaced with a spare IO segment column in the spare die of the spare wafer (i.e., wafer W1). In this way, the target wafer W7 can be repaired on an IO segment-by-IO segment basis.

[0048] FIG. 5D illustrates a repair operation for replacing a target IO segment SEG0 of a target wafer W7 with a corresponding spare IO segment SEG0 of a spare wafer W1, according to some embodiments. As shown in FIG. 5D , each of wafers W1 and W7 includes multiple IO segments SEG0-SEG31. Each of the IO segments SEG0-SEG31 can receive an input column select signal CLxx[0:31], where xx represents an IO segment among the IO segments SEG0-SEG31. For example, 00 in xx represents the IO segment SEG0, and 31 in xx represents the IO segment SEG31. Each of the IO segments SEG0-SEG31 can output data MDQxx[0:7]. The data MDQxx[0:7] output by the IO segments SEG0-SEG31 can be combined to form output data DQ_TSV[0:255] of the IO segments SEG0-SEG31.

[0049] 5D, when the target IO segment SEG0 of the target wafer W7 is replaced with the corresponding IO segment SEG0 of the spare wafer W1, the data output by the IO segment SEG0 of the target wafer W7 is replaced with the data MDQ00[0:7] output by the IO segment SEG0 of the target wafer W1. In this way, the target wafer W7 can be repaired on an IO segment-by-IO basis or an IO-by-IO basis.

[0050] In the above embodiment, the laminated semiconductor wafer may include a spare wafer for repairing a target wafer (or a defective wafer) in the laminated semiconductor wafer. The repair operation may be performed using a repair information block located in the logic wafer or spare wafer of the laminated semiconductor wafer. In this manner, the yield of the laminated semiconductor wafer is improved. Furthermore, the repair operation may be performed on a die-by-die, pseudo channel-by-channel, memory bank-by-memory row-by-memory row basis, improving the flexibility of the repair scheme. IO segments of the target wafer may also be repaired, thereby further improving the flexibility of the repair scheme.

[0051] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the invention. In view of this, it is intended that the present invention cover modifications and variations that come within the scope of the following claims and their equivalents. [Industrial Applicability]

[0052] The present invention relates to laminated semiconductor wafers with repair schemes that can improve the yield of the laminated semiconductor wafers. [Explanation of symbols]

[0053] 100 Semiconductor laminated wafer 200 memory devices 310, 410 Repair Information Block 510 Repair Information Block 512 IO Repair Information Block 514 decoder BK0~BK15 memory banks D, D0, D1, D2, D3, D4, D5, D6, D7 Semiconductor die IN_S Input signal PC0, PC1, PC2, PC3 pseudo channels R0, R1 memory rank RE_S1, RE_S2 Repair information signal W0, W1, W2, W3, W4, W5, W6, W7 wafers

Claims

1. a plurality of wafers, each including a plurality of dies, including a logic wafer and a target wafer; a spare wafer configured to repair the target wafer among the wafers based on a repair enable signal and a repair information signal; a repair information block located within the spare wafer or the logic wafer, receiving an input signal and outputting the repair enable signal and the repair information signal based on the input signal; A semiconductor laminated wafer comprising:

2. when the repair enable signal is in a first logic state, a repair operation for repairing the target wafer is disabled; The laminated semiconductor wafer of claim 1 , wherein the repair operation for repairing the target wafer is enabled when the repair enable signal is in a second logic state.

3. the target wafer is repaired on a die-by-die basis; The laminated semiconductor wafer of claim 2 , wherein the repair operation replaces a target die in the target wafer with a spare die in the spare wafer.

4. the input signals include a rank select signal, a bank select signal, and a row select signal; 4. The laminated semiconductor wafer of claim 3, wherein the repair information signal includes a target wafer selection signal, a spare wafer selection signal, the bank selection signal, and the row selection signal, the target wafer selection signal being configured to select the target wafer for the repair operation, and the spare wafer selection signal being configured to select the spare wafer for the repair operation.

5. the repair information block transmits the target wafer select signal to the die of the wafer; the repair information block transmits the spare wafer select signal to a spare die of the spare wafer; The laminated semiconductor wafer of claim 4 , wherein the repair information block transmits the bank select signal and the row select signal to the die of the wafer and to the spare die of the spare wafer.

6. 5. The laminated semiconductor wafer of claim 4, wherein, during the repair operation to repair the target wafer, the spare wafer select signal is in the first logic state, the target wafer select signal sent to the target die of the target wafer is in the second logic state, and the target wafer select signal sent to the non-target die of the target wafer is in the first logic state.

7. 5. The laminated semiconductor wafer of claim 4, wherein when the repair operation to repair the target wafer is disabled, the spare wafer select signal is in the second logic state and the target wafer select signal sent to all dies of the target wafer is in the first logic state.

8. each of the dies includes a plurality of pseudo channels; The target wafer is repaired on a pseudo channel-by-channel basis; 3. The laminated wafer of claim 2, wherein the repair operation replaces a target pseudo channel of the target wafer with a spare pseudo channel in the spare wafer.

9. the input signals include a rank select signal, a bank select signal, and a row select signal; the repair information signals include a target wafer select signal, a spare wafer select signal, a pseudo channel select signal, a spare pseudo channel select signal, the bank select signal, and the row select signal; 9. The semiconductor laminated wafer of claim 8, wherein the pseudo channel selection signal is configured to select the target pseudo channel of the target die of the target wafer to perform the repair operation, and the spare pseudo channel selection signal is configured to select a spare pseudo channel corresponding to the target pseudo channel.

10. the repair information block transmits the target wafer select signal and the pseudo channel select signal to a die on the wafer; the repair information block transmits the spare wafer select signal and the spare pseudo channel select signal to a spare die of the spare wafer; The laminated semiconductor wafer of claim 9 , wherein the repair information block transmits the bank select signal and the row select signal to the die of the wafer and to the spare die of the spare wafer.

11. In the repair operation for repairing the target pseudo channel, the spare wafer select signal is in the first logic state, the target wafer select signal sent to the target die of the target wafer is in the second logic state, and the target wafer select signal sent to the non-target die in the target wafer is in the first logic state; the pseudo channel select signal sent to the target pseudo channel of the target die is in the second logic state, and the pseudo channel select signal sent to the non-target pseudo channel of the target die is in the second logic state; 10. The laminated semiconductor wafer of claim 9, wherein the auxiliary pseudo channel selection signal sent to the auxiliary pseudo channel corresponding to the target pseudo channel is in the first logic state, and the auxiliary pseudo channel selection signal sent to the auxiliary pseudo channel corresponding to the non-target pseudo channel is in the second logic state.

12. 10. The laminated semiconductor wafer of claim 9, wherein when a repair operation to repair the target wafer is disabled, the spare wafer select signal is in the second logic state, the target wafer select signal is in the first logic state, the pseudo channel select signal is in the first logic state, and the spare pseudo channel select signal is in the second logic state.

13. each of the dies includes a plurality of pseudo channels; each of the pseudo channels includes a plurality of memory banks; The target wafer is repaired in units of memory banks, 3. The laminated semiconductor wafer according to claim 2, wherein in the repair operation, a target memory bank of a target pseudo channel of the target wafer is replaced with a spare memory bank in the spare wafer.

14. the input signals include a rank select signal, a bank select signal, and a row select signal; the repair information signals include a target wafer select signal, a spare wafer select signal, a pseudo channel select signal, a spare pseudo channel select signal, the bank select signal, and the row select signal; 4. The laminated semiconductor wafer of claim 3, wherein the target wafer select signal is configured to select the target wafer, the pseudo channel select signal is configured to select the target pseudo channel, and the bank select information is configured to select the target memory bank.

15. each of the dies includes a plurality of pseudo channels; each of the pseudo channels includes a plurality of memory banks; each of the memory banks includes a plurality of memory rows; The target wafer is repaired on a memory row-by-row basis; The laminated semiconductor wafer according to claim 2 , wherein in the repair operation, a target memory row in a target memory bank of a target pseudo channel of the target wafer is replaced with a spare memory row in the spare wafer.

16. a plurality of wafers each including a plurality of dies, the wafer including a logic wafer and a target die, each die including a plurality of input / output segments; a spare wafer configured to repair a target wafer among the wafers based on the repair information signal, the spare wafer including a plurality of spare dies, each of the spare dies including a plurality of spare IO segments corresponding to the IO segments of each die of the wafer; a repair information block located within the spare wafer or the logic wafer, the repair information block receiving an input signal and generating a repair information signal; wherein the target wafer is repaired in units of IO segments, and in the repair operation, target IO segments in the target wafer are replaced with spare IO segments in the spare wafer.

17. the input signals include a column address signal; the repair information signals include an IO segment select signal, a spare IO segment select signal, and a column select signal; 17. The semiconductor laminated wafer of claim 16, wherein the IO segment select signal is configured to select a target IO segment within the target wafer, and the spare IO segment select signal is configured to select a spare IO segment corresponding to the target IO segment within the spare wafer.

18. In the repair operation for repairing the target wafer, the IO segment select signal sent to the target IO segment of the target wafer is in the second logic state and the IO segment select signal sent to the non-target IO segment of the target wafer is in the first logic state; 17. The semiconductor laminated wafer of claim 16, wherein the spare IO segment select signal sent to the spare IO segment corresponding to the target IO segment is in the first logic state, and the spare IO segment select signal sent to the spare IO segment corresponding to the non-target IO segment is in the second logic state.

19. In a repair operation for repairing the target wafer, the column select signal sent to the target IO segment of the target wafer is in the second logic state and the column select signal sent to the non-target IO segment of the target wafer is in the first logic state; 20. The semiconductor laminated wafer of claim 18, wherein the spare column select signal sent to the spare IO segment corresponding to the target IO segment is in the first logic state, and the column select signal sent to the spare IO segment corresponding to the non-target IO segment is in the second logic state.

20. 20. The laminated semiconductor wafer of claim 19, wherein when the repair operation to repair the target wafer is disabled, the spare IO segment select signal is in the first logic state, the spare IO segment select signal is in the second logic state, and the column select signals sent to all IO segments of the target wafer are in the first logic state.

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