Semiconductor device, memory device, and memory system
The semiconductor device addresses excessive voltage drop fluctuations by arranging source drawer contacts uniformly and integrating a metal interconnect layer, resulting in stable voltage distribution and improved performance.
Patent Information
- Application Number
- JP2025146735
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2021-03-26
- Filing Date
- 2025-09-04
- Publication Date
- 2025-11-28
AI Technical Summary
Existing semiconductor devices experience excessive fluctuations in voltage drop between NAND strings and source draw contacts, affecting device performance.
The semiconductor device incorporates a design with source drawer contacts arranged in orthogonal projections at equal intervals, aligned with channel structures, and a metal interconnect layer that covers these contacts, ensuring uniform distribution and stable voltage drops.
This design stabilizes voltage drops between channel structures and source drawer contacts, reducing fluctuations and enhancing device performance by maintaining consistent electrical connections.
Smart Images
Figure 2025175024000001_ABST
Abstract
Description
[Technical Field]
[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This disclosure is based on and claims priority to Chinese Patent Application No. 202110323821.9, filed on March 26, 2021, the entire contents of which are incorporated herein by reference.
[0002] The present disclosure relates generally to electronic devices, and more particularly to semiconductor devices, memories, and memory systems. [Background technology]
[0003] In the novel 3D NAND structure, a first silicon substrate is first formed, and a plurality of array devices, each comprising a plurality of NAND strings, are formed on the front surface of the first silicon substrate. Then, an array interconnect layer is formed on the plurality of NAND strings. Meanwhile, a second silicon substrate is formed, and peripheral devices are formed on the second silicon substrate, and a peripheral interconnect layer is formed on the peripheral devices. The array interconnect layer on the array device is then connected to the peripheral interconnect layer on the peripheral devices using a method such as bonding. Then, the first silicon substrate is removed, and a source layer is formed on the side of the array device from which the first silicon substrate was removed. A source lead contact, such as an N-well pickup layer (NPU), is formed on the source layer, and the source end is connected to the outside. The NPU is then bonded to an Al metal layer (connected to the peripheral device), thereby enabling the array device to be electrically connected to the peripheral device for signal transmission.
[0004] However, in the prior art, the voltage drop between the NAND string and the source draw contact varies excessively, thus affecting device performance. Summary of the Invention
[0005] The present disclosure aims to provide a semiconductor device, a memory, and a memory system to avoid excessive fluctuations in the voltage drop between a NAND string and a source draw contact to improve device performance.
[0006] In one aspect, the present disclosure provides a semiconductor device comprising: an array device comprising a plurality of channel structures and a source layer connected to the plurality of channel structures; a plurality of source drawer contacts connected to the source layer, the plurality of source drawer contacts and the plurality of channel structures being respectively located on both sides of the source layer, and orthogonal projections of the plurality of source drawer contacts on the source layer being distributed at equal intervals; A semiconductor device comprising:
[0007] In some embodiments, the semiconductor device further includes multiple rows of gate line slit structures extending along a first direction parallel to the source layer, and two adjacent rows of gate line slit structures have a first pitch therebetween.
[0008] In some embodiments, the plurality of source extraction contacts are arranged in a plurality of rows along the first direction, and the source extraction contacts in the same row are distributed at equal intervals along the first direction.
[0009] In some embodiments, the plurality of source extraction contacts are arranged in a plurality of rows along the first direction, and two adjacent rows of gate line slit structures have a second pitch therebetween, and the second pitch between any two adjacent rows of gate line slit structures is the same.
[0010] In some embodiments, the first pitch is equal to the second pitch.
[0011] In some embodiments, the orthogonal projection of each of the source extraction contacts on the source layer is located between the orthogonal projections of two adjacent rows of gate line slit structures on the source layer.
[0012] In some embodiments, the orthogonal projection of each of the source extraction contacts on the source layer is located at the center between the orthogonal projections of two adjacent rows of gate line slit structures on the source layer.
[0013] In some embodiments, the orthogonal projections of two adjacent rows of gate line slit structures on the source layer have orthogonal projections of multiple rows of source extraction contacts on the source layer therebetween.
[0014] In some embodiments, the orthogonal projection of each of the source extraction contacts on the source layer has an overlap with the orthogonal projection of one of the gate line slit structures on the source layer.
[0015] In some embodiments, the source pull-out contact comprises a first source pull-out contact and a second source pull-out contact, wherein the orthogonal projection of the first source pull-out contact on the source layer is located between the orthogonal projections of two adjacent rows of gate line slit structures on the source layer, and the orthogonal projection of the second source pull-out contact has an overlapping portion with the orthogonal projection of the gate line slit structures on the source layer.
[0016] In some embodiments, the plurality of source extraction contacts are arranged in one-to-one correspondence with the plurality of channel structures.
[0017] In some embodiments, the orthogonal projection of the source extraction contact on the source layer is strip-shaped, with its length direction aligned along a first direction parallel to the source layer.
[0018] In some embodiments, the orthogonal projection of the source extraction contact on the source layer is strip-shaped, and the width direction of the strip is disposed along a first direction parallel to the source layer.
[0019] In some embodiments, the orthogonal projection of the source extraction contact on the source layer is strip-shaped, the length direction of which forms an included angle with a first direction parallel to the source layer.
[0020] In some embodiments, the plurality of source extraction contacts are arranged in a plurality of rows along a first direction parallel to the source layer, and the source extraction contacts in the plurality of rows are aligned in a second direction perpendicular to the first direction and parallel to the source layer.
[0021] In some embodiments, the plurality of source extension contacts are arranged in a plurality of rows along a first direction parallel to the source layer, and the gate line slit structures of two adjacent rows are distributed in a staggered manner in the first direction.
[0022] In some embodiments, the semiconductor device further comprises a metal interconnect layer covering the plurality of source pull contacts.
[0023] In some embodiments, the metal interconnect layer comprises a plurality of continuously extending, parallel first vias and second vias for connecting two adjacent ones of the first vias.
[0024] In some embodiments, the orthogonal projection of the source puller contacts on the source layer is strip-shaped, and the plurality of first paths cover the plurality of source puller contacts and extend continuously along the length of the source puller contacts.
[0025] In some embodiments, the plurality of second vias cover a plurality of source pull-out contacts, and the plurality of first vias cover a plurality of columns of gate line slit structures.
[0026] In some embodiments, the region between two adjacent ones of the first paths is a second path region, and the second paths within two adjacent ones of the second path regions are interleaved.
[0027] In some embodiments, the orthogonal projection of the source extraction contact on the source layer is circular or square.
[0028] In another aspect, the present disclosure provides a memory, comprising: a semiconductor device provided by any of the above embodiments; and a peripheral circuit electrically connected to the semiconductor device; A memory comprising:
[0029] In yet another aspect, the present disclosure provides a memory system, comprising: a memory provided by any of the preceding embodiments; and a controller electrically connected to the memory and used to control the memory to store data; A memory system comprising:
[0030] The present disclosure has the beneficial effect of providing a semiconductor device, a memory, and a memory system, wherein the semiconductor device comprises an array device and a plurality of source drawer contacts, the array device comprises a plurality of channel structures and a source layer connected to the plurality of channel structures, the plurality of source drawer contacts are connected to the source layer, and the plurality of source drawer contacts and the plurality of channel structures are located on both sides of the source layer, respectively. The orthogonal projections of the plurality of source drawer contacts on the source layer are distributed at equal intervals, which can reduce the fluctuation of the voltage drop between the channel structure and the source drawer contact, control the voltage drop within a narrower range, and improve the performance of the semiconductor device. [Brief explanation of the drawings]
[0031] Specific embodiments of the present disclosure will be described in detail below in conjunction with drawings to reveal the technical solutions and other beneficial effects of the present disclosure. [Figure 1] 1 is a top view structural diagram I of a semiconductor device provided according to a first embodiment of the present disclosure; [Figure 2] 2 is a top view structural view II of a semiconductor device provided according to the first embodiment of the present disclosure; [Figure 3] 3 is a top view structural view III of a semiconductor device provided according to the first embodiment of the present disclosure; [Figure 4] FIG. 2 is a cross-sectional structural view taken along A-A1 in FIG. 1 of the present disclosure. [Figure 5]1 is a top view structural view of a semiconductor device having a metal interconnect layer provided by a first embodiment of the present disclosure. [Figure 6] 1 is a top view structural diagram I of a semiconductor device provided according to a second embodiment of the present disclosure; [Figure 7] 2 is a top view structural view II of a semiconductor device provided according to a second embodiment of the present disclosure; [Figure 8] FIG. 2 is a top view structural diagram of a semiconductor device having a metal interconnect layer provided by a second embodiment of the present disclosure. [Figure 9] 3 is a top view structural view III of a semiconductor device provided according to a second embodiment of the present disclosure; [Figure 10] FIG. 10 is a top structural view of a semiconductor device provided according to a third embodiment of the present disclosure. [Figure 11] FIG. 10 is a top view structural diagram of a semiconductor device having a metal interconnect layer provided by a third embodiment of the present disclosure. [Figure 12] FIG. 10 is a top view structural diagram I of a semiconductor device provided according to a fourth embodiment of the present disclosure. [Figure 13] FIG. 10 is a top view structural view I of a semiconductor device having a metal interconnect layer provided by a fourth embodiment of the present disclosure. [Figure 14] FIG. 2 is a top view structural view II of a semiconductor device provided according to a fourth embodiment of the present disclosure. [Figure 15] 2 is a top view structural view II of a semiconductor device having a metal interconnect layer provided by a fourth embodiment of the present disclosure. [Figure 16] FIG. 10 is a top structural view of a semiconductor device provided according to a fifth embodiment of the present disclosure. [Figure 17] FIG. 10 is a top structural view of a semiconductor device provided according to a sixth embodiment of the present disclosure. [Figure 18] FIG. 10 is a top structural view of a semiconductor device provided by a seventh embodiment of the present disclosure. [Figure 19] 1 is a structural diagram of a memory provided by an embodiment of the present disclosure. [Figure 20]1 is a structural diagram of a memory system provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION
[0032] The technical solutions in the embodiments of the present disclosure are clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative work shall fall within the protection scope of the present disclosure.
[0033] In this specification, terms such as "first," "second," etc. may be used to describe various components, but it should be understood that these components are not limited to such terms. Such terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the present disclosure.
[0034] When one element is referred to as being "on" or "connected to" another element, it should be understood that this may be directly on or connected to the other element, or there may be intervening elements. Other words used to describe relationships between elements should be interpreted similarly.
[0035] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend throughout an underlying or overlying structure, or may have an extent that is smaller than the extent of the underlying or overlying structure. Furthermore, a layer can be a uniform or non-uniform region of a continuous structure that has a thickness that is smaller than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of a continuous structure, or between any set of horizontal surfaces at the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer and can include one or more layers therein and / or have one or more layers above, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers and contact layers (in which contacts, interconnect lines, and / or vertical interconnect accesses (VIAs) are formed), as well as one or more dielectric layers.
[0036] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a landscape substrate such that the array structure extends in a direction perpendicular to the substrate. Using Cartesian coordinates to represent directions and referring to a substrate or source layer herein, the term "first direction" refers to a direction parallel to the substrate (or source layer), denoted by "X," the term "longitudinal direction" refers to a direction perpendicular to the substrate (or source layer) and also perpendicular to the X direction, denoted by "Z," and the term "second direction" refers to a direction perpendicular to X and Z, denoted by "Y," i.e., a direction parallel to the substrate (or source layer) and perpendicular to X.
[0037] It should be noted that the graphical representations provided in the embodiments of the present disclosure merely exemplarily illustrate the basic concepts of the present disclosure, and the graphical representations only show relevant components of the present disclosure, which are not drawn according to the number and shape of components or scale in the actual embodiment, but the shapes, number and scale of various components may be freely changed in the actual embodiment, and the layout form of the components may be more complicated.
[0038] An embodiment of the present disclosure provides a semiconductor device. For example, referring to FIGS. 1 to 4, a semiconductor device 100 may include an array device including multiple columns of gate line slit structures 10 extending in a first direction (X), channel structures 11 located between the gate line slit structures 10 in each column, and a source layer 1042 electrically connected to the multiple channel structures 11. The semiconductor device 100 further includes multiple source drawer contacts 12 electrically connected to the source layer 1042 and distributed at equal intervals on the surface of the source layer 1042, i.e., orthogonal projections of the multiple source drawer contacts 12 on the source layer 1042 are distributed at equal intervals. The source layer is located between the channel structure 11 and the source drawer contacts 12, i.e., the channel structure 11 and the multiple source drawer contacts 12 are located on both sides of the source layer in the vertical direction (e.g., the Z direction in FIG. 1). The semiconductor device 100 further comprises a metal interconnect layer 105 covering the source withdrawal contact 12 to electrically connect the source withdrawal contact 12 to the metal interconnect layer 105, and the metal interconnect layer 105 electrically connects the channel structure to an external circuit.
[0039] In some embodiments, the gate line slit structure 10 comprises at least two rows of first gate line slit structures 101 and at least one row of second gate line slit structures 102 between two adjacent rows of the first gate line slit structures 101, the first gate line slit structures 101 dividing the array device into a plurality of memory blocks and the second gate line slit structures 102 dividing the memory blocks into a plurality of finger memory blocks G1, wherein the first gate line slit structures 101 extend continuously in a first direction (X) and the second gate line slit structures 102 are separated along a second direction (Y), i.e., have a plurality of spaced apart segments smaller than the second gate line slit structures.
[0040] In some embodiments, the distance between the first gate line slit structures 101 in two adjacent rows may be equal. In some embodiments, the distance between the second gate line slit structures 102 in two adjacent rows may be equal. In some embodiments, the distance between any two adjacent rows of gate line slit structures 10 may be equal. For example, the two adjacent rows of gate line slit structures 10 have a first pitch P1 in the second direction (Y), and the first pitch P1 may refer to the distance from the top of the gate line slit structures 10 in one row to the top of the gate line slit structures 10 in the other row, or the distance from the bottom of the gate line slit structures 10 in one row to the bottom of the gate line slit structures 10 in the other row, in the two adjacent rows of gate line slit structures 10 in FIG. 1 .
[0041] Meanwhile, referring to Figure 4, Figure 4 is a cross-sectional structural view taken along A-A1 of Figure 1 of the present disclosure. The semiconductor device 100 comprises a substrate 110 in a longitudinal direction (Z), a peripheral device layer 120 on the substrate 110, a peripheral interconnect layer 102 on the peripheral device layer 120, an array interconnect layer 103 on the peripheral interconnect layer 102, an array device 104 on the array interconnect layer 103, a source pull-out contact 12 on the array device 104, and a metal interconnect layer 105 on the source pull-out contact 12.
[0042] In some embodiments, the array device 104 includes a deck 1041, a channel structure 11 passing through the deck 1041 in the longitudinal direction (Z), a gate line slit structure (not shown) passing through the deck 1041 in the longitudinal direction (Z), and a source layer 1042 located on the deck 1041 and electrically connected to the channel structure 11. The channel structure 11 includes an insulating layer 111 extending in the longitudinal direction (Z), a channel layer 112 surrounding the insulating layer 111, a memory layer 113 surrounding the channel layer 112, and the channel layer 112 having an end 1121 that is not covered by the memory layer 113. Specifically, the source layer 1042 covers the end 1121 of the channel layer 112 and is connected to the channel layer 112 of the channel structure 11.
[0043] In some embodiments, the metal interconnect layer 105 may comprise an Al path, the source layer 1042 may be N-type doped polysilicon, and the deck 1041 is formed by alternating stacks of interlayer insulating layers and gate layers. The top surface graphic of the source drawer contact 12 (see FIG. 4) or the orthogonal projection of the source drawer contact 12 on the source layer 1042 may be circular or square, or in some other embodiments, the top surface graphic of the source drawer contact 12 (see FIG. 4) or the orthogonal projection of the source drawer contact 12 on the source layer 1042 may be other shapes, for example, strip-shaped, petal-shaped, spindle-shaped, dumbbell-shaped.
[0044] When the channel layer 112 of the channel structure 11 forms an electrical connection with the source drawer contact 12 through the source layer 1042, the distribution state of the source drawer contact 12 becomes particularly important given the length of the channel structure 11 and the thickness of the source layer 1042, so the distance from different channel structures 11 to the source drawer contact 12 depends on the distance between the channel structure 11 and the source drawer contact 12 in the XY plane, and it can be understood that the distribution of the channel structures 11 around the source drawer contact 12 and the distance from the channel structure 11 to the source drawer contact 12 affect the voltage drop.
[0045] In some embodiments of the present disclosure, the orthogonal projections of the multiple source drawer contacts 12 on the source layer 1042 are equally spaced, and the equally spaced distribution may be embodied using a number of forms, for example, by an equally spaced distribution in the first direction (X) and / or the second direction (Y) and / or other directions, for example, in some embodiments, the multiple source drawer contacts 12 are arranged in multiple rows along the first direction (X), and the source drawer contacts 12 in the same row are equally spaced along the first direction (X). Alternatively, in some embodiments, the multiple source drawer contacts 12 are arranged in multiple rows along the first direction (X), and the distance between the source drawer contacts 12 in any two adjacent rows is equal. Alternatively, in some embodiments, the plurality of source drawer contacts 12 are arranged in a plurality of rows along the first direction (X), with the source drawer contacts 12 in the same row being equally spaced along the first direction (X), and the source drawer contacts 12 in different rows being aligned in the second direction (Y). Alternatively, in some embodiments, the plurality of source drawer contacts 12 are arranged in a plurality of rows along the first direction (X), with the source drawer contacts 12 in the same row being equally spaced along the first direction (X), and the source drawer contacts 12 in two adjacent rows being offset in the first direction (X). It will be understood that the above embodiments may be freely combined to obtain a plurality of arrangement methods for equally spaced distribution of the source drawer contacts 12. For example, the source drawer contacts 12 in the same row are equally spaced along the first direction (X), while the distance between the source drawer contacts 12 in two adjacent rows is equal.
[0046] In an embodiment of the present disclosure, the source drawer contacts 12 in the semiconductor device 100 are distributed at equal intervals on the surface of the source layer 1042, while the source layer 1042 covers the channel structures 11, and the channel structures 11 are distributed at relatively equal intervals around each source drawer contact 12, resulting in approximately the same distribution of voltage drops around all the source drawer contacts 12, which can reduce the voltage drop between the channel structures 11 and the source drawer contacts 12 and improve the performance of the semiconductor device.
[0047] 1 to 3, FIGS. 1 to 3 may be considered as structural diagrams of a semiconductor device provided by the first embodiment of the present disclosure, where FIG. 1 is a top structural diagram I of a semiconductor device provided by the first embodiment of the present disclosure, FIG. 2 is a top structural diagram II of a semiconductor device provided by the first embodiment of the present disclosure, and FIG. 3 is a top structural diagram III of a semiconductor device provided by the first embodiment of the present disclosure.
[0048] In this embodiment, the two adjacent rows of source drawer contacts 12 have a second pitch P2 in a second direction (Y) perpendicular to the first direction (X), and the second pitch P2 may refer to the distance from the top of the source drawer contacts 12 in one row to the top of the source drawer contacts 12 in a row adjacent to the source drawer contacts 12 in that row, or the distance from the bottom of the source drawer contacts 12 in one row to the bottom of the source drawer contacts 12 in a row adjacent to the source drawer contacts 12 in that row, in the two adjacent rows of source drawer contacts 12 in Figures 1 to 3.
[0049] 1, the first pitch P1 of the finger memory block G1 is smaller than the second pitch P2 between the source drawer contacts 12. As shown in FIG. 2, the first pitch P1 of the finger memory block G1 is larger than the second pitch P2 between the source drawer contacts 12. As shown in FIGS. 1 and 2, the source drawer contacts 12 include a first source drawer contact 121 and a second source drawer contact 122. A projection of the first source drawer contact 121 on a plane (XY plane) formed by the source layer 1042 is located between projections of two adjacent rows of gate line slit structures 10 on the plane. A projection of the second source drawer contact 122 has an overlapping portion with a projection of the gate line slit structure 10 on the plane.
[0050] As shown in FIG. 3, the first pitch P1 of the finger memory block G1 is perfectly matched with the second pitch P2 of the source draw contacts 12, i.e., P1=P2, so that the positions of all the source draw contacts 12 within one finger memory block G1 are the same, and then the voltage drop distributions around all the source draw contacts 12 are substantially the same.
[0051] Continuing with reference to FIG. 3, when the source drawer contacts 12 and finger memory blocks G1 are projected onto a single XY plane along the longitudinal direction (Z), the source drawer contacts 12 of each column (arranged in the first direction (X)) may be located at the center of the finger memory block G1, i.e., the source drawer contacts 12 are located at the center of the finger memory block G1 in the second direction (Y), and in the second direction (Y), the channel structures 11 on both sides of the source drawer contacts 12 are all distributed symmetrically, and the voltage drop distribution on both sides of the source drawer contacts 12 is approximately the same. More specifically, in one finger memory block G1, the distance D1 from the channel structure 11 of the first column and the channel structure 11 of the ninth column to the source draw contact 12 is the same (same voltage drop), and the distance D2 from the channel structure 11 of the second column and the channel structure 11 of the eighth column to the source draw contact 12 is the same (same voltage drop) so that the voltage drop also varies evenly within each finger memory block G1.
[0052] In the semiconductor device 100 provided by the first embodiment of the present disclosure, the source drawer contacts 12 are uniformly distributed on the source layer 1042, the distribution of the channel structures 11 around all the source drawer contacts 12 is approximately the same, and the voltage drop changes around all the source drawer contacts 12 are approximately the same, which can make the voltage drop between the source drawer contacts 12 and the channel structures 11 relatively stable, control the voltage drop within a narrower range, and improve device performance. In one embodiment, the source drawer contacts 12 in FIG. 3 are located in the center of the finger memory block G1 so that the channel structures 11 around them are symmetrically distributed with respect to the source drawer contacts 12. For example, the channel structures 11 in the region R in FIG. 3 function as the channel structures 11 around the source drawer contacts 12 therein. Taking the region R as an example, the channel structures 11 above and below this source drawer contact 12 in FIG. 3 are symmetrically distributed, and the channel structures 11 on the left and right sides of this source drawer contact 12 in FIG. 3 are symmetrically distributed.
[0053] Continuing with reference to FIG. 5, FIG. 5 is a top structural view of a semiconductor device having a metal interconnection layer provided by a first embodiment of the present disclosure. The semiconductor device 100 further includes a metal interconnection layer 13 covering a plurality of source draw contacts 12. This embodiment takes the semiconductor device 100 of FIG. 3 as an example to describe the pattern of the metal interconnection layer 13 of the semiconductor device 100. The metal interconnection layer 13 includes a plurality of first paths 131 that extend continuously and are parallel to each other, and a plurality of second paths 132 that connect two adjacent ones of the first paths 131 and intersect with (e.g., perpendicular to) the first paths 131. Therefore, all the metal paths are connected to each other, and if one of the first paths 131 fails anywhere, a signal may be transmitted to the failed first path 131 through another first path 131 and the second path 132, thereby improving the stability and reliability of signal transmission.
[0054] In this embodiment, one first path 131 covers one row of source lead contacts 12, and the second paths 132 are located between two adjacent first paths 131 and are arranged perpendicular to the first paths 131. The region between two adjacent ones of the first paths 131 is a second path region, and the second paths 132 in two adjacent ones of the second path regions are interleaved.
[0055] Regarding the structure of the metal interconnect layer of the semiconductor device 100 of Figures 1 and 2, referring to Figure 5, it can be understood that the corresponding structure of the metal interconnect layer can be obtained by adjusting the distance between the first paths.
[0056] 6, which is a top structural view I of a semiconductor device provided by a second embodiment of the present disclosure. The semiconductor device 200 includes a plurality of gate line slit structures 20 (comprising a first gate line slit structure 201 and a second gate line slit structure 202) extending in a first direction (X), a channel structure 21 located between the plurality of gate line slit structures 20, a source layer electrically connected to the channel structure 21, a plurality of source drawer contacts 22 on the source layer, and a metal interconnection layer covering the plurality of source drawer contacts 22.
[0057] The top graphic of the source drawer contacts 22 is strip-shaped, and the orthogonal projection of the source drawer contacts 22 on the source layer is strip-shaped. The length direction of the source drawer contacts 22 coincides with the first direction (X), and the width direction coincides with the second direction (Y). The source drawer contacts 22 in the same row are distributed at equal intervals along the first direction (X), and the source drawer contacts 22 in different rows are aligned in the second direction (Y).
[0058] Any two adjacent rows of gate line slit structures 20 have a first pitch P3 in the second direction (Y), and any two adjacent rows of source drawer contacts 22 have a second pitch P4 in the second direction (Y), where the second pitch P4 is equal to the first pitch P3. Note that the first pitch P3 refers to the distance from the top of the gate line slit structures 20 in one row to the top of the gate line slit structures 20 in the other row, or the distance from the bottom of the gate line slit structures 20 in one row to the bottom of the gate line slit structures 20 in the other row, in the two adjacent rows of gate line slit structures 20 in Figure 6. The second pitch P4 refers to the distance from the top of the source drawer contacts 22 in one row to the top of the source drawer contacts 22 in the other row, or the distance from the bottom of the source drawer contacts 22 in one row to the bottom of the source drawer contacts 22 in the other row, in the two adjacent rows of source drawer contacts 22 in Figure 6.
[0059] In this embodiment, the source drawer contact 22 is located between two rows of gate line slit structures 20 and is located in the center of the finger memory block G2 in the second direction (Y), i.e., the distance from the source drawer contact 22 to the upper row of gate line slit structures 20 and the lower row of gate line slit structures 20 is equal, and therefore the channel structures 21 around each of the source drawer contacts 22 are distributed symmetrically; for example, in Figure 6, the channel structures 21 above and below the source drawer contact 22 are distributed symmetrically, and the channel structures 21 on the left and right sides of the source drawer contact 22 are distributed symmetrically.
[0060] 4, the source draw contact 22 of the semiconductor device 200 of the second embodiment increases the contact area with the source layer in the first direction (X), and therefore can reduce the voltage drop caused by resistance and capacitance. Meanwhile, because the size of the source draw contact 22 increases in the first direction (X), the metal interconnect layer can be more easily aligned with the source draw contact 22 during the fabrication of the subsequent metal interconnect layer, and the effective process window for fabricating the source draw contact 22 and the metal interconnect layer is also increased.
[0061] 7, which is a top structural view II of a semiconductor device provided by a second embodiment of the present disclosure. The semiconductor device 200 differs from the second embodiment in that the source drawer contacts 22 in different columns are not aligned one by one in the second direction (Y). In particular, the source drawer contacts 22 in the second column are offset relative to the source drawer contacts 22 in the first column in the first direction (X). For example, the offset distance of the source drawer contacts 22 in the second column is W compared to the source drawer contacts 22 in the first column in the first direction (X). One source drawer contact 22 in the second column is located exactly midway between two adjacent source drawer contacts 22 in the first column. In other words, when two adjacent source drawer contacts 22 in one column have a symmetry axis B-B1, the left and right sides of one source drawer contact 22 in another column adjacent to the source drawer contact 22 in that column are symmetrical with respect to the symmetry axis B-B1. Therefore, the offset source lead contacts 22 are also evenly distributed within one memory block. In Fig. 7, the source lead contacts 22 may be located in the center of the finger memory block G2 to evenly change the voltage drop of each finger memory block G2, thereby improving the uniformity of device performance.
[0062] 8, which is a top structural view of a semiconductor device having a metal interconnect layer provided by a second embodiment of the present disclosure. The semiconductor device 200 further includes a metal interconnect layer 23 covering the plurality of source pull-out contacts 22. The metal interconnect layer 23 includes a plurality of continuously extending parallel first paths 231 and a plurality of second paths 232 connecting two adjacent ones of the first paths 231 and intersecting (e.g., perpendicular to) the first paths 231. Therefore, all the metal paths are connected to each other, and if one of the first paths 231 fails anywhere, a signal can be transmitted to the failed first path 231 via another first path 231 and the second path 232.
[0063] In the second embodiment, the plurality of first paths 231 cover the plurality of source drawer contacts 22 and extend continuously along the length direction of the source drawer contacts 22. The region between two adjacent ones of the first paths 231 is a second path region, and the second paths 232 in two adjacent ones of the second path regions are interleaved. Specifically, the orthogonal projection of one second path 232 in the second column on the XY plane is located midway between the orthogonal projections of two adjacent second paths 232 in the first column on the XY plane to evenly distribute the metal paths within the memory block.
[0064] 9, which is a top view structural diagram III of a semiconductor device provided by a second embodiment of the present disclosure. The semiconductor device 200 differs from that of FIG. 6 in that the length direction of the source drawer contacts 22 has an included angle with the first direction (X), that is, the source drawer contacts 22 are inclinedly distributed within the finger memory block G2. In this embodiment, the source drawer contacts 22 are aligned in the second direction (Y). In some embodiments, the source drawer contacts 22 of different columns may be interleaved in the first direction (X), and details may refer to FIG. 7.
[0065] Referring to FIG. 10, FIG. 10 is a top structural view of a semiconductor device provided according to a third embodiment of the present disclosure. For ease of understanding, the semiconductor device 300 uses the same structural numbers as the semiconductor device 200 of the second embodiment. The semiconductor device 300 differs from the semiconductor device 200 in that any adjacent gate line slit structures 20 have a first pitch P5 therebetween, and any two adjacent rows of source lead contacts 22′ have a second pitch P6 therebetween, P5 being larger than P6. Note that the first pitch P5 refers to the distance from the top of one row of gate line slit structures 20 to the top of the other row of gate line slit structures 20, or the distance from the bottom of one row of gate line slit structures 20 to the bottom of the other row of gate line slit structures 20, in the two adjacent rows of gate line slit structures 20 in FIG. 10. The second pitch P6 refers to the distance from the top of the source drawer contacts 22 in one row to the top of the source drawer contacts 22 in the other row in two adjacent rows of source drawer contacts 22 in Figure 10, or the distance from the bottom of the source drawer contacts 22 in one row to the bottom of the source drawer contacts 22 in the other row.
[0066] 10, in some embodiments, the projection of two adjacent rows of gate line slit structures 20 on the XY plane simply has the projection of multiple rows of source draw contacts 22′ on the plane, i.e., the projection of adjacent gate line slit structures 20 simply has the projection of multiple rows of source draw contacts 22′. In other words, one finger memory block G2 has multiple rows of source draw contacts 22′ therein. In this embodiment, one finger memory block G2 has two rows of source draw contacts 22′ therein.
[0067] In some embodiments, the distance between any source pull-out contact 22' and the adjacent gate line slit structure 20 is P0, and the distance between any two rows of source pull-out contacts 22' is equal to 2P0. The difference between P6 and 2P0 is equal to the width of the source pull-out contacts 22' in the second direction (Y).
[0068] In some embodiments, P5=2P6, so the difference between P5 and 4P0 is equal to twice the width of the source lead contact 22'.
[0069] 11, which is a top structural view of a semiconductor device having a metal interconnect layer provided according to a third embodiment of the present disclosure. The path distribution of the metal interconnect layer 23′ is similar to that of FIG. 8, except that the number of first paths 231′ increases according to the number of columns of source extraction contacts 22′, so that the number of second paths 232′ also increases.
[0070] In some embodiments, the width of the source drawer contact 22′ in the second direction (Y) may be narrower than the width of the source drawer contact 22 in the second direction (Y) in the semiconductor device 200. The width of the source drawer contact 22′ in the second direction (Y) may be narrower than the width of the source drawer contact 12 in the second direction (Y) in the semiconductor device 100, and the width of the source drawer contact 22′ (referring to the length of the strip-shaped source drawer contact 22′) in the first direction (X) may be narrower than the width of the source drawer contact 12 in the first direction (X) in the semiconductor device 100. When the width of the source drawer contact 22′ in the second direction (Y) is reduced, the width of the first vias 231′ in the metal interconnect layer 23′ in the second direction (Y) can also be reduced accordingly, thereby ensuring that the pitch of the first vias 231′ is not too small and reducing the electrical influence between the first vias 231′.
[0071] 12, which is a top structural view I of a semiconductor device provided by a fourth embodiment of the present disclosure. The semiconductor device 400 includes a gate line slit structure 30 (including a first gate line slit structure 301 and a second gate line slit structure 302), a channel structure 31, a source layer, a source drawer contact 32, and a metal interconnect layer. The semiconductor device 400 differs from the semiconductor device 200 in that the orientation of the source drawer contact 32 in the finger memory block G3 is different, and the length direction of the source drawer contact 32 coincides with the second direction (Y) and the width direction thereof coincides with the first direction (X). The source drawer contacts 32 in different columns are aligned in the second direction (Y).
[0072] 13, which is a top structural view I of a semiconductor device having a metal interconnection layer provided by a fourth embodiment of the present disclosure. The semiconductor device 400 further includes a metal interconnection layer 33 covering a plurality of source drawer contacts 32. Taking the semiconductor device 400 of FIG. 12 as an example, the metal interconnection layer 33, which has a pattern similar to that of the metal interconnection layer 23 of FIG. 8, includes a plurality of first paths 331 that extend continuously and are parallel to each other, and a plurality of second paths 332 that connect two adjacent ones of the first paths 331 and are perpendicular to the first paths 331. The plurality of first paths 331 cover the plurality of source drawer contacts 32 and extend continuously along the length direction of the source drawer contacts 32, and the second paths 332 of adjacent second path regions are interleaved and distributed in the second direction (Y).
[0073] 14, which is a top structural view II of a semiconductor device provided by a fourth embodiment of the present disclosure. The semiconductor device 400 differs from the semiconductor device 300 of the fourth embodiment in that the source drawer contacts 32 of different columns are distributed in a shifted position in the first direction (X). In some embodiments, the source drawer contacts 32 of one column are located exactly in the center of the source drawer contacts 32 of an adjacent column, and the source drawer contacts 32 of two columns separated by one column are aligned in the second direction (Y), so that the source drawer contacts 32 are evenly distributed within the memory block, thereby controlling the voltage drop within a narrower range.
[0074] 15, which is a top view structural diagram II of a semiconductor device having a metal interconnection layer provided by a fourth embodiment of the present disclosure. In this embodiment, taking the semiconductor device 400 of FIG. 14 as an example, the metal interconnection layer 33 includes a plurality of first paths 331 that extend continuously and are parallel to each other, and a plurality of second paths 332 that connect two adjacent rows of the plurality of first paths 331 and are perpendicular to the plurality of first paths 331. As can be seen from the second embodiment of FIG. 8, the third embodiment of FIG. 11, and the fourth embodiment of FIG. 13, the continuously extending first paths 331 all run along the length of the source draw contact 32. However, in the embodiment of FIG. 15, the continuous first paths 331 extend along the gate line slit structure 30, with each first path 331 covering one row of the gate line slit structure 30, and the first paths 331 of two adjacent rows being connected to both ends of the source draw contact 32. The second vias 332 only cover the source drawer contacts 32 and are the same in number and position as the source drawer contacts 32 except that the second vias 332 are longer and wider than the source drawer contacts 32 .
[0075] 16, which is a top structural view of a semiconductor device provided by a fifth embodiment of the present disclosure. For ease of understanding, the semiconductor device 500 continues to use the structural numbers of the second embodiment 200. The semiconductor device 500 differs from the semiconductor device 200 in that, when the source drawer contact 22 and the gate line slit structure 20 are projected onto an XY plane along the longitudinal direction (Z), the source drawer contact 22 has an overlapping portion with the gate line slit structure 20. For example, the projection of the source drawer contact 22 on the XY plane along the longitudinal direction (Z) is symmetrical with respect to the projection of the gate line slit structure 20 on the XY plane along the longitudinal direction (Z).
[0076] In the fifth embodiment, the metal interconnect layer has the same pattern as the metal interaction layer 23 of the second embodiment, and the metal interconnect layer of the semiconductor device 500 of the fifth embodiment can be obtained by shifting the entire pattern of the metal interconnect layer 23 of FIG. 8 by a distance in the second direction (Y) to move the metal interconnect layer 23 to a position that coincides with the gate line slit structure 20.
[0077] 17, which is a top structural view of a semiconductor device provided by a sixth embodiment of the present disclosure. For ease of understanding, the semiconductor device 600 continues to use the structural numbers of the second embodiment 200. When the source lead contact 22 and the gate line slit structure 20 are projected onto an XY plane along the longitudinal direction (Z), the source lead contact 22 has an overlapping portion with the gate line slit structure 20.
[0078] The semiconductor device 600 differs from the semiconductor device 500 of the fifth embodiment in that a first pitch P1 between the two rows of gate line slit structures 20 is smaller than a second pitch P2 between the two rows of source drawer contacts 22, for example, P2=2P1. This distribution of the source drawer contacts 22 can also make the distribution of the channel structures around each of the source drawer contacts 22 the same, i.e., the channel structures 21 around the source drawer contacts 22 are symmetrically distributed with a uniform change in distance, so that the voltage drop from the channel structures 21 to the source drawer contacts 22 changes evenly, thereby improving the uniformity of device performance.
[0079] In some embodiments, to reduce the range of voltage drop, the size of the source drawer contact 22 can be increased, which corresponds to an increase in the contact area between the source drawer contact 22 and the source layer. For example, the source drawer contact 22 of the semiconductor device 600 may be larger in size than the source drawer contact 22 of the semiconductor device 500.
[0080] 18, which is a top structural view of a semiconductor device provided by a seventh embodiment of the present disclosure. The semiconductor device 700 includes multiple rows of gate line slit structures 40 and a channel structure 41 between two adjacent rows of the gate line slit structures 40. The gate line slit structures 40 include at least two rows of first gate line slit structures 401 and at least one row of second gate line slit structures 402 between the two adjacent rows of the first gate line slit structures 401. One finger memory block G4 may be located between the two adjacent rows of the gate line slit structures 40. Note that the channel structure 41 is not actually visible in the top view and is shown in FIG. 18 only to illustrate the positional relationship between the source lead contact 42 and the channel structure 41.
[0081] In some embodiments, the source drawer contacts 42 are arranged in one-to-one correspondence with the channel structures 41. In some embodiments, the channel structures 41 are distributed at equal intervals, and the source drawer contacts 42 are also distributed at equal intervals. The orthogonal projection of each source drawer contact 42 on the XY plane overlaps with the orthogonal projection of one channel structure 41 on the XY plane. In one embodiment, the orthogonal projection of the channel structure 41 is located at the center of the orthogonal projection of the source drawer contact 42.
[0082] 19, which is a structural diagram of a memory provided by an embodiment of the present disclosure. The memory 800 may be a three-dimensional memory, such as a 3D NAND memory and a 3D NOR memory.
[0083] The memory 800 includes a semiconductor device 801 and a peripheral circuit 802. The semiconductor device 801 may be any of the semiconductor devices in the above embodiments, and the peripheral circuit 802 may be a CMOS (Complementary Metal Oxide Semiconductor). The peripheral circuit 802 is electrically connected to the semiconductor device 801 for communicating signals with the semiconductor device 801. The peripheral circuit 802 may be used for logic operations and for controlling and detecting the switching states of various memory cells in the semiconductor device 801 through metal lines to store and read data.
[0084] The semiconductor device 801 includes an array device having a plurality of channel structures and a source layer connected to the plurality of channel structures, and a plurality of source drawer contacts connected to the source layer. The plurality of source drawer contacts and the plurality of channel structures are located on both sides of the source layer, respectively, and orthogonal projections of the plurality of source drawer contacts on the source layer are distributed at equal intervals.
[0085] 20, which is a structural diagram of a memory system provided by an embodiment of the present disclosure. The memory system 900 includes a memory 901 and a controller 902. The memory 901 may be the memory in any of the above embodiments or may include any of the semiconductor devices in the above embodiments. The controller 902 is electrically connected to the memory 901 and is used to control the memory 901 to store data, and the memory 901 may perform an operation to store data based on the control of the controller 902.
[0086] In some embodiments, the memory system may be implemented as, for example, a Universal Flash Storage (UFS) device, a Solid State Disk (SSD), a Multimedia Card in MMC, eMMC, RS-MMC, and microMMC formats, a Secure Digital Card in SD, miniSD, and microSD formats, a PC Memory Card International Association (PCMCIA) card type memory device, a Peripheral Component Interconnect (PCI) type memory device, a PCI Express (PCI-E) type memory device, a CompactFlash (registered trademark) (CF) card, a SmartMedia card, or a memory stick.
[0087] The semiconductor device in the memory 901 includes an array device having a plurality of channel structures and a source layer connected to the plurality of channel structures, and a plurality of source drawer contacts connected to the source layer. The plurality of source drawer contacts and the plurality of channel structures are located on both sides of the source layer, respectively, and orthogonal projections of the plurality of source drawer contacts on the source layer are distributed at equal intervals.
[0088] The above description of the embodiments is only used to help understand the technical solutions of the present disclosure and their core ideas. Those skilled in the art should understand that the technical solutions specified in the above embodiments can be modified or some of the technical features can be replaced with equivalents, but these modifications and replacements will not deviate the essence of each technical solution from the scope of the technical solutions of the various embodiments of the present disclosure.
Claims
1. A semiconductor device comprising: an array device comprising a channel structure and a source layer connected to the channel structure; a source lead contact connected to the source layer; Equipped with the channel structure and the source extraction contact are located on opposite sides of the source layer, respectively; the orthogonal projections of the source extension contacts on the source layer are equally spaced; the semiconductor device further comprises a row of gate line slit structures extending along a first direction parallel to the source layer; an orthogonal projection of each of the source lead contacts on the source layer is located between orthogonal projections of two adjacent rows of gate line slit structures on the source layer; Semiconductor devices.
2. The semiconductor device of claim 1 , wherein two adjacent rows of the gate line slit structures have a first pitch therebetween.
3. the source lead contacts are arranged in a plurality of rows along the first direction; the source lead contacts in the same row are equally spaced along the first direction; The semiconductor device of claim 2 .
4. the source lead contacts are arranged in a plurality of rows along the first direction; two adjacent rows of the source lead contacts have a second pitch therebetween; the second pitch between the source lead contacts of any two adjacent rows is the same; The semiconductor device of claim 2 .
5. The semiconductor device of claim 4 , wherein the first pitch is equal to the second pitch.
6. 2. The semiconductor device of claim 1, wherein an orthogonal projection of each of the source pull-out contacts on the source layer is located at a center between orthogonal projections of two adjacent rows of gate line slit structures on the source layer.
7. 2. The semiconductor device according to claim 1, wherein the orthogonal projections of two adjacent rows of gate line slit structures on the source layer have orthogonal projections of the rows of source lead contacts on the source layer therebetween.
8. A semiconductor device comprising: an array device comprising a channel structure and a source layer connected to the channel structure; a source lead contact connected to the source layer; Equipped with the channel structure and the source extraction contact are located on opposite sides of the source layer, respectively; the semiconductor device further comprises a row of gate line slit structures extending along a first direction parallel to the source layer; the orthogonal projections of the source extension contacts on the source layer are equally spaced; two adjacent rows of the gate line slit structures have a first pitch therebetween; the source lead contacts are arranged in a plurality of rows along the first direction; two adjacent rows of the source lead contacts have a second pitch therebetween; the second pitch between the source lead contacts of any two adjacent rows is the same; The first pitch is smaller than the second pitch.
9. A semiconductor device comprising: an array device comprising a channel structure and a source layer connected to the channel structure; a source lead contact connected to the source layer; Equipped with the channel structure and the source extraction contact are located on opposite sides of the source layer, respectively; the orthogonal projections of the source extension contacts on the source layer are equally spaced; the semiconductor device further comprises a row of gate line slit structures extending along a first direction parallel to the source layer; the source lead contacts include a first source lead contact and a second source lead contact; an orthogonal projection of the first source lead contact on the source layer is located between orthogonal projections of two adjacent rows of gate line slit structures on the source layer; an orthogonal projection of the second source lead contact on the source layer has an overlapping portion with an orthogonal projection of the gate line slit structure on the source layer; Semiconductor devices.
10. The semiconductor device of claim 1 , wherein the source extraction contacts are disposed in one-to-one correspondence with the channel structures.
11. an orthogonal projection of the source extraction contact on the source layer is strip-shaped; The length direction is aligned along the first direction. The semiconductor device of claim 1 .
12. an orthogonal projection of the source extraction contact on the source layer is strip-shaped; The width direction is arranged along the first direction. The semiconductor device of claim 1 .
13. an orthogonal projection of the source extraction contact on the source layer is strip-shaped; The length direction has an included angle with the first direction. The semiconductor device of claim 1 .
14. the source lead contacts are arranged in a plurality of rows along the first direction; the plurality of rows of source lead contacts are aligned in a second direction perpendicular to the first direction and parallel to the source layers; The semiconductor device of claim 1 .
15. the source lead contacts are arranged in a plurality of rows along the first direction; the source lead contacts in two adjacent rows are distributed with a shift in position in the first direction; The semiconductor device of claim 1 .
16. The semiconductor device of claim 1 , further comprising a metal interconnect layer covering the source lead contact.
17. The semiconductor device of claim 1 , wherein an orthogonal projection of the source extraction contact on the source layer is circular or square.
18. 1. A memory device comprising: an array device comprising a channel structure and a source layer connected to the channel structure; a source lead contact connected to the source layer; the channel structure and the source extraction contact are located on opposite sides of the source layer, respectively; the orthogonal projections of the source extension contacts on the source layer are equally spaced; a semiconductor device; a peripheral circuit electrically connected to the semiconductor device; Equipped with the semiconductor device further comprises a row of gate line slit structures extending along a first direction parallel to the source layer; A memory device, wherein the orthogonal projection of each of the source lead contacts on the source layer is located between the orthogonal projections of two adjacent rows of gate line slit structures on the source layer.
19. 1. A memory system comprising: an array device comprising a channel structure and a source layer connected to the channel structure; a source lead contact connected to the source layer; the channel structure and the source extraction contact are located on opposite sides of the source layer, respectively; the orthogonal projections of the source extension contacts on the source layer are equally spaced; a semiconductor device; a peripheral circuit electrically connected to the semiconductor device; a memory device comprising: a controller electrically connected to the memory device and used to control the memory device to store data; Equipped with the semiconductor device further comprises a row of gate line slit structures extending along a first direction parallel to the source layer; A memory system, wherein an orthogonal projection of each of the source lead contacts on the source layer is located between orthogonal projections of two adjacent rows of gate line slit structures on the source layer.