Optical device

Abstract

To provide an optical device in which a decrease in light-emitting efficiency is suppressed.SOLUTION: A method for manufacturing an optical device includes: an etching step of exposing a first semiconductor layer having active layers (first active layer 12, second active layer 14, third active layer 16) made of a Group III nitride semiconductor containing In to the atmosphere, and then etching the surface of the first semiconductor layer using gas containing hydrogen; and a regrowth step of forming a second semiconductor layer (electron blocking layers 19A-19C, p-type layers 20A-20C) made of a Group III nitride semiconductor on the first semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to optical devices. [Background technology]

[0002] In recent years, there has been a demand for higher resolution displays, and micro LED displays, in which each pixel is a tiny LED on the order of 1 to 100 μm, have been attracting attention. There are various methods for achieving full color, including a method in which three active layers that emit light in blue, green, and red, respectively, are stacked in order on the same substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-195529 Summary of the Invention [Problem to be solved by the invention]

[0004] In a light-emitting device in which three active layers are stacked in order on the same substrate, a process is required in which crystal growth is completed, the wafer is removed from the growth furnace, grooves are formed, and then the wafer is returned to the growth furnace to re-grow the semiconductor layers.

[0005] However, the inventors' investigations revealed that this process contaminates the wafer with impurities. These impurities result in unintended n-type doping, which creates non-radiative recombination centers. Furthermore, an unintended n-type layer is formed at the regrowth interface, changing the band structure. Furthermore, dry etching to form the grooves creates damage to the surface. This results in problems such as reduced internal quantum efficiency and reduced injection efficiency. The presence of a regrowth interface in the region close to the active layer, especially within the pn junction interface, significantly reduces luminous efficiency.

[0006] The present invention has been made in view of the above background, and aims to provide an optical device in which the decrease in light emission efficiency is suppressed. [Means for solving the problem]

[0007] One aspect of the present invention is an etching step of exposing a first semiconductor layer having an active layer made of a group III nitride semiconductor containing In to the atmosphere, and then etching a surface of the first semiconductor layer using a gas containing hydrogen; a regrowth step of forming a second semiconductor layer made of a Group III nitride semiconductor on the first semiconductor layer; The present invention relates to a method for manufacturing an optical device having the above structure.

[0008] Another aspect of the present invention is an n-type layer forming step of forming an n-type layer made of an n-type Group III nitride semiconductor on the substrate; a first active layer forming step of forming a first active layer on the n-type layer, the first active layer including a well layer made of a group III nitride semiconductor containing In and having a predetermined emission wavelength; an intermediate layer forming step of forming an intermediate layer made of a group III nitride semiconductor containing In on the first active layer; a second active layer forming step of forming a second active layer on the intermediate layer, the second active layer including a well layer made of a group III nitride semiconductor containing In and having an emission wavelength different from that of the first active layer; a groove forming step of forming a groove having a depth reaching the intermediate layer from the second active layer side; an etching step of etching the bottom surface of the groove using a gas containing hydrogen after the bottom surface of the groove is exposed to the atmosphere in the groove forming step; a p-type layer forming step of forming a first p-type layer and a second p-type layer made of a p-type Group III nitride semiconductor on the second active layer and on the bottom surface of the groove, respectively; The present invention relates to a method for manufacturing an optical device having the above structure. [Effects of the Invention]

[0009] In the above embodiment, the surface of the first semiconductor layer can be etched with a gas containing hydrogen, thereby reducing impurities. Then, the second semiconductor layer can be regrown on the first semiconductor layer with reduced impurities. Therefore, a decrease in luminous efficiency can be suppressed.

[0010] As described above, according to the above aspect, it is possible to provide an optical device in which the decrease in light emission efficiency is suppressed. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view showing the configuration of a light-emitting element according to an embodiment, taken along a plane perpendicular to a main surface of a substrate. [Figure 2] 8A to 8C are diagrams illustrating a manufacturing process of the light emitting device according to the embodiment, and correspond to step S1 in FIG. 7. [Figure 3] 8A to 8C are diagrams illustrating a manufacturing process of the light emitting device according to the embodiment, and correspond to step S2 in FIG. 7. [Figure 4] 8A to 8C are diagrams illustrating a manufacturing process of the light emitting device according to the embodiment, and correspond to step S3 in FIG. 7. [Figure 5] 8A to 8C are diagrams illustrating a manufacturing process of the light emitting device according to the embodiment, and correspond to step S4 in FIG. 7. [Figure 6] 8A to 8C are diagrams illustrating a manufacturing process of the light emitting device according to the embodiment, and correspond to step S5 in FIG. 7. [Figure 7] 3 is a flowchart showing a manufacturing process of a light emitting element according to an embodiment. [Figure 8] 10 is a graph showing the relationship between the flow rate ratio of hydrogen gas and the light output. DETAILED DESCRIPTION OF THE INVENTION

[0012] A method for manufacturing an optical device includes the steps of: exposing a first semiconductor layer having an active layer made of a group III nitride semiconductor containing In to the atmosphere; etching a surface of the first semiconductor layer using a gas containing hydrogen; and regrowing a second semiconductor layer made of a group III nitride semiconductor on the first semiconductor layer. The second semiconductor layer may include a p-type layer.

[0013] a first active layer forming step of forming a first active layer on the n-type layer, the first active layer including a well layer made of a Group III nitride semiconductor containing In and having a predetermined emission wavelength; an intermediate layer forming step of forming an intermediate layer on the first active layer, the intermediate layer including an In-containing Group III nitride semiconductor; a second active layer forming step of forming a second active layer on the intermediate layer, the second active layer including a well layer made of a Group III nitride semiconductor containing In and having an emission wavelength different from that of the first active layer; a groove forming step of forming grooves having a depth reaching from the second active layer side to the intermediate layer; an etching step of exposing the bottom surfaces of the grooves to the atmosphere in the groove forming step and then etching the bottom surfaces of the grooves using a hydrogen-containing gas; and a p-type layer forming step of forming a first p-type layer and a second p-type layer, each made of a p-type Group III nitride semiconductor, on the second active layer and on the bottom surfaces of the grooves, respectively.

[0014] In the method for manufacturing an optical device, the hydrogen-containing gas may be a mixed gas of hydrogen and ammonia. This allows the etching rate to be suppressed and the etching depth to be controlled with precision. In this case, the volume ratio of hydrogen to the entire mixed gas may be greater than the volume ratio of ammonia to the entire mixed gas.

[0015] In the method for manufacturing an optical device, the etching step may be performed while raising the temperature, which can serve as the temperature increase for the subsequent crystal growth step, thereby simplifying the manufacturing process.

[0016] In the method for manufacturing an optical device, the etching step is performed while increasing the temperature to a temperature higher than 600°C. At temperatures below 600°C, the hydrogen-containing gas may be hydrogen gas or a mixed gas of hydrogen and ammonia, in which the volumetric ratio of hydrogen to the entire mixed gas is 90% by volume to 97% by volume and the volumetric ratio of ammonia to the entire mixed gas is 10% by volume or less. At temperatures above 600°C, the hydrogen-containing gas may be a mixed gas of hydrogen and ammonia, in which the volumetric ratio of hydrogen to the entire mixed gas is 70% by volume to 92% by volume and the volumetric ratio of ammonia to the entire mixed gas is 7% by volume to 30% by volume. This allows for better control of the etching rate.

[0017] (Embodiment 1) 1 is a cross-sectional view showing the configuration of a light-emitting element in embodiment 1, taken perpendicular to the main surface of the substrate. The light-emitting element in this embodiment is capable of emitting blue, green, and red light. The light-emitting element in this embodiment is a flip-chip type that extracts light from the back side of the substrate, and is mounted face-down on a mounting substrate (not shown).

[0018] Furthermore, the light-emitting element in the embodiment may be a monolithic micro LED display element. That is, the blue, green, and red light-emitting portions in the embodiment may be one pixel, and the structure of that one pixel may be arranged in a matrix on the same substrate. This structure makes it possible to realize a display with a single chip. In this case, the size of the subpixel is, for example, 1 to 100 μm.

[0019] Furthermore, the light emitting element in the embodiment may have a structure in which one pixel is one chip.

[0020] 1. Structure of light-emitting element As shown in FIG. 1, the light-emitting element in this embodiment includes a substrate 10, an n-type layer 11, a first active layer 12, a first intermediate layer 13, a second active layer 14, a second intermediate layer 15, a third active layer 16, electron blocking layers 17, 19A to 19C, p-type layers 18, 20A to 20C, an n-side electrode 21, and p-side electrodes 22A to 22C.

[0021] The substrate 10 is a growth substrate for growing a group III nitride semiconductor, such as sapphire, Si, GaN, or ScAlMgO4 (SAM).

[0022] The n-type layer 11 is an n-type semiconductor provided on the substrate 10 via a low-temperature buffer layer or a high-temperature buffer layer (not shown). However, the buffer layer may be provided as needed, and if the substrate is GaN, the buffer layer may not be provided. The n-type layer 11 is, for example, n-GaN, n-AlGaN, or n-InGaN. The Si concentration is, for example, 1×10 18 ~100×10 18 cm -3 is.

[0023] The first active layer 12 is a light emitting layer of SQW or MQW structure provided on the n-type layer 11. The emitted light wavelength is blue, 430 to 480 nm. The first active layer 12 has a structure in which barrier layers made of AlGaN and well layers made of InGaN are alternately stacked in 1 to 9 pairs, more preferably 1 to 7 pairs, and even more preferably 1 to 5 pairs.

[0024] An underlayer may be provided between the n-type layer 11 and the first active layer 12, if necessary. The underlayer is a semiconductor layer with a superlattice structure provided on the n-type layer 11, and serves to alleviate lattice distortion of the semiconductor layer formed on the underlayer. The underlayer is formed by alternately laminating III nitride semiconductor thin films with different compositions (for example, two of GaN, InGaN, and AlGaN), and the number of pairs is, for example, 3 to 30. The underlayer may be undoped or may contain 1×10 Si. 17 ~100×10 17 cm -3Also, as long as the strain can be relaxed, the superlattice structure is not necessary.

[0025] An ESD layer may be provided between the n-type layer 11 and the underlayer. The ESD layer is a layer provided to improve electrostatic breakdown voltage. The ESD layer may be made of, for example, undoped or lightly Si-doped GaN, InGaN, or AlGaN.

[0026] The first intermediate layer 13 is a semiconductor layer provided on the first active layer 12. The first intermediate layer 13 is a layer provided to enable separate control of light emission from the first active layer 12 and light emission from the second active layer 14. The first intermediate layer 13 also serves to protect the first active layer 12 from etching damage when forming second grooves 31, which will be described later.

[0027] The first intermediate layer 13 has a structure in which an undoped intermediate layer 13A and an n-type intermediate layer 13B are laminated in this order from the first active layer 12 side. The undoped intermediate layer 12A and the n-type intermediate layer 12B may be made of the same material except for impurities. The reason for making the first intermediate layer 13 have such a two-layer structure will be explained later.

[0028] The material of the first intermediate layer 13 is a group III nitride semiconductor containing In, such as InGaN. The surfactant effect of In can suppress roughness on the surface of the first intermediate layer 13, improving surface flatness. It can also alleviate lattice distortion.

[0029] The In composition of the first intermediate layer 13 (the molar ratio of In to the total Group III metals of the Group III nitride semiconductor) may be set to have a band gap that does not absorb light emitted from the first active layer 12 and the second active layer 14. A preferred In composition is 10% or less, more preferably 5% or less, and even more preferably 2% or less. If the In composition is greater than 10%, it will cause the surface of the first intermediate layer 13 to become rough. The In content may be any value greater than 0%, and may be at a doping level (a level that does not form a mixed crystal). For example, if the In concentration is 1×10 14 cm -3 More than 1×10 22cm -3 The following is GaN.

[0030] The non-doped intermediate layer 13A is non-doped, and the n-type intermediate layer 13B is Si-doped. The Si concentration of the n-type intermediate layer 13B is 1×10 17 ~1000×10 17 cm -3 It is preferable to set it to 10×10 17 ~100×10 17 cm -3 , and more preferably 20×10 17 ~80×10 17 cm -3 The n-type intermediate layer 13B may be modulation doped with Si, or a part of the n-type intermediate layer 13B may have an undoped region.

[0031] The thickness of the first intermediate layer 13 is preferably 20 to 150 nm. If it is thicker than 150 nm, the surface of the first intermediate layer 13 may become rough. If it is thinner than 20 nm, it may be difficult to control the depth of the second grooves 31 (described later) so that they lie within the non-doped intermediate layer 13A when they are formed. The thickness is more preferably 30 to 100 nm, and even more preferably 50 to 80 nm.

[0032] The thickness of the non-doped intermediate layer 13A is preferably 10 nm or more in order to control the etching depth and avoid etching damage to the first active layer 12. The thickness of the n-type intermediate layer 13B is preferably 10 nm or more in order to independently control the light-emitting characteristics of each active layer.

[0033] The second active layer 14 is a layer provided on the first intermediate layer 13 and has a quantum well structure of SQW or MQW. The emission wavelength is green and is 510 to 570 nm. The quantum well structure is formed by alternately stacking 1 to 7 pairs of barrier layers made of GaN or AlGaN and well layers made of InGaN.

[0034] A strain relaxation layer may be provided between the first intermediate layer 13 and the second active layer 14. By providing the strain relaxation layer, the strain in the second active layer 14 stacked thereon can be relaxed, improving the crystal quality. The strain relaxation layer has an SQW structure or MQW structure in which a barrier layer and a well layer are stacked in order, and is a quantum well structure in which the thickness of the well layer is adjusted to be thin so as not to emit light. For example, light emission can be prevented by setting the thickness of the well layer to 1 nm or less. The barrier layer is made of AlGaN, and the well layer is made of InGaN. The wavelength corresponding to the band edge energy of the well layer of the strain relaxation layer needs to be shorter than the emission wavelength of the second active layer 14; for example, if the emission wavelength is 500 to 560 nm, it is 400 to 460 nm.

[0035] The second intermediate layer 15 is a semiconductor layer provided on the second active layer 14. The second intermediate layer 15 is provided for the same reason as the first intermediate layer 13, and is a layer provided to enable separate control of the light emission from the second active layer 14 and the light emission from the third active layer 16. The second intermediate layer 15 also serves to protect the second active layer 14 from etching damage when forming the first grooves 30 described below.

[0036] The second intermediate layer 15 has a structure in which an undoped intermediate layer 15A and an n-type intermediate layer 15B are laminated in this order from the second active layer 14 side. The undoped intermediate layer 15A and the n-type intermediate layer 15B have the same structures as the undoped intermediate layer 13A and the n-type intermediate layer 13B. In other words, the undoped intermediate layer 15A and the n-type intermediate layer 15B are made of the same materials as the undoped intermediate layer 13A and the n-type intermediate layer 13B except for the impurities, and the thickness ranges and the like are also the same as the undoped intermediate layer 13A and the n-type intermediate layer 13B. The undoped intermediate layer 15A is undoped, and the n-type intermediate layer 15B is Si-doped.

[0037] The third active layer 16 is a layer provided on the second intermediate layer 15, and has a quantum well structure of SQW or MQW. The emission wavelength is red, 590 to 750 nm. The quantum well structure is formed by alternately stacking 1 to 7 pairs of barrier layers made of InGaN and well layers made of InGaN. The number of pairs is more preferably 1 to 5, and even more preferably 1 to 3.

[0038] A strain relaxation layer may be provided between the second intermediate layer 15 and the third active layer 16. By providing the strain relaxation layer, it is possible to relieve the strain in the third active layer 16 laminated thereon, thereby improving the crystal quality. The strain relaxation layer has a structure in which, for example, a first strain relaxation layer and a second strain relaxation layer are laminated in this order from the second intermediate layer 15 side.

[0039] The first and second strain relaxation layers have the same structure as the strain relaxation layer between the first intermediate layer 13 and the second active layer 14. The wavelength corresponding to the band edge energy of the well layer of the first strain relaxation layer is, for example, 400 to 460 nm. The wavelength corresponding to the band edge energy of the well layer of the second strain relaxation layer is, for example, 510 to 570 nm.

[0040] The electron blocking layer 17 is a semiconductor layer provided on the third active layer 16. The electron blocking layer 17 is a layer that blocks electrons injected from the n-type layer 11 in order to confine them efficiently in the third active layer 16. The electron blocking layer 17 not only functions as an electron blocking layer but also as a protective layer that protects the active layer. The electron blocking layer 17 may be made of a material that has a wider band gap than the well layer of the third active layer 16, such as AlGaN, GaN, or InGaN. The thickness of the electron blocking layer 17 is preferably 2.0 to 50 nm, and more preferably 2 to 25 nm. The electron blocking layer 17 may be doped with an impurity, or may be doped with Mg. In this case, the Mg concentration should be 1×10 18 ~1000×10 18 cm -3 It is best to do so.

[0041] Between the third active layer 16 and the electron blocking layer 17, a strain relaxation layer made of InGaN having a narrower band gap than the electron blocking layer 17 may be provided.

[0042] The p-type layer 18 is a semiconductor layer provided on the electron blocking layer 17. The p-type layer 18 is preferably p-GaN or p-InGaN. The thickness of the p-type layer 18 is preferably 10 to 500 nm, more preferably 10 to 200 nm, and even more preferably 10 to 100 nm. The Mg concentration of the p-type layer 18 is 1×10 19 ~100×10 19 cm -3 It is best to do so.

[0043] A portion of the surface of the p-type layer 18 is etched to form grooves, and a first groove 30 extending from the p-type layer 18 to the second intermediate layer 15, a second groove 31 extending to the first intermediate layer 13, and a third groove 32 extending to the n-type layer 11 are provided.

[0044] The first grooves 30 have a depth that reaches the non-doped intermediate layer 15A of the second intermediate layer 15. By removing the n-type intermediate layer 15B of the second intermediate layer 15 below the p-side electrode 22B in this way, an n-type layer is prevented from being positioned above the second active layer 14, allowing the second active layer 14 to emit light.

[0045] The second grooves 31 are deep enough to reach the non-doped intermediate layer 13A of the first intermediate layer 13. This is also for the same reason, and by removing the n-type intermediate layer 13B of the first intermediate layer 13 below the p-side electrode 22C, an n-type layer is prevented from being positioned above the first active layer 12, allowing the first active layer 12 to emit light.

[0046] The electron blocking layers 19A to 19C are semiconductor layers respectively provided on the p-type layer 18, on the undoped intermediate layer 15A exposed at the bottom of the first groove 30, and on the undoped intermediate layer 13A exposed at the bottom of the second groove 31, and are layers that block electrons injected from the n-type layer 11 in order to efficiently confine them in the first active layer 12, the second active layer 14, and the third active layer 16.

[0047] Here, as described in the manufacturing method section below, electron blocking layers 19A-19C are formed after etching the bottom surfaces of first groove 30 and second groove 31 with a gas containing hydrogen. Therefore, no impurity layer containing impurities such as O or Si exists at the interface between undoped intermediate layer 15A and electron blocking layer 19A and at the interface between undoped intermediate layer 13A and electron blocking layer 19B. In addition, no damaged layer resulting from the formation of first groove 30 and second groove 31 exists.

[0048] Here, the absence of an impurity layer containing impurities such as O or Si means that the impurity concentration is sufficiently low, approximately at the normal background level. Generally, when grown by the MOCVD method, the impurity concentration is 1×10 16 ~100×10 16 cm -3 Therefore, the absence of the above impurity layer means that the impurity layer is less than 1×10 16 ~100×10 16 cm -3 This means that residual impurities are suppressed to a certain extent.

[0049] If an impurity layer such as O or Si exists at the interface between the undoped intermediate layer 15A and the electron blocking layer 19A or at the interface between the undoped intermediate layer 13A and the electron blocking layer 19B, the impurities will function as n-type dopants to form an n-type layer. This results in an n-type layer being located between the second active layer 14 and the p-type layer 20B, and between the first active layer 12 and the p-type layer 20C, significantly reducing the light-emitting efficiency. However, in the embodiment, as described above, the residual impurities are kept at a level of about 1×10, which is typical for a layer grown by MOCVD. 16 ~100×10 16 cm -3 Since impurities can be suppressed to a certain extent, a decrease in luminous efficiency can be suppressed.

[0050] The electron blocking layers 19A to 19C may be single layers of GaN or AlGaN, or may have a structure in which two or more of AlGaN, GaN, and InGaN are stacked, or a structure in which layers are stacked with only the composition ratio changed. They may also have a superlattice structure. The superlattice structure can block electrons more efficiently. Examples of the superlattice structure include a structure in which p-AlGaN and p-InGaN are stacked alternately, or a structure in which p-AlGaN and p-GaN are stacked alternately.

[0051] The thickness of the electron blocking layers 19A to 19C is preferably 2 to 50 nm, and more preferably 2 to 25 nm.

[0052] The electron blocking layers 19A to 19C are p-type doped with Mg. By making them p-type, holes can be efficiently injected into the active layer. Furthermore, a larger barrier against electrons can be formed, enhancing the electron blocking function. The electron blocking layers 19A to 19C may be non-doped, but for the reasons mentioned above, they are preferably p-type by doping with Mg. The Mg concentration of the electron blocking layers 19A to 19C is 1×10 19 ~100×10 19 cm -3 It is best to do so.

[0053] The p-type layers 20A to 20C are semiconductor layers provided on the electron blocking layers 19A to 19C, respectively, and are composed of a first layer and a second layer in that order from the electron blocking layer 19A to 19C side.

[0054] The first layer is preferably p-GaN or p-InGaN. The thickness of the first layer is preferably 10 to 500 nm, more preferably 10 to 200 nm, and further preferably 10 to 100 nm. The Mg concentration of the first layer is 1×10 19 ~100×10 19 cm -3 The second layer is preferably p-GaN or p-InGaN. The thickness of the second layer is preferably 2 to 50 nm, more preferably 4 to 20 nm, and further preferably 6 to 10 nm. The Mg concentration of the second layer is 1×10 20 ~100×10 20cm -3 It is best to do so.

[0055] In the embodiment, the electron blocking layers 19A to 19C are formed separately from each other, and the p-type layers 20A to 20C are formed separately from each other, but they may be formed as a continuous film. In this case, layers made of the same material as the electron blocking layers 19A to 19C are also formed on the side surfaces of the first groove 30 and the second groove 31, and layers made of the same material as the p-type layers 20A to 20C are also formed.

[0056] The n-side electrode 21 is an electrode provided on the n-type layer 11 exposed at the bottom surface of the third groove 32. When the substrate 10 is made of a conductive material, the n-side electrode 21 may be provided on the back surface of the substrate 10 without providing the third groove 32. The material of the n-side electrode 21 is, for example, Ti / Al or V / Al.

[0057] The p-side electrodes 22A-22C are electrodes provided on the p-type layers 20A-20C, respectively. The p-side electrodes 22A-22C are preferably made of a material that has high reflectivity for light of the emission wavelength and low contact resistance with the p-type layers 20A-20C. Examples include Ag, Ni / Au, Co / Au, ITO / Ni / Al, Rh, and Ru. Of the red light emitted from the third active layer 16, the light traveling toward the p-type layer 20A is reflected by the p-side electrode 22A and travels toward the substrate 10. Similarly, of the green light emitted from the second active layer 14, the light traveling toward the p-type layer 20B is reflected by the p-side electrode 22B and travels toward the substrate 10. Meanwhile, of the blue light emitted from the first active layer 12, the light traveling toward the p-type layer 20C is reflected by the p-side electrode 22C and travels toward the substrate 10.

[0058] In the light-emitting device according to the embodiment, the impurity concentration between the non-doped intermediate layer 15A and the electron blocking layer 19A and between the non-doped intermediate layer 13A and the electron blocking layer 19B is set to about the same as the general residual impurity concentration in a layer grown by MOCVD, for example, 1×10 16 ~100×10 16 cm -3In addition, the damage layer caused by dry etching can be removed. Therefore, the light emitting device according to the embodiment can suppress the decrease in luminous efficiency.

[0059] 2. Operation of light-emitting element Next, the operation of the light-emitting device in the embodiment will be described. In the light-emitting device in the embodiment, red light can be emitted from the third active layer 16 by applying a voltage between the p-side electrode 22A and the n-side electrode 21, green light can be emitted from the second active layer 14 by applying a voltage between the p-side electrode 22B and the n-side electrode 21, and blue light can be emitted from the first active layer 12 by applying a voltage between the p-side electrode 22C and the n-side electrode 21. These lights can be controlled individually, and two or more of blue, green, and red can also be emitted simultaneously.

[0060] In this way, in the light-emitting element of the embodiment, the light emission of blue, green, and red can be controlled by selecting the electrode to which the voltage is applied, and it can be used as one pixel in a micro LED display.

[0061] 3. Light-emitting element manufacturing process Next, a manufacturing process of the light-emitting device in this embodiment will be described with reference to Figures 2 to 7. Figure 7 is a flowchart showing the manufacturing process, and Figures 2 to 6 are cross-sectional views showing the configuration of the light-emitting device at each stage of the manufacturing process.

[0062] First, the substrate 10 is prepared, and hydrogen, nitrogen, and, if necessary, ammonia are added to perform a heat treatment on the substrate.

[0063] Next, a buffer layer is formed on the substrate 10, and then an n-type layer 11, a first active layer 12, a first intermediate layer 13, a second active layer 14, a second intermediate layer 15, a third active layer 16, an electron blocking layer 17, and a p-type layer 18 are formed in this order on the buffer layer (see FIG. 2, step S1 in FIG. 7). Each layer is formed using the MOCVD method. The preferred growth temperatures for each layer are as follows:

[0064] The growth temperature of the first active layer 12 is preferably 700 to 950°C. This can improve the crystal quality and increase the light emission efficiency. The first active layer 12 is composed of a well layer and a barrier layer, and the well layer and the barrier layer may be formed at the same temperature or at different temperatures within the above temperature range. If they are formed at different temperatures, it is preferable that the growth temperature of the well layer is lower than the growth temperature of the barrier layer.

[0065] The growth temperature of the first intermediate layer 13 is preferably 700 to 1000°C. This is to suppress thermal damage to the first active layer 12. Furthermore, if the temperature is lower than 700°C, pits and point defects due to threading dislocations are likely to occur. The temperature is more preferably 800 to 950°C, and even more preferably 850 to 950°C.

[0066] The growth temperature of the second active layer 14 is preferably 650 to 950°C. This can improve the crystal quality and increase the light emission efficiency. The second active layer 14 is composed of a well layer and a barrier layer, and the well layer and the barrier layer may be formed at the same temperature or at different temperatures within the above temperature range. If they are formed at different temperatures, it is preferable that the growth temperature of the well layer is lower than that of the barrier layer. Furthermore, it is preferable that the growth temperature of the second active layer 14 is lower than that of the first active layer 12.

[0067] The growth temperature of the second intermediate layer 15 is preferably in the same range as the growth temperature of the first intermediate layer 13. However, the growth temperature of the second intermediate layer 15 is preferably lower than the growth temperature of the first intermediate layer 13. This is because the green-emitting second active layer 14 is more susceptible to thermal damage than the blue-emitting first active layer 12, and is more susceptible to strain at the interface.

[0068] The growth temperature of the third active layer 16 is preferably 500 to 950°C. This can improve the crystal quality and increase the light emission efficiency. The third active layer 16 is composed of a well layer and a barrier layer, and the well layer and the barrier layer may be formed at the same temperature or at different temperatures within the above temperature range. If they are formed at different temperatures, it is preferable that the growth temperature of the well layer is lower than that of the barrier layer. Furthermore, it is preferable that the growth temperature of the third active layer 16 is lower than that of the second active layer 14.

[0069] The growth temperature of the electron blocking layer 17 and the p-type layer 18 is preferably 500 to 950°C to prevent thermal damage to the first active layer 12, the second active layer 14, and the third active layer 16. To improve the crystallinity of the electron blocking layer 17 and the p-type layer 18, a higher growth temperature is preferred, more preferably 600 to 900°C, and even more preferably 700 to 900°C.

[0070] Next, a portion of the surface of the p-type layer 18 is dry-etched until it reaches the non-doped intermediate layer 15A of the second intermediate layer 15 to form a first groove 30, and then dry-etched until it reaches the non-doped intermediate layer 13A of the first intermediate layer 13 to form a second groove 31 (see Figure 3, step S2 of Figure 7).

[0071] In the process of forming the first grooves 30 and the second grooves 31, the wafer is temporarily removed from the growth furnace and subjected to an etching process. As a result, the wafer is exposed to the atmosphere, and the wafer surface is contaminated with impurities such as O and Si, forming an impurity layer containing these impurities. Furthermore, because the first grooves 30 and the second grooves 31 are formed by dry etching, damaged layers are formed on the bottom and side surfaces of the first grooves 30 and the second grooves 31.

[0072] Next, the wafer is loaded back into the growth furnace, and the furnace is evacuated. Hydrogen gas is then introduced into the furnace. The pressure is set to, for example, atmospheric pressure (100 kPa). A reduced pressure may also be used.

[0073] Next, the temperature is raised from room temperature to the growth temperature of the electron blocking layers 19A to 19C. Because a hydrogen gas atmosphere is used, the group III nitride semiconductor on the wafer surface is etched during the temperature rise (see FIG. 4, step S3 in FIG. 7). That is, the surface of the p-type layer 18 and the bottom and side surfaces of the first grooves 30 and second grooves 31 are etched. As a result, the impurity layers on the bottom and side surfaces of the first grooves 30 and second grooves 31 can be removed. Furthermore, layers damaged by etching can also be removed. Because the well layers of the first active layer 12, second active layer 14, and third active layer 16 are made of InGaN, etching must be performed at a low temperature to suppress damage, but the above etching can be performed at a low temperature.

[0074] The etching rate of a Group III nitride semiconductor using hydrogen gas is strongly dependent on temperature. Therefore, the etching rate may be controlled by appropriately mixing ammonia. Using a mixed gas of hydrogen and ammonia can suppress the etching rate and improve the controllability of the etching depth. Furthermore, as the etching rate increases, the in-plane variation in the etching depth also increases, resulting in the formation of random unevenness on the surface. However, by suppressing the etching rate, such in-plane variation can also be suppressed.

[0075] In addition to ammonia, a gas that does not react with Group III nitride semiconductors may be mixed. For example, nitrogen may be included. Furthermore, the volume ratio of hydrogen to the entire mixed gas may be greater than the volume ratio of ammonia to the entire mixed gas. This allows for efficient etching of Group III nitride semiconductors.

[0076] At temperatures below 600°C, the etching rate is sufficiently slow that hydrogen gas alone may be used. Alternatively, a small amount of ammonia may be mixed in. For example, the volume ratio of hydrogen to the entire mixed gas may be 90 to 97% by volume, and the mixture ratio of ammonia to hydrogen gas may be 10% by volume or less.

[0077] At temperatures above 600°C, the etching rate increases, so a mixed gas of hydrogen and ammonia is preferable. This reduces the etching rate and allows for precise control of the etching depth. It also reduces variations in the etching depth within the surface. The addition of ammonia also has the effect of suppressing nitrogen loss from the Group III nitride semiconductor. For example, it is preferable that the volumetric ratio of hydrogen to the entire mixed gas is 70 to 92% by volume, and the mixing ratio of ammonia to hydrogen gas is 7 to 30% by volume. The ratio of ammonia may be increased continuously or stepwise as the temperature rises.

[0078] When a mixed gas of hydrogen and ammonia is used for growth at 100 kPa, the flow rate of ammonia is preferably 0.3 to 8 m / min, which can sufficiently suppress the etching rate, and more preferably 0.8 to 4 m / min.

[0079] In the embodiment, etching with hydrogen gas is performed while the temperature is increased, but etching may be performed while maintaining a predetermined temperature. For example, after the temperature is increased to the growth temperature of the electron blocking layers 19A to 19C, the temperature may be maintained and then the supply of a mixed gas of hydrogen and ammonia may be started to perform etching.

[0080] After etching, the flow rate of ammonia is adjusted stepwise to the flow rate of ammonia used in the electron blocking layers 19A to 19C.

[0081] Once the growth temperature for the electron blocking layers 19A to 19C is reached, the growth temperature is maintained and the electron blocking layers 19A to 19C are formed by MOCVD on the p-type layer 18, on the non-doped intermediate layer 15A of the second intermediate layer 15 exposed by the first groove 30, and on the non-doped intermediate layer 13A of the first intermediate layer 13 exposed by the second groove 31.

[0082] The growth temperature of the electron blocking layers 19A to 19C is preferably 950°C or lower. This is to prevent thermal damage to the InGaN contained in the first active layer 12, second active layer 14, and third active layer 16. A temperature of 900°C or lower is more preferable. The growth temperature of the electron blocking layers 19A to 19C is preferably 750°C or higher, and more preferably 800°C or higher.

[0083] Here, electron blocking layers 19A to 19C are formed on a surface that has been etched in a previous process. Therefore, impurity layers due to exposure to the atmosphere are removed from the interface between undoped intermediate layer 15A and electron blocking layer 19B and the interface between undoped intermediate layer 13A and electron blocking layer 19C. Damage layers due to etching are also removed.

[0084] Next, p-type layers 20A-20C are formed on the electron blocking layers 19A-19C by MOCVD (see FIG. 5, step S4 in FIG. 7). Note that although the p-type layers 20A-20C are not p-type at this stage, they are referred to as such because they will become p-type later. The growth temperature for the p-type layers 20A-20C is preferably 650-1000°C, more preferably 700-950°C, and even more preferably 750-900°C.

[0085] Next, a partial surface area of ​​the p-type layer 20C is dry-etched until it reaches the n-type layer 11, thereby forming a third groove 32 (see FIG. 6, step S5 in FIG. 7). Then, an n-side electrode 21 is formed on the n-type layer 11 exposed at the bottom of the third groove 32, and p-side electrodes 22A to 22C are formed on the p-type layers 18, 20A, and 20B. In this manner, the light-emitting element of this embodiment is manufactured.

[0086] As described above, in the method for manufacturing a light-emitting element according to the embodiment, the impurity layer containing impurities such as O and Si can be removed using a gas containing hydrogen. Damaged layers on the bottom and side surfaces of the first groove 30 and the second groove 31 can also be removed. Therefore, the impurity concentration at the interface between the non-doped intermediate layer 15A and the electron blocking layer 19B and the interface between the non-doped intermediate layer 13A and the electron blocking layer 19C can be reduced to the same level as the general residual impurities grown by MOCVD, for example, 1×1016 ~100×10 16 cm -3 Furthermore, the damage layer caused by dry etching can be removed, and as a result, the decrease in luminous efficiency can be suppressed.

[0087] 4. Experimental Results Next, experimental results according to the embodiment will be described.

[0088] The light-emitting device according to the present example was fabricated as follows. First, an n-type layer, a blue light-emitting layer, and a non-doped intermediate layer were formed in this order on a sapphire substrate by MOCVD. Then, the wafer was removed from the MOCVD apparatus and exposed to the atmosphere.

[0089] The wafer was then returned to the MOCVD apparatus, and the surface of the non-doped intermediate layer was etched for a predetermined time using a hydrogen-containing gas at a temperature of 600°C or higher. The hydrogen-containing gas was either hydrogen alone or a mixture of hydrogen and ammonia. When using the hydrogen and ammonia mixture, the ammonia flow rate was set to 10 slm, and the hydrogen flow rate was varied. When using hydrogen gas alone, the flow rate was set to two levels: 35 slm and 140 slm.

[0090] Next, an electron blocking layer and a p-type contact layer were formed in that order on the non-doped intermediate layer by MOCVD. Next, a predetermined region of the p-type contact layer was dry-etched until the n-type layer was exposed, forming a recess. A p-side electrode was formed on the p-type contact layer, and an n-side electrode was formed on the bottom of the recess. This completed the fabrication of the light-emitting device of this example.

[0091] Furthermore, as a comparative example, a light-emitting element was fabricated in the same manner as in Example 1, except that instead of etching the surface of the non-doped intermediate layer with a gas containing hydrogen, a mixed gas of nitrogen and ammonia was supplied. The flow rate of nitrogen was 140 slm, and the flow rate of ammonia was 10 slm.

[0092] The light output of the light-emitting devices of the example and comparative example was measured. Figure 8 is a graph showing the relationship between the hydrogen gas flow rate ratio (the ratio of the hydrogen gas flow rate to the sum of the hydrogen gas flow rate and the ammonia flow rate) and the light output at 100 mA. The light output is a relative value, with the light output of the comparative example light-emitting device at 100 mA set to 1.

[0093] As shown in Figure 8, when the hydrogen gas flow rate ratio was 70 to 92%, the light output was improved compared to the light-emitting device of the comparative example. This is thought to be because the surface of the non-doped intermediate layer, which had been exposed to the atmosphere and contaminated with impurities, was sufficiently reduced by etching with hydrogen. Furthermore, when hydrogen gas alone was used, the light output was 0 at both hydrogen gas flow rates of 35 slm and 140 slm. This is thought to be because the etching rate was so fast that it reached the blue light-emitting layer.

[0094] (Other variations) In the embodiment, the wafer surface is exposed to the atmosphere when the first grooves 30 and the second grooves 31 are formed by dry etching, but the exposure to the atmosphere is not limited to this. The method can be applied to any optical device manufacturing method as long as it includes a regrowth step of forming a second semiconductor layer on the first semiconductor layer after exposing the first semiconductor layer to the atmosphere.

[0095] Although the light-emitting element in the embodiment emits light of three colors, red, green, and blue, the present invention is not limited to this, and any light emitting element may emit light of two or more colors with different emission wavelengths. For example, the light emitting element may emit light of four colors, red, yellow, green, and blue.

[0096] Although the first embodiment is directed to a light emitting device, the present invention can be applied to optical devices using semiconductors other than light emitting devices, such as light receiving elements and solar cells.

[0097] Furthermore, the light-emitting element and light-receiving element of the present invention can be used as a light source for generating an optical signal and a light-receiving element for receiving an optical signal in a wavelength division multiplexing optical communication device, thereby simplifying the optical communication device and reducing its cost. For example, a transmission signal can be generated and transmitted by wavelength-multiplexing red light, green light, and blue light emitted by the light-emitting element of the embodiment. Furthermore, when a received signal is received by the light-receiving element of the present invention, the red light, green light, and blue light can be separately received. [Explanation of symbols]

[0098] 10: Circuit board 11:n-type layer 12: 1st active layer 13: First middle class 14:Second active layer 15: Second middle class 16: 3rd active layer 17, 19A, 19B: Electron blocking layer 18, 20A, 20B: p-type layer 21:n side electrode 22A~22C:p side electrode

Claims

1. an etching step of exposing a first semiconductor layer having an active layer made of an In-containing Group III nitride semiconductor to the atmosphere, and then etching a surface of the first semiconductor layer using a gas containing hydrogen; a regrowth step of forming a second semiconductor layer made of a Group III nitride semiconductor on the first semiconductor layer; A method for manufacturing an optical device having the above structure.

2. The method for manufacturing an optical device according to claim 1 , wherein the second semiconductor layer includes a p-type layer.

3. an n-type layer forming step of forming an n-type layer made of an n-type Group III nitride semiconductor on the substrate; a first active layer forming step of forming a first active layer on the n-type layer, the first active layer including a well layer made of a group III nitride semiconductor containing In and having a predetermined emission wavelength; an intermediate layer forming step of forming an intermediate layer made of a Group III nitride semiconductor containing In on the first active layer; a second active layer forming step of forming a second active layer on the intermediate layer, the second active layer including a well layer made of a Group III nitride semiconductor containing In and having an emission wavelength different from that of the first active layer; a groove forming step of forming a groove having a depth reaching the intermediate layer from the second active layer side; an etching step of etching the bottom surface of the groove using a gas containing hydrogen after the bottom surface of the groove is exposed to the atmosphere in the groove forming step; a p-type layer forming step of forming a first p-type layer and a second p-type layer made of a p-type Group III nitride semiconductor on the second active layer and on a bottom surface of the groove, respectively; A method for manufacturing an optical device having the above structure.

4. 4. The method for manufacturing an optical device according to claim 1, wherein the hydrogen-containing gas is a mixed gas of hydrogen and ammonia.

5. The method for manufacturing an optical device according to claim 4 , wherein a volume ratio of hydrogen to the entire mixed gas is greater than a volume ratio of ammonia to the entire mixed gas.

6. The method for manufacturing an optical device according to claim 1 , wherein the etching step is performed while increasing the temperature.

7. The etching step is carried out while increasing the temperature to a temperature higher than 600°C, At temperatures below 600°C, the hydrogen-containing gas is hydrogen gas or a mixed gas of hydrogen and ammonia, the volume ratio of hydrogen to the entire mixed gas being 90% by volume or more and 97% by volume or less, and the volume ratio of ammonia to the entire mixed gas being 10% by volume or less, 7. The method for manufacturing an optical device according to claim 6, wherein at 600°C or higher, a mixed gas of hydrogen and ammonia is used as the hydrogen-containing gas, wherein the volume ratio of hydrogen to the entire mixed gas is 70% by volume or more and 92% by volume or less, and the volume ratio of ammonia to the entire mixed gas is 7% by volume or more and 30% by volume or less.

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