Semiconductor testing device and semiconductor device manufacturing method

Abstract

To provide a semiconductor testing device capable of setting rimmed semiconductor wafers of a plurality of sizes, and a method for manufacturing a semiconductor device using the semiconductor testing device.SOLUTION: A semiconductor testing device includes a disk-shaped chuck top on whose upper surface a semiconductor wafer having a rim is mounted, and a contact probe. The upper surface of the chuck top is formed with a circular rim recess groove formed concentrically with the outer edge of the chuck top, a first suction hole formed inside the rim recess groove and configured to suck a semiconductor wafer, and a second suction hole formed outside the rim recess groove and configured to suck a semiconductor wafer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor testing device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a suction plate for semiconductor wafer processing that can suction a semiconductor wafer with a rim structure. This suction plate has a convex surface that comes into close contact with the flat surface of the bottom of the wafer recess on the inner periphery of the back surface of the wafer, and an outer circumferential recess that houses an annular reinforcing rib on the outer periphery of the back surface of the wafer. Multiple vacuum holes for pressure reduction are symmetrically arranged on a circle 2 mm to 5 mm from the outer periphery of the convex surface. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-216440 Summary of the Invention [Problem to be solved by the invention]

[0004] Generally, chuck tops for mounting semiconductor wafers are manufactured specifically for a single semiconductor wafer size. In other words, it is often not anticipated that semiconductor wafers of multiple sizes can be mounted on a single chuck top. For example, it is possible to mount an 8-inch semiconductor wafer on a chuck top designed for 12-inch semiconductor wafers. However, if the wafer has a rim on its outer periphery that protrudes beyond the inner periphery, even if a wafer smaller than the intended size is mounted on the chuck top, the influence of the rim will prevent the semiconductor wafer from being properly attracted to the chuck top.

[0005] Patent Document 1 discloses a chuck top compatible with semiconductor wafers having rims. However, even in Patent Document 1, it is assumed that a semiconductor wafer of a specific size will be set on the chuck top. In other words, it is impossible to set a semiconductor wafer smaller than the semiconductor wafer that the chuck top is designed for. Therefore, in order to set a semiconductor wafer of a different size, it is necessary to either replace the entire chuck top or install new dedicated equipment. This poses the problem of significant effort and cost.

[0006] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor testing device that can set rimmed semiconductor wafers of multiple sizes, and a method for manufacturing a semiconductor device using the semiconductor testing device. [Means for solving the problem]

[0007] The semiconductor testing apparatus according to the first disclosure includes a disk-shaped chuck top on whose upper surface a semiconductor wafer having a rim is mounted, and a contact probe. The upper surface of the chuck top is formed with a circular rim recess groove formed concentrically with the outer edge of the chuck top, a first suction hole formed inward from the rim recess groove and configured to suction the semiconductor wafer, and a second suction hole formed outward from the rim recess groove and configured to suction the semiconductor wafer.

[0008] The semiconductor testing apparatus according to the second disclosure comprises a chuck top having a main surface and a convex portion protruding from the main surface, a replaceable spacer ring that is annular and arranged on the main surface so as to surround the convex portion, and a contact probe, and the semiconductor wafer is mounted on the upper surface of the convex portion and the upper surface of the spacer ring so that the side surface that forms the outer edge of the spacer ring faces the rim of the semiconductor wafer having a rim.

[0009] A method for manufacturing a semiconductor device according to a first disclosure includes: mounting a rimmed semiconductor wafer on the top surface of a disk-shaped chuck top having an annular rim recessed groove formed concentrically with the outer edge of the chuck top, a first suction hole formed inside the rim recessed groove, and a second suction hole formed outside the rim recessed groove; and measuring electrical characteristics of the semiconductor wafer with the semiconductor wafer mounted on the top surface of the chuck top using a contact probe. With the semiconductor wafer mounted on the top surface of the chuck top, the rim is positioned in the rim recessed groove or opposed to a side surface forming the outer edge of the chuck top, depending on the size of the semiconductor wafer. When the rim is positioned in the rim recessed groove, the first suction hole attracts the semiconductor wafer, and when the rim is positioned opposed to the side surface of the chuck top, the second suction hole attracts the semiconductor wafer.

[0010] A method for manufacturing a semiconductor device according to the second disclosure includes: placing an annular spacer ring on a main surface of a chuck top having a main surface and a convex portion protruding from the main surface so as to surround the convex portion; mounting a semiconductor wafer on an upper surface of the convex portion and an upper surface of the spacer ring so that a side surface forming an outer edge of the spacer ring faces a rim of the semiconductor wafer; measuring electrical characteristics of the semiconductor wafer with a contact probe while the semiconductor wafer is mounted on the upper surface of the convex portion and the upper surface of the spacer ring; and replacing the spacer ring to match the size of the semiconductor wafer. [Effects of the Invention]

[0011] In the semiconductor testing apparatus and semiconductor device manufacturing method according to the first disclosure, the rim is positioned in the rim recess or facing the side surface that forms the outer edge of the chuck top depending on the size of the semiconductor wafer, so that rimmed semiconductor wafers of various sizes can be set in the semiconductor testing apparatus. In the semiconductor testing device and semiconductor device manufacturing method according to the second disclosure, the spacer ring can be replaced to match the size of the semiconductor wafer, so that rimmed semiconductor wafers of a variety of sizes can be set in the semiconductor testing device. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a plan view of a semiconductor testing device according to a first embodiment. [Figure 2] 1 is a cross-sectional view of a semiconductor testing device according to a first embodiment. [Figure 3] 1 is a cross-sectional view of a semiconductor testing device according to a first embodiment. [Figure 4] 1 is a cross-sectional view of an edge of a semiconductor wafer. [Figure 5] FIG. 10 is a cross-sectional view of a rim recess groove according to a first modified example of the first embodiment. [Figure 6] FIG. 10 is a diagram showing a state in which a rimmed semiconductor wafer is set on a chuck top according to a first comparative example. [Figure 7] FIG. 10 is a diagram showing a state in which a rimmed semiconductor wafer is set on a chuck top according to a second comparative example. [Figure 8] 5A and 5B are diagrams illustrating the function of a recess according to the first embodiment. [Figure 9] FIG. 10 is a cross-sectional view of a semiconductor testing device according to a second modification of the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view of a semiconductor testing device according to a third modification of the first embodiment. [Figure 11] FIG. 10 is a plan view of a semiconductor testing device according to a third modification of the first embodiment. [Figure 12] 10A and 10B are diagrams illustrating a lift-up pin according to a third modified example of the first embodiment. [Figure 13] FIG. 10 is a cross-sectional view of a semiconductor testing device according to a second embodiment. [Figure 14] FIG. 10 is a plan view of a semiconductor testing device according to a second embodiment. [Figure 15] FIG. 10 is a cross-sectional view of a semiconductor testing device according to a second embodiment. [Figure 16] FIG. 10 is an enlarged cross-sectional view of a semiconductor testing device according to a second embodiment. [Figure 17] FIG. 16 is a further enlarged view of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0013] A semiconductor testing device and a method for manufacturing a semiconductor device according to each embodiment will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and repeated description may be omitted.

[0014] Embodiment 1 FIG. 1 is a plan view of a semiconductor testing apparatus 100 according to the first embodiment. FIGS. 2 and 3 are cross-sectional views of the semiconductor testing apparatus according to the first embodiment. FIGS. 2 and 3 show a state in which a semiconductor wafer 1 is set on a chuck top 3. FIG. 2 is a cross-sectional view taken along the line A-A' in FIG. 1, showing a state in which, for example, an 8-inch semiconductor wafer 1b has been set. FIG. 3 is a cross-sectional view taken along the line A-A' in FIG. 1, showing a state in which, for example, a 12-inch semiconductor wafer 1a, which is larger than the semiconductor wafer 1b, has been set. Hereinafter, the semiconductor wafers 1a and 1b may be collectively referred to as the semiconductor wafer 1.

[0015] Semiconductor wafers 1a and 1b are rimmed semiconductor wafers. FIG. 4 is a cross-sectional view of the edge of semiconductor wafer 1. A semiconductor wafer may be ground thin to improve the characteristics of the semiconductor device. At this time, the outer periphery of the semiconductor wafer may be left thick and not ground to maintain the strength of the entire semiconductor wafer. A semiconductor wafer 1 having a rim 12 on its outer periphery that protrudes more than its inner periphery is called a rimmed semiconductor wafer. A rimmed semiconductor wafer is also called a rim-structured semiconductor wafer. The semiconductor testing device 100 of this embodiment is intended for a semiconductor wafer 1 having a rim 12 on its outer periphery.

[0016] The semiconductor testing device 100 includes a disk-shaped chuck top 3 on which a semiconductor wafer 1 is mounted, and a contact probe 30. Note that the contact probe 30, suction mechanism 40, and pressure gauge 42 are omitted from Figures 1 and 3.

[0017] In a method for inspecting or manufacturing a semiconductor device using semiconductor testing apparatus 100, a semiconductor wafer 1 is mounted on the upper surface of chuck top 3 and fixed by suction to chuck top 3. Next, with semiconductor wafer 1 mounted on the upper surface of chuck top 3, electrical characteristics of semiconductor wafer 1 are measured using contact probes 30. Specifically, a plurality of contact probes 30 are brought into contact with surface electrodes of a semiconductor chip, which is a semiconductor device formed on the semiconductor wafer, or a TEG (Test Element Group), which is a semiconductor chip for characteristic measurement, to acquire the electrical characteristics. A measuring device (not shown) having an electrical characteristic measurement function is connected to contact probes 30.

[0018] The chuck top 3 is a plate-like member made of a conductive material. An annular rim recess 4 is formed on the upper surface of the chuck top 3, concentrically with the outer edge of the chuck top 3. Suction holes 5b configured to hold the semiconductor wafer 1 by suction are formed on the chuck top 3, more inward than the rim recess 4. Suction holes 5a configured to hold the semiconductor wafer 1 by suction are formed on the chuck top 3, more outward than the rim recess 4.

[0019] Depending on the size of the semiconductor wafer 1, the rim 12 of the semiconductor wafer 1 is disposed in the rim recess 4 as shown in Fig. 2, or disposed so as to face the side surface forming the outer edge of the chuck top 3 as shown in Fig. 3. The rim recess 4 has a depth sufficient to accommodate the rim 12. The depth of the rim recess 4 is preferably set to, for example, 0.5 mm to 5.0 mm.

[0020] Furthermore, the width of the rim recess groove 4 is preferably made larger than the width of the rim 12, taking into consideration positional deviation errors during wafer transport. However, if the width of the rim recess groove 4 is too large, when a large-sized semiconductor wafer 1a is set, the area of ​​the backside of the semiconductor wafer 1a that is not held by the chuck top 3 increases. For this reason, the rim recess groove 4 must have an appropriate width. Specifically, the width of the rim recess groove 4 is preferably set to 3 to 10 mm.

[0021] FIG. 5 is a cross-sectional view of a rim recess groove 204 according to a first modified example of the first embodiment. The rim recess groove 204 is formed in a chuck top 203 according to the first modified example. The width of the rim recess groove 204 is wider on the top side than on the bottom side. In other words, the rim recess groove 204 has a tapered shape. This enables the rim 12 to be smoothly recessed into the rim recess groove 204 and prevents damage to the semiconductor wafer 1 during recessing. Note that while the width of the rim recess groove 204 changes only on the top side in FIG. 5, the width of the entire rim recess groove 204 may increase toward the top surface.

[0022] Next, the suction holes 5a and 5b will be described. The suction holes 5a and 5b penetrate the chuck top 3 from the top surface to the bottom surface and are connected to the suction mechanism 40 on the bottom surface side of the chuck top 3. This allows the semiconductor wafer 1 to be sucked and held on the top surface of the chuck top 3. It is preferable to provide at least four suction holes 5a and at least four suction holes 5b.

[0023] As shown in Fig. 2, when the rim 12 of a small-sized semiconductor wafer 1b is placed in the rim recess groove 4, the suction holes 5b adsorb the semiconductor wafer 1b. As shown in Fig. 3, when the rim 12 of a large-sized semiconductor wafer 1a is placed so as to face the side surface of the chuck top 3, the suction holes 5a and 5b adsorb the semiconductor wafer 1a.

[0024] Next, the effects of this embodiment will be described. Fig. 6 is a diagram showing a state in which a rimmed semiconductor wafer is set on a chuck top 803a according to a first comparative example. The chuck top 803a does not have a rim recess groove 4. Therefore, the chuck top 803a cannot properly adsorb the semiconductor wafer 1 due to the influence of the rim 12. In this state, there is a risk that a portion 13 where loads are concentrated may occur around the rim 12, which may cause, for example, deflection near the rim 12 and damage the semiconductor wafer 1.

[0025] 7 is a diagram showing a state in which a rimmed semiconductor wafer is set on a chuck top 803b according to a second comparative example. The chuck top 803b is designed to accommodate a rimmed semiconductor wafer. However, it is not possible to set a semiconductor wafer smaller than the assumed semiconductor wafer 1.

[0026] In contrast, in this embodiment, the rim 12 is disposed in the rim recess 4 or disposed opposite the side surface that forms the outer edge of the chuck top 3, depending on the size of the semiconductor wafer 1. Therefore, rimmed semiconductor wafers of a variety of sizes can be set in the semiconductor testing apparatus 100. This eliminates the need to replace the entire chuck top in order to set a semiconductor wafer 1 of a different size, thereby reducing the effort and cost.

[0027] Next, the function of the recesses 6a and 6b will be described. On the upper surface of the chuck top 3, on the inside of the rim recess groove 4, the recess 6b is formed, which is connected to a pressure system independent of the suction holes 5a and 5b. A pressure gauge 42 configured to detect the pressure inside the recess 6b is connected to the recess 6b. Furthermore, on the upper surface of the chuck top 3, on the outside of the rim recess groove 4, the recess 6a is formed, which is connected to a pressure system independent of the suction holes 5a and 5b. A pressure gauge 42 configured to detect the pressure inside the recess 6a is connected to the recess 6a.

[0028] 8 is a diagram illustrating the function of the recesses 6a and 6b according to the first embodiment. Fig. 8 shows a state in which the wafer transfer position onto the chuck top 3 is shifted, causing the rim 12 to ride up on the chuck top without entering the rim recess groove 4. If the wafer is then sucked up in this state, the center of the wafer will come into contact with the chuck top 3 due to the wafer's deflection and be sucked up, but the outer periphery of the wafer will not be sucked up because it is supported by the rim 12. As a result, the rim 12 rides up on the chuck top 3, creating a portion 13 where the load is concentrated near the rim, potentially damaging the wafer.

[0029] As a countermeasure, recesses 6a and 6b are provided for the purpose of detecting when the rim 12 rides over the chuck top 3. The recesses 6a and 6b are suction holes for detecting misalignment. The recesses 6a and 6b may be through-holes or grooves. Misalignment of the small semiconductor wafer 1b is detected from the pressure in the recess 6b, and misalignment of the large semiconductor wafer 1a is detected from the pressure in the recess 6a.

[0030] The pressure gauge 42 is configured to monitor the suction pressure in the recesses 6a and 6b. If the entire wafer is suctioned normally, the degree of vacuum in the recesses 6a and 6b will be high. On the other hand, if the rim 12 rides up on the chuck top 3, leakage will occur from the gap created by the ride-up, and the degree of vacuum in the recesses 6a and 6b will not be high enough. This difference in vacuum level will enable detection of the semiconductor wafer 1 riding up. Specifically, normal suction pressure data measured in advance using the pressure gauge 42 is compared with current suction pressure data measured using the pressure gauge 42, and the difference between these values ​​will determine whether the pressure is normal or abnormal. This makes it possible to detect misalignment of the semiconductor wafer 1, i.e., riding up.

[0031] If the recesses 6a and 6b are positioned too far from the edge of the rim recess groove 4 or the chuck top 3, it may be impossible to detect riding-on due to the influence of deflection of the semiconductor wafer 1. For this reason, it is preferable to locate the recesses 6a and 6b as close as possible to the edge of the rim recess groove 4 or the chuck top 3. Specifically, it is preferable that the recesses 6a and 6b be located within a range of 10 mm from the edge of the rim recess groove 4 or the chuck top 3. The recess 6b may be located between the suction hole 5b and the rim recess groove 4. The recess 6a may be located outside the suction hole 5a.

[0032] Furthermore, in order to increase the detection sensitivity of the run-up, the recesses 6a and 6b must be in a vacuum system independent of the vacuum system of the suction holes 5a and 5b. The shape of the recesses 6a and 6b is not limited. For example, the recesses 6a and 6b may be hole-shaped as shown in FIG. 1, or may be annular grooves formed along the rim recess groove 4.

[0033] FIG. 9 is a cross-sectional view of a semiconductor testing apparatus 300 according to a second modification of the first embodiment. The semiconductor testing apparatus 300 includes a chuck top 303. In the second modification, a sensor 320 is provided in the recesses 6a and 6b. The sensor 320 is a proximity sensor or an optical sensor. The sensor 320, such as a proximity sensor or an optical sensor, can also be used to detect misalignment or overhanging of the semiconductor wafer 1. The most effective installation position for the sensor 320 is the same as the recesses 6a and 6b, i.e., inside the chuck top 3. In this case, misalignment of the semiconductor wafer 1 can be detected by comparing the measurement value obtained by the sensor 320 with the normal value obtained when the semiconductor wafer 1 is placed in the normal position.

[0034] It is also possible to perform both the detection of positional deviation by the pressure gauge 42 and the detection of positional deviation by the sensor 320, or to detect positional deviation by only one of the means.

[0035] Fig. 10 is a cross-sectional view of a semiconductor testing device 400 according to a third modification of embodiment 1. Fig. 11 is a plan view of the semiconductor testing device 400 according to the third modification of embodiment 1. The semiconductor testing device 400 includes a chuck top 403 and a spacer 407 that fills the rim recess groove 4.

[0036] When a large-sized semiconductor wafer 1a is set on the chuck top 3, the influence of the rim recessed groove 4 provided in the chuck top 3 is a concern. For example, a cavity may be formed between the rim recessed groove 4 and the back surface of the semiconductor wafer 1a, causing the semiconductor wafer 1a to be partially unsupported. This may cause warping of the semiconductor wafer 1a or lead to poor contact when pressure is applied to a portion of the wafer with the contact probe 30. Furthermore, if the semiconductor device formed on the semiconductor wafer 1a has a back surface electrode, electrical continuity between the back surface electrode and the chuck top 3 may not be properly established, potentially preventing normal processing during testing.

[0037] To address this issue, a ring-shaped spacer 407 may be provided that has a shape corresponding to the rim recess groove 4. The spacer 407 has, for example, the same height as the rim recess groove 4. This allows the spacer 407 to support the backside of the semiconductor wafer 1a when the large semiconductor wafer 1a is set on the chuck top 403.

[0038] Preferably, at least the surface of the spacer 407 is conductive. The spacer 407 is preferably formed of a conductive material similar to the chuck top 403, or is surface-treated with a conductive material. This reduces the risk of poor contact between the back electrode and the chuck top 403, even when testing a semiconductor device with a back electrode.

[0039] Furthermore, suction holes 414 configured to suck and hold the spacers 407 are formed in the bottom of the rim recess groove 4 of the chuck top 403. This allows the spacers 407 to be sucked and fixed, preventing them from falling off. Note that the other suction holes 5a, 5b and recesses 6a, 6b are omitted in Figures 10 and 11.

[0040] 12 is a diagram illustrating a lift-up pin 408 according to a third modification of the first embodiment. The semiconductor testing device 400 may further include a lift-up pin 408. The lift-up pin 408 is configured to protrude from the bottom of the rim recess groove 4 into the rim recess groove 4 and lift up the spacer 407. This facilitates removal of the spacer 407. In other words, for example, there is no need to provide a structure such as a recess on the top surface of the chuck top 3 for removing the spacer 407. This makes it possible to employ a spacer 407 that fills the rim recess groove 4 even more tightly.

[0041] Furthermore, when removing the semiconductor wafer 1, the semiconductor wafer 1 may be lifted up by lift-up pins 408. This facilitates removal of the semiconductor wafer 1. Note that other suction holes 5a, 5b and recesses 6a, 6b are omitted in Figure 12.

[0042] The number and arrangement of the suction holes 5a, 5b and recesses 6a, 6b shown in FIG. 1 are merely an example and are not limiting.

[0043] The above-described modifications can be applied as appropriate to the semiconductor test apparatus and semiconductor device manufacturing method according to the following embodiments. Note that the semiconductor test apparatus and semiconductor device manufacturing method according to the following embodiments have many points in common with the first embodiment, so the following description will focus on the differences from the first embodiment.

[0044] Embodiment 2 FIG. 13 is a cross-sectional view of a semiconductor testing apparatus 500 according to the second embodiment. FIG. 14 is a plan view of the semiconductor testing apparatus 500 according to the second embodiment. FIG. 15 is a cross-sectional view of the semiconductor testing apparatus 500 according to the second embodiment. FIGS. 13 and 15 show a state in which a semiconductor wafer 1 is set on a chuck top 503. FIG. 13 is a cross-sectional view showing a state in which, for example, an 8-inch semiconductor wafer 1b is set. FIG. 15 is a cross-sectional view showing a state in which, for example, a 12-inch semiconductor wafer 1a that is larger than the semiconductor wafer 1b is set. Also, suction holes for suctioning the semiconductor wafer 1 are omitted in FIGS. 13 to 15.

[0045] The semiconductor testing device 500 includes a chuck top 503, a spacer ring 509, and a contact probe. The chuck top 503 has a main surface and a protrusion 503a protruding from the main surface. The spacer ring 509 is annular and is disposed on the main surface of the chuck top 503 so as to surround the protrusion 503a. The spacer ring 509 is detachable from the chuck top 503 and is replaceable. Note that the contact probe 30 and the suction mechanism 40 are omitted from FIGS. 13-15.

[0046] In a method for inspecting or manufacturing a semiconductor device using semiconductor testing device 500, first, a spacer ring 509 is placed on the main surface of chuck top 503 so as to surround convex portion 503a. Next, semiconductor wafer 1 is mounted on the upper surface of convex portion 503a and the upper surface of spacer ring 509 so that the side surface forming the outer edge of spacer ring 509 faces rim 12 of semiconductor wafer 1. In this way, semiconductor wafer 1 is fixed by suction to chuck top 503.

[0047] Next, with semiconductor wafer 1 mounted on the upper surface of convex portion 503a and the upper surface of spacer ring 509, the electrical characteristics of the semiconductor wafer are measured using contact probe 30. The method for acquiring the electrical characteristics is the same as in embodiment 1. Spacer ring 509 is replaced according to the size of semiconductor wafer 1.

[0048] In this embodiment, when processing a small semiconductor wafer 1b, for example, 8 inches, a spacer ring 509b corresponding to the size of the semiconductor wafer 1b is installed on the chuck top 503 as shown in FIG. 13 . Furthermore, by replacing the spacer ring 509 with a larger spacer ring 509a, a larger-sized semiconductor wafer 1a can be set. Here, a difference in the size of the spacer ring 509 means a difference in width W. Thus, in this embodiment, the spacer ring 509 can be replaced according to the size of the semiconductor wafer 1. Therefore, rimmed semiconductor wafers of a variety of sizes can be set in the semiconductor testing device 500. Furthermore, in this embodiment, simply by fabricating the spacer ring 509, the size of the semiconductor wafer 1 can be flexibly accommodated.

[0049] The height H of the spacer ring 509 is preferably the same as the height of the upper surface of the convex portion 503a relative to the main surface of the chuck top 503. The width W of the spacer ring 509 is set so that the distance from the center of the chuck top 503 to the outer edge of the spacer ring 509 is equal to or less than the desired radius of the semiconductor wafer 1. By setting the width W of the spacer ring 509 in consideration of the width of the rim 12 of the semiconductor wafer 1, the rim 12 of the semiconductor wafer 1 and the side surfaces of the spacer ring 509 can be arranged to face each other. This prevents the rim 12 from climbing up onto the spacer ring 509.

[0050] The spacer ring 509 preferably has at least a conductive surface, similar to the spacer 407 of the first embodiment. Specifically, the spacer ring 509 preferably has the same level of conductivity as the chuck top 503. This reduces the risk of poor contact between the back electrode and the chuck top 503, even when testing a semiconductor device having a back electrode.

[0051] 16 is an enlarged cross-sectional view of a semiconductor testing device 500 according to the second embodiment. Adsorption holes 515 configured to adsorb a spacer ring 509 are formed in the main surface of the chuck top 503. The adsorption holes 515 are connected to an adsorption mechanism similar to that of the first embodiment on the underside of the chuck top 503. This allows the spacer ring 509 to be fixed.

[0052] 17 is a further enlarged view of FIG. 16. Suction holes 511 are formed in spacer ring 509. Suction holes 510 are formed in the main surface of chuck top 503, which are connected to suction holes 511 and configured to suck semiconductor wafer 1 via suction holes 511. Suction holes 510 are connected to a suction mechanism similar to that in the first embodiment on the underside of chuck top 503. This enables suction of the portion of semiconductor wafer 1 provided on spacer ring 509. Although not shown, suction holes configured to suck a semiconductor wafer are also formed in protrusion 503a.

[0053] Furthermore, the width of the suction holes 511 of the spacer ring 509 may be narrower on the upper surface side of the spacer ring 509 than on the main surface side of the chuck top 503. This facilitates alignment when placing the spacer ring 509 on the chuck top 503. Furthermore, the width of the suction holes 511 on the side that comes into contact with the semiconductor wafer 1 can be narrowed while improving the workability when replacing the spacer ring 509, thereby ensuring the suction function of the semiconductor wafer 1.

[0054] Alignment pins or notches may be provided to align the suction holes 510 of the chuck top 503 with the suction holes 511 of the spacer ring 509. This makes it easier to attach the spacer ring 509.

[0055] In the semiconductor testing device 500, a small-sized semiconductor wafer 1 may be set on the convex portion 503a without attaching the spacer ring 509. In this case, the convex portion 503a may be circular in plan view. On the other hand, if the spacer ring 509 is to be used, the convex portion 503a may not be circular. Furthermore, the chuck top 503 may not be circular in plan view. However, considering the arrangement of the suction holes 510, 511, and 515, it is preferable that the chuck top 503 be circular in plan view.

[0056] The technical features described in each embodiment may be used in appropriate combination.

[0057] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) a disk-shaped chuck top on which a semiconductor wafer having a rim is mounted; A contact probe; Equipped with The upper surface of the chuck top has: an annular rim recess groove formed concentrically with an outer edge of the chuck top; a first suction hole formed inside the rim recess groove and configured to suck and hold a semiconductor wafer; a second suction hole formed outside the rim recessed groove and configured to suction-hold a semiconductor wafer; A semiconductor testing device characterized in that: (Appendix 2) a first recessed portion connected to a pressure system independent of the first suction hole and the second suction hole is formed on the top surface of the chuck top, the first recessed portion being located on the inner side of the rim recessed groove; 2. The semiconductor testing device according to claim 1, wherein a pressure gauge configured to detect the pressure inside the first recess is connected to the first recess. (Appendix 3) 3. The semiconductor testing device according to claim 2, wherein the first recess is provided with a proximity sensor or an optical sensor. (Appendix 4) a second recess connected to a pressure system independent of the first suction hole and the second suction hole is formed on the top surface of the chuck top outside the rim recess groove; A semiconductor testing device according to any one of appendices 1 to 3, characterized in that a pressure gauge configured to detect the pressure inside the second recess is connected to the second recess. (Appendix 5) 5. The semiconductor testing device according to claim 4, wherein the second recess is provided with a proximity sensor or an optical sensor. (Appendix 6) 6. The semiconductor testing device according to any one of claims 1 to 5, further comprising a spacer that fills the rim recess groove. (Appendix 7) 7. The semiconductor testing device according to claim 6, wherein at least the surface of the spacer is conductive. (Appendix 8) 8. The semiconductor testing device according to claim 6, wherein a third suction hole configured to adsorb the spacer is formed at the bottom of the rim recess groove. (Appendix 9) 9. A semiconductor testing device according to any one of claims 6 to 8, further comprising a lift-up pin configured to protrude from the bottom of the rim recess into the rim recess and to lift the spacer. (Appendix 10) 10. The semiconductor testing device according to any one of claims 1 to 9, wherein the width of the rim recess groove is wider on the top side than on the bottom side. (Appendix 11) a chuck top having a main surface and a protrusion protruding from the main surface; a spacer ring having an annular shape, disposed on the main surface so as to surround the protrusion, and which is replaceable; A contact probe; Equipped with A semiconductor testing device characterized in that the semiconductor wafer is mounted on the upper surface of the convex portion and the upper surface of the spacer ring so that the side forming the outer edge of the spacer ring faces the rim of the rim-equipped semiconductor wafer. (Appendix 12) 12. The semiconductor testing device according to claim 11, wherein at least the surface of the spacer ring is conductive. (Appendix 13) The spacer ring has a first suction hole formed therein, 13. The semiconductor testing device according to claim 11, wherein second suction holes are formed in the main surface, the second suction holes being connected to the first suction holes and configured to suck the semiconductor wafer via the first suction holes. (Appendix 14) 14. The semiconductor testing device according to claim 13, wherein the width of the first suction hole is narrower on the upper surface side than on the main surface side. (Appendix 15) 15. The semiconductor testing device according to any one of claims 11 to 14, wherein the main surface is formed with a third suction hole configured to suction the spacer ring. (Appendix 16) a chuck top having a disk-like shape, the chuck top having an annular rim recess formed concentrically with an outer edge of the chuck top, a first suction hole formed inside the rim recess, and a second suction hole formed outside the rim recess, the chuck top having a rim-shaped semiconductor wafer mounted on the upper surface thereof; measuring electrical characteristics of the semiconductor wafer with a contact probe while the semiconductor wafer is mounted on the upper surface of the chuck top; When the semiconductor wafer is mounted on the upper surface of the chuck top, the rim is disposed in the rim recess groove or opposed to a side surface forming the outer edge of the chuck top, depending on the size of the semiconductor wafer; When the rim is placed in the rim recess, the first suction holes suction-hold the semiconductor wafer, a second suction hole for suction-holding the semiconductor wafer when the rim is positioned so as to face the side surface of the chuck top; (Appendix 17) a chuck top having a main surface and a protruding portion protruding from the main surface; and an annular spacer ring disposed on the main surface so as to surround the protruding portion; a semiconductor wafer is mounted on the upper surface of the convex portion and the upper surface of the spacer ring so that a side surface forming an outer edge of the spacer ring faces the rim of the rim-equipped semiconductor wafer; measuring electrical characteristics of the semiconductor wafer with a contact probe while the semiconductor wafer is mounted on the upper surface of the convex portion and the upper surface of the spacer ring; The method for manufacturing a semiconductor device, wherein the spacer ring is replaced according to the size of the semiconductor wafer. [Explanation of symbols]

[0058] 1, 1a, 1b semiconductor wafer, 3 chuck top, 4 rim recess, 5a, 5b suction hole, 6a, 6b recess, 9 spacer ring, 12 rim, 30 contact probe, 40 suction mechanism, 42 pressure gauge, 100 semiconductor test equipment, 203 chuck top, 204 rim recess, 300 semiconductor test equipment, 303 chuck top, 320 sensor, 400 semiconductor test equipment, 403 chuck top, 407 spacer, 408 lift-up pin, 414 suction hole, 500 semiconductor test equipment, 503 chuck top, 503a protrusion, 509, 509a, 509b spacer ring, 510, 511, 515 suction hole

Claims

1. a disk-shaped chuck top on which a semiconductor wafer having a rim is mounted; A contact probe; Equipped with The upper surface of the chuck top has: an annular rim recess groove formed concentrically with an outer edge of the chuck top; a first suction hole formed inside the rim recessed groove and configured to suck and hold a semiconductor wafer; a second suction hole formed outside the rim recessed groove and configured to suck and hold a semiconductor wafer; A semiconductor testing device characterized in that:

2. a first recess portion connected to a pressure system independent of the first suction hole and the second suction hole is formed on the upper surface of the chuck top, the first recess portion being located inside the rim recess groove; 2. The semiconductor testing device according to claim 1, wherein a pressure gauge configured to detect a pressure inside the first recess is connected to the first recess.

3. 3. The semiconductor testing device according to claim 2, wherein the first recess is provided with a proximity sensor or an optical sensor.

4. a second recess portion connected to a pressure system independent of the first suction hole and the second suction hole is formed on the top surface of the chuck top outside the rim recess groove; 4. The semiconductor testing device according to claim 1, wherein a pressure gauge configured to detect a pressure inside the second recess is connected to the second recess.

5. 5. The semiconductor testing device according to claim 4, wherein the second recess is provided with a proximity sensor or an optical sensor.

6. 4. The semiconductor testing device according to claim 1, further comprising a spacer that fills the rim recess.

7. 7. The semiconductor testing device according to claim 6, wherein at least the surface of said spacer is conductive.

8. 7. The semiconductor testing device according to claim 6, wherein a third suction hole configured to suck the spacer is formed in the bottom of the rim recess groove.

9. 7. The semiconductor testing device according to claim 6, further comprising a lift-up pin configured to protrude from a bottom of the rim recess into the rim recess and to lift up the spacer.

10. 4. The semiconductor testing device according to claim 1, wherein the width of the rim recess groove is wider on the top side than on the bottom side.

11. a chuck top having a main surface and a protrusion protruding from the main surface; a spacer ring that is annular, that is disposed on the main surface so as to surround the protrusion, and that is replaceable; A contact probe; Equipped with A semiconductor testing device characterized in that the semiconductor wafer is mounted on the upper surface of the convex portion and the upper surface of the spacer ring so that the side forming the outer edge of the spacer ring faces the rim of the rim-equipped semiconductor wafer.

12. 12. The semiconductor testing device according to claim 11, wherein at least a surface of the spacer ring is conductive.

13. The spacer ring has a first suction hole formed therein, 13. The semiconductor testing device according to claim 11, wherein second suction holes are formed in the main surface, the second suction holes being connected to the first suction holes and configured to suck the semiconductor wafer via the first suction holes.

14. 14. The semiconductor testing device according to claim 13, wherein the width of the first suction hole is narrower on the upper surface side than on the main surface side.

15. 13. The semiconductor testing device according to claim 11, wherein a third suction hole configured to suck the spacer ring is formed in the main surface.

16. a chuck top having a disk-like shape, the chuck top having an annular rim recess formed concentrically with an outer edge of the chuck top, a first suction hole formed inside the rim recess, and a second suction hole formed outside the rim recess, the chuck top having a rim-shaped semiconductor wafer mounted on the upper surface thereof; measuring electrical characteristics of the semiconductor wafer with a contact probe while the semiconductor wafer is mounted on the upper surface of the chuck top; When the semiconductor wafer is mounted on the upper surface of the chuck top, the rim is disposed in the rim recess or opposed to a side surface forming the outer edge of the chuck top, depending on the size of the semiconductor wafer; When the rim is placed in the rim recess, the first suction holes suction-hold the semiconductor wafer, a second suction hole for suction-holding the semiconductor wafer when the rim is positioned so as to face the side surface of the chuck top;

17. a chuck top having a main surface and a protruding portion protruding from the main surface; and an annular spacer ring disposed on the main surface so as to surround the protruding portion; a semiconductor wafer is mounted on the upper surface of the convex portion and the upper surface of the spacer ring so that a side surface forming an outer edge of the spacer ring faces the rim of the rim-equipped semiconductor wafer; measuring electrical characteristics of the semiconductor wafer with a contact probe while the semiconductor wafer is mounted on the upper surface of the convex portion and the upper surface of the spacer ring; The method for manufacturing a semiconductor device, wherein the spacer ring is replaced according to the size of the semiconductor wafer.

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