Normally-off HEMT device with improved dynamic performances and manufacturing method thereof

Abstract

To provide a normally-off HEMT device with reduced degradation in the ON-state resistance.SOLUTION: A high electron mobility (HEMT) device 20 includes a source electrode 36 that includes a first conductive region 36a and a second conductive region 36b stacked on a first conductive portion. The first conductive region extends completely through two-dimensional gas, 2DEG, of a channel layer 30 and consists of one or more materials that enable ohmic contact with the channel layer, and consists of a metal material with a reduced work function value (e.g., 3.5 to 4.5 eV). The second conductive region is made of one or more materials that enable ohmic contact with a buried layer 25, and is made of a metal material having a high work function value (e.g., 4.5 to 5.6 eV). The work function value of the first conductive region is lower than the work function value of the second conductive region.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a HEMT device and a method for manufacturing the same, and in particular to a normally-off HEMT device with reduced degradation of on-state resistance. [Background technology]

[0002] 2. Description of Related Art HEMT transistors with heterostructures are known, particularly in gallium nitride (GaN) and aluminum gallium nitride (AlGaN), at whose interfaces a conducting channel, particularly a two-dimensional electron gas (2DEG), can be formed. For example, HEMT transistors are valued for use as high frequency and power switches due to their high breakdown threshold and high electron mobility and charge carrier density in the conducting channel. Furthermore, the high current density in the conducting channel of a HEMT transistor allows for a low on-state resistance (or simply R) of the conducting channel. ON ) can be obtained.

[0003] In a known type of HEMT transistor in which the gate electrode extends over an AlGaN / GaN heterostructure, the conduction channel is normally on due to the presence of a high density of charge carriers even when no gate voltage is applied to the heterostructure.

[0004] For safety reasons and to simplify the drive circuitry of HEMT transistors, thereby enabling their use in industrial applications, HEMT transistors with normally-off conduction channels have been introduced. Various approaches have been proposed to obtain normally-off HEMTs, such as recessed-gate or p-GaN-gate HEMTs. Summary of the Invention

[0005] According to the present disclosure, there is provided a HEMT device and method of fabricating the same. The HEMT device comprises a semiconductor body including a substrate, a P-type doped buried layer on the substrate, and a heterostructure on the buried layer including an intrinsic channel layer configured to accommodate a conductive channel of the HEMT device, in use. A source contact extends into the semiconductor body and includes a first L-shaped contact portion that extends partially through the heterostructure to the channel layer and terminates in the channel layer, and a second L-shaped contact portion that extends completely through the heterostructure and partially through the buried layer and terminates in the buried layer. The first contact portion includes a first metallic material that extends in direct electrical contact with the channel layer and forms an ohmic contact with the channel layer, and the second contact portion includes a second metallic material different from the first metallic material that extends in direct electrical contact with the buried layer and forms an ohmic contact with the buried layer. [Brief explanation of the drawings]

[0006] In order that the present disclosure may be better understood, some embodiments will now be described, purely by way of non-limiting example, with reference to the accompanying drawings, in which: [Figure 1] 1 shows a schematic cross-sectional side view of a portion of a HEMT according to one embodiment of a known type; [Figure 2] 1 illustrates a schematic cross-sectional side view of a first portion of a HEMT according to an embodiment of the present disclosure. [Figure 3] 3 shows a schematic cross-sectional side view of a second portion of a HEMT including the first portion of FIG. 2 according to one embodiment of the present disclosure. [Figure 4] 3 shows a schematic cross-sectional side view of a second portion including the first portion of FIG. 2 of a HEMT according to a further embodiment of the present disclosure; [Figure 5A] 3 illustrates steps in fabricating the HEMT of FIG. 2 according to one embodiment of the present disclosure. [Figure 5B]3 illustrates steps in fabricating the HEMT of FIG. 2 according to one embodiment of the present disclosure. [Figure 5C] 3 illustrates steps in fabricating the HEMT of FIG. 2 according to one embodiment of the present disclosure. [Figure 5D] 3 illustrates steps in fabricating the HEMT of FIG. 2 according to one embodiment of the present disclosure. [Figure 5E] 3 illustrates steps in fabricating the HEMT of FIG. 2 according to one embodiment of the present disclosure. [Figure 6A] 3 illustrates manufacturing steps for the HEMT of FIG. 2 according to a further embodiment of the present disclosure. [Figure 6B] 3 illustrates manufacturing steps for the HEMT of FIG. 2 according to a further embodiment of the present disclosure. [Figure 6C] 3 illustrates manufacturing steps for the HEMT of FIG. 2 according to a further embodiment of the present disclosure. [Figure 6D] 3 illustrates manufacturing steps for the HEMT of FIG. 2 according to a further embodiment of the present disclosure. [Figure 6E] 3 illustrates manufacturing steps for the HEMT of FIG. 2 according to a further embodiment of the present disclosure. [Figure 7] 1 shows a schematic cross-sectional side view of a portion of a HEMT according to a further embodiment of the present disclosure; DETAILED DESCRIPTION OF THE INVENTION

[0007] 1 shows a schematic side cross-sectional view in the xz plane of a portion of a HEMT device 1 of known type in a three-axis system of mutually orthogonal axes x, y and z. In particular, the HEMT transistor 1 is a recessed gate transistor.

[0008] HEMT transistor 1 includes a semiconductor body 2 that includes a substrate 4, a buffer layer 6 extending over a face 4a of substrate 4, a buried layer 5 made of P-type doped GaN, and a heterostructure 7 extending over buried layer 5.

[0009] The substrate 4 is, for example, silicon, silicon carbide (SiC), sapphire (Al2O3), or GaN.

[0010] The buffer layer 6 is made of aluminum gallium nitride (AlGaN) or gallium nitride (GaN), either intrinsic or compensated (e.g., carbon and / or iron doping may be employed to compensate for unwanted N-type impurities present as a result of the manufacturing process).

[0011] Heterostructure 7 includes, inter alia, a channel layer 10 extending over buried layer 5 and a barrier layer 9 extending over channel layer 10. Channel layer 10 is made of intrinsic gallium nitride (GaN) and barrier layer 9 is made of undoped aluminum gallium nitride (AlGaN).

[0012] Furthermore, a layer of insulating or dielectric material 11 extends over the barrier layer 9 .

[0013] The HEMT transistor 1 further comprises a source electrode 16 and a drain electrode 18, both of which are made of a conductive material such as titanium (Ti), aluminum (Al), tantalum (Ta) or titanium nitride (TiN).

[0014] The drain electrode 18 extends through the insulating layer 11 onto the heterostructure 7, more precisely, in electrical contact with the upper surface 9a of the barrier layer 9 without penetrating into the barrier layer 9, and the source electrode 16 extends through the insulating layer 11 and depthwise into the semiconductor body 2, completely through the heterostructure 7 (making electrical contact with the channel layer 10 and the 2DEG), partially through the buried layer 5 and terminates in the buried layer 5.

[0015] The HEMT transistor 1 further comprises a gate region 12 which extends depthwise into the semiconductor body 2 until it reaches the interface between the barrier layer 9 and the channel layer 10. In particular, the gate region 12 comprises a gate conductive region 12a and a gate dielectric 12b which, in a manner known per se, surrounds the gate conductive region 12a and electrically insulates it from the semiconductor body.

[0016] One of the key challenges associated with GaN-based HEMT power devices is the R due to high drain bias values, e.g., 400-600 V, when the device is switched on (transition from the off state to the on state). ON The trade-off between the degradation of the GaN layer and the breakdown voltage in the off-state must be found. Indeed, to obtain acceptable values ​​of the longitudinal leakage current, it is necessary to compensate for the unintentional n-type doping of the GaN by introducing other elements such as iron and / or carbon. However, the presence of these elements increases the R ON Such degradation can actually contribute to an increase in the on-resistance between the gate and drain terminals, which is at least partly related to trapping mechanisms (e.g., interface traps, hot electron injection, and traps in the buffer layer 6). Therefore, minimizing this contribution is extremely important.

[0017] 1 and as mentioned above, known solutions envisage electrically coupling buried layer 5 to source terminal 16, thereby enabling or promoting the injection of holes into carbon-rich buffer layer 6 during switching from the off state to the on state, thereby preventing the accumulation of negative charges in buffer layer 6 and the resulting depletion of the 2DEG (and therefore R ON Furthermore, the buried layer 5 plays an important role in the operation of the device under stress conditions caused by the application of a bias to the substrate 4.

[0018] However, the solution of Figure 1 is not optimal because it does not simultaneously provide good ohmic contact to the buried layer 5 and the channel layer 10. Therefore, the solution of Figure 1 reduces the R ON This makes it impossible to fully utilize the effect provided by the buried layer, which mitigates the effect of ionized carbon atoms on the gate and drain terminals and simultaneously reshapes the electric field in the region between the gate and drain terminals (the so-called "gate-drain access region").

[0019] The present invention therefore provides a HEMT device and method for fabricating the same that overcomes the shortcomings of the prior art.

[0020] FIG. 2 shows a schematic side cross-sectional view of a portion of a HEMT device 20 in a three-axis coordinate system with mutually orthogonal axes x, y, and z in the xz plane.

[0021] Device 20 comprises a semiconductor body 22 including a substrate 24, a buffer layer 26 extending over face 24a of substrate 24, a buried layer 25 of P-type doped GaN, and a heterostructure 27 extending over buried layer 25.

[0022] The substrate 24 may be, for example, silicon, silicon carbide (SiC), sapphire (Al2O3), or GaN.

[0023] The buffer layer 26 is made of aluminum gallium nitride (AlGaN) or gallium nitride (GaN). Because N-type impurities are naturally present as a result of the manufacturing process for the buffer layer 26, in one embodiment, P-type doping (e.g., carbon and / or iron doping) is introduced to compensate for the inherently unwanted N-type charge. If the buffer layer 26 is originally intrinsic, P-type doping is not used.

[0024] Heterostructure 27 includes, inter alia, a channel layer 30 extending over buried layer 25, and a barrier layer 29 extending over channel layer 30. A conducting channel, in particular a two-dimensional electron gas (2DEG), is formed at interface 33 between channel layer 30 and barrier layer 29, in use.

[0025] The channel layer 30 is made of intrinsic (undoped) gallium nitride (GaN), and the barrier layer 29 is made of undoped aluminum gallium nitride (AlGaN). x2 It consists of GaN, with x2 in the range of 15% to 30%.

[0026] The buffer layer 26 has a thickness along the Z axis of, for example, 1 μm to 8 μm, for example, 5 μm.

[0027] The buried layer 25 has a thickness of, for example, 100 nm to 500 nm along the Z axis. 18 -3×10 19 at / cm 3 It is doped P-type in the range of

[0028] The channel layer 30 has a thickness along the Z axis of, for example, 10 nm to 1 μm, particularly 100 nm to 500 nm, and is undoped or intrinsic.

[0029] The barrier layer 29 has a thickness along the Z axis of, for example, 5 nm to 30 nm, for example 15 nm, and is undoped or intrinsic.

[0030] Device 20 further includes an insulating or dielectric material layer 31 extending over barrier layer 29. Insulating layer 31 has a thickness of, for example, 50 nm to 200 nm. Insulating layer 31 may be composed of a single insulating or dielectric material, or may include multiple insulating and / or dielectric materials stacked to form a stack. Such materials include, for example, silicon oxide, silicon nitride, and aluminum oxide.

[0031] HEMT transistor 20 further comprises a source electrode 36. Source electrode 36 extends through insulating layer 31 and partially through semiconductor body 22, and is in direct electrical contact with channel layer 30 (and the 2DEG, if present in use) and buried layer 25, terminating within semiconductor body 22.

[0032] Optionally, a passivation or insulating material layer 39 (e.g., SiN) extends over the source electrode 36 to protect and electrically insulate the source electrode 36. Electrical contact areas for applying a bias to the source terminal 36 are formed through the passivation layer in a manner known per se.

[0033] In particular, according to the present disclosure, the source electrode 36 includes a first conductive region 36a and a second conductive region 36b stacked on top of each other.

[0034] First conductive region 36 a extends completely through barrier layer 29 and partially through channel layer 30 , terminating within and in direct electrical contact with channel layer 30 .

[0035] In particular, the first conductive region 36a extends completely through the two-dimensional gas, or 2DEG, of the channel layer 30. The first conductive region 36a is made of one or more materials that allow for ohmic contact with the channel layer 30. In particular, the first conductive region 36a is made of a metallic material with a reduced work function value (e.g., 3.5 to 4.5 eV).

[0036] In one embodiment, the first conductive region 36a includes titanium (Ti) or tantalum (Ta). In a further embodiment, the first conductive region 36a includes two or more stacked layers of conductive materials, such as Ti (or Ta), AlCu, or TiN (or TaN). In one embodiment, the first conductive region 36a is a Ti / AlCu / TiN stack. Tantalum can also be used instead of titanium (e.g., Ta / AlCu / TaN or Ta / AlCu / Ta). When the conductive region 36a includes multiple stacked layers as described above, the titanium (or tantalum) is in direct contact with the channel layer 30.

[0037] In an embodiment in which the first conductive region 36a is a Ti / AlCu / TiN laminate, the thickness of the Ti (or Ta) layer is approximately 3 to 20 nm, the thickness of the AlCu layer is approximately 100 to 300 nm, and the thickness of the TiN (or TaN) layer is approximately 10 to 40 nm.

[0038] The use of a laminate in the first conductive region 36a can reduce the resistivity of the conductive region 36a and improve heat dissipation.

[0039] The second conductive region 36b extends completely through the heterostructure 27 (i.e., the barrier layer 29 and the channel layer 30) and partially through the buried layer 25, terminating within the buried layer 25 and making direct electrical contact with the buried layer 25.

[0040] The second conductive region 36b is made of one or more materials that allow for ohmic contact with the buried layer 25. In particular, the second conductive region 36b is made of a metallic material with a high work function (e.g., 4.5 to 5.6 eV). In particular, the work function of the first conductive region 36a is selected to be lower than the work function of the second conductive region 36b. In one embodiment, the second conductive region 36b includes nickel (Ni) or ruthenium (Ru). In a further embodiment, the second conductive region 36b includes two or more stacked layers of a conductive material, such as Ni, Au, Pt, or Ag. In one embodiment, the second conductive region 36b is a stack of Ni / Au, Ni / Pt / Au, Ni / Ag / Au, or Ni / Ag. When the conductive region 36b includes multiple stacked layers as described above, the nickel is in direct contact with the buried layer 25.

[0041] In embodiments where the second conductive region 36b is a laminate (Ni / Au, Ni / Pt / Au, or Ni / Ag / Au), the Ni layer has a thickness of about 5-50 nm. Other layers on top of the Ni are useful for reducing resistivity and are optional. For example, the thickness of the Au layer ranges from 5-100 nm.

[0042] Using one of the stacks described above for the second conductive region 36b can reduce the resistivity of the conductive region 36b and improve heat dissipation.

[0043] 3, device 20 further comprises a drain electrode 38 made of a conductive material such as titanium (Ti), aluminum (Al), tantalum (Ta) or titanium nitride (TiN), which extends through insulating layer 31 onto heterostructure 27 and, more precisely, is in electrical contact with the upper surface of barrier layer 29 without penetrating it.

[0044] Additionally, device 20 includes a gate terminal 32 extending between a source terminal 36 and a drain terminal 38. Gate terminal 32 may be of the recessed gate or trench gate type, similar to that shown and described in connection with FIG.

[0045] Alternatively, as shown in FIG. 4, the gate terminal is of the “doped gate” type and is identified by the reference numeral 42. Referring to FIG. 4, the gate terminal 42 extends over the heterostructure 27, between and spaced apart from the source electrode 36 and the drain electrode 38. In particular, the gate terminal 42 includes a doped gate region 42a made of p-type doped gallium nitride (GaN), for example, doped with magnesium (Mg), and a gate electrode 42b extending over the doped gate region 42a, the gate electrode 42b being made of a conductive material such as tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), palladium (Pd), tungsten (W), tungsten silicide (WSi), titanium aluminum (Ti / Al), or nickel gold (Ni / Au). The structure formed by the gate electrode 42b and the doped gate region 42a is known in the art as a “p-GaN gate.” As is well known, doped gate region 42a alters the band diagram of heterostructure 27 such that the 2DEG is depleted in the region below doped gate region 42a with no gate voltage applied to gate electrode 42b, and as a result, no conductive channel exists connecting source electrode 36 and drain electrode 38 with no gate voltage applied.

[0046] The doped gate region 42a has a thickness of, for example, 10 nm to 200 nm, for example, 50 nm.

[0047] 5A-5E, fabrication steps for the portion of device 20 shown in Figure 2 will now be described according to one embodiment, limited to the formation of source terminal 36. Figures 5A-5E are side cross-sectional views in the xz plane.

[0048] 5A, after forming semiconductor body 22 in a manner known per se (e.g., by epitaxial growth on one or more substrates 24 with appropriate doping), one or more masked etching steps of semiconductor body 22 are carried out (e.g., by photolithography steps known per se) to remove selected portions of insulating layer 31, barrier layer 29, and channel layer 30. As a result, trench 50 is formed extending into semiconductor body 22 and terminating in channel layer 30. Trench 50 has sidewalls 50a and a bottom wall 50b.

[0049] 5B, a further etching step is performed on semiconductor body 22 at bottom wall 50b of trench 50 until buried layer 25 is reached, resulting in the formation of second trench 52 that terminates within buried layer 25. Second trench 52 has sidewalls 52a and a bottom wall 52b, respectively.

[0050] In the cross-sectional side view, the extension of bottom wall 50b along the x-axis direction is greater than the corresponding extension of bottom wall 52b, i.e., second trench 52 is entirely contained within first trench 50 and has a smaller bottom area (bottom wall 52b) than the bottom area (bottom wall 50b) of first trench 50.

[0051] 5C, a deposition step of a conductive material is then performed to form a first fill layer 56, which will form the first conductive region 36a in subsequent fabrication steps. In particular, a titanium or tantalum deposition step is performed. Alternatively, as described above, a series of depositions may be performed to form a stack including Ti or Ta, AlCu, TiN or Ta, or TaN. The first fill layer 56 extends along the sidewalls 50a and 52a and also over the remainder of the bottom wall 50b and bottom wall 52b of each trench 50 and 52.

[0052] Next, in FIG. 5D, a masked etching step is performed to remove a portion of the first fill layer 56 on the sidewalls 52a and bottom wall 52b of the second trench 52, leaving the first fill layer 56 on the sidewalls 50a and bottom wall 50b of the first trench 50 to form the first conductive region 36a.

[0053] 5E, a further conductive material deposition step is performed to form a second fill layer 58 that forms the second conductive region 36b. In particular, a nickel deposition step is performed. Alternatively, as described above, a series of depositions is performed to form a stack including Ni, Au, Ag, and Pt. The second fill layer 58 extends over the first fill layer 56 (at least over the portion of the first fill layer 56 that extends along the sidewall 50a) and also extends along the sidewall 52a and onto the bottom wall 52b of the trench 52.

[0054] Known types of patterning processes (eg, deposition followed by etching or lift-off) may be used to form second fill layer 58 only where desired (specifically, only within trenches 50 and 52).

[0055] Optionally, a step of depositing a passivation or insulating material (e.g., SiN) on the second conductive region 36b is also performed to protect and electrically isolate the second conductive region 36b. Electrical contact areas for applying a bias to the source terminal 36 are formed through the passivation layer in a manner known per se.

[0056] Next, an optional rapid thermal processing (RTP) step is performed, for example, at a temperature of 500°C to 800°C, to enable or promote the formation of ohmic contacts between the first conductive region 36a and the channel layer 30, and between the second conductive region 36b and the buried layer 25.

[0057] In this way, the device 20 of FIG. 2 is obtained.

[0058] 5A-5E, the fabrication steps of the portion of device 20 shown in Figure 2 will now be described according to embodiments with reference to Figures 6A-6E, limited to the formation of source terminal 36. Figures 6A-6E are side cross-sectional views in the xz plane.

[0059] 6A, after forming semiconductor body 22 in a manner known per se (e.g., by epitaxial growth on substrate 24 in one or more steps with appropriate doping), one or more masked etching steps of semiconductor body 22 are carried out (e.g., by photolithography steps known per se) in order to remove selected portions of insulating layer 31, barrier layer 29, and channel layer 30. As a result, a first trench 60 is formed that extends into semiconductor body 22 and terminates in channel layer 30. First trench 60 has sidewalls 60 a and a bottom wall 60 b.

[0060] 6B, a deposition step of a conductive material is performed to form a first fill layer 66, which will form the first conductive region 36a in a subsequent manufacturing step. In particular, a deposition step of titanium or tantalum is performed. Alternatively, as described above, a series of depositions is performed to form a stack including Ti or Ta, AlCu, TiN or Ta, or TaN. The first fill layer 66 extends along the sidewall 60a and bottom wall 60b of the first trench 60.

[0061] 6C, a patterning step of the first fill layer 66 is then performed to remove selected portions of the first fill layer 66 that extend to the bottom wall 60b of the first trench 60, while retaining portions of the first fill layer 66 that extend to the sidewalls 60a. This step may include, for example, a masked etch, in which an etch mask is shaped to expose the portions of the first fill layer 66 that extend to the bottom wall 60b to an etchant. This at least partially exposes the bottom wall 60b of the first trench 60. Next, an optional rapid thermal processing (RTP) step is performed, for example, at a temperature of 500°C to 800°C, to enable / facilitate the formation of an ohmic contact between the first fill layer 66 and the channel layer 30.

[0062] 6D, a further etching step of semiconductor body 22 is then performed at bottom wall 60b of first trench 60 until buried layer 25 is reached, resulting in the formation of second trench 62 that terminates within buried layer 25. Second trench 62 has sidewalls 62a and bottom wall 62b, respectively.

[0063] In the cross-sectional side view, the extension of bottom wall 60b along the x-axis direction is greater than the corresponding extension of bottom wall 62b, i.e., second trench 62 is entirely contained within first trench 60 and has a smaller bottom area (bottom wall 62b) than the bottom area (bottom wall 60b) of first trench 60.

[0064] 6E, a further conductive material deposition step is performed to form a second fill layer 68 that forms the second conductive region 36b. In particular, a nickel deposition step is performed. Alternatively, as described above, a series of depositions is performed to form a stack including Ni, Au, Ag, and Pt. The second fill layer 68 extends over the first fill layer 66 (at least in the portion of the first fill layer 66 that extends along the sidewall 60a) and also extends along the sidewall 62a onto the bottom wall 62b of the second trench 62.

[0065] Known types of patterning processes (eg, deposition followed by etching or lift-off) may be used to form second fill layer 68 only where desired (specifically, only within trenches 60 and 62).

[0066] Next, an optional rapid thermal processing (RTP) step is performed at a temperature of, for example, 500°C to 800°C to enable / facilitate the formation of an ohmic contact between the second fill layer 68 and the buried layer 25.

[0067] Optionally, a step of depositing a passivation or insulating material (e.g., SiN) on the second conductive region 36b is also performed to protect and electrically isolate the second conductive region 36b. Electrical contact areas for applying a bias to the source terminal 36 are formed through the passivation layer in a manner known per se.

[0068] The RTP described above may be performed only once at the end of the process.

[0069] In this way, the device 20 of FIG. 2 is obtained.

[0070] Finally, it will be apparent that various modifications and variations can be made to what has been described and illustrated herein without departing from the scope of the present disclosure.

[0071] 7, the first conductive regions 36a may extend in an "L-shape" in a cross-sectional side view within each trench. That is, the first conductive regions 36a include a portion 36a' parallel to the yz plane and a portion 36a" parallel to the xy plane that are structurally and electrically continuous with each other.

[0072] Both portions 36 a ′ and 36 a ″ are in direct electrical contact with channel layer 30 .

[0073] It should be further noted that the numerical ranges given herein should be understood to be inclusive of the limits of the range.

[0074] Furthermore, according to further embodiments, the first conductive region 36 a and the second conductive region 36 b may be insulated from one another by an insulating layer (not shown) extending between the first conductive region 36 a and the second conductive region 36 b, in which case, in use, the first conductive region 36 a and the second conductive region 36 b may be biased at different voltage values.

[0075] From the foregoing, the advantages offered by the present invention are clear.

[0076] In particular, the on-state drain-source resistance (R DSon ) resulting in improved dynamic performance.

[0077] The presence of the p-GaN buried layer 25 has the effect of shielding the 2DEG from the substrate voltage (in certain embodiments where a voltage difference is applied between the source and the substrate).

[0078] The HEMT device (20) is summarized as comprising a semiconductor body (22) including a substrate (24), a P-type doped buried layer (25) on the substrate (24), and a heterostructure (27) on the buried layer, the heterostructure (27) including an intrinsic type channel layer (30) configured to accommodate a conductive channel of the HEMT device in use; and a source contact (36) extending depthwise into the semiconductor body, the source contact (36) including a first contact portion (36a) that extends partially through the heterostructure (27) to reach the channel layer (30) and terminates within the channel layer (30); and a second contact portion (36b) that extends completely through the heterostructure (27) and partially through the buried layer (25) and terminates within the buried layer (25), wherein the first contact portion (36a) comprises a first metallic material that extends in direct electrical contact with the channel layer (30) and is for forming an ohmic contact with the channel layer (30), and the second contact portion (36b) comprises a second metallic material that is different from the first metallic material and that extends in direct electrical contact with the buried layer (25) and is for forming an ohmic contact with the buried layer (25).

[0079] The first metallic material has a work function value of 3.5 to 4.5 eV.

[0080] The second metallic material has a work function value of 4.5 to 5.6 eV.

[0081] The first metallic material has a work function value that is lower than the work function value of the second metallic material.

[0082] The first metallic material is or includes titanium or tantalum.

[0083] The second metallic material is or includes nickel or ruthenium.

[0084] The first contact portion (36a) includes a plurality of layered materials including Ti, AlCu, TiN, particularly a Ti / AlCu / TiN stack, or Ta, AlCu, TaN, particularly a Ta / AlCu / TaN stack or a Ta / AlCu / Ta stack.

[0085] The second contact portion (36b) includes a multi-layer material including Ni, Au, Pt, Ag, and in particular includes a stack of Ni / Au, Ni / Pt / Au, Ni / Ag / Au, or Ni / Ag.

[0086] The semiconductor body (22) further includes a buffer layer (26) between the substrate (24) and the buried layer (25), the buffer layer (26) being made of intrinsic or compensated AlGaN or GaN, the buried layer (25) being made of P-type doped GaN, the channel layer (30) being made of intrinsic GaN, and the heterostructure (27) further includes a barrier layer (29) made of AlGaN on and in direct contact with the channel layer (30).

[0087] The HEMT device further includes a recessed gate region (32) extending into the semiconductor body and terminating in the heterostructure (27), or a doped gate region (42) extending over the heterostructure (7) and including P-type doping impurities.

[0088] A method of fabricating a HEMT device (20) is summarized as comprising forming a source contact (36) depthwise in a semiconductor body including a substrate (24), a P-type doped buried layer (25) on the substrate (24), and a heterostructure (27) on the buried layer, the heterostructure (27) including an intrinsic type channel layer (30) configured to accommodate a conductive channel of the HEMT device, in use, wherein forming the source contact (36) comprises forming a first contact portion (36a) partially through the heterostructure (27) to reach the channel layer (30) and terminating within the channel layer (30), the first contact portion (36a) being formed in the channel layer (30). forming a first contact portion (36a) including a step of depositing a first metallic material in direct electrical contact with the channel layer (30), the first metallic material being for forming an ohmic contact with the channel layer (30); and forming a second contact portion (36b) completely through the heterostructure (27) and partially through the buried layer (25) to terminate within the buried layer (25), the second contact portion (36b) including a step of depositing a second metallic material, different from the first metallic material, in direct electrical contact with the buried layer (25), for forming an ohmic contact with the buried layer (25).

[0089] Forming the source contact (36) includes forming a first trench (50) partially through the heterostructure (27), the first trench (50) having sidewalls (50a) and a bottom wall (50b) that exposes the channel layer (30), and forming a second trench (52) by removing selected portions of the channel layer (30) and buried layer (25) at the bottom wall (50b) of the first trench (50). The method includes sequentially performing the steps of depositing a first metal material (56) in the first trench (50) and the second trench (52), removing selected portions of the first metal material (56) from the second trench (52) and retaining the first metal material (56) on the sidewalls (50a) of the first trench (50), and depositing a second metal material (58) in the first trench (50) and the second trench (52).

[0090] The method further includes performing a rapid thermal process after the step of depositing the second metallic material (58).

[0091] Forming the source contact (36) includes forming a first trench (60) partially through the heterostructure (27), the first trench (60) having sidewalls (60a) and a bottom wall (60b) that exposes the channel layer (30); depositing a first metal material (66) in the first trench (60); removing selected portions of the first metal material (66) at the bottom wall (60b); forming a second trench (62) by removing selected portions of the channel layer (30) and the buried layer (25) at the bottom wall (60b) of the first trench (60); and depositing a second metal material (58) in the first trench (60) and the second trench (62).

[0092] The method further includes performing a first rapid thermal process after the step of depositing the first metallic material (66) and before the step of removing selected portions of the first metallic material (66), performing a second rapid thermal process after the step of depositing the second metallic material (68), or alternatively performing a rapid thermal process of the first metallic material (66) and the second metallic material (68) after the step of depositing the second metallic material (68).

[0093] The various embodiments described above can be combined to provide further embodiments, and aspects of the embodiments can be modified, if necessary, to employ concepts from various patents, applications, and publications to provide further embodiments.

[0094] These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but rather to include all possible embodiments, along with the full range of equivalents to which such claims are entitled. Accordingly, the claims are not limited by this disclosure.

Claims

1. A HEMT device, comprising: A semiconductor body comprising: A substrate; a P-type doped buried layer on the substrate; a heterostructure on the buried layer, the heterostructure including an intrinsic channel layer configured, in use, to accommodate a conductive channel of the HEMT device; a semiconductor body including: a source contact extending into the semiconductor body; Equipped with the source contact is a first L-shaped contact portion extending partially through the heterostructure to the channel layer and terminating within the channel layer; a second L-shaped contact portion extending completely through the heterostructure and partially through the buried layer and terminating within the buried layer; Including, the first contact portion comprises a first metallic material that extends in direct electrical contact with the channel layer and forms an ohmic contact with the channel layer; the second contact portion comprises a second metallic material different from the first metallic material, the second metallic material extending in direct electrical contact with the buried layer and forming an ohmic contact with the buried layer; HEMT device.

2. The HEMT device of claim 1 , wherein the first metallic material has a work function value in the range of 3.5 to 4.5 eV.

3. The HEMT device of claim 1 , wherein the second metallic material has a work function value in the range of 4.5 to 5.6 eV.

4. 10. The HEMT device of claim 1, wherein the first metallic material has a first work function value that is lower than a second work function value of the second metallic material.

5. The HEMT device of claim 1 , wherein the first metallic material comprises titanium.

6. The HEMT device of claim 1 , wherein the second metallic material comprises nickel.

7. The HEMT device of claim 1 , wherein the first contact portion comprises a plurality of layered materials including Ti, AlCu, and TiN arranged in a stack.

8. The HEMT device of claim 1 , wherein the second contact portion comprises a plurality of layered materials including Ni, Au, Pt, and Ag arranged in a stack.

9. 10. The HEMT device of claim 1, wherein the semiconductor body further comprises a buffer layer between the substrate and the buried layer, the buffer layer comprising AlGaN, the buried layer comprising P-type doped GaN, the channel layer comprising intrinsic GaN, and the heterostructure further comprises a barrier layer comprising AlGaN overlying and in direct contact with the channel layer.

10. The HEMT device of claim 1 further comprising a recessed gate region extending into said semiconductor body and terminating within said heterostructure.

11. 1. A method of manufacturing a HEMT device, comprising: forming a source contact comprising a substrate, a P-type doped buried layer on the substrate, and a heterostructure on the buried layer, the heterostructure including a channel layer; forming the source contact forming a first contact portion, the first contact portion having a first portion extending partially through the heterostructure along a first direction and terminating in the channel layer and a second portion of the first contact portion lateral to the first portion, the first contact portion comprising depositing a first metallic material in direct electrical contact with the channel layer; forming a second contact portion, the second contact portion having a first portion extending completely through the heterostructure along the first direction and partially through the buried layer, and a second portion of the second contact portion lateral to the first portion of the second contact portion, the second contact portion comprising depositing a second metallic material, different from the first metallic material, in direct electrical contact with the buried layer and forming an ohmic contact with the buried layer; Including, method.

12. forming the source contact forming a first trench partially through the heterostructure, the first trench having sidewalls extending along the first direction and a bottom wall transverse to the first direction, the bottom wall exposing the channel layer; forming a second trench by removing a portion of the channel layer and the buried layer at the bottom wall of the first trench; depositing the first metallic material in the first trench and the second trench; removing a portion of the first metal material from the second trench and retaining the first metal material on the sidewalls of the first trench; depositing the second metallic material in the first trench and the second trench; Including, The method of claim 11.

13. The method of claim 12 further comprising performing a rapid thermal process after depositing the second metallic material.

14. forming the source contact forming a first trench partially through the heterostructure, the first trench having sidewalls extending along the first direction and a bottom wall transverse to the first direction, the bottom wall exposing the channel layer; depositing the first metallic material in the first trench; removing a portion of the first metallic material in the bottom wall; forming a second trench by removing a portion of the channel layer and the buried layer at the bottom wall of the first trench; depositing the second metallic material in the first trench and the second trench; Including, The method of claim 11.

15. performing a first rapid thermal process after depositing the first metallic material and before removing a portion of the first metallic material; performing a second rapid thermal process after depositing the second metallic material; 15. The method of claim 14, further comprising:

16. A substrate; a buried layer on the substrate; a heterostructure on the buried layer; A source electrode; wherein the source electrode is a first conductive region; a second conductive region; and Including, The first conductive region is a first portion extending at least partially through the heterostructure along a first direction; a second portion extending along a second direction transverse to the first direction, the second portion being on the heterostructure; Including, The second conductive region is a first portion extending along the first direction completely through the heterostructure and at least partially through the buried layer; a second portion extending along the second direction over the second portion of the first conductive region; Including, device.

17. 17. The device of claim 16, further comprising an insulating layer between the heterostructure and the second portion of the first conductive region.

18. 17. The device of claim 16, wherein the heterostructure includes a barrier layer over a channel layer, the first portion of the first conductive region extending completely through the barrier layer and at least partially through the channel layer along the first direction.

19. 17. The device of claim 16, wherein the second portion of the first conductive region and the second portion of the second conductive region are covered by a layer of insulating material.

20. 20. The device of claim 17, wherein the device further comprises a gate terminal that extends along the first direction completely through the insulating layer and at least partially through the heterostructure, and a drain electrode that extends completely through the insulating layer.

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