Fast initial phase search for digital clock and data recovery and related system, device, and method

Abstract

To provide a physical layer device and method for selecting a sample phase of a signal.SOLUTION: A physical layer device 1000 includes: sampling circuitry 1006 configured to receive a signal 1002, which may be delivered to an input 1004 of the physical layer device 1000 from a shared transmission medium 106, and measure sample values 1008 at a plurality of different sample phases 1022; an edge detector 1010 configured to determine an edge sample phase 1012 of the different sample phases corresponding to an edge of a symbol, based on the sample values; a center detector 1014 configured to determine a center sample phase 1016 of the different sample phases, based on the determined edge sample phase; and sampling circuitry 1018 configured to determine center sample values 1020 using the determined center sample phase.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] (Priority Claim) This application claims the benefit of backdating to Chinese Patent Application No. 201910784610.8, filed on August 23, 2019, entitled "FAST INITIAL PHASE SEARCH FOR DIGITAL CLOCK AND DATA RECOVERY AND RELATED SYSTEMS, DEVICES, AND METHODS," and to U.S. Patent Application No. 16 / 588,621, filed on September 30, 2019, entitled "FAST INITIAL PHASE SEARCH FOR DIGITAL CLOCK AND DATA RECOVERY AND RELATED SYSTEMS, DEVICES, AND METHODS" (pending), the disclosures of each of which are incorporated herein by reference in their entireties.

[0002] (Technical field) The present disclosure relates generally to setting the initial phase of a digital clock data recovery (DCDR), and more particularly to DCDR of signals received over a shared transmission medium of a wired local area network. [Background technology]

[0003] In data communications, it is useful to identify the appropriate sample phase of a signal. Typically, a sample phase near the center of a symbol is the best sample phase. As the sample phase approaches the transition between symbols (e.g., an edge), there may be a greater chance of errors, especially in environments prone to noise and interference. An automotive environment is one such environment that may be prone to noise and interference. To complicate matters, received packets may come from many different transmitters, and the symbols may not be aligned with each other in time. As a result, it may be necessary to find a suitable sampling phase for each different received packet. While the present disclosure concludes with claims that particularly point out and distinctly claim certain embodiments, the various features and advantages of embodiments within the scope of the present disclosure can be more readily ascertained from the following description when read in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 2 is a block diagram of a portion of a network segment, according to some embodiments. [Figure 2] 1 is an eye diagram according to some embodiments. [Figure 3] FIG. 10 is a symbol sampling diagram according to some embodiments. [Figure 4] 1 is a flowchart illustrating a method for selecting a sample phase of a signal from a plurality of different sample phases, according to some embodiments. [Figure 5] FIG. 10 is another symbol sampling diagram according to some embodiments. [Figure 6] 1 is a flowchart illustrating a method for determining an edge sample phase according to some embodiments. [Figure 7] FIG. 10 is yet another symbol sampling diagram according to some embodiments. [Figure 8] 10 is a flowchart illustrating another method for determining an edge sample phase according to some embodiments. [Figure 9] 10 is a flowchart illustrating yet another method for determining an edge sample phase, according to some embodiments. [Figure 10] FIG. 2 is a block diagram of a physical layer device according to some embodiments. [Figure 11] FIG. 1 is a block diagram of a computing device that may be used in some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0005] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and which show, by way of illustration, specific embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure. However, as enabled herein, other embodiments may be used, and changes in structure, materials, and processes may be made without departing from the scope of the present disclosure.

[0006] The figures presented herein are not intended to be actual illustrations of any particular method, system, device, or structure, but merely idealized representations used to describe embodiments of the present disclosure. In some cases, similar structures or components in various figures may retain the same or similar numbering for the convenience of the reader. However, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0007] The following description may include examples to assist those skilled in the art in practicing the disclosed embodiments. The use of the terms "exemplary," "example," and "for example" means that the associated description is explanatory, and the scope of the present disclosure is intended to encompass examples and legal equivalents. The use of such terms is not intended to limit the embodiments or the scope of the present disclosure to specific components, steps, features, functions, etc.

[0008] It will be readily understood that the components of the embodiments, as generally described herein and illustrated in the figures, could be arranged and designed in a wide variety of different configurations. Thus, the following description of various embodiments is not intended to limit the scope of the disclosure, but is merely representative of various embodiments. While various aspects of the embodiments may be presented in drawings, the drawings are not necessarily drawn to scale unless otherwise noted.

[0009] Furthermore, the specific implementations shown and described are merely examples and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions may be shown in block diagram form so as not to obscure the present disclosure in unnecessary detail. Conversely, the specific implementations shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Furthermore, the block definitions and partitioning of logic among various blocks are exemplary specific implementations. It will be readily apparent to one skilled in the art that the present disclosure can be implemented with numerous other partitioning solutions. For the most part, details regarding timing considerations and the like have been omitted; such details are not necessary to obtain a complete understanding of the present disclosure and are within the capabilities of those skilled in the art.

[0010] Those skilled in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. Some figures may illustrate a signal as a single signal for clarity of presentation and explanation. Those skilled in the art will understand that a signal may represent a bus of signals, which may have various bit widths, and that the present disclosure may be implemented with any number of data signals, including a single data signal.

[0011] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (sometimes referred to herein as a host processor or simply a host) may be a microprocessor, although the processor may alternatively be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer, and a general-purpose computer is configured to execute computing instructions (e.g., software code) related to the embodiments of the present disclosure.

[0012] The embodiments may be described in terms of a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. While a flowchart may describe operational acts as a sequential process, many of these acts can be performed in a different order, in parallel, or substantially simultaneously. Additionally, the order of acts may be rearranged. A process may correspond to a method, a thread, a function, a procedure, a subroutine, a subprogram, other structure, or combinations thereof. Furthermore, methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, such as any medium that facilitates transfer of a computer program from one place to another.

[0013] Any reference to elements herein using designations such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitation is expressly stated. Rather, these designations may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, reference to a first element and a second element does not imply that only two elements may be used or that the first element must precede the second element in any way. Additionally, unless otherwise specified, a set of elements may include one or more elements.

[0014] As used herein, the term "substantially" when referring to a given parameter, characteristic, or condition means and includes the extent to which one of ordinary skill in the art would understand that the given parameter, characteristic, or condition is met with small variations, e.g., within acceptable manufacturing tolerances. As an example, depending on the particular parameter, characteristic, or condition that is substantially met, the parameter, characteristic, or condition may be at least 90% met, at least 95% met, or even at least 99% met.

[0015] Mobile machines, such as automobiles, trucks, buses, ships, and / or aircraft, may include a mobile machine communication network. The complexity of the mobile machine communication network may vary depending on the number of electronic devices in the network. For example, an advanced mobile machine communication network may include various control modules, such as for engine control, transmission control, safety control (e.g., anti-lock brakes), and emissions control. To support these modules, the automotive industry relies on a variety of communication protocols.

[0016] 10SPE (i.e., 10Mbps Single Pair Ethernet) is a network technology specification currently under development by the Institute of Electrical and Electronic Engineers as specification IEEE 802.3cg™. 10SPE can be used to provide collision-free, deterministic transmission over multidrop networks. IEEE 802.3cg™ defines 10BASE-T1S (also known as "cg") for use with automotive sensors, acoustics, other devices, or a combination thereof. 10BASE-T1S can also be used in backplanes and Internet of Things (IoT) networks. The cg specification targets a 10 megabits per second (Mbps) multidrop bus using carrier sense multiple access (CSMA) in conjunction with physical layer collision avoidance (PLCA).

[0017] In certain environments where wired local area networks (e.g., Ethernet) are used, it may be desirable to quickly identify the appropriate sampling phase of a signal. Digital clock data recovery (CDR) (DCDR) based on multiple sampling typically requires a relatively large amount of training data to determine acceptable sampling phases (e.g., the best sampling phase). Traditionally, CDRs for point-to-point links use different coding schemes and rely on extensive digital signal processing (DSP) training periods before link-up. However, the 10SPE frame structure includes a frame preamble preceded by a SYNC pattern, which contains only 10 symbols (e.g., in a Differential Manchester Encoding (DME) code, one symbol is approximately 40 nanoseconds long). As a result, the 10SPE frame preamble does not have enough data for traditional CDR training to find the best sampling phase. To complicate matters further, 10SPE includes stringent tests (e.g., bulk current injection (BCI) tests and direct power injection (DPI) tests) designed to generate common-mode interference (e.g., high common-mode creation events), and Ethernet devices may be required to pass these tests. Due to the shortness of the 10SPE frame preamble, it is desirable to find the best sampling phase within a few symbols (e.g., 10 symbols or less).

[0018] Some embodiments disclosed herein enable fast (e.g., within 10 symbols or less) and reliable CDR even in relatively noisy and high-level interference situations, making the embodiments disclosed herein suitable for 10SPE in automotive environments. For example, the embodiments disclosed herein are directed to a DCDR that improves jitter / interference tolerance based on the multi-sampling involved in 10SPE. The embodiments disclosed herein also enable data recovery from signals and clocks with few bits / symbols. As a result, the embodiments disclosed herein enable robust and reliable CDR in very noisy environments (e.g., automotive environments), pass rigorous BCI and DPI automotive tests, and determine the best sampling phase within approximately 10 symbols or less (e.g., within 8 symbols, 6 symbols, or even within 3 or 4 symbols), allowing the DCDR to function properly and fully recover the 10SPE frame. Instead of a traditional training phase, two different solutions are disclosed herein to find the best sampling phase within a small number of symbols.

[0019] The embodiments disclosed herein use a quadrature clock to oversample the received signal. Oversampling is used by the DCDR to identify bit (e.g., symbol) boundaries. A phase search block is introduced to find the best initial phase for the DCDR within a few symbols, replacing the training phase used in conventional systems. The phase search block counts the number of edges for each sampling phase and selects the phase with the most edges as the initial phase. In this circuit, the DCDR initial phase can be set to 10 symbols (e.g., bit times) or less. This allows the DCDR to lock by the start of the preamble (e.g., using a SYNC pattern bit before the preamble. Since there are two SYNCs in a 10-SPE frame, and the second SYNC is used to determine the 5B boundary for 4B5B decoding, acquiring lock within the first SYNC is useful), allowing the DCDR to decode the complete frame. This is useful because the preamble time is used to synchronize the multiplicative descrambler and may be used in future Operation, Administration, and Management (OAM) applications.

[0020] 1 is a functional block diagram of a network segment 100 including a link layer device, a MAC shared transmission medium 106, and a physical layer (PHY) device (PHY 102) according to some embodiments. By way of non-limiting example, network segment 100 may be a segment of a multi-drop network, a segment of a multi-drop subnetwork, a segment of a mixed-media network, or any combination or sub-combination thereof. By way of non-limiting example, network segment 100 may be, be part of, or include one or more of, without limitation, a microcontroller-based embedded system, a user-type computer, a computer server, a notebook computer, a tablet, a handheld device, a mobile device, a wireless earphone or headphone device, a wired earphone or headphone device, an appliance subsystem, a lighting subsystem, an audio subsystem, a building management system, a home monitoring system (e.g., without limitation, for security or utility usage), an elevator system or subsystem, a public transportation control system (e.g., without limitation, for surface trains, subways, trolleys, or buses), an automobile system or automobile subsystem, or an industrial control system.

[0021] PHY 102 may be configured to interface with MAC 104. As a non-limiting example, PHY 102 and / or MAC 104 may be a chip package including memory and / or logic configured to perform all or a portion of the embodiments described herein. As a non-limiting example, PHY 102 and MAC 104 may be implemented as separate chip packages or circuits (e.g., integrated circuits) within a single chip package (e.g., a system-in-a-package (SIP)).

[0022] PHY 102 also interfaces with shared transmission medium 106, the physical medium that is the communication path for nodes that are part of network segment 100, or with the network of which network segment 100 is a part, such as the node that includes PHY 102 and MAC 104. As a non-limiting example, shared transmission medium 106 can be a single twisted pair (e.g., unshielded twisted pair, or UTP) such as used in single-pair Ethernet.

[0023] In some embodiments, network segment 100 may be used in an automotive environment. By way of non-limiting example, network segment 100 may be configured to connect one or more sensors in an automobile to a computer or controller. Also by way of non-limiting example, PHY 102 may be used in 10BASE-T1S endpoints and switches.

[0024] Differential Manchester Encoding (DME) is used to encode the clock and data. The PHY 102 may act as a receiver for one or more such encoded signals, which may be received over the shared transmission medium 106. The clock and data of the received signal are decoded. In a 10SPE system, there may be no time or pattern provided for training to enable CDR. Therefore, the PHY 102 must be configured to quickly identify the appropriate sample phase.

[0025] 2 is an eye diagram 200 according to some embodiments. The eye diagram 200 includes a signal 206 that rises and falls between different voltage levels corresponding to different logic levels. In the example shown in FIG. 2, the signal 206 is configured to transition between two voltages, including a logic level high and a logic level low.

[0026] When PHY 102 (FIG. 1) receives signal 206, PHY 102 samples signal 206 to determine whether signal 206 is a logic high or a logic low for each symbol carried by signal 206. When sampling signal 206, the best sampling phase will be at the center 202 of each symbol. Center 202 can be determined if the edges 204 of the symbols are known or have been detected and the length of time of each symbol is known.

[0027] The embodiments disclosed herein enable detection of symbol edges 204 in a received signal 206 through oversampling of the signal 206. As a non-limiting example, 4x multisampling can be used (4 samples per symbol). As a result, four different sample phases a, b, c, and d can be used to sample the signal 206. Once the edge 204 is detected, it can be used to estimate which of the four different sample phases a, b, c, and d may be near the center 202.

[0028] It should be noted that in some embodiments, sample phases a, b, c, and d may be substantially equally spaced in time, as shown in Figure 2. However, in some embodiments, sample phases a, b, c, and d may be unequally spaced in time without departing from the embodiments disclosed herein.

[0029] FIG. 3 illustrates a symbol sampling diagram 300 according to some embodiments. The symbol sampling diagram 300 includes a signal 302. The signal 302 includes symbols 304, 306, 308, 310, 312, 314, and 316. As previously discussed, the signal 302 may be multisampled (e.g., two or more samples per symbol). In the example of FIG. 3, the signal 302 is multisampled by four (four samples per symbol) using sample phases a, b, c, and d. Sample phase a has one sample value from each of the symbols 304-316. As a result, a = [a0 a1 a2 a3 a4 a5 a6...]. Similarly, sample phases b, c, and d each have one sample value from each of the symbols 304-316. As a result, b=[b0 b1 b2 b3 b4 b5 b6...], c=[c0 c1 c2 c3 c4 c5 c6...], and d=[d0 d1 d2 d3 d4 d5 d6...].

[0030] Proposed herein are two different solutions to find which of the sample phases a, b, c, and d are edge sample phases so that the center sample phase can be determined.

[0031] 4 is a flowchart illustrating a method 400 for selecting a sample phase (e.g., a center sample phase) of a signal (e.g., signal 302 of FIG. 3) from a plurality of different sample phases (e.g., a, b, c, and d of FIG. 3) according to some embodiments. Referring jointly to FIGS. 3 and 4, at operation 402, method 400 samples signal 302 including a plurality of symbols 304-316 using a plurality of different sample phases a, b, c, and d at a physical layer circuit (e.g., PHY 102 of FIG. 1) of a wired local area network (e.g., network segment 100 of FIG. 1) to obtain respective sample values ​​a0-d6 of the plurality of symbols 304-316 at each of the plurality of different sample phases a, b, c, and d. Signal 302 is received from shared transmission medium 106 operatively coupled to PHY 102 (FIG. 1).

[0032] In operation 404, the method 400 determines, based on the sample values ​​a0-d6, edge sample phases from a plurality of different sample phases a, b, c, d that correspond to edges of the symbol 304 316. The following discussion, taken together with Figures 5 and 6, illustrates a first method 600 for determining edge sample phases. The following discussion, taken together with Figures 7, 8, and 9, illustrates two subsets of a second method 800, 900 for determining edge sample phases.

[0033] In operation 406, the method 400 determines a center sample phase of a plurality of different sample phases corresponding to the center of a symbol based on the determined edge sample phase. In some embodiments, determining a center sample phase of a, b, c, d of the plurality of different sample phases corresponding to the center of the symbol 304-316 based on the edge sample phase includes determining the center sample phase to be a sample phase that is approximately one-half symbol time from the edge sample phase. As a non-limiting example, if the edge sample phase is determined to be a, either b or c may be determined to be the center sample phase. Also, as a non-limiting example, if the edge sample phase is determined to be sample phase d, either b or c may be determined to be the center sample phase.

[0034] At operation 408, method 400 determines values ​​of symbols using the center sample phase determined in operation 406. As a non-limiting example, if b is determined to be the center sample phase, the values ​​of symbols 304-316 may be determined to be b=[b0 b1 b2 b3 b4 b5 b6...]. Also, as a non-limiting example, if c is determined to be the center sample phase, the values ​​of symbols 304-316 may be determined to be c=[c0 c1 c2 c3 c4 c5 c6...].

[0035] FIG. 5 is another symbol sampling diagram 500 according to some embodiments. The symbol sampling diagram 500 includes the signal 302, symbols 304, 316, sampling phases a, b, c, d, and sampling values ​​a0 through d6 of FIG. 3 . In addition, FIG. 5 shows the values ​​of the sampling values ​​a0 through d6. For example, a=[1 −1 1 1 −1 1 −1 1 −1...], b=[1 −1 1 1 −1 1 −1...], c=[1 −1 1 1 −1 1 −1...], and d=[1 −1 1 1 −1 1 −1...]. Note that a sampled logic level high is represented by “1” and a sampled logic level low is represented by “−1.” Note also that for purposes of FIGS. 5 and 6 , a predetermined value may be used to represent a logic level high, and the negative of a predetermined value may be used to represent a logic level low.

[0036] The edge sample phase may be determined by counting the edges at each sampling phase a, b, c, d, which may be accomplished using method 600 of FIG.

[0037] 6 is a flowchart illustrating a method 600 for determining an edge sample phase according to some embodiments. Referring to FIGS. 5 and 6 together, in operation 602, the method 600 performs, for each sample phase among a plurality of different sample phases a, b, c, and d, an exclusive-or (XOR) calculation between the sample value corresponding to the sample phase and the sample value corresponding to the sample phase immediately adjacent in time to the sample phase. For example, the edge of each sampling phase may be determined corresponding to the sample phase immediately preceding the sample phase. More specifically, the following may be calculated: ●e(a,n)=a(n)XOR d(n-1) ●e(b,n)=b(n)XOR a(n) ●e(c,n)=c(n)XOR b(n) ●e(d,n)=d(n)XOR c(n) where e(x,n) denotes the edge calculation of sample phase x for bit n.

[0038] The calculation result of e(a,n)=a(n)XORd(n-1) is [1 -1 1 1 -1 1 -1...]XOR[ * 1 -1 1 1 -1 1...], and this result is e(a,n)=[ * 1 1 0 1 1 1...] (where " * (" indicates an unknown quantity). The result of e(b,n)=b(n)XOR a(n) is obtained by computing [1 -1 1 1 -1 1 -1 1 -1...]XOR[1 -1 1 1 -1 1 -1...], which results in e(b,n)=[0 0 0 0 0 0 0...]. The result of e(c,n)=c(n)XOR b(n) is obtained by computing [1 -1 1 1 -1 1 -1 1 -1...]XOR[1 -1 1 1 -1 1 -1...], which results in e(c,n)=[0 0 0 0 0 0 0...]. The result of calculating e(d,n)=d(n) XOR c(n) is obtained by calculating [1 -1 1 1 -1 1 -1 1 -1...] XOR [1 -1 1 1 -1 1 -1...], which results in e(d,n)=[0 0 0 0 0 0 0...].

[0039] In operation 604, the method 600 sums the results of each XOR calculation to obtain a total number of edges for each sampling phase. The total number of edges for each sample phase a, b, c, and d is obtained by summing the elements in e(x) (e.g., e(a,n), e(b,n), e(c,n), e(d,n)) (sum(e(x)=e(x,1)+e(x,2)+e(x,3)+...). For example, the total number of edges for sample phase a is obtained by summing the elements in e(a,n)=[-1 1 0 1 1 1] (1+1+0+1+1+1=5). The total number of edges for sample phases b, c, and d is obtained by summing the elements in e(b,n), e(c,n), and e(d,n) ([0 0 0 0 0 0 0], respectively, and the total number of edges for b, c, and d is equal to zero (the sum of [0 0 0 0 0 0 0] is 0).

[0040] In operation 606, the method 600 determines the edge sample phase, which is the sample phase corresponding to the highest sum of the results of each XOR calculation. In this case, the highest sum of the results of the XOR calculation corresponds to sample phase a (sum of e(a,n)=5 compared to sum of e(b,n)=0, sum of e(c,n)=0, and sum of e(d,n)=0), so the sample phase is determined to be the edge sample phase.

[0041] 5, it should be noted that the sample value of each sample phase a, b, c, d was XORed with the sample value of the sample phase immediately preceding the sample phase in time (i.e., a(n) was XORed with d(n-1), b(n) was XORed with a(n), c(n) was XORed with b(n), and d(n) was XORed with c(n). In other words, in some embodiments, operation 602 includes performing an XOR calculation between the sample value corresponding to the sample phase and the sample value corresponding to the sample phase immediately preceding the sample phase in time.

[0042] However, it should be noted that in some embodiments, the sample values ​​of each sample phase a, b, c, d may be XORed with the sample values ​​of the sample phase immediately following the sample phase in time (i.e., a(n) may be XORed with b(n), b(n) may be XORed with c(n), c(n) may be XORed with d(n), and d(n) may be XORed with a(n+1)). In such an embodiment, e(a,n)=[1 -1 1 1 -1 1 -1 1 -1...]XOR[1 -1 1 1 -1 1 -1...]=[0 0 0 0 0 0 0...], e(b,n)=[1 -1 1 1 -1 1 -1...]XOR [1 -1 1 1 -1 1 -1...]=[0 0 0 0 0 0 0...], e(c,n)=[1 -1 1 1 -1 1 -1 1...]XOR[1 -1 1 1 -1 1 -1...]=[0 0 0 0 0 0 0...], and e(d,n)=[1 -1 1 1 -1 1 -1 1...]XOR[-1 1 1 -1 1 -1 * ...]=[1 1 0 1 1 1 *...]. As a result, the sum e(x) of each of the sample phases a, b, c, and d is 0, 0, 0, and 5, respectively. In this case, d is selected to be the edge sample phase. In other words, in some embodiments, operation 602 includes performing an XOR calculation between a sample value corresponding to the sample phase and a sample value corresponding to a sample phase immediately following the sample phase in time. While + / -1 is used to indicate logic levels high and low, respectively, any value other than + / -1 (e.g., + / -2, + / -3) may be used in place of + / -1 without departing from embodiments disclosed herein. Also, note that because e(x,n) is determined using an XOR calculation, "1" and "0" may be used in place of + / -1 to represent signal 302 without departing from embodiments disclosed herein.

[0043] Figure 7 is yet another symbol sampling diagram 700 according to some embodiments. The symbol sampling diagram 700 includes the signal 302 of Figure 3. The signal 302 includes the symbols 304-316, sampling phases a, b, c, and d, and sampling values ​​a0-d6 of Figure 3. In addition, Figure 7 shows values ​​for the sampling values ​​a0-d6 similar to Figure 5. For example, a = [1 -1 1 1 -1 1 -1...], b = [1 -1 1 1 -1 1 -1...], c = [1 -1 1 1 -1 1 -1...], and d = [1 -1 1 1 -1 1 -1...].

[0044] The edge sample phases may be determined by calculating the absolute sum of the symbol times at each sampling phase a, b, c, d, which may be accomplished using method 800 of FIG. 8 or method 900 of FIG. 9.

[0045] 8 is a flowchart illustrating another method 800 for determining an edge sample phase according to some embodiments. Referring to FIGS. 7 and 8 together, in operation 802, the method 800 calculates, for each sample value of a plurality of different sample phases, a sum of the sample value and each of the other sample values ​​within one symbol time period after the sample value to obtain a plurality of sums of the sample values. Each of the plurality of sums corresponds to a different one of the plurality of different sample phases. For example, the plurality of sums can be expressed as follows: ●sum(a,n)=a(n)+b(n)+c(n)+d(n) ●sum(b,n)=b(n)+c(n)+d(n)+a(n+1) ●sum(c,n)=c(n)+d(n)+a(n+1)+b(n+1) ●sum(d,n)=d(n)+a(n+1)+b(n+1)+c(n+1)

[0046] At operation 804, method 800 determines the absolute value of each of the plurality of sums for the plurality of different sample phases to obtain a plurality of absolute values ​​for the plurality of different sample phases. As a result, the plurality of absolute values ​​can be expressed as: ●s(a,n)=abs(sum(a,n)) ●s(b,n)=abs(sum(b,n)) ●s(c,n)=abs(sum(c,n)) ●s(d,n)=abs(sum(d,n))

[0047] Calculating these absolute values ​​for each sample frequency and symbol yields the following absolute values, as shown in the bottom four rows of FIG. ●s(a,0)=4, s(a,1)=4, s(a,2)=4, s(a,3)=4, s(a,4)=4, s(a,5)=4, s(a,6)=4 ●s(b,0)=2, s(b,1)=2, s(b,2)=4, s(b,3)=2, s(a,4)=2, s(b,5)=2, s(b,6)=2 ●s(c,0)=0, s(c,1)=0, s(c,2)=4, s(c,3)=0, s(a,4)=0, s(c,5)=0, s(c,6)=0 ●s(d,0)=2, s(d,1)=2, s(d,2)=4, s(d,3)=2, s(a,4)=2, s(d,5)=2, s(d,6)=2

[0048] In operation 806, the method 800 calculates a plurality of sums of absolute values ​​for a plurality of different sample phases to obtain a plurality of sums of absolute values, each of the plurality of sums of absolute values ​​corresponding to a different one of the plurality of different sample phases. Each of the plurality of sums of absolute values ​​is obtained as sum(x)=s(x,1)+s(x,2)+s(x,3)+..., where x is a, b, c, or d. The plurality of sums of absolute values ​​for each sample phase a, b, c, d are shown below. ●Sum of the absolute values ​​of sample phase a: 4+4+4+4+4+4+4+4=28 ●Sum of absolute values ​​of sample phase b: 2 + 2 + 4 + 2 + 2 + 2 + 2 = 16 ●Sum of the absolute values ​​of sample phase c: 0+0+4+0+0+0+0=4 ●Sum of absolute values ​​of sample phase d: 2 + 2 + 4 + 2 + 2 + 2 + 2 = 16

[0049] In operation 808, the method 800 determines the edge sample phase, which is the sample phase corresponding to the largest sum of the sums of the absolute values. In other words, the sampling phase with the largest sum of the absolute values ​​is most likely to be the edge sample phase. In the example above, the largest sum of the absolute values ​​is 28, which corresponds to sample phase a. Therefore, in this embodiment, sample phase a is selected to be the edge sample phase.

[0050] Note that method 800 of FIG. 8 obtains multiple sums of the sample value in operation 802 using a sum of the sample value with each of the other sample values ​​within one symbol time period after the sample value. As a result, the edge sample phase determined in operation 808 is the first sample phase after the symbol edge. Note also that in some embodiments, rather than using a sum of the sample value with each of the other sample values ​​within one symbol time period after the sample value, multiple sums of the sample value can be obtained using a sum of the sample value with each of the other sample values ​​within one symbol time period before the sample value. FIG. 9 below is directed to such embodiments.

[0051] FIG. 9 is a flowchart illustrating yet another method 900 for determining an edge sample phase according to some embodiments. Method 900 of FIG. 9 is similar to method 800 of FIG. 8 , except that operation 902 replaces operation 802. In operation 902, method 900 calculates, for each sample value at a plurality of different sample phases, a sum of the sample value and each of the other sample values ​​within one symbol time period preceding the sample value to obtain a plurality of sums of the sample value. Similar to operation 802 of FIG. 8 , each of the plurality of sums corresponds to a different one of the plurality of different sample phases. However, in contrast to method 800 of FIG. 8 , operation 902 uses a sum of the sample value and each of the other sample values ​​within one symbol time period preceding the sample value, so that the edge sample phase determined in operation 808 of FIG. 9 will be the last sample phase occurring within each symbol. In the example shown in FIG. 7 , the edge sample phase would be determined to be sample phase d.

[0052] 10 is a block diagram of a physical layer device 1000 according to some embodiments. In some embodiments, PHY 102 (FIG. 1) may embody physical layer device 1000. Physical layer device 1000 includes an input 1004 (e.g., a pin of a semiconductor device package including physical layer device 1000) configured to receive signal 1002 from shared transmission medium 106 (FIG. 1). Physical layer device 1000 is configured to detect center sample phase 1016 of signal 1002 and sample signal 1002 using center sample phase 1016.

[0053] The physical layer device 1000 includes a sampling circuit 1006 configured to receive a signal 1002 that may be delivered to an input 1004 of the physical layer device 1000 from a shared transmission medium 106. The sampling circuit 1006 is configured to measure sample values ​​1008 of the signal 1002 at a plurality of different sample phases 1022 and provide the sample values ​​1008 to an edge detector 1010.

[0054] The edge detector 1010 is configured to receive the sample values ​​1008 from the sampling circuit 1006 and to determine an edge sample phase 1012 from a plurality of different sample phases 1022 based at least in part on the sample values ​​1008. For example, the edge detector 1010 may be configured to determine the edge sample phase 1012 using method 600 of Figure 6, method 800 of Figure 8, or method 900 of Figure 9. The edge detector 1010 is configured to provide the edge sample phase 1012 to a center detector 1014.

[0055] The center detector 1014 is configured to receive the edge sample phase 1012 from the edge detector 1010 and to determine a center sample phase 1016 based at least in part on the edge sample phase 1012. The sampling circuit 1018 is configured to provide a center sample value 1020 of the signal 1002. In some embodiments, the sampling circuit 1018 is configured to use the sample values ​​1008 provided by the sampling circuit 1006, allowing the sampling circuit 1018 to identify the center sample value 1020 without resampling the signal 1002, simply by selecting the center sample value of the sample values ​​1008 that corresponds to the center sample phase 1016. In some embodiments, the sampling circuit 1018 is configured to resample the signal 1002 at the center sample phase 1016 indicated by the center detector 1014.

[0056] In some embodiments, physical layer device 1000 includes one or more processors configured to perform the operations of physical layer device 1000. In some embodiments, part or all of physical layer device 1000 may be implemented using software or firmware stored by one or more data storage devices and executed by processing circuitry (see computing device 1100 of FIG. 11). In some embodiments, part or all of physical layer device 1000 may be implemented using electrical hardware components, such as combinational logic. As a non-limiting example, part or all of physical layer device 1000 may be implemented using a field programmable gate array (FPGA), a programmable logic controller (PLC), other logic devices, or a combination thereof.

[0057] 11 is a block diagram of a computing device 1100 that may be used in some embodiments. The computing device 1100 includes one or more processors 1102 (sometimes referred to herein as “processors” 1102) operably coupled to one or more data storage devices 1104 (sometimes referred to herein as “storage devices” 1104). The storage devices 1104 include computer-readable instructions stored thereon. The computer-readable instructions are configured to instruct the processor 1102 to perform operations of embodiments disclosed herein. For example, the computer-readable instructions may be configured to instruct the processor 1102 to perform at least a portion of, or all of, method 400 of FIG. 4, method 600 of FIG. 6, method 800 of FIG. 8, and / or method 900 of FIG. 9. As another example, the computer-readable instructions may be configured to instruct the processor 1102 to perform at least a portion of, or all of, the operations discussed for PHY 102 of FIG. 1. As a further example, the computer-readable instructions may be configured to instruct the processor 1102 to perform at least some or all of the operations discussed for the physical layer device 1000 of Figure 10. As a specific, non-limiting example, the computer-readable instructions may be configured to instruct the processor 1102 to sample a signal received from a shared transmission medium using a plurality of different sample phases, determine edge sample phases of the plurality of different sample phases, and determine a center sample phase of the plurality of different sample phases based on the edge sample phases.

[0058] As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation configured to perform the actions of a module or component and / or software object or routine that may be stored on and / or executed by general-purpose hardware (e.g., computer-readable media, processing device, etc.) of a computing system. In some embodiments, different components, modules, engines, and services described in this disclosure may be implemented as objects or processes that run on a computing system (e.g., as separate threads). While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations, or a combination of software and specific hardware implementations, are also possible and contemplated.

[0059] The terms used in this disclosure, and particularly in the appended claims (e.g., the body of the appended claims), are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "having" should be interpreted as "having at least," the term "including" should be interpreted as "including, but not limited to," etc.).

[0060] Additionally, where a specific number of introduced claim recitations is intended, such intention will be explicitly stated in the claim; absent such recitation, no such intention exists. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed as introducing a claim recitation with the indefinite article "a" or "an" limiting any particular claim including such introduced claim recitation to embodiments including only one of such recitations (e.g., "a" and / or "an" should be construed to mean "at least one" or "one or more"). The same applies to the use of definite articles used to introduce claim recitations, even if the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a" or "an" (e.g., "a" and / or "an" should be construed to mean "at least one" or "one or more").

[0061] Additionally, even when a specific number in an introduced claim is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., an explicit recitation of "two ____" without other modifiers means "at least two ____" or "two or more ____"). Furthermore, when conventions similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." are used, generally, such structures are intended to include A only, B only, C only, A and B together, A and C together, B and C together, or A, B, and C together.

[0062] Furthermore, any disjunction or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibility of including one of the terms, either of the terms, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B."

[0063] Example A non-exhaustive, non-limiting list of exemplary embodiments follows: Each of the exemplary embodiments listed below is not individually indicated as combinable with all other of the exemplary embodiments listed below and discussed above, but it is intended that these exemplary embodiments be combinable with all other exemplary embodiments and with the embodiments described above, except where it is apparent to one skilled in the art that the embodiments are not combinable.

[0064] Example 1: A physical layer device comprising: an input configured to receive a signal including a plurality of symbols from a shared transmission medium of a wired local area network; and one or more processors configured to perform the following: sampling the signal using a plurality of different sample phases to obtain sample values ​​for each of the plurality of symbols at each of the plurality of different sample phases; determining edge sample phases of the plurality of different sample phases in response to the obtained sample values ​​for each of the plurality of symbols at each of the plurality of different sample phases; determining center sample phases of the plurality of different sample phases in response to the determined edge sample phases; and using the determined center sample phase to determine values ​​for each of the plurality of symbols.

[0065] Example 2: A physical layer device as described in Example 1, wherein the one or more processors are configured to determine an edge sample phase for each sample phase of a plurality of different sample phases by performing an exclusive OR (XOR) calculation between a sample value corresponding to the sample phase and a sample value corresponding to a sample phase immediately adjacent in time to the sample phase, summing the results for each XOR calculation, and determining an edge sample phase corresponding to the highest sum of the results of the XOR calculation.

[0066] Example 3: The physical layer device of example 2, wherein the sample phase immediately adjacent in time to the sample phase comprises the sample phase immediately preceding in time the sample phase.

[0067] Example 4: The physical layer device of Example 1, wherein the one or more processors are configured to perform the following operations to determine the edge sample phase: for each sample value at a plurality of different sample phases, calculate a sum of the sample value and each of other sample values ​​within one symbol time period after the sample value to obtain a plurality of sums of the sample values, wherein each of the plurality of sums corresponds to a different one of the plurality of different sample phases; determine an absolute value of each of the plurality of sums for a plurality of different sample phases to obtain a plurality of absolute values ​​for a plurality of different sample phases; calculate a sum of the plurality of absolute values ​​for a plurality of different sample phases to obtain a plurality of sums of absolute values, wherein each of the plurality of sums of absolute values ​​corresponds to a different one of the plurality of different sample phases; and determine an edge sample phase that is the sample phase corresponding to the maximum sum of the plurality of sums of absolute values.

[0068] Example 5: A physical layer device as described in Example 1, wherein the one or more processors are configured to perform the following operations to determine the edge sample phase: for each sample value of a plurality of different sample phases, calculate a sum of the sample value and each of other sample values ​​within one symbol time period preceding the sample value to obtain a plurality of sums of the sample values, wherein each of the plurality of sums corresponds to a different one of the plurality of different sample phases; determine an absolute value of each of the plurality of sums for the plurality of different sample phases to obtain a plurality of absolute values ​​for the plurality of different sample phases; calculate a sum of the plurality of absolute values ​​for the plurality of different sample phases to obtain a plurality of sums of absolute values, wherein each of the plurality of sums of absolute values ​​corresponds to a different one of the plurality of different sample phases; and determine an edge sample phase which is the sample phase corresponding to the maximum sum of the plurality of sums of absolute values.

[0069] Example 6: The physical layer device of any one of Examples 1 to 5, wherein the plurality of different sample phases are spaced apart by substantially equal time intervals.

[0070] Example 7: A physical layer device described in any one of Examples 1 to 6, further comprising: a sampling circuit configured to determine sample values ​​of the signal; an edge detector configured to determine an edge sample phase based at least in part on the sample values; and a center detector configured to determine a center sample phase based at least in part on the determined edge sample phase.

[0071] Example 8: A physical layer device as described in any one of Examples 1 to 7, further comprising a computer-readable medium operably coupled to one or more processors, the computer-readable medium having computer-readable instructions stored thereon, the computer-readable instructions configured to instruct the one or more processors to perform at least a portion of the method described in Example 1.

[0072] Example 9: A method for selecting a sample phase for a signal from a plurality of different sample phases, the method comprising: sampling a signal including a plurality of symbols using a plurality of different sample phases to obtain respective sample values ​​of the plurality of symbols at each of the plurality of different sample phases, the signal being received from a shared transmission medium of a wired local area network; determining an edge sample phase of the plurality of different sample phases in response to the obtained sample values ​​of each of the plurality of symbols at each of the plurality of different sample phases; determining a center sample phase of the plurality of different sample phases in response to the determined edge sample phase; and using the determined center sample phase to determine a value of the symbol.

[0073] Example 10: The method described in Example 9, wherein the step of determining a center sample phase of a plurality of different sample phases includes a step of determining a center sample phase that is a sample phase that is approximately 1 / 2 symbol time length from the determined edge sample phase.

[0074] Example 11: The step of determining an edge sample phase of a plurality of different sample phases includes determining, for each sample phase of the plurality of different sample phases, a sample value corresponding to the sample phase and A method as described in any one of Examples 9 and 10, comprising the steps of: performing an exclusive OR (XOR) calculation between the sample phase and sample values ​​corresponding to sample phases immediately adjacent in time to the sample phase; summing the results for each XOR calculation; and determining the edge sample phase that corresponds to the highest sum of the results of the XOR calculation.

[0075] Example 12: The method of example 11, wherein the sample phase immediately adjacent in time to the sample phase includes the sample phase immediately preceding in time the sample phase.

[0076] Example 13: The method described in any one of Examples 9 and 10, wherein the step of determining the edge sample phase of a plurality of different sample phases includes: a step of calculating, for each sample value of the plurality of different sample phases, a sum of the sample value and each of other sample values ​​within one symbol time period after the sample value to obtain a plurality of sums of the sample values, wherein each of the plurality of sums corresponds to a different one of the plurality of different sample phases; a step of determining an absolute value of each of the plurality of sums for the plurality of different sample phases to obtain a plurality of absolute values ​​for the plurality of different sample phases; a step of calculating a sum of the plurality of absolute values ​​for the plurality of different sample phases to obtain a plurality of sums of absolute values, wherein each of the plurality of sums of absolute values ​​corresponds to a different one of the plurality of different sample phases; and a step of determining the edge sample phase which is the sample phase corresponding to the maximum sum of the plurality of sums of absolute values.

[0077] Example 14: The method described in any of Examples 9 and 10, wherein the step of determining the edge sample phase of a plurality of different sample phases includes: for each sample value of the plurality of different sample phases, calculating a sum of each of the sample values ​​with each of the sample values ​​within one symbol time period prior to the sample value to obtain a plurality of sums of the sample values, wherein each of the plurality of sums corresponds to a different one of the plurality of different sample phases; determining an absolute value of each of the plurality of sums for each of the plurality of different sample phases to obtain a plurality of absolute values ​​for the plurality of different sample phases; calculating a sum of the plurality of absolute values ​​for each of the plurality of different sample phases to obtain a plurality of sums of absolute values, wherein each of the plurality of sums of absolute values ​​corresponds to a different one of the plurality of different sample phases; and determining the edge sample phase which is the sample phase corresponding to the maximum sum of the plurality of sums of absolute values.

[0078] Example 15: The method described in Example 14, wherein the number of different sample phases includes four different sample phases, and the center sample phase is selected to be one of the two sample phases that immediately precede the edge sample phase.

[0079] Example 16: A non-transitory computer-readable storage medium comprising instructions, which, when executed by one or more processors, cause the one or more processors to sample a signal comprising a plurality of symbols using a plurality of different sample phases to obtain respective sample values ​​of the plurality of symbols at each of the plurality of different sample phases, the signal being received from a shared transmission medium of a wired local area network; determining edge sample phases of the plurality of different sample phases based on the sample values; determining center sample phases of the plurality of different sample phases based on the determined edge sample phases; and using the determined center sample phase to determine a value of the symbol.

[0080] conclusion While the present disclosure has been described herein with reference to certain illustrated embodiments, those skilled in the art will recognize and appreciate that the present invention is not so limited. Rather, numerous additions, deletions, and modifications can be made to the illustrated and described embodiments without departing from the scope of the invention as claimed below, along with their legal equivalents. In addition, features of one embodiment can be combined, as contemplated by the inventor, with features of other disclosed embodiments and still fall within the scope of the present disclosure.

Claims

1. A physical layer device, comprising: an input configured to receive a signal comprising a plurality of symbols from a shared transmission medium of a wired local area network; one or more processors, sampling the signal using a plurality of different sample phases to obtain sample values ​​for each of the plurality of symbols at each of the plurality of different sample phases; determining edge sample phases for the plurality of different sample phases in response to the obtained sample values ​​for each of the plurality of symbols at each of the plurality of different sample phases; determining a center sample phase of the plurality of different sample phases in response to the determined edge sample phase; and and one or more processors configured to perform the steps of: using the determined center sample phase to determine a value for each of the plurality of symbols.

2. The one or more processors: for each sample phase of the plurality of different sample phases, performing an exclusive-or (XOR) calculation between the sample value corresponding to the sample phase and the sample value corresponding to the sample phase that is immediately adjacent in time to the sample phase; summing the results for each XOR calculation; and 2. The physical layer device of claim 1, configured to determine the edge sample phase by determining the edge sample phase that corresponds to a highest sum of the results of the XOR calculations.

3. The physical layer device of claim 2 , wherein the sample phases immediately adjacent in time to the sample phase include the sample phase immediately preceding in time the sample phase.

4. The one or more processors: for each sample value of the plurality of different sample phases, calculating a sum of the sample value with each other sample value within one symbol time period after the sample value to obtain a plurality of sums of sample values, each sum corresponding to a different one of the plurality of different sample phases; determining an absolute value of each sum of the plurality of sums for each of the plurality of different sample phases to obtain a plurality of absolute values ​​for each of the plurality of different sample phases; calculating the plurality of sums of absolute values ​​for each of the plurality of different sample phases to obtain a plurality of sums of absolute values, each of the plurality of sums of absolute values ​​corresponding to a different one of the plurality of different sample phases; and 2. The physical layer device of claim 1, wherein the physical layer device determines the edge sample phase by being configured to perform: determining an edge sample phase, the edge sample phase being a sample phase corresponding to a maximum sum of a plurality of sums of the absolute values.

5. The one or more processors: for each sample value of the plurality of different sample phases, calculating a sum of the sample value with each other sample value within one symbol time period preceding the sample value to obtain a plurality of sums of sample values, each sum corresponding to a different one of the plurality of different sample phases; determining an absolute value of each sum of the plurality of sums for each of the plurality of different sample phases to obtain a plurality of absolute values ​​for each of the plurality of different sample phases; calculating the plurality of sums of absolute values ​​for each of the plurality of different sample phases to obtain a plurality of sums of absolute values, each of the plurality of sums of absolute values ​​corresponding to a different one of the plurality of different sample phases; and 2. The physical layer device of claim 1, wherein the physical layer device determines the edge sample phase by being configured to perform the steps of: determining the edge sample phase, the edge sample phase being a sample phase corresponding to a maximum sum of a plurality of sums of the absolute values.

6. The physical layer device of claim 1 , wherein the different sample phases are spaced apart by substantially equal time intervals.

7. a sampling circuit configured to determine the sample values ​​of the signal; an edge detector configured to determine the edge sample phase based at least in part on the sample value; 10. The physical layer device of claim 1, further comprising: a center detector configured to determine the center sample phase based at least in part on the determined edge sample phase.

8. 10. The physical layer device of claim 1, further comprising: a computer-readable medium operably coupled to the one or more processors, the computer-readable medium having computer-readable instructions stored thereon, the computer-readable instructions configured to instruct the one or more processors to perform at least a portion of the functions of the one or more processors.

9. 1. A method for selecting a sample phase of a signal from a plurality of different sample phases, the method comprising: sampling a signal comprising a plurality of symbols using a plurality of different sample phases to obtain sample values ​​for each of the plurality of symbols at each of the plurality of different sample phases, the signal being received from a shared transmission medium of a wired local area network; determining edge sample phases for the plurality of different sample phases in response to the obtained sample values ​​for each of the plurality of symbols at each of the plurality of different sample phases; determining a center sample phase of the plurality of different sample phases in response to the determined edge sample phases; and using the determined center sample phase to determine a value of the symbol.

10. 10. The method of claim 9, wherein determining a center sample phase of the plurality of different sample phases comprises determining the center sample phase to be a sample phase that is approximately one-half symbol time length from the determined edge sample phase.

11. determining the edge sample phases of the plurality of different sample phases includes: for each sample phase of the plurality of different sample phases, performing an exclusive-or (XOR) calculation between the sample value corresponding to the sample phase and the sample value corresponding to a sample phase immediately adjacent in time to the sample phase; summing the results of each XOR calculation; determining the edge sample phase to be the sample phase corresponding to the highest sum of the results of the XOR calculations.

12. The method of claim 11 , wherein the sample phases immediately adjacent in time to the sample phase include the sample phase immediately preceding in time the sample phase.

13. determining the edge sample phases of the plurality of different sample phases includes: calculating, for each sample value of the plurality of different sample phases, a sum of the sample value with each other sample value within one symbol time period after the sample value to obtain a plurality of sums of the sample values, each sum corresponding to a different one of the plurality of different sample phases; determining an absolute value of each of the plurality of sums for the plurality of different sample phases to obtain a plurality of absolute values ​​for the plurality of different sample phases; calculating the plurality of sums of absolute values ​​for each of the plurality of different sample phases to obtain a plurality of sums of absolute values, each of the plurality of sums of absolute values ​​corresponding to a different one of the plurality of different sample phases; and determining the edge sample phase to be the sample phase corresponding to the maximum sum of the plurality of sums of the absolute values.

14. determining the edge sample phases of the plurality of different sample phases includes: calculating, for each sample value of the plurality of different sample phases, a sum of the sample value with each sample value within one symbol time period preceding the sample value to obtain a plurality of sums of the sample values, each sum corresponding to a different one of the plurality of different sample phases; determining an absolute value of each of the plurality of sums for each of the plurality of different sample phases to obtain a plurality of absolute values ​​for each of the plurality of different sample phases; calculating the plurality of sums of absolute values ​​for each of the plurality of different sample phases to obtain a plurality of sums of absolute values, each of the plurality of sums of absolute values ​​corresponding to a different one of the plurality of different sample phases; and determining the edge sample phase to be the sample phase corresponding to the maximum sum of the plurality of sums of the absolute values.

15. 15. The method of claim 14, wherein the number of different sample phases includes four different sample phases, and the center sample phase is selected to be one of two sample phases immediately preceding in time the edge sample phase.

16. A non-transitory computer-readable storage medium that, when executed by one or more processors, causes the one or more processors to: sampling a signal comprising a plurality of symbols using a plurality of different sample phases to obtain sample values ​​for each of the plurality of symbols at each of the plurality of different sample phases, the signal being received from a shared transmission medium of a wired local area network; determining edge sample phases of the plurality of different sample phases based on the sample values; determining a center sample phase of the plurality of different sample phases based on the determined edge sample phases; and and using the determined center sample phase to determine a value of the symbol.

Images